1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2017 NXP
4  * Copyright 2016 Freescale Semiconductor, Inc.
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/perf_event.h>
17 #include <linux/slab.h>
18 
19 #define COUNTER_CNTL		0x0
20 #define COUNTER_READ		0x20
21 
22 #define COUNTER_DPCR1		0x30
23 
24 #define CNTL_OVER		0x1
25 #define CNTL_CLEAR		0x2
26 #define CNTL_EN			0x4
27 #define CNTL_EN_MASK		0xFFFFFFFB
28 #define CNTL_CLEAR_MASK		0xFFFFFFFD
29 #define CNTL_OVER_MASK		0xFFFFFFFE
30 
31 #define CNTL_CSV_SHIFT		24
32 #define CNTL_CSV_MASK		(0xFFU << CNTL_CSV_SHIFT)
33 
34 #define EVENT_CYCLES_ID		0
35 #define EVENT_CYCLES_COUNTER	0
36 #define NUM_COUNTERS		4
37 
38 #define AXI_MASKING_REVERT	0xffff0000	/* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
39 
40 #define to_ddr_pmu(p)		container_of(p, struct ddr_pmu, pmu)
41 
42 #define DDR_PERF_DEV_NAME	"imx8_ddr"
43 #define DDR_CPUHP_CB_NAME	DDR_PERF_DEV_NAME "_perf_pmu"
44 
45 static DEFINE_IDA(ddr_ida);
46 
47 /* DDR Perf hardware feature */
48 #define DDR_CAP_AXI_ID_FILTER			0x1     /* support AXI ID filter */
49 #define DDR_CAP_AXI_ID_FILTER_ENHANCED		0x3     /* support enhanced AXI ID filter */
50 
51 struct fsl_ddr_devtype_data {
52 	unsigned int quirks;    /* quirks needed for different DDR Perf core */
53 	const char *identifier;	/* system PMU identifier for userspace */
54 };
55 
56 static const struct fsl_ddr_devtype_data imx8_devtype_data;
57 
58 static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
59 	.quirks = DDR_CAP_AXI_ID_FILTER,
60 };
61 
62 static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
63 	.quirks = DDR_CAP_AXI_ID_FILTER,
64 	.identifier = "i.MX8MQ",
65 };
66 
67 static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
68 	.quirks = DDR_CAP_AXI_ID_FILTER,
69 	.identifier = "i.MX8MM",
70 };
71 
72 static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
73 	.quirks = DDR_CAP_AXI_ID_FILTER,
74 	.identifier = "i.MX8MN",
75 };
76 
77 static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
78 	.quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
79 	.identifier = "i.MX8MP",
80 };
81 
82 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
83 	{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
84 	{ .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
85 	{ .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
86 	{ .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
87 	{ .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
88 	{ .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
89 	{ /* sentinel */ }
90 };
91 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
92 
93 struct ddr_pmu {
94 	struct pmu pmu;
95 	void __iomem *base;
96 	unsigned int cpu;
97 	struct	hlist_node node;
98 	struct	device *dev;
99 	struct perf_event *events[NUM_COUNTERS];
100 	enum cpuhp_state cpuhp_state;
101 	const struct fsl_ddr_devtype_data *devtype_data;
102 	int irq;
103 	int id;
104 };
105 
106 static ssize_t ddr_perf_identifier_show(struct device *dev,
107 					struct device_attribute *attr,
108 					char *page)
109 {
110 	struct ddr_pmu *pmu = dev_get_drvdata(dev);
111 
112 	return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
113 }
114 
115 static umode_t ddr_perf_identifier_attr_visible(struct kobject *kobj,
116 						struct attribute *attr,
117 						int n)
118 {
119 	struct device *dev = kobj_to_dev(kobj);
120 	struct ddr_pmu *pmu = dev_get_drvdata(dev);
121 
122 	if (!pmu->devtype_data->identifier)
123 		return 0;
124 	return attr->mode;
125 };
126 
127 static struct device_attribute ddr_perf_identifier_attr =
128 	__ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
129 
130 static struct attribute *ddr_perf_identifier_attrs[] = {
131 	&ddr_perf_identifier_attr.attr,
132 	NULL,
133 };
134 
135 static const struct attribute_group ddr_perf_identifier_attr_group = {
136 	.attrs = ddr_perf_identifier_attrs,
137 	.is_visible = ddr_perf_identifier_attr_visible,
138 };
139 
140 enum ddr_perf_filter_capabilities {
141 	PERF_CAP_AXI_ID_FILTER = 0,
142 	PERF_CAP_AXI_ID_FILTER_ENHANCED,
143 	PERF_CAP_AXI_ID_FEAT_MAX,
144 };
145 
146 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap)
147 {
148 	u32 quirks = pmu->devtype_data->quirks;
149 
150 	switch (cap) {
151 	case PERF_CAP_AXI_ID_FILTER:
152 		return !!(quirks & DDR_CAP_AXI_ID_FILTER);
153 	case PERF_CAP_AXI_ID_FILTER_ENHANCED:
154 		quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED;
155 		return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED;
156 	default:
157 		WARN(1, "unknown filter cap %d\n", cap);
158 	}
159 
160 	return 0;
161 }
162 
163 static ssize_t ddr_perf_filter_cap_show(struct device *dev,
164 					struct device_attribute *attr,
165 					char *buf)
166 {
167 	struct ddr_pmu *pmu = dev_get_drvdata(dev);
168 	struct dev_ext_attribute *ea =
169 		container_of(attr, struct dev_ext_attribute, attr);
170 	int cap = (long)ea->var;
171 
172 	return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap));
173 }
174 
175 #define PERF_EXT_ATTR_ENTRY(_name, _func, _var)				\
176 	(&((struct dev_ext_attribute) {					\
177 		__ATTR(_name, 0444, _func, NULL), (void *)_var		\
178 	}).attr.attr)
179 
180 #define PERF_FILTER_EXT_ATTR_ENTRY(_name, _var)				\
181 	PERF_EXT_ATTR_ENTRY(_name, ddr_perf_filter_cap_show, _var)
182 
183 static struct attribute *ddr_perf_filter_cap_attr[] = {
184 	PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER),
185 	PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED),
186 	NULL,
187 };
188 
189 static const struct attribute_group ddr_perf_filter_cap_attr_group = {
190 	.name = "caps",
191 	.attrs = ddr_perf_filter_cap_attr,
192 };
193 
194 static ssize_t ddr_perf_cpumask_show(struct device *dev,
195 				struct device_attribute *attr, char *buf)
196 {
197 	struct ddr_pmu *pmu = dev_get_drvdata(dev);
198 
199 	return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
200 }
201 
202 static struct device_attribute ddr_perf_cpumask_attr =
203 	__ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
204 
205 static struct attribute *ddr_perf_cpumask_attrs[] = {
206 	&ddr_perf_cpumask_attr.attr,
207 	NULL,
208 };
209 
210 static const struct attribute_group ddr_perf_cpumask_attr_group = {
211 	.attrs = ddr_perf_cpumask_attrs,
212 };
213 
214 static ssize_t
215 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr,
216 		   char *page)
217 {
218 	struct perf_pmu_events_attr *pmu_attr;
219 
220 	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
221 	return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
222 }
223 
224 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id)		\
225 	PMU_EVENT_ATTR_ID(_name, ddr_pmu_event_show, _id)
226 
227 static struct attribute *ddr_perf_events_attrs[] = {
228 	IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID),
229 	IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01),
230 	IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
231 	IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
232 	IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
233 	IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
234 	IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
235 	IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
236 	IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
237 	IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
238 	IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
239 	IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
240 	IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
241 	IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
242 	IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
243 	IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
244 	IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
245 	IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
246 	IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
247 	IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
248 	IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
249 	IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31),
250 	IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32),
251 	IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
252 	IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
253 	IMX8_DDR_PMU_EVENT_ATTR(read, 0x35),
254 	IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
255 	IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37),
256 	IMX8_DDR_PMU_EVENT_ATTR(write, 0x38),
257 	IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
258 	IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
259 	IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
260 	NULL,
261 };
262 
263 static const struct attribute_group ddr_perf_events_attr_group = {
264 	.name = "events",
265 	.attrs = ddr_perf_events_attrs,
266 };
267 
268 PMU_FORMAT_ATTR(event, "config:0-7");
269 PMU_FORMAT_ATTR(axi_id, "config1:0-15");
270 PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
271 
272 static struct attribute *ddr_perf_format_attrs[] = {
273 	&format_attr_event.attr,
274 	&format_attr_axi_id.attr,
275 	&format_attr_axi_mask.attr,
276 	NULL,
277 };
278 
279 static const struct attribute_group ddr_perf_format_attr_group = {
280 	.name = "format",
281 	.attrs = ddr_perf_format_attrs,
282 };
283 
284 static const struct attribute_group *attr_groups[] = {
285 	&ddr_perf_events_attr_group,
286 	&ddr_perf_format_attr_group,
287 	&ddr_perf_cpumask_attr_group,
288 	&ddr_perf_filter_cap_attr_group,
289 	&ddr_perf_identifier_attr_group,
290 	NULL,
291 };
292 
293 static bool ddr_perf_is_filtered(struct perf_event *event)
294 {
295 	return event->attr.config == 0x41 || event->attr.config == 0x42;
296 }
297 
298 static u32 ddr_perf_filter_val(struct perf_event *event)
299 {
300 	return event->attr.config1;
301 }
302 
303 static bool ddr_perf_filters_compatible(struct perf_event *a,
304 					struct perf_event *b)
305 {
306 	if (!ddr_perf_is_filtered(a))
307 		return true;
308 	if (!ddr_perf_is_filtered(b))
309 		return true;
310 	return ddr_perf_filter_val(a) == ddr_perf_filter_val(b);
311 }
312 
313 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event)
314 {
315 	unsigned int filt;
316 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
317 
318 	filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED;
319 	return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) &&
320 		ddr_perf_is_filtered(event);
321 }
322 
323 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
324 {
325 	int i;
326 
327 	/*
328 	 * Always map cycle event to counter 0
329 	 * Cycles counter is dedicated for cycle event
330 	 * can't used for the other events
331 	 */
332 	if (event == EVENT_CYCLES_ID) {
333 		if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
334 			return EVENT_CYCLES_COUNTER;
335 		else
336 			return -ENOENT;
337 	}
338 
339 	for (i = 1; i < NUM_COUNTERS; i++) {
340 		if (pmu->events[i] == NULL)
341 			return i;
342 	}
343 
344 	return -ENOENT;
345 }
346 
347 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
348 {
349 	pmu->events[counter] = NULL;
350 }
351 
352 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
353 {
354 	struct perf_event *event = pmu->events[counter];
355 	void __iomem *base = pmu->base;
356 
357 	/*
358 	 * return bytes instead of bursts from ddr transaction for
359 	 * axid-read and axid-write event if PMU core supports enhanced
360 	 * filter.
361 	 */
362 	base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 :
363 						       COUNTER_READ;
364 	return readl_relaxed(base + counter * 4);
365 }
366 
367 static int ddr_perf_event_init(struct perf_event *event)
368 {
369 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
370 	struct hw_perf_event *hwc = &event->hw;
371 	struct perf_event *sibling;
372 
373 	if (event->attr.type != event->pmu->type)
374 		return -ENOENT;
375 
376 	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
377 		return -EOPNOTSUPP;
378 
379 	if (event->cpu < 0) {
380 		dev_warn(pmu->dev, "Can't provide per-task data!\n");
381 		return -EOPNOTSUPP;
382 	}
383 
384 	/*
385 	 * We must NOT create groups containing mixed PMUs, although software
386 	 * events are acceptable (for example to create a CCN group
387 	 * periodically read when a hrtimer aka cpu-clock leader triggers).
388 	 */
389 	if (event->group_leader->pmu != event->pmu &&
390 			!is_software_event(event->group_leader))
391 		return -EINVAL;
392 
393 	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
394 		if (!ddr_perf_filters_compatible(event, event->group_leader))
395 			return -EINVAL;
396 		for_each_sibling_event(sibling, event->group_leader) {
397 			if (!ddr_perf_filters_compatible(event, sibling))
398 				return -EINVAL;
399 		}
400 	}
401 
402 	for_each_sibling_event(sibling, event->group_leader) {
403 		if (sibling->pmu != event->pmu &&
404 				!is_software_event(sibling))
405 			return -EINVAL;
406 	}
407 
408 	event->cpu = pmu->cpu;
409 	hwc->idx = -1;
410 
411 	return 0;
412 }
413 
414 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
415 				  int counter, bool enable)
416 {
417 	u8 reg = counter * 4 + COUNTER_CNTL;
418 	int val;
419 
420 	if (enable) {
421 		/*
422 		 * cycle counter is special which should firstly write 0 then
423 		 * write 1 into CLEAR bit to clear it. Other counters only
424 		 * need write 0 into CLEAR bit and it turns out to be 1 by
425 		 * hardware. Below enable flow is harmless for all counters.
426 		 */
427 		writel(0, pmu->base + reg);
428 		val = CNTL_EN | CNTL_CLEAR;
429 		val |= FIELD_PREP(CNTL_CSV_MASK, config);
430 		writel(val, pmu->base + reg);
431 	} else {
432 		/* Disable counter */
433 		val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
434 		writel(val, pmu->base + reg);
435 	}
436 }
437 
438 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter)
439 {
440 	int val;
441 
442 	val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL);
443 
444 	return val & CNTL_OVER;
445 }
446 
447 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter)
448 {
449 	u8 reg = counter * 4 + COUNTER_CNTL;
450 	int val;
451 
452 	val = readl_relaxed(pmu->base + reg);
453 	val &= ~CNTL_CLEAR;
454 	writel(val, pmu->base + reg);
455 
456 	val |= CNTL_CLEAR;
457 	writel(val, pmu->base + reg);
458 }
459 
460 static void ddr_perf_event_update(struct perf_event *event)
461 {
462 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
463 	struct hw_perf_event *hwc = &event->hw;
464 	u64 new_raw_count;
465 	int counter = hwc->idx;
466 	int ret;
467 
468 	new_raw_count = ddr_perf_read_counter(pmu, counter);
469 	local64_add(new_raw_count, &event->count);
470 
471 	/*
472 	 * For legacy SoCs: event counter continue counting when overflow,
473 	 *                  no need to clear the counter.
474 	 * For new SoCs: event counter stop counting when overflow, need
475 	 *               clear counter to let it count again.
476 	 */
477 	if (counter != EVENT_CYCLES_COUNTER) {
478 		ret = ddr_perf_counter_overflow(pmu, counter);
479 		if (ret)
480 			dev_warn_ratelimited(pmu->dev,  "events lost due to counter overflow (config 0x%llx)\n",
481 					     event->attr.config);
482 	}
483 
484 	/* clear counter every time for both cycle counter and event counter */
485 	ddr_perf_counter_clear(pmu, counter);
486 }
487 
488 static void ddr_perf_event_start(struct perf_event *event, int flags)
489 {
490 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
491 	struct hw_perf_event *hwc = &event->hw;
492 	int counter = hwc->idx;
493 
494 	local64_set(&hwc->prev_count, 0);
495 
496 	ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
497 
498 	hwc->state = 0;
499 }
500 
501 static int ddr_perf_event_add(struct perf_event *event, int flags)
502 {
503 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
504 	struct hw_perf_event *hwc = &event->hw;
505 	int counter;
506 	int cfg = event->attr.config;
507 	int cfg1 = event->attr.config1;
508 
509 	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
510 		int i;
511 
512 		for (i = 1; i < NUM_COUNTERS; i++) {
513 			if (pmu->events[i] &&
514 			    !ddr_perf_filters_compatible(event, pmu->events[i]))
515 				return -EINVAL;
516 		}
517 
518 		if (ddr_perf_is_filtered(event)) {
519 			/* revert axi id masking(axi_mask) value */
520 			cfg1 ^= AXI_MASKING_REVERT;
521 			writel(cfg1, pmu->base + COUNTER_DPCR1);
522 		}
523 	}
524 
525 	counter = ddr_perf_alloc_counter(pmu, cfg);
526 	if (counter < 0) {
527 		dev_dbg(pmu->dev, "There are not enough counters\n");
528 		return -EOPNOTSUPP;
529 	}
530 
531 	pmu->events[counter] = event;
532 	hwc->idx = counter;
533 
534 	hwc->state |= PERF_HES_STOPPED;
535 
536 	if (flags & PERF_EF_START)
537 		ddr_perf_event_start(event, flags);
538 
539 	return 0;
540 }
541 
542 static void ddr_perf_event_stop(struct perf_event *event, int flags)
543 {
544 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
545 	struct hw_perf_event *hwc = &event->hw;
546 	int counter = hwc->idx;
547 
548 	ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
549 	ddr_perf_event_update(event);
550 
551 	hwc->state |= PERF_HES_STOPPED;
552 }
553 
554 static void ddr_perf_event_del(struct perf_event *event, int flags)
555 {
556 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
557 	struct hw_perf_event *hwc = &event->hw;
558 	int counter = hwc->idx;
559 
560 	ddr_perf_event_stop(event, PERF_EF_UPDATE);
561 
562 	ddr_perf_free_counter(pmu, counter);
563 	hwc->idx = -1;
564 }
565 
566 static void ddr_perf_pmu_enable(struct pmu *pmu)
567 {
568 	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
569 
570 	/* enable cycle counter if cycle is not active event list */
571 	if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
572 		ddr_perf_counter_enable(ddr_pmu,
573 				      EVENT_CYCLES_ID,
574 				      EVENT_CYCLES_COUNTER,
575 				      true);
576 }
577 
578 static void ddr_perf_pmu_disable(struct pmu *pmu)
579 {
580 	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
581 
582 	if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
583 		ddr_perf_counter_enable(ddr_pmu,
584 				      EVENT_CYCLES_ID,
585 				      EVENT_CYCLES_COUNTER,
586 				      false);
587 }
588 
589 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
590 			 struct device *dev)
591 {
592 	*pmu = (struct ddr_pmu) {
593 		.pmu = (struct pmu) {
594 			.module	      = THIS_MODULE,
595 			.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
596 			.task_ctx_nr = perf_invalid_context,
597 			.attr_groups = attr_groups,
598 			.event_init  = ddr_perf_event_init,
599 			.add	     = ddr_perf_event_add,
600 			.del	     = ddr_perf_event_del,
601 			.start	     = ddr_perf_event_start,
602 			.stop	     = ddr_perf_event_stop,
603 			.read	     = ddr_perf_event_update,
604 			.pmu_enable  = ddr_perf_pmu_enable,
605 			.pmu_disable = ddr_perf_pmu_disable,
606 		},
607 		.base = base,
608 		.dev = dev,
609 	};
610 
611 	pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL);
612 	return pmu->id;
613 }
614 
615 static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
616 {
617 	int i;
618 	struct ddr_pmu *pmu = (struct ddr_pmu *) p;
619 	struct perf_event *event;
620 
621 	/* all counter will stop if cycle counter disabled */
622 	ddr_perf_counter_enable(pmu,
623 			      EVENT_CYCLES_ID,
624 			      EVENT_CYCLES_COUNTER,
625 			      false);
626 	/*
627 	 * When the cycle counter overflows, all counters are stopped,
628 	 * and an IRQ is raised. If any other counter overflows, it
629 	 * continues counting, and no IRQ is raised. But for new SoCs,
630 	 * such as i.MX8MP, event counter would stop when overflow, so
631 	 * we need use cycle counter to stop overflow of event counter.
632 	 *
633 	 * Cycles occur at least 4 times as often as other events, so we
634 	 * can update all events on a cycle counter overflow and not
635 	 * lose events.
636 	 *
637 	 */
638 	for (i = 0; i < NUM_COUNTERS; i++) {
639 
640 		if (!pmu->events[i])
641 			continue;
642 
643 		event = pmu->events[i];
644 
645 		ddr_perf_event_update(event);
646 	}
647 
648 	ddr_perf_counter_enable(pmu,
649 			      EVENT_CYCLES_ID,
650 			      EVENT_CYCLES_COUNTER,
651 			      true);
652 
653 	return IRQ_HANDLED;
654 }
655 
656 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
657 {
658 	struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
659 	int target;
660 
661 	if (cpu != pmu->cpu)
662 		return 0;
663 
664 	target = cpumask_any_but(cpu_online_mask, cpu);
665 	if (target >= nr_cpu_ids)
666 		return 0;
667 
668 	perf_pmu_migrate_context(&pmu->pmu, cpu, target);
669 	pmu->cpu = target;
670 
671 	WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
672 
673 	return 0;
674 }
675 
676 static int ddr_perf_probe(struct platform_device *pdev)
677 {
678 	struct ddr_pmu *pmu;
679 	struct device_node *np;
680 	void __iomem *base;
681 	char *name;
682 	int num;
683 	int ret;
684 	int irq;
685 
686 	base = devm_platform_ioremap_resource(pdev, 0);
687 	if (IS_ERR(base))
688 		return PTR_ERR(base);
689 
690 	np = pdev->dev.of_node;
691 
692 	pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
693 	if (!pmu)
694 		return -ENOMEM;
695 
696 	num = ddr_perf_init(pmu, base, &pdev->dev);
697 
698 	platform_set_drvdata(pdev, pmu);
699 
700 	name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
701 			      num);
702 	if (!name) {
703 		ret = -ENOMEM;
704 		goto cpuhp_state_err;
705 	}
706 
707 	pmu->devtype_data = of_device_get_match_data(&pdev->dev);
708 
709 	pmu->cpu = raw_smp_processor_id();
710 	ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
711 				      DDR_CPUHP_CB_NAME,
712 				      NULL,
713 				      ddr_perf_offline_cpu);
714 
715 	if (ret < 0) {
716 		dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n");
717 		goto cpuhp_state_err;
718 	}
719 
720 	pmu->cpuhp_state = ret;
721 
722 	/* Register the pmu instance for cpu hotplug */
723 	ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
724 	if (ret) {
725 		dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
726 		goto cpuhp_instance_err;
727 	}
728 
729 	/* Request irq */
730 	irq = of_irq_get(np, 0);
731 	if (irq < 0) {
732 		dev_err(&pdev->dev, "Failed to get irq: %d", irq);
733 		ret = irq;
734 		goto ddr_perf_err;
735 	}
736 
737 	ret = devm_request_irq(&pdev->dev, irq,
738 					ddr_perf_irq_handler,
739 					IRQF_NOBALANCING | IRQF_NO_THREAD,
740 					DDR_CPUHP_CB_NAME,
741 					pmu);
742 	if (ret < 0) {
743 		dev_err(&pdev->dev, "Request irq failed: %d", ret);
744 		goto ddr_perf_err;
745 	}
746 
747 	pmu->irq = irq;
748 	ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
749 	if (ret) {
750 		dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
751 		goto ddr_perf_err;
752 	}
753 
754 	ret = perf_pmu_register(&pmu->pmu, name, -1);
755 	if (ret)
756 		goto ddr_perf_err;
757 
758 	return 0;
759 
760 ddr_perf_err:
761 	cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
762 cpuhp_instance_err:
763 	cpuhp_remove_multi_state(pmu->cpuhp_state);
764 cpuhp_state_err:
765 	ida_free(&ddr_ida, pmu->id);
766 	dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
767 	return ret;
768 }
769 
770 static int ddr_perf_remove(struct platform_device *pdev)
771 {
772 	struct ddr_pmu *pmu = platform_get_drvdata(pdev);
773 
774 	cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
775 	cpuhp_remove_multi_state(pmu->cpuhp_state);
776 
777 	perf_pmu_unregister(&pmu->pmu);
778 
779 	ida_free(&ddr_ida, pmu->id);
780 	return 0;
781 }
782 
783 static struct platform_driver imx_ddr_pmu_driver = {
784 	.driver         = {
785 		.name   = "imx-ddr-pmu",
786 		.of_match_table = imx_ddr_pmu_dt_ids,
787 		.suppress_bind_attrs = true,
788 	},
789 	.probe          = ddr_perf_probe,
790 	.remove         = ddr_perf_remove,
791 };
792 
793 module_platform_driver(imx_ddr_pmu_driver);
794 MODULE_LICENSE("GPL v2");
795