1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2016 Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/init.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_irq.h> 14 #include <linux/perf_event.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 18 #define COUNTER_CNTL 0x0 19 #define COUNTER_READ 0x20 20 21 #define COUNTER_DPCR1 0x30 22 23 #define CNTL_OVER 0x1 24 #define CNTL_CLEAR 0x2 25 #define CNTL_EN 0x4 26 #define CNTL_EN_MASK 0xFFFFFFFB 27 #define CNTL_CLEAR_MASK 0xFFFFFFFD 28 #define CNTL_OVER_MASK 0xFFFFFFFE 29 30 #define CNTL_CSV_SHIFT 24 31 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) 32 33 #define EVENT_CYCLES_ID 0 34 #define EVENT_CYCLES_COUNTER 0 35 #define NUM_COUNTERS 4 36 37 #define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */ 38 39 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) 40 41 #define DDR_PERF_DEV_NAME "imx8_ddr" 42 #define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu" 43 44 static DEFINE_IDA(ddr_ida); 45 46 /* DDR Perf hardware feature */ 47 #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ 48 #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */ 49 50 struct fsl_ddr_devtype_data { 51 unsigned int quirks; /* quirks needed for different DDR Perf core */ 52 const char *identifier; /* system PMU identifier for userspace */ 53 }; 54 55 static const struct fsl_ddr_devtype_data imx8_devtype_data; 56 57 static const struct fsl_ddr_devtype_data imx8m_devtype_data = { 58 .quirks = DDR_CAP_AXI_ID_FILTER, 59 }; 60 61 static const struct fsl_ddr_devtype_data imx8mq_devtype_data = { 62 .quirks = DDR_CAP_AXI_ID_FILTER, 63 .identifier = "i.MX8MQ", 64 }; 65 66 static const struct fsl_ddr_devtype_data imx8mm_devtype_data = { 67 .quirks = DDR_CAP_AXI_ID_FILTER, 68 .identifier = "i.MX8MM", 69 }; 70 71 static const struct fsl_ddr_devtype_data imx8mn_devtype_data = { 72 .quirks = DDR_CAP_AXI_ID_FILTER, 73 .identifier = "i.MX8MN", 74 }; 75 76 static const struct fsl_ddr_devtype_data imx8mp_devtype_data = { 77 .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED, 78 .identifier = "i.MX8MP", 79 }; 80 81 static const struct of_device_id imx_ddr_pmu_dt_ids[] = { 82 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data}, 83 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data}, 84 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data}, 85 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data}, 86 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data}, 87 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data}, 88 { /* sentinel */ } 89 }; 90 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); 91 92 struct ddr_pmu { 93 struct pmu pmu; 94 void __iomem *base; 95 unsigned int cpu; 96 struct hlist_node node; 97 struct device *dev; 98 struct perf_event *events[NUM_COUNTERS]; 99 enum cpuhp_state cpuhp_state; 100 const struct fsl_ddr_devtype_data *devtype_data; 101 int irq; 102 int id; 103 }; 104 105 static ssize_t ddr_perf_identifier_show(struct device *dev, 106 struct device_attribute *attr, 107 char *page) 108 { 109 struct ddr_pmu *pmu = dev_get_drvdata(dev); 110 111 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); 112 } 113 114 static umode_t ddr_perf_identifier_attr_visible(struct kobject *kobj, 115 struct attribute *attr, 116 int n) 117 { 118 struct device *dev = kobj_to_dev(kobj); 119 struct ddr_pmu *pmu = dev_get_drvdata(dev); 120 121 if (!pmu->devtype_data->identifier) 122 return 0; 123 return attr->mode; 124 }; 125 126 static struct device_attribute ddr_perf_identifier_attr = 127 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL); 128 129 static struct attribute *ddr_perf_identifier_attrs[] = { 130 &ddr_perf_identifier_attr.attr, 131 NULL, 132 }; 133 134 static const struct attribute_group ddr_perf_identifier_attr_group = { 135 .attrs = ddr_perf_identifier_attrs, 136 .is_visible = ddr_perf_identifier_attr_visible, 137 }; 138 139 enum ddr_perf_filter_capabilities { 140 PERF_CAP_AXI_ID_FILTER = 0, 141 PERF_CAP_AXI_ID_FILTER_ENHANCED, 142 PERF_CAP_AXI_ID_FEAT_MAX, 143 }; 144 145 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) 146 { 147 u32 quirks = pmu->devtype_data->quirks; 148 149 switch (cap) { 150 case PERF_CAP_AXI_ID_FILTER: 151 return !!(quirks & DDR_CAP_AXI_ID_FILTER); 152 case PERF_CAP_AXI_ID_FILTER_ENHANCED: 153 quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED; 154 return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED; 155 default: 156 WARN(1, "unknown filter cap %d\n", cap); 157 } 158 159 return 0; 160 } 161 162 static ssize_t ddr_perf_filter_cap_show(struct device *dev, 163 struct device_attribute *attr, 164 char *buf) 165 { 166 struct ddr_pmu *pmu = dev_get_drvdata(dev); 167 struct dev_ext_attribute *ea = 168 container_of(attr, struct dev_ext_attribute, attr); 169 int cap = (long)ea->var; 170 171 return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap)); 172 } 173 174 #define PERF_EXT_ATTR_ENTRY(_name, _func, _var) \ 175 (&((struct dev_ext_attribute) { \ 176 __ATTR(_name, 0444, _func, NULL), (void *)_var \ 177 }).attr.attr) 178 179 #define PERF_FILTER_EXT_ATTR_ENTRY(_name, _var) \ 180 PERF_EXT_ATTR_ENTRY(_name, ddr_perf_filter_cap_show, _var) 181 182 static struct attribute *ddr_perf_filter_cap_attr[] = { 183 PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER), 184 PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED), 185 NULL, 186 }; 187 188 static const struct attribute_group ddr_perf_filter_cap_attr_group = { 189 .name = "caps", 190 .attrs = ddr_perf_filter_cap_attr, 191 }; 192 193 static ssize_t ddr_perf_cpumask_show(struct device *dev, 194 struct device_attribute *attr, char *buf) 195 { 196 struct ddr_pmu *pmu = dev_get_drvdata(dev); 197 198 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); 199 } 200 201 static struct device_attribute ddr_perf_cpumask_attr = 202 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL); 203 204 static struct attribute *ddr_perf_cpumask_attrs[] = { 205 &ddr_perf_cpumask_attr.attr, 206 NULL, 207 }; 208 209 static const struct attribute_group ddr_perf_cpumask_attr_group = { 210 .attrs = ddr_perf_cpumask_attrs, 211 }; 212 213 static ssize_t 214 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, 215 char *page) 216 { 217 struct perf_pmu_events_attr *pmu_attr; 218 219 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 220 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); 221 } 222 223 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \ 224 PMU_EVENT_ATTR_ID(_name, ddr_pmu_event_show, _id) 225 226 static struct attribute *ddr_perf_events_attrs[] = { 227 IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID), 228 IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01), 229 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04), 230 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05), 231 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08), 232 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09), 233 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10), 234 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11), 235 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12), 236 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20), 237 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21), 238 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22), 239 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23), 240 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24), 241 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25), 242 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26), 243 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27), 244 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29), 245 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a), 246 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b), 247 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30), 248 IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31), 249 IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32), 250 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33), 251 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34), 252 IMX8_DDR_PMU_EVENT_ATTR(read, 0x35), 253 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36), 254 IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37), 255 IMX8_DDR_PMU_EVENT_ATTR(write, 0x38), 256 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39), 257 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41), 258 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42), 259 NULL, 260 }; 261 262 static const struct attribute_group ddr_perf_events_attr_group = { 263 .name = "events", 264 .attrs = ddr_perf_events_attrs, 265 }; 266 267 PMU_FORMAT_ATTR(event, "config:0-7"); 268 PMU_FORMAT_ATTR(axi_id, "config1:0-15"); 269 PMU_FORMAT_ATTR(axi_mask, "config1:16-31"); 270 271 static struct attribute *ddr_perf_format_attrs[] = { 272 &format_attr_event.attr, 273 &format_attr_axi_id.attr, 274 &format_attr_axi_mask.attr, 275 NULL, 276 }; 277 278 static const struct attribute_group ddr_perf_format_attr_group = { 279 .name = "format", 280 .attrs = ddr_perf_format_attrs, 281 }; 282 283 static const struct attribute_group *attr_groups[] = { 284 &ddr_perf_events_attr_group, 285 &ddr_perf_format_attr_group, 286 &ddr_perf_cpumask_attr_group, 287 &ddr_perf_filter_cap_attr_group, 288 &ddr_perf_identifier_attr_group, 289 NULL, 290 }; 291 292 static bool ddr_perf_is_filtered(struct perf_event *event) 293 { 294 return event->attr.config == 0x41 || event->attr.config == 0x42; 295 } 296 297 static u32 ddr_perf_filter_val(struct perf_event *event) 298 { 299 return event->attr.config1; 300 } 301 302 static bool ddr_perf_filters_compatible(struct perf_event *a, 303 struct perf_event *b) 304 { 305 if (!ddr_perf_is_filtered(a)) 306 return true; 307 if (!ddr_perf_is_filtered(b)) 308 return true; 309 return ddr_perf_filter_val(a) == ddr_perf_filter_val(b); 310 } 311 312 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event) 313 { 314 unsigned int filt; 315 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 316 317 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED; 318 return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) && 319 ddr_perf_is_filtered(event); 320 } 321 322 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) 323 { 324 int i; 325 326 /* 327 * Always map cycle event to counter 0 328 * Cycles counter is dedicated for cycle event 329 * can't used for the other events 330 */ 331 if (event == EVENT_CYCLES_ID) { 332 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL) 333 return EVENT_CYCLES_COUNTER; 334 else 335 return -ENOENT; 336 } 337 338 for (i = 1; i < NUM_COUNTERS; i++) { 339 if (pmu->events[i] == NULL) 340 return i; 341 } 342 343 return -ENOENT; 344 } 345 346 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) 347 { 348 pmu->events[counter] = NULL; 349 } 350 351 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) 352 { 353 struct perf_event *event = pmu->events[counter]; 354 void __iomem *base = pmu->base; 355 356 /* 357 * return bytes instead of bursts from ddr transaction for 358 * axid-read and axid-write event if PMU core supports enhanced 359 * filter. 360 */ 361 base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 : 362 COUNTER_READ; 363 return readl_relaxed(base + counter * 4); 364 } 365 366 static int ddr_perf_event_init(struct perf_event *event) 367 { 368 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 369 struct hw_perf_event *hwc = &event->hw; 370 struct perf_event *sibling; 371 372 if (event->attr.type != event->pmu->type) 373 return -ENOENT; 374 375 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 376 return -EOPNOTSUPP; 377 378 if (event->cpu < 0) { 379 dev_warn(pmu->dev, "Can't provide per-task data!\n"); 380 return -EOPNOTSUPP; 381 } 382 383 /* 384 * We must NOT create groups containing mixed PMUs, although software 385 * events are acceptable (for example to create a CCN group 386 * periodically read when a hrtimer aka cpu-clock leader triggers). 387 */ 388 if (event->group_leader->pmu != event->pmu && 389 !is_software_event(event->group_leader)) 390 return -EINVAL; 391 392 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { 393 if (!ddr_perf_filters_compatible(event, event->group_leader)) 394 return -EINVAL; 395 for_each_sibling_event(sibling, event->group_leader) { 396 if (!ddr_perf_filters_compatible(event, sibling)) 397 return -EINVAL; 398 } 399 } 400 401 for_each_sibling_event(sibling, event->group_leader) { 402 if (sibling->pmu != event->pmu && 403 !is_software_event(sibling)) 404 return -EINVAL; 405 } 406 407 event->cpu = pmu->cpu; 408 hwc->idx = -1; 409 410 return 0; 411 } 412 413 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, 414 int counter, bool enable) 415 { 416 u8 reg = counter * 4 + COUNTER_CNTL; 417 int val; 418 419 if (enable) { 420 /* 421 * cycle counter is special which should firstly write 0 then 422 * write 1 into CLEAR bit to clear it. Other counters only 423 * need write 0 into CLEAR bit and it turns out to be 1 by 424 * hardware. Below enable flow is harmless for all counters. 425 */ 426 writel(0, pmu->base + reg); 427 val = CNTL_EN | CNTL_CLEAR; 428 val |= FIELD_PREP(CNTL_CSV_MASK, config); 429 writel(val, pmu->base + reg); 430 } else { 431 /* Disable counter */ 432 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; 433 writel(val, pmu->base + reg); 434 } 435 } 436 437 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) 438 { 439 int val; 440 441 val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); 442 443 return val & CNTL_OVER; 444 } 445 446 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter) 447 { 448 u8 reg = counter * 4 + COUNTER_CNTL; 449 int val; 450 451 val = readl_relaxed(pmu->base + reg); 452 val &= ~CNTL_CLEAR; 453 writel(val, pmu->base + reg); 454 455 val |= CNTL_CLEAR; 456 writel(val, pmu->base + reg); 457 } 458 459 static void ddr_perf_event_update(struct perf_event *event) 460 { 461 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 462 struct hw_perf_event *hwc = &event->hw; 463 u64 new_raw_count; 464 int counter = hwc->idx; 465 int ret; 466 467 new_raw_count = ddr_perf_read_counter(pmu, counter); 468 local64_add(new_raw_count, &event->count); 469 470 /* 471 * For legacy SoCs: event counter continue counting when overflow, 472 * no need to clear the counter. 473 * For new SoCs: event counter stop counting when overflow, need 474 * clear counter to let it count again. 475 */ 476 if (counter != EVENT_CYCLES_COUNTER) { 477 ret = ddr_perf_counter_overflow(pmu, counter); 478 if (ret) 479 dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n", 480 event->attr.config); 481 } 482 483 /* clear counter every time for both cycle counter and event counter */ 484 ddr_perf_counter_clear(pmu, counter); 485 } 486 487 static void ddr_perf_event_start(struct perf_event *event, int flags) 488 { 489 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 490 struct hw_perf_event *hwc = &event->hw; 491 int counter = hwc->idx; 492 493 local64_set(&hwc->prev_count, 0); 494 495 ddr_perf_counter_enable(pmu, event->attr.config, counter, true); 496 497 hwc->state = 0; 498 } 499 500 static int ddr_perf_event_add(struct perf_event *event, int flags) 501 { 502 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 503 struct hw_perf_event *hwc = &event->hw; 504 int counter; 505 int cfg = event->attr.config; 506 int cfg1 = event->attr.config1; 507 508 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { 509 int i; 510 511 for (i = 1; i < NUM_COUNTERS; i++) { 512 if (pmu->events[i] && 513 !ddr_perf_filters_compatible(event, pmu->events[i])) 514 return -EINVAL; 515 } 516 517 if (ddr_perf_is_filtered(event)) { 518 /* revert axi id masking(axi_mask) value */ 519 cfg1 ^= AXI_MASKING_REVERT; 520 writel(cfg1, pmu->base + COUNTER_DPCR1); 521 } 522 } 523 524 counter = ddr_perf_alloc_counter(pmu, cfg); 525 if (counter < 0) { 526 dev_dbg(pmu->dev, "There are not enough counters\n"); 527 return -EOPNOTSUPP; 528 } 529 530 pmu->events[counter] = event; 531 hwc->idx = counter; 532 533 hwc->state |= PERF_HES_STOPPED; 534 535 if (flags & PERF_EF_START) 536 ddr_perf_event_start(event, flags); 537 538 return 0; 539 } 540 541 static void ddr_perf_event_stop(struct perf_event *event, int flags) 542 { 543 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 544 struct hw_perf_event *hwc = &event->hw; 545 int counter = hwc->idx; 546 547 ddr_perf_counter_enable(pmu, event->attr.config, counter, false); 548 ddr_perf_event_update(event); 549 550 hwc->state |= PERF_HES_STOPPED; 551 } 552 553 static void ddr_perf_event_del(struct perf_event *event, int flags) 554 { 555 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 556 struct hw_perf_event *hwc = &event->hw; 557 int counter = hwc->idx; 558 559 ddr_perf_event_stop(event, PERF_EF_UPDATE); 560 561 ddr_perf_free_counter(pmu, counter); 562 hwc->idx = -1; 563 } 564 565 static void ddr_perf_pmu_enable(struct pmu *pmu) 566 { 567 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 568 569 /* enable cycle counter if cycle is not active event list */ 570 if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) 571 ddr_perf_counter_enable(ddr_pmu, 572 EVENT_CYCLES_ID, 573 EVENT_CYCLES_COUNTER, 574 true); 575 } 576 577 static void ddr_perf_pmu_disable(struct pmu *pmu) 578 { 579 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 580 581 if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) 582 ddr_perf_counter_enable(ddr_pmu, 583 EVENT_CYCLES_ID, 584 EVENT_CYCLES_COUNTER, 585 false); 586 } 587 588 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, 589 struct device *dev) 590 { 591 *pmu = (struct ddr_pmu) { 592 .pmu = (struct pmu) { 593 .module = THIS_MODULE, 594 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 595 .task_ctx_nr = perf_invalid_context, 596 .attr_groups = attr_groups, 597 .event_init = ddr_perf_event_init, 598 .add = ddr_perf_event_add, 599 .del = ddr_perf_event_del, 600 .start = ddr_perf_event_start, 601 .stop = ddr_perf_event_stop, 602 .read = ddr_perf_event_update, 603 .pmu_enable = ddr_perf_pmu_enable, 604 .pmu_disable = ddr_perf_pmu_disable, 605 }, 606 .base = base, 607 .dev = dev, 608 }; 609 610 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL); 611 return pmu->id; 612 } 613 614 static irqreturn_t ddr_perf_irq_handler(int irq, void *p) 615 { 616 int i; 617 struct ddr_pmu *pmu = (struct ddr_pmu *) p; 618 struct perf_event *event; 619 620 /* all counter will stop if cycle counter disabled */ 621 ddr_perf_counter_enable(pmu, 622 EVENT_CYCLES_ID, 623 EVENT_CYCLES_COUNTER, 624 false); 625 /* 626 * When the cycle counter overflows, all counters are stopped, 627 * and an IRQ is raised. If any other counter overflows, it 628 * continues counting, and no IRQ is raised. But for new SoCs, 629 * such as i.MX8MP, event counter would stop when overflow, so 630 * we need use cycle counter to stop overflow of event counter. 631 * 632 * Cycles occur at least 4 times as often as other events, so we 633 * can update all events on a cycle counter overflow and not 634 * lose events. 635 * 636 */ 637 for (i = 0; i < NUM_COUNTERS; i++) { 638 639 if (!pmu->events[i]) 640 continue; 641 642 event = pmu->events[i]; 643 644 ddr_perf_event_update(event); 645 } 646 647 ddr_perf_counter_enable(pmu, 648 EVENT_CYCLES_ID, 649 EVENT_CYCLES_COUNTER, 650 true); 651 652 return IRQ_HANDLED; 653 } 654 655 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) 656 { 657 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); 658 int target; 659 660 if (cpu != pmu->cpu) 661 return 0; 662 663 target = cpumask_any_but(cpu_online_mask, cpu); 664 if (target >= nr_cpu_ids) 665 return 0; 666 667 perf_pmu_migrate_context(&pmu->pmu, cpu, target); 668 pmu->cpu = target; 669 670 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); 671 672 return 0; 673 } 674 675 static int ddr_perf_probe(struct platform_device *pdev) 676 { 677 struct ddr_pmu *pmu; 678 struct device_node *np; 679 void __iomem *base; 680 char *name; 681 int num; 682 int ret; 683 int irq; 684 685 base = devm_platform_ioremap_resource(pdev, 0); 686 if (IS_ERR(base)) 687 return PTR_ERR(base); 688 689 np = pdev->dev.of_node; 690 691 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); 692 if (!pmu) 693 return -ENOMEM; 694 695 num = ddr_perf_init(pmu, base, &pdev->dev); 696 697 platform_set_drvdata(pdev, pmu); 698 699 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", 700 num); 701 if (!name) { 702 ret = -ENOMEM; 703 goto cpuhp_state_err; 704 } 705 706 pmu->devtype_data = of_device_get_match_data(&pdev->dev); 707 708 pmu->cpu = raw_smp_processor_id(); 709 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 710 DDR_CPUHP_CB_NAME, 711 NULL, 712 ddr_perf_offline_cpu); 713 714 if (ret < 0) { 715 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n"); 716 goto cpuhp_state_err; 717 } 718 719 pmu->cpuhp_state = ret; 720 721 /* Register the pmu instance for cpu hotplug */ 722 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); 723 if (ret) { 724 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); 725 goto cpuhp_instance_err; 726 } 727 728 /* Request irq */ 729 irq = of_irq_get(np, 0); 730 if (irq < 0) { 731 dev_err(&pdev->dev, "Failed to get irq: %d", irq); 732 ret = irq; 733 goto ddr_perf_err; 734 } 735 736 ret = devm_request_irq(&pdev->dev, irq, 737 ddr_perf_irq_handler, 738 IRQF_NOBALANCING | IRQF_NO_THREAD, 739 DDR_CPUHP_CB_NAME, 740 pmu); 741 if (ret < 0) { 742 dev_err(&pdev->dev, "Request irq failed: %d", ret); 743 goto ddr_perf_err; 744 } 745 746 pmu->irq = irq; 747 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); 748 if (ret) { 749 dev_err(pmu->dev, "Failed to set interrupt affinity!\n"); 750 goto ddr_perf_err; 751 } 752 753 ret = perf_pmu_register(&pmu->pmu, name, -1); 754 if (ret) 755 goto ddr_perf_err; 756 757 return 0; 758 759 ddr_perf_err: 760 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 761 cpuhp_instance_err: 762 cpuhp_remove_multi_state(pmu->cpuhp_state); 763 cpuhp_state_err: 764 ida_free(&ddr_ida, pmu->id); 765 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret); 766 return ret; 767 } 768 769 static int ddr_perf_remove(struct platform_device *pdev) 770 { 771 struct ddr_pmu *pmu = platform_get_drvdata(pdev); 772 773 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 774 cpuhp_remove_multi_state(pmu->cpuhp_state); 775 776 perf_pmu_unregister(&pmu->pmu); 777 778 ida_free(&ddr_ida, pmu->id); 779 return 0; 780 } 781 782 static struct platform_driver imx_ddr_pmu_driver = { 783 .driver = { 784 .name = "imx-ddr-pmu", 785 .of_match_table = imx_ddr_pmu_dt_ids, 786 .suppress_bind_attrs = true, 787 }, 788 .probe = ddr_perf_probe, 789 .remove = ddr_perf_remove, 790 }; 791 792 module_platform_driver(imx_ddr_pmu_driver); 793 MODULE_LICENSE("GPL v2"); 794