1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2016-2020 Arm Limited 3 // CMN-600 Coherent Mesh Network PMU driver 4 5 #include <linux/acpi.h> 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/sort.h> 20 21 /* Common register stuff */ 22 #define CMN_NODE_INFO 0x0000 23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0) 24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16) 25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32) 26 27 #define CMN_CHILD_INFO 0x0080 28 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0) 29 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16) 30 31 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) 32 #define CMN_CHILD_NODE_EXTERNAL BIT(31) 33 34 #define CMN_MAX_DIMENSION 12 35 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) 36 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) 37 38 /* Currently XPs are the node type we can have most of; others top out at 128 */ 39 #define CMN_MAX_NODES_PER_EVENT CMN_MAX_XPS 40 41 /* The CFG node has various info besides the discovery tree */ 42 #define CMN_CFGM_PERIPH_ID_01 0x0008 43 #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0) 44 #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32) 45 #define CMN_CFGM_PERIPH_ID_23 0x0010 46 #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4) 47 48 #define CMN_CFGM_INFO_GLOBAL 0x900 49 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63) 50 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52) 51 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50) 52 53 #define CMN_CFGM_INFO_GLOBAL_1 0x908 54 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2) 55 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0) 56 57 /* XPs also have some local topology info which has uses too */ 58 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p)) 59 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(4, 0) 60 61 #define CMN_MAX_PORTS 6 62 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10 63 64 /* PMU registers occupy the 3rd 4KB page of each node's region */ 65 #define CMN_PMU_OFFSET 0x2000 66 67 /* For most nodes, this is all there is */ 68 #define CMN_PMU_EVENT_SEL 0x000 69 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42) 70 #define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39) 71 #define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37) 72 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35) 73 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ 74 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32) 75 76 /* Some types are designed to coexist with another device in the same node */ 77 #define CMN_CCLA_PMU_EVENT_SEL 0x008 78 #define CMN_HNP_PMU_EVENT_SEL 0x008 79 80 /* DTMs live in the PMU space of XP registers */ 81 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18) 82 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00) 83 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19) 84 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17) 85 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9) 86 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8) 87 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6) 88 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5) 89 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4) 90 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1) 91 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0) 92 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08) 93 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10) 94 95 #define CMN_DTM_PMU_CONFIG 0x210 96 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32) 97 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00 98 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04 99 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10 100 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16) 101 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4) 102 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n)) 103 #define CMN__PMEVCNT23_COMBINED BIT(2) 104 #define CMN__PMEVCNT01_COMBINED BIT(1) 105 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0) 106 107 #define CMN_DTM_PMEVCNT 0x220 108 109 #define CMN_DTM_PMEVCNTSR 0x240 110 111 #define CMN650_DTM_UNIT_INFO 0x0910 112 #define CMN_DTM_UNIT_INFO 0x0960 113 #define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0) 114 115 #define CMN_DTM_NUM_COUNTERS 4 116 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ 117 #define CMN_DTM_OFFSET(n) ((n) * 0x200) 118 119 /* The DTC node is where the magic happens */ 120 #define CMN_DT_DTC_CTL 0x0a00 121 #define CMN_DT_DTC_CTL_DT_EN BIT(0) 122 123 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ 124 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4) 125 #define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n)) 126 #define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40) 127 128 #define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n)) 129 #define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90) 130 131 #define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100) 132 #define CMN_DT_PMCR_PMU_EN BIT(0) 133 #define CMN_DT_PMCR_CNTR_RST BIT(5) 134 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6) 135 136 #define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118) 137 #define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120) 138 139 #define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128) 140 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n) 141 142 #define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130) 143 #define CMN_DT_PMSRR_SS_REQ BIT(0) 144 145 #define CMN_DT_NUM_COUNTERS 8 146 #define CMN_MAX_DTCS 4 147 148 /* 149 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, 150 * so throwing away one bit to make overflow handling easy is no big deal. 151 */ 152 #define CMN_COUNTER_INIT 0x80000000 153 /* Similarly for the 40-bit cycle counter */ 154 #define CMN_CC_INIT 0x8000000000ULL 155 156 157 /* Event attributes */ 158 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0) 159 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16) 160 #define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27) 161 #define CMN_CONFIG_BYNODEID BIT_ULL(31) 162 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32) 163 164 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config) 165 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config) 166 #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config) 167 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config) 168 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config) 169 170 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27) 171 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48) 172 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51) 173 /* Note that we don't yet support the tertiary match group on newer IPs */ 174 #define CMN_CONFIG_WP_GRP BIT_ULL(56) 175 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57) 176 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0) 177 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0) 178 179 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config) 180 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config) 181 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config) 182 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config) 183 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config) 184 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1) 185 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2) 186 187 /* Made-up event IDs for watchpoint direction */ 188 #define CMN_WP_UP 0 189 #define CMN_WP_DOWN 2 190 191 192 /* Internal values for encoding event support */ 193 enum cmn_model { 194 CMN600 = 1, 195 CMN650 = 2, 196 CMN700 = 4, 197 CI700 = 8, 198 /* ...and then we can use bitmap tricks for commonality */ 199 CMN_ANY = -1, 200 NOT_CMN600 = -2, 201 CMN_650ON = CMN650 | CMN700, 202 }; 203 204 /* Actual part numbers and revision IDs defined by the hardware */ 205 enum cmn_part { 206 PART_CMN600 = 0x434, 207 PART_CMN650 = 0x436, 208 PART_CMN700 = 0x43c, 209 PART_CI700 = 0x43a, 210 }; 211 212 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ 213 enum cmn_revision { 214 REV_CMN600_R1P0, 215 REV_CMN600_R1P1, 216 REV_CMN600_R1P2, 217 REV_CMN600_R1P3, 218 REV_CMN600_R2P0, 219 REV_CMN600_R3P0, 220 REV_CMN600_R3P1, 221 REV_CMN650_R0P0 = 0, 222 REV_CMN650_R1P0, 223 REV_CMN650_R1P1, 224 REV_CMN650_R2P0, 225 REV_CMN650_R1P2, 226 REV_CMN700_R0P0 = 0, 227 REV_CMN700_R1P0, 228 REV_CMN700_R2P0, 229 REV_CMN700_R3P0, 230 REV_CI700_R0P0 = 0, 231 REV_CI700_R1P0, 232 REV_CI700_R2P0, 233 }; 234 235 enum cmn_node_type { 236 CMN_TYPE_INVALID, 237 CMN_TYPE_DVM, 238 CMN_TYPE_CFG, 239 CMN_TYPE_DTC, 240 CMN_TYPE_HNI, 241 CMN_TYPE_HNF, 242 CMN_TYPE_XP, 243 CMN_TYPE_SBSX, 244 CMN_TYPE_MPAM_S, 245 CMN_TYPE_MPAM_NS, 246 CMN_TYPE_RNI, 247 CMN_TYPE_RND = 0xd, 248 CMN_TYPE_RNSAM = 0xf, 249 CMN_TYPE_MTSX, 250 CMN_TYPE_HNP, 251 CMN_TYPE_CXRA = 0x100, 252 CMN_TYPE_CXHA, 253 CMN_TYPE_CXLA, 254 CMN_TYPE_CCRA, 255 CMN_TYPE_CCHA, 256 CMN_TYPE_CCLA, 257 CMN_TYPE_CCLA_RNI, 258 CMN_TYPE_HNS = 0x200, 259 CMN_TYPE_HNS_MPAM_S, 260 CMN_TYPE_HNS_MPAM_NS, 261 /* Not a real node type */ 262 CMN_TYPE_WP = 0x7770 263 }; 264 265 enum cmn_filter_select { 266 SEL_NONE = -1, 267 SEL_OCCUP1ID, 268 SEL_CLASS_OCCUP_ID, 269 SEL_CBUSY_SNTHROTTLE_SEL, 270 SEL_HBT_LBT_SEL, 271 SEL_SN_HOME_SEL, 272 SEL_MAX 273 }; 274 275 struct arm_cmn_node { 276 void __iomem *pmu_base; 277 u16 id, logid; 278 enum cmn_node_type type; 279 280 /* XP properties really, but replicated to children for convenience */ 281 u8 dtm; 282 s8 dtc; 283 u8 portid_bits:4; 284 u8 deviceid_bits:4; 285 /* DN/HN-F/CXHA */ 286 struct { 287 u8 val : 4; 288 u8 count : 4; 289 } occupid[SEL_MAX]; 290 union { 291 u8 event[4]; 292 __le32 event_sel; 293 u16 event_w[4]; 294 __le64 event_sel_w; 295 }; 296 }; 297 298 struct arm_cmn_dtm { 299 void __iomem *base; 300 u32 pmu_config_low; 301 union { 302 u8 input_sel[4]; 303 __le32 pmu_config_high; 304 }; 305 s8 wp_event[4]; 306 }; 307 308 struct arm_cmn_dtc { 309 void __iomem *base; 310 int irq; 311 int irq_friend; 312 bool cc_active; 313 314 struct perf_event *counters[CMN_DT_NUM_COUNTERS]; 315 struct perf_event *cycles; 316 }; 317 318 #define CMN_STATE_DISABLED BIT(0) 319 #define CMN_STATE_TXN BIT(1) 320 321 struct arm_cmn { 322 struct device *dev; 323 void __iomem *base; 324 unsigned int state; 325 326 enum cmn_revision rev; 327 enum cmn_part part; 328 u8 mesh_x; 329 u8 mesh_y; 330 u16 num_xps; 331 u16 num_dns; 332 bool multi_dtm; 333 u8 ports_used; 334 struct { 335 unsigned int rsp_vc_num : 2; 336 unsigned int dat_vc_num : 2; 337 unsigned int snp_vc_num : 2; 338 unsigned int req_vc_num : 2; 339 }; 340 341 struct arm_cmn_node *xps; 342 struct arm_cmn_node *dns; 343 344 struct arm_cmn_dtm *dtms; 345 struct arm_cmn_dtc *dtc; 346 unsigned int num_dtcs; 347 348 int cpu; 349 struct hlist_node cpuhp_node; 350 351 struct pmu pmu; 352 struct dentry *debug; 353 }; 354 355 #define to_cmn(p) container_of(p, struct arm_cmn, pmu) 356 357 static int arm_cmn_hp_state; 358 359 struct arm_cmn_nodeid { 360 u8 port; 361 u8 dev; 362 }; 363 364 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) 365 { 366 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1)); 367 } 368 369 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn_node *dn) 370 { 371 struct arm_cmn_nodeid nid; 372 373 nid.dev = dn->id & ((1U << dn->deviceid_bits) - 1); 374 nid.port = (dn->id >> dn->deviceid_bits) & ((1U << dn->portid_bits) - 1); 375 return nid; 376 } 377 378 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, 379 const struct arm_cmn_node *dn) 380 { 381 int id = dn->id >> (dn->portid_bits + dn->deviceid_bits); 382 int bits = arm_cmn_xyidbits(cmn); 383 int x = id >> bits; 384 int y = id & ((1U << bits) - 1); 385 386 return cmn->xps + cmn->mesh_x * y + x; 387 } 388 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, 389 enum cmn_node_type type) 390 { 391 struct arm_cmn_node *dn; 392 393 for (dn = cmn->dns; dn->type; dn++) 394 if (dn->type == type) 395 return dn; 396 return NULL; 397 } 398 399 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn) 400 { 401 switch (cmn->part) { 402 case PART_CMN600: 403 return CMN600; 404 case PART_CMN650: 405 return CMN650; 406 case PART_CMN700: 407 return CMN700; 408 case PART_CI700: 409 return CI700; 410 default: 411 return 0; 412 }; 413 } 414 415 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn, 416 const struct arm_cmn_node *xp, int port) 417 { 418 int offset = CMN_MXP__CONNECT_INFO(port); 419 420 if (port >= 2) { 421 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650) 422 return 0; 423 /* 424 * CI-700 may have extra ports, but still has the 425 * mesh_port_connect_info registers in the way. 426 */ 427 if (cmn->part == PART_CI700) 428 offset += CI700_CONNECT_INFO_P2_5_OFFSET; 429 } 430 431 return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset); 432 } 433 434 static struct dentry *arm_cmn_debugfs; 435 436 #ifdef CONFIG_DEBUG_FS 437 static const char *arm_cmn_device_type(u8 type) 438 { 439 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) { 440 case 0x00: return " |"; 441 case 0x01: return " RN-I |"; 442 case 0x02: return " RN-D |"; 443 case 0x04: return " RN-F_B |"; 444 case 0x05: return "RN-F_B_E|"; 445 case 0x06: return " RN-F_A |"; 446 case 0x07: return "RN-F_A_E|"; 447 case 0x08: return " HN-T |"; 448 case 0x09: return " HN-I |"; 449 case 0x0a: return " HN-D |"; 450 case 0x0b: return " HN-P |"; 451 case 0x0c: return " SN-F |"; 452 case 0x0d: return " SBSX |"; 453 case 0x0e: return " HN-F |"; 454 case 0x0f: return " SN-F_E |"; 455 case 0x10: return " SN-F_D |"; 456 case 0x11: return " CXHA |"; 457 case 0x12: return " CXRA |"; 458 case 0x13: return " CXRH |"; 459 case 0x14: return " RN-F_D |"; 460 case 0x15: return "RN-F_D_E|"; 461 case 0x16: return " RN-F_C |"; 462 case 0x17: return "RN-F_C_E|"; 463 case 0x18: return " RN-F_E |"; 464 case 0x19: return "RN-F_E_E|"; 465 case 0x1c: return " MTSX |"; 466 case 0x1d: return " HN-V |"; 467 case 0x1e: return " CCG |"; 468 default: return " ???? |"; 469 } 470 } 471 472 static void arm_cmn_show_logid(struct seq_file *s, const struct arm_cmn_node *xp, int p, int d) 473 { 474 struct arm_cmn *cmn = s->private; 475 struct arm_cmn_node *dn; 476 u16 id = xp->id | d | (p << xp->deviceid_bits); 477 478 for (dn = cmn->dns; dn->type; dn++) { 479 int pad = dn->logid < 10; 480 481 if (dn->type == CMN_TYPE_XP) 482 continue; 483 /* Ignore the extra components that will overlap on some ports */ 484 if (dn->type < CMN_TYPE_HNI) 485 continue; 486 487 if (dn->id != id) 488 continue; 489 490 seq_printf(s, " %*c#%-*d |", pad + 1, ' ', 3 - pad, dn->logid); 491 return; 492 } 493 seq_puts(s, " |"); 494 } 495 496 static int arm_cmn_map_show(struct seq_file *s, void *data) 497 { 498 struct arm_cmn *cmn = s->private; 499 int x, y, p, pmax = fls(cmn->ports_used); 500 501 seq_puts(s, " X"); 502 for (x = 0; x < cmn->mesh_x; x++) 503 seq_printf(s, " %-2d ", x); 504 seq_puts(s, "\nY P D+"); 505 y = cmn->mesh_y; 506 while (y--) { 507 int xp_base = cmn->mesh_x * y; 508 struct arm_cmn_node *xp = cmn->xps + xp_base; 509 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION]; 510 511 for (x = 0; x < cmn->mesh_x; x++) 512 seq_puts(s, "--------+"); 513 514 seq_printf(s, "\n%-2d |", y); 515 for (x = 0; x < cmn->mesh_x; x++) { 516 for (p = 0; p < CMN_MAX_PORTS; p++) 517 port[p][x] = arm_cmn_device_connect_info(cmn, xp + x, p); 518 seq_printf(s, " XP #%-3d|", xp_base + x); 519 } 520 521 seq_puts(s, "\n |"); 522 for (x = 0; x < cmn->mesh_x; x++) { 523 s8 dtc = xp[x].dtc; 524 525 if (dtc < 0) 526 seq_puts(s, " DTC ?? |"); 527 else 528 seq_printf(s, " DTC %d |", dtc); 529 } 530 seq_puts(s, "\n |"); 531 for (x = 0; x < cmn->mesh_x; x++) 532 seq_puts(s, "........|"); 533 534 for (p = 0; p < pmax; p++) { 535 seq_printf(s, "\n %d |", p); 536 for (x = 0; x < cmn->mesh_x; x++) 537 seq_puts(s, arm_cmn_device_type(port[p][x])); 538 seq_puts(s, "\n 0|"); 539 for (x = 0; x < cmn->mesh_x; x++) 540 arm_cmn_show_logid(s, xp + x, p, 0); 541 seq_puts(s, "\n 1|"); 542 for (x = 0; x < cmn->mesh_x; x++) 543 arm_cmn_show_logid(s, xp + x, p, 1); 544 } 545 seq_puts(s, "\n-----+"); 546 } 547 for (x = 0; x < cmn->mesh_x; x++) 548 seq_puts(s, "--------+"); 549 seq_puts(s, "\n"); 550 return 0; 551 } 552 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map); 553 554 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) 555 { 556 const char *name = "map"; 557 558 if (id > 0) 559 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id); 560 if (!name) 561 return; 562 563 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops); 564 } 565 #else 566 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {} 567 #endif 568 569 struct arm_cmn_hw_event { 570 struct arm_cmn_node *dn; 571 u64 dtm_idx[DIV_ROUND_UP(CMN_MAX_NODES_PER_EVENT * 2, 64)]; 572 s8 dtc_idx[CMN_MAX_DTCS]; 573 u8 num_dns; 574 u8 dtm_offset; 575 bool wide_sel; 576 enum cmn_filter_select filter_sel; 577 }; 578 579 #define for_each_hw_dn(hw, dn, i) \ 580 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++) 581 582 /* @i is the DTC number, @idx is the counter index on that DTC */ 583 #define for_each_hw_dtc_idx(hw, i, idx) \ 584 for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0) 585 586 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event) 587 { 588 BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target)); 589 return (struct arm_cmn_hw_event *)&event->hw; 590 } 591 592 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val) 593 { 594 x[pos / 32] |= (u64)val << ((pos % 32) * 2); 595 } 596 597 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) 598 { 599 return (x[pos / 32] >> ((pos % 32) * 2)) & 3; 600 } 601 602 struct arm_cmn_event_attr { 603 struct device_attribute attr; 604 enum cmn_model model; 605 enum cmn_node_type type; 606 enum cmn_filter_select fsel; 607 u16 eventid; 608 u8 occupid; 609 }; 610 611 struct arm_cmn_format_attr { 612 struct device_attribute attr; 613 u64 field; 614 int config; 615 }; 616 617 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\ 618 (&((struct arm_cmn_event_attr[]) {{ \ 619 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \ 620 .model = _model, \ 621 .type = _type, \ 622 .eventid = _eventid, \ 623 .occupid = _occupid, \ 624 .fsel = _fsel, \ 625 }})[0].attr.attr) 626 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \ 627 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE) 628 629 static ssize_t arm_cmn_event_show(struct device *dev, 630 struct device_attribute *attr, char *buf) 631 { 632 struct arm_cmn_event_attr *eattr; 633 634 eattr = container_of(attr, typeof(*eattr), attr); 635 636 if (eattr->type == CMN_TYPE_DTC) 637 return sysfs_emit(buf, "type=0x%x\n", eattr->type); 638 639 if (eattr->type == CMN_TYPE_WP) 640 return sysfs_emit(buf, 641 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n", 642 eattr->type, eattr->eventid); 643 644 if (eattr->fsel > SEL_NONE) 645 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n", 646 eattr->type, eattr->eventid, eattr->occupid); 647 648 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type, 649 eattr->eventid); 650 } 651 652 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj, 653 struct attribute *attr, 654 int unused) 655 { 656 struct device *dev = kobj_to_dev(kobj); 657 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 658 struct arm_cmn_event_attr *eattr; 659 enum cmn_node_type type; 660 u16 eventid; 661 662 eattr = container_of(attr, typeof(*eattr), attr.attr); 663 664 if (!(eattr->model & arm_cmn_model(cmn))) 665 return 0; 666 667 type = eattr->type; 668 eventid = eattr->eventid; 669 670 /* Watchpoints aren't nodes, so avoid confusion */ 671 if (type == CMN_TYPE_WP) 672 return attr->mode; 673 674 /* Hide XP events for unused interfaces/channels */ 675 if (type == CMN_TYPE_XP) { 676 unsigned int intf = (eventid >> 2) & 7; 677 unsigned int chan = eventid >> 5; 678 679 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3))) 680 return 0; 681 682 if (chan == 4 && cmn->part == PART_CMN600) 683 return 0; 684 685 if ((chan == 5 && cmn->rsp_vc_num < 2) || 686 (chan == 6 && cmn->dat_vc_num < 2) || 687 (chan == 7 && cmn->snp_vc_num < 2) || 688 (chan == 8 && cmn->req_vc_num < 2)) 689 return 0; 690 } 691 692 /* Revision-specific differences */ 693 if (cmn->part == PART_CMN600) { 694 if (cmn->rev < REV_CMN600_R1P3) { 695 if (type == CMN_TYPE_CXRA && eventid > 0x10) 696 return 0; 697 } 698 if (cmn->rev < REV_CMN600_R1P2) { 699 if (type == CMN_TYPE_HNF && eventid == 0x1b) 700 return 0; 701 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA) 702 return 0; 703 } 704 } else if (cmn->part == PART_CMN650) { 705 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) { 706 if (type == CMN_TYPE_HNF && eventid > 0x22) 707 return 0; 708 if (type == CMN_TYPE_SBSX && eventid == 0x17) 709 return 0; 710 if (type == CMN_TYPE_RNI && eventid > 0x10) 711 return 0; 712 } 713 } else if (cmn->part == PART_CMN700) { 714 if (cmn->rev < REV_CMN700_R2P0) { 715 if (type == CMN_TYPE_HNF && eventid > 0x2c) 716 return 0; 717 if (type == CMN_TYPE_CCHA && eventid > 0x74) 718 return 0; 719 if (type == CMN_TYPE_CCLA && eventid > 0x27) 720 return 0; 721 } 722 if (cmn->rev < REV_CMN700_R1P0) { 723 if (type == CMN_TYPE_HNF && eventid > 0x2b) 724 return 0; 725 } 726 } 727 728 if (!arm_cmn_node(cmn, type)) 729 return 0; 730 731 return attr->mode; 732 } 733 734 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \ 735 _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel) 736 #define CMN_EVENT_DTC(_name) \ 737 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0) 738 #define CMN_EVENT_HNF(_model, _name, _event) \ 739 CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event) 740 #define CMN_EVENT_HNI(_name, _event) \ 741 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event) 742 #define CMN_EVENT_HNP(_name, _event) \ 743 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event) 744 #define __CMN_EVENT_XP(_name, _event) \ 745 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event) 746 #define CMN_EVENT_SBSX(_model, _name, _event) \ 747 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event) 748 #define CMN_EVENT_RNID(_model, _name, _event) \ 749 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event) 750 #define CMN_EVENT_MTSX(_name, _event) \ 751 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event) 752 #define CMN_EVENT_CXRA(_model, _name, _event) \ 753 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event) 754 #define CMN_EVENT_CXHA(_name, _event) \ 755 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event) 756 #define CMN_EVENT_CCRA(_name, _event) \ 757 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event) 758 #define CMN_EVENT_CCHA(_name, _event) \ 759 CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event) 760 #define CMN_EVENT_CCLA(_name, _event) \ 761 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event) 762 #define CMN_EVENT_CCLA_RNI(_name, _event) \ 763 CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event) 764 #define CMN_EVENT_HNS(_name, _event) \ 765 CMN_EVENT_ATTR(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 766 767 #define CMN_EVENT_DVM(_model, _name, _event) \ 768 _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE) 769 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \ 770 _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \ 771 _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \ 772 _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID) 773 774 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \ 775 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_OCCUP1ID), \ 776 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 1, SEL_OCCUP1ID), \ 777 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 2, SEL_OCCUP1ID), \ 778 _CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, 3, SEL_OCCUP1ID), \ 779 _CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, 4, SEL_OCCUP1ID) 780 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \ 781 _CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, 0, SEL_CLASS_OCCUP_ID), \ 782 _CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, 1, SEL_CLASS_OCCUP_ID), \ 783 _CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, 2, SEL_CLASS_OCCUP_ID), \ 784 _CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, 3, SEL_CLASS_OCCUP_ID) 785 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \ 786 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \ 787 _CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \ 788 _CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \ 789 _CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \ 790 _CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \ 791 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \ 792 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL) 793 794 #define CMN_EVENT_HNF_OCC(_model, _name, _event) \ 795 CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event) 796 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \ 797 CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event) 798 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \ 799 CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event) 800 801 #define CMN_EVENT_HNS_OCC(_name, _event) \ 802 CMN_EVENT_HN_OCC(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event), \ 803 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_rxsnp, CMN_TYPE_HNS, _event, 5, SEL_OCCUP1ID), \ 804 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 6, SEL_OCCUP1ID), \ 805 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 7, SEL_OCCUP1ID) 806 #define CMN_EVENT_HNS_CLS( _name, _event) \ 807 CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 808 #define CMN_EVENT_HNS_SNT(_name, _event) \ 809 CMN_EVENT_HN_SNT(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event) 810 #define CMN_EVENT_HNS_HBT(_name, _event) \ 811 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_HBT_LBT_SEL), \ 812 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 1, SEL_HBT_LBT_SEL), \ 813 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 2, SEL_HBT_LBT_SEL) 814 #define CMN_EVENT_HNS_SNH(_name, _event) \ 815 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_SN_HOME_SEL), \ 816 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_sn, CMN_TYPE_HNS, _event, 1, SEL_SN_HOME_SEL), \ 817 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_home, CMN_TYPE_HNS, _event, 2, SEL_SN_HOME_SEL) 818 819 #define _CMN_EVENT_XP_MESH(_name, _event) \ 820 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \ 821 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \ 822 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \ 823 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)) 824 825 #define _CMN_EVENT_XP_PORT(_name, _event) \ 826 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \ 827 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \ 828 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \ 829 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2)) 830 831 #define _CMN_EVENT_XP(_name, _event) \ 832 _CMN_EVENT_XP_MESH(_name, _event), \ 833 _CMN_EVENT_XP_PORT(_name, _event) 834 835 /* Good thing there are only 3 fundamental XP events... */ 836 #define CMN_EVENT_XP(_name, _event) \ 837 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \ 838 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \ 839 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \ 840 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \ 841 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \ 842 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \ 843 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \ 844 _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)), \ 845 _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5)) 846 847 #define CMN_EVENT_XP_DAT(_name, _event) \ 848 _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)), \ 849 _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5)) 850 851 852 static struct attribute *arm_cmn_event_attrs[] = { 853 CMN_EVENT_DTC(cycles), 854 855 /* 856 * DVM node events conflict with HN-I events in the equivalent PMU 857 * slot, but our lazy short-cut of using the DTM counter index for 858 * the PMU index as well happens to avoid that by construction. 859 */ 860 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01), 861 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02), 862 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03), 863 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04), 864 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05), 865 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01), 866 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02), 867 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03), 868 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04), 869 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05), 870 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06), 871 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07), 872 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08), 873 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09), 874 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a), 875 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b), 876 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c), 877 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha, 0x0d), 878 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn, 0x0e), 879 CMN_EVENT_DVM(CMN700, trk_alloc, 0x0f), 880 CMN_EVENT_DVM(CMN700, trk_cxha_alloc, 0x10), 881 CMN_EVENT_DVM(CMN700, trk_pdn_alloc, 0x11), 882 CMN_EVENT_DVM(CMN700, txsnp_stall_limit, 0x12), 883 CMN_EVENT_DVM(CMN700, rxsnp_stall_starv, 0x13), 884 CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op, 0x14), 885 886 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01), 887 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02), 888 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03), 889 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04), 890 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05), 891 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06), 892 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07), 893 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08), 894 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09), 895 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a), 896 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b), 897 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c), 898 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d), 899 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e), 900 CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f), 901 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10), 902 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11), 903 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12), 904 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13), 905 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14), 906 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15), 907 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16), 908 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17), 909 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18), 910 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19), 911 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a), 912 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b), 913 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c), 914 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d), 915 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e), 916 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f), 917 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20), 918 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21), 919 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22), 920 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23), 921 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24), 922 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25), 923 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26), 924 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27), 925 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28), 926 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29), 927 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a), 928 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b), 929 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c), 930 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d), 931 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e), 932 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f), 933 934 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20), 935 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21), 936 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22), 937 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23), 938 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24), 939 CMN_EVENT_HNI(rrt_rd_alloc, 0x25), 940 CMN_EVENT_HNI(rrt_wr_alloc, 0x26), 941 CMN_EVENT_HNI(rdt_rd_alloc, 0x27), 942 CMN_EVENT_HNI(rdt_wr_alloc, 0x28), 943 CMN_EVENT_HNI(wdb_alloc, 0x29), 944 CMN_EVENT_HNI(txrsp_retryack, 0x2a), 945 CMN_EVENT_HNI(arvalid_no_arready, 0x2b), 946 CMN_EVENT_HNI(arready_no_arvalid, 0x2c), 947 CMN_EVENT_HNI(awvalid_no_awready, 0x2d), 948 CMN_EVENT_HNI(awready_no_awvalid, 0x2e), 949 CMN_EVENT_HNI(wvalid_no_wready, 0x2f), 950 CMN_EVENT_HNI(txdat_stall, 0x30), 951 CMN_EVENT_HNI(nonpcie_serialization, 0x31), 952 CMN_EVENT_HNI(pcie_serialization, 0x32), 953 954 /* 955 * HN-P events squat on top of the HN-I similarly to DVM events, except 956 * for being crammed into the same physical node as well. And of course 957 * where would the fun be if the same events were in the same order... 958 */ 959 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01), 960 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02), 961 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03), 962 CMN_EVENT_HNP(rrt_wr_alloc, 0x04), 963 CMN_EVENT_HNP(rdt_wr_alloc, 0x05), 964 CMN_EVENT_HNP(wdb_alloc, 0x06), 965 CMN_EVENT_HNP(awvalid_no_awready, 0x07), 966 CMN_EVENT_HNP(awready_no_awvalid, 0x08), 967 CMN_EVENT_HNP(wvalid_no_wready, 0x09), 968 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11), 969 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12), 970 CMN_EVENT_HNP(rrt_rd_alloc, 0x13), 971 CMN_EVENT_HNP(rdt_rd_alloc, 0x14), 972 CMN_EVENT_HNP(arvalid_no_arready, 0x15), 973 CMN_EVENT_HNP(arready_no_arvalid, 0x16), 974 975 CMN_EVENT_XP(txflit_valid, 0x01), 976 CMN_EVENT_XP(txflit_stall, 0x02), 977 CMN_EVENT_XP_DAT(partial_dat_flit, 0x03), 978 /* We treat watchpoints as a special made-up class of XP events */ 979 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP), 980 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN), 981 982 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01), 983 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02), 984 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03), 985 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04), 986 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05), 987 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06), 988 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11), 989 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12), 990 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13), 991 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14), 992 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15), 993 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16), 994 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17), 995 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21), 996 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22), 997 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23), 998 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24), 999 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25), 1000 1001 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01), 1002 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02), 1003 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03), 1004 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04), 1005 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05), 1006 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06), 1007 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07), 1008 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08), 1009 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09), 1010 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a), 1011 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b), 1012 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c), 1013 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d), 1014 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e), 1015 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f), 1016 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10), 1017 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11), 1018 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12), 1019 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13), 1020 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14), 1021 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11), 1022 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12), 1023 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13), 1024 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14), 1025 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15), 1026 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16), 1027 CMN_EVENT_RNID(CMN700, ldb_full, 0x17), 1028 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18), 1029 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19), 1030 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a), 1031 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b), 1032 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c), 1033 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d), 1034 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e), 1035 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f), 1036 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20), 1037 CMN_EVENT_RNID(CMN700, awid_hash, 0x21), 1038 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22), 1039 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23), 1040 1041 CMN_EVENT_MTSX(tc_lookup, 0x01), 1042 CMN_EVENT_MTSX(tc_fill, 0x02), 1043 CMN_EVENT_MTSX(tc_miss, 0x03), 1044 CMN_EVENT_MTSX(tdb_forward, 0x04), 1045 CMN_EVENT_MTSX(tcq_hazard, 0x05), 1046 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06), 1047 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07), 1048 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08), 1049 CMN_EVENT_MTSX(axi_rd_req, 0x09), 1050 CMN_EVENT_MTSX(axi_wr_req, 0x0a), 1051 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b), 1052 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c), 1053 1054 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01), 1055 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02), 1056 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03), 1057 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04), 1058 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05), 1059 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06), 1060 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07), 1061 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08), 1062 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09), 1063 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a), 1064 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b), 1065 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c), 1066 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d), 1067 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e), 1068 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f), 1069 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10), 1070 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11), 1071 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12), 1072 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13), 1073 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14), 1074 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15), 1075 1076 CMN_EVENT_CXHA(rddatbyp, 0x21), 1077 CMN_EVENT_CXHA(chirsp_up_stall, 0x22), 1078 CMN_EVENT_CXHA(chidat_up_stall, 0x23), 1079 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24), 1080 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25), 1081 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26), 1082 CMN_EVENT_CXHA(reqtrk_occ, 0x27), 1083 CMN_EVENT_CXHA(rdb_occ, 0x28), 1084 CMN_EVENT_CXHA(rdbyp_occ, 0x29), 1085 CMN_EVENT_CXHA(wdb_occ, 0x2a), 1086 CMN_EVENT_CXHA(snptrk_occ, 0x2b), 1087 CMN_EVENT_CXHA(sdb_occ, 0x2c), 1088 CMN_EVENT_CXHA(snphaz_occ, 0x2d), 1089 1090 CMN_EVENT_CCRA(rht_occ, 0x41), 1091 CMN_EVENT_CCRA(sht_occ, 0x42), 1092 CMN_EVENT_CCRA(rdb_occ, 0x43), 1093 CMN_EVENT_CCRA(wdb_occ, 0x44), 1094 CMN_EVENT_CCRA(ssb_occ, 0x45), 1095 CMN_EVENT_CCRA(snp_bcasts, 0x46), 1096 CMN_EVENT_CCRA(req_chains, 0x47), 1097 CMN_EVENT_CCRA(req_chain_avglen, 0x48), 1098 CMN_EVENT_CCRA(chirsp_stalls, 0x49), 1099 CMN_EVENT_CCRA(chidat_stalls, 0x4a), 1100 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b), 1101 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c), 1102 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d), 1103 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e), 1104 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f), 1105 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50), 1106 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51), 1107 CMN_EVENT_CCRA(external_chidat_stalls, 0x52), 1108 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53), 1109 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54), 1110 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55), 1111 CMN_EVENT_CCRA(rht_alloc, 0x56), 1112 CMN_EVENT_CCRA(sht_alloc, 0x57), 1113 CMN_EVENT_CCRA(rdb_alloc, 0x58), 1114 CMN_EVENT_CCRA(wdb_alloc, 0x59), 1115 CMN_EVENT_CCRA(ssb_alloc, 0x5a), 1116 1117 CMN_EVENT_CCHA(rddatbyp, 0x61), 1118 CMN_EVENT_CCHA(chirsp_up_stall, 0x62), 1119 CMN_EVENT_CCHA(chidat_up_stall, 0x63), 1120 CMN_EVENT_CCHA(snppcrd_link0_stall, 0x64), 1121 CMN_EVENT_CCHA(snppcrd_link1_stall, 0x65), 1122 CMN_EVENT_CCHA(snppcrd_link2_stall, 0x66), 1123 CMN_EVENT_CCHA(reqtrk_occ, 0x67), 1124 CMN_EVENT_CCHA(rdb_occ, 0x68), 1125 CMN_EVENT_CCHA(rdbyp_occ, 0x69), 1126 CMN_EVENT_CCHA(wdb_occ, 0x6a), 1127 CMN_EVENT_CCHA(snptrk_occ, 0x6b), 1128 CMN_EVENT_CCHA(sdb_occ, 0x6c), 1129 CMN_EVENT_CCHA(snphaz_occ, 0x6d), 1130 CMN_EVENT_CCHA(reqtrk_alloc, 0x6e), 1131 CMN_EVENT_CCHA(rdb_alloc, 0x6f), 1132 CMN_EVENT_CCHA(rdbyp_alloc, 0x70), 1133 CMN_EVENT_CCHA(wdb_alloc, 0x71), 1134 CMN_EVENT_CCHA(snptrk_alloc, 0x72), 1135 CMN_EVENT_CCHA(sdb_alloc, 0x73), 1136 CMN_EVENT_CCHA(snphaz_alloc, 0x74), 1137 CMN_EVENT_CCHA(pb_rhu_req_occ, 0x75), 1138 CMN_EVENT_CCHA(pb_rhu_req_alloc, 0x76), 1139 CMN_EVENT_CCHA(pb_rhu_pcie_req_occ, 0x77), 1140 CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc, 0x78), 1141 CMN_EVENT_CCHA(pb_pcie_wr_req_occ, 0x79), 1142 CMN_EVENT_CCHA(pb_pcie_wr_req_alloc, 0x7a), 1143 CMN_EVENT_CCHA(pb_pcie_reg_req_occ, 0x7b), 1144 CMN_EVENT_CCHA(pb_pcie_reg_req_alloc, 0x7c), 1145 CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ, 0x7d), 1146 CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc, 0x7e), 1147 CMN_EVENT_CCHA(pb_rhu_dat_occ, 0x7f), 1148 CMN_EVENT_CCHA(pb_rhu_dat_alloc, 0x80), 1149 CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ, 0x81), 1150 CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc, 0x82), 1151 CMN_EVENT_CCHA(pb_pcie_wr_dat_occ, 0x83), 1152 CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc, 0x84), 1153 1154 CMN_EVENT_CCLA(rx_cxs, 0x21), 1155 CMN_EVENT_CCLA(tx_cxs, 0x22), 1156 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23), 1157 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24), 1158 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25), 1159 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26), 1160 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27), 1161 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28), 1162 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29), 1163 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a), 1164 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b), 1165 1166 CMN_EVENT_HNS_HBT(cache_miss, 0x01), 1167 CMN_EVENT_HNS_HBT(slc_sf_cache_access, 0x02), 1168 CMN_EVENT_HNS_HBT(cache_fill, 0x03), 1169 CMN_EVENT_HNS_HBT(pocq_retry, 0x04), 1170 CMN_EVENT_HNS_HBT(pocq_reqs_recvd, 0x05), 1171 CMN_EVENT_HNS_HBT(sf_hit, 0x06), 1172 CMN_EVENT_HNS_HBT(sf_evictions, 0x07), 1173 CMN_EVENT_HNS(dir_snoops_sent, 0x08), 1174 CMN_EVENT_HNS(brd_snoops_sent, 0x09), 1175 CMN_EVENT_HNS_HBT(slc_eviction, 0x0a), 1176 CMN_EVENT_HNS_HBT(slc_fill_invalid_way, 0x0b), 1177 CMN_EVENT_HNS(mc_retries_local, 0x0c), 1178 CMN_EVENT_HNS_SNH(mc_reqs_local, 0x0d), 1179 CMN_EVENT_HNS(qos_hh_retry, 0x0e), 1180 CMN_EVENT_HNS_OCC(qos_pocq_occupancy, 0x0f), 1181 CMN_EVENT_HNS(pocq_addrhaz, 0x10), 1182 CMN_EVENT_HNS(pocq_atomic_addrhaz, 0x11), 1183 CMN_EVENT_HNS(ld_st_swp_adq_full, 0x12), 1184 CMN_EVENT_HNS(cmp_adq_full, 0x13), 1185 CMN_EVENT_HNS(txdat_stall, 0x14), 1186 CMN_EVENT_HNS(txrsp_stall, 0x15), 1187 CMN_EVENT_HNS(seq_full, 0x16), 1188 CMN_EVENT_HNS(seq_hit, 0x17), 1189 CMN_EVENT_HNS(snp_sent, 0x18), 1190 CMN_EVENT_HNS(sfbi_dir_snp_sent, 0x19), 1191 CMN_EVENT_HNS(sfbi_brd_snp_sent, 0x1a), 1192 CMN_EVENT_HNS(intv_dirty, 0x1c), 1193 CMN_EVENT_HNS(stash_snp_sent, 0x1d), 1194 CMN_EVENT_HNS(stash_data_pull, 0x1e), 1195 CMN_EVENT_HNS(snp_fwded, 0x1f), 1196 CMN_EVENT_HNS(atomic_fwd, 0x20), 1197 CMN_EVENT_HNS(mpam_hardlim, 0x21), 1198 CMN_EVENT_HNS(mpam_softlim, 0x22), 1199 CMN_EVENT_HNS(snp_sent_cluster, 0x23), 1200 CMN_EVENT_HNS(sf_imprecise_evict, 0x24), 1201 CMN_EVENT_HNS(sf_evict_shared_line, 0x25), 1202 CMN_EVENT_HNS_CLS(pocq_class_occup, 0x26), 1203 CMN_EVENT_HNS_CLS(pocq_class_retry, 0x27), 1204 CMN_EVENT_HNS_CLS(class_mc_reqs_local, 0x28), 1205 CMN_EVENT_HNS_CLS(class_cgnt_cmin, 0x29), 1206 CMN_EVENT_HNS_SNT(sn_throttle, 0x2a), 1207 CMN_EVENT_HNS_SNT(sn_throttle_min, 0x2b), 1208 CMN_EVENT_HNS(sf_precise_to_imprecise, 0x2c), 1209 CMN_EVENT_HNS(snp_intv_cln, 0x2d), 1210 CMN_EVENT_HNS(nc_excl, 0x2e), 1211 CMN_EVENT_HNS(excl_mon_ovfl, 0x2f), 1212 CMN_EVENT_HNS(snp_req_recvd, 0x30), 1213 CMN_EVENT_HNS(snp_req_byp_pocq, 0x31), 1214 CMN_EVENT_HNS(dir_ccgha_snp_sent, 0x32), 1215 CMN_EVENT_HNS(brd_ccgha_snp_sent, 0x33), 1216 CMN_EVENT_HNS(ccgha_snp_stall, 0x34), 1217 CMN_EVENT_HNS(lbt_req_hardlim, 0x35), 1218 CMN_EVENT_HNS(hbt_req_hardlim, 0x36), 1219 CMN_EVENT_HNS(sf_reupdate, 0x37), 1220 CMN_EVENT_HNS(excl_sf_imprecise, 0x38), 1221 CMN_EVENT_HNS(snp_pocq_addrhaz, 0x39), 1222 CMN_EVENT_HNS(mc_retries_remote, 0x3a), 1223 CMN_EVENT_HNS_SNH(mc_reqs_remote, 0x3b), 1224 CMN_EVENT_HNS_CLS(class_mc_reqs_remote, 0x3c), 1225 1226 NULL 1227 }; 1228 1229 static const struct attribute_group arm_cmn_event_attrs_group = { 1230 .name = "events", 1231 .attrs = arm_cmn_event_attrs, 1232 .is_visible = arm_cmn_event_attr_is_visible, 1233 }; 1234 1235 static ssize_t arm_cmn_format_show(struct device *dev, 1236 struct device_attribute *attr, char *buf) 1237 { 1238 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr); 1239 int lo = __ffs(fmt->field), hi = __fls(fmt->field); 1240 1241 if (lo == hi) 1242 return sysfs_emit(buf, "config:%d\n", lo); 1243 1244 if (!fmt->config) 1245 return sysfs_emit(buf, "config:%d-%d\n", lo, hi); 1246 1247 return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi); 1248 } 1249 1250 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \ 1251 (&((struct arm_cmn_format_attr[]) {{ \ 1252 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \ 1253 .config = _cfg, \ 1254 .field = _fld, \ 1255 }})[0].attr.attr) 1256 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld) 1257 1258 static struct attribute *arm_cmn_format_attrs[] = { 1259 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE), 1260 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID), 1261 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID), 1262 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID), 1263 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID), 1264 1265 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL), 1266 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL), 1267 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP), 1268 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE), 1269 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE), 1270 1271 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL), 1272 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK), 1273 1274 NULL 1275 }; 1276 1277 static const struct attribute_group arm_cmn_format_attrs_group = { 1278 .name = "format", 1279 .attrs = arm_cmn_format_attrs, 1280 }; 1281 1282 static ssize_t arm_cmn_cpumask_show(struct device *dev, 1283 struct device_attribute *attr, char *buf) 1284 { 1285 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1286 1287 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu)); 1288 } 1289 1290 static struct device_attribute arm_cmn_cpumask_attr = 1291 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL); 1292 1293 static ssize_t arm_cmn_identifier_show(struct device *dev, 1294 struct device_attribute *attr, char *buf) 1295 { 1296 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev)); 1297 1298 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev); 1299 } 1300 1301 static struct device_attribute arm_cmn_identifier_attr = 1302 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL); 1303 1304 static struct attribute *arm_cmn_other_attrs[] = { 1305 &arm_cmn_cpumask_attr.attr, 1306 &arm_cmn_identifier_attr.attr, 1307 NULL, 1308 }; 1309 1310 static const struct attribute_group arm_cmn_other_attrs_group = { 1311 .attrs = arm_cmn_other_attrs, 1312 }; 1313 1314 static const struct attribute_group *arm_cmn_attr_groups[] = { 1315 &arm_cmn_event_attrs_group, 1316 &arm_cmn_format_attrs_group, 1317 &arm_cmn_other_attrs_group, 1318 NULL 1319 }; 1320 1321 static int arm_cmn_wp_idx(struct perf_event *event) 1322 { 1323 return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event); 1324 } 1325 1326 static u32 arm_cmn_wp_config(struct perf_event *event) 1327 { 1328 u32 config; 1329 u32 dev = CMN_EVENT_WP_DEV_SEL(event); 1330 u32 chn = CMN_EVENT_WP_CHN_SEL(event); 1331 u32 grp = CMN_EVENT_WP_GRP(event); 1332 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event); 1333 u32 combine = CMN_EVENT_WP_COMBINE(event); 1334 bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600; 1335 1336 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) | 1337 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) | 1338 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) | 1339 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1); 1340 if (exc) 1341 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE : 1342 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE; 1343 if (combine && !grp) 1344 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE : 1345 CMN_DTM_WPn_CONFIG_WP_COMBINE; 1346 return config; 1347 } 1348 1349 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state) 1350 { 1351 if (!cmn->state) 1352 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR); 1353 cmn->state |= state; 1354 } 1355 1356 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state) 1357 { 1358 cmn->state &= ~state; 1359 if (!cmn->state) 1360 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, 1361 cmn->dtc[0].base + CMN_DT_PMCR); 1362 } 1363 1364 static void arm_cmn_pmu_enable(struct pmu *pmu) 1365 { 1366 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED); 1367 } 1368 1369 static void arm_cmn_pmu_disable(struct pmu *pmu) 1370 { 1371 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED); 1372 } 1373 1374 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw, 1375 bool snapshot) 1376 { 1377 struct arm_cmn_dtm *dtm = NULL; 1378 struct arm_cmn_node *dn; 1379 unsigned int i, offset, dtm_idx; 1380 u64 reg, count = 0; 1381 1382 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT; 1383 for_each_hw_dn(hw, dn, i) { 1384 if (dtm != &cmn->dtms[dn->dtm]) { 1385 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1386 reg = readq_relaxed(dtm->base + offset); 1387 } 1388 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1389 count += (u16)(reg >> (dtm_idx * 16)); 1390 } 1391 return count; 1392 } 1393 1394 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc) 1395 { 1396 u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR); 1397 1398 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); 1399 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1); 1400 } 1401 1402 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx) 1403 { 1404 u32 val, pmevcnt = CMN_DT_PMEVCNT(idx); 1405 1406 val = readl_relaxed(dtc->base + pmevcnt); 1407 writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt); 1408 return val - CMN_COUNTER_INIT; 1409 } 1410 1411 static void arm_cmn_init_counter(struct perf_event *event) 1412 { 1413 struct arm_cmn *cmn = to_cmn(event->pmu); 1414 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1415 u64 count; 1416 1417 for_each_hw_dtc_idx(hw, i, idx) { 1418 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + CMN_DT_PMEVCNT(idx)); 1419 cmn->dtc[i].counters[idx] = event; 1420 } 1421 1422 count = arm_cmn_read_dtm(cmn, hw, false); 1423 local64_set(&event->hw.prev_count, count); 1424 } 1425 1426 static void arm_cmn_event_read(struct perf_event *event) 1427 { 1428 struct arm_cmn *cmn = to_cmn(event->pmu); 1429 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1430 u64 delta, new, prev; 1431 unsigned long flags; 1432 1433 if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) { 1434 delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]); 1435 local64_add(delta, &event->count); 1436 return; 1437 } 1438 new = arm_cmn_read_dtm(cmn, hw, false); 1439 prev = local64_xchg(&event->hw.prev_count, new); 1440 1441 delta = new - prev; 1442 1443 local_irq_save(flags); 1444 for_each_hw_dtc_idx(hw, i, idx) { 1445 new = arm_cmn_read_counter(cmn->dtc + i, idx); 1446 delta += new << 16; 1447 } 1448 local_irq_restore(flags); 1449 local64_add(delta, &event->count); 1450 } 1451 1452 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn, 1453 enum cmn_filter_select fsel, u8 occupid) 1454 { 1455 u64 reg; 1456 1457 if (fsel == SEL_NONE) 1458 return 0; 1459 1460 if (!dn->occupid[fsel].count) { 1461 dn->occupid[fsel].val = occupid; 1462 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL, 1463 dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) | 1464 FIELD_PREP(CMN__PMU_SN_HOME_SEL, 1465 dn->occupid[SEL_SN_HOME_SEL].val) | 1466 FIELD_PREP(CMN__PMU_HBT_LBT_SEL, 1467 dn->occupid[SEL_HBT_LBT_SEL].val) | 1468 FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID, 1469 dn->occupid[SEL_CLASS_OCCUP_ID].val) | 1470 FIELD_PREP(CMN__PMU_OCCUP1_ID, 1471 dn->occupid[SEL_OCCUP1ID].val); 1472 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); 1473 } else if (dn->occupid[fsel].val != occupid) { 1474 return -EBUSY; 1475 } 1476 dn->occupid[fsel].count++; 1477 return 0; 1478 } 1479 1480 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx, 1481 int eventid, bool wide_sel) 1482 { 1483 if (wide_sel) { 1484 dn->event_w[dtm_idx] = eventid; 1485 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); 1486 } else { 1487 dn->event[dtm_idx] = eventid; 1488 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); 1489 } 1490 } 1491 1492 static void arm_cmn_event_start(struct perf_event *event, int flags) 1493 { 1494 struct arm_cmn *cmn = to_cmn(event->pmu); 1495 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1496 struct arm_cmn_node *dn; 1497 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1498 int i; 1499 1500 if (type == CMN_TYPE_DTC) { 1501 i = hw->dtc_idx[0]; 1502 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR); 1503 cmn->dtc[i].cc_active = true; 1504 } else if (type == CMN_TYPE_WP) { 1505 int wp_idx = arm_cmn_wp_idx(event); 1506 u64 val = CMN_EVENT_WP_VAL(event); 1507 u64 mask = CMN_EVENT_WP_MASK(event); 1508 1509 for_each_hw_dn(hw, dn, i) { 1510 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1511 1512 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); 1513 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); 1514 } 1515 } else for_each_hw_dn(hw, dn, i) { 1516 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1517 1518 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), 1519 hw->wide_sel); 1520 } 1521 } 1522 1523 static void arm_cmn_event_stop(struct perf_event *event, int flags) 1524 { 1525 struct arm_cmn *cmn = to_cmn(event->pmu); 1526 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1527 struct arm_cmn_node *dn; 1528 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1529 int i; 1530 1531 if (type == CMN_TYPE_DTC) { 1532 i = hw->dtc_idx[0]; 1533 cmn->dtc[i].cc_active = false; 1534 } else if (type == CMN_TYPE_WP) { 1535 int wp_idx = arm_cmn_wp_idx(event); 1536 1537 for_each_hw_dn(hw, dn, i) { 1538 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); 1539 1540 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); 1541 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); 1542 } 1543 } else for_each_hw_dn(hw, dn, i) { 1544 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1545 1546 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); 1547 } 1548 1549 arm_cmn_event_read(event); 1550 } 1551 1552 struct arm_cmn_val { 1553 u8 dtm_count[CMN_MAX_DTMS]; 1554 u8 occupid[CMN_MAX_DTMS][SEL_MAX]; 1555 u8 wp[CMN_MAX_DTMS][4]; 1556 int dtc_count; 1557 bool cycles; 1558 }; 1559 1560 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val, 1561 struct perf_event *event) 1562 { 1563 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1564 struct arm_cmn_node *dn; 1565 enum cmn_node_type type; 1566 int i; 1567 1568 if (is_software_event(event)) 1569 return; 1570 1571 type = CMN_EVENT_TYPE(event); 1572 if (type == CMN_TYPE_DTC) { 1573 val->cycles = true; 1574 return; 1575 } 1576 1577 val->dtc_count++; 1578 1579 for_each_hw_dn(hw, dn, i) { 1580 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel; 1581 1582 val->dtm_count[dtm]++; 1583 1584 if (sel > SEL_NONE) 1585 val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1; 1586 1587 if (type != CMN_TYPE_WP) 1588 continue; 1589 1590 wp_idx = arm_cmn_wp_idx(event); 1591 val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1; 1592 } 1593 } 1594 1595 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event) 1596 { 1597 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1598 struct arm_cmn_node *dn; 1599 struct perf_event *sibling, *leader = event->group_leader; 1600 enum cmn_node_type type; 1601 struct arm_cmn_val *val; 1602 int i, ret = -EINVAL; 1603 1604 if (leader == event) 1605 return 0; 1606 1607 if (event->pmu != leader->pmu && !is_software_event(leader)) 1608 return -EINVAL; 1609 1610 val = kzalloc(sizeof(*val), GFP_KERNEL); 1611 if (!val) 1612 return -ENOMEM; 1613 1614 arm_cmn_val_add_event(cmn, val, leader); 1615 for_each_sibling_event(sibling, leader) 1616 arm_cmn_val_add_event(cmn, val, sibling); 1617 1618 type = CMN_EVENT_TYPE(event); 1619 if (type == CMN_TYPE_DTC) { 1620 ret = val->cycles ? -EINVAL : 0; 1621 goto done; 1622 } 1623 1624 if (val->dtc_count == CMN_DT_NUM_COUNTERS) 1625 goto done; 1626 1627 for_each_hw_dn(hw, dn, i) { 1628 int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel; 1629 1630 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS) 1631 goto done; 1632 1633 if (sel > SEL_NONE && val->occupid[dtm][sel] && 1634 val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1) 1635 goto done; 1636 1637 if (type != CMN_TYPE_WP) 1638 continue; 1639 1640 wp_idx = arm_cmn_wp_idx(event); 1641 if (val->wp[dtm][wp_idx]) 1642 goto done; 1643 1644 wp_cmb = val->wp[dtm][wp_idx ^ 1]; 1645 if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1) 1646 goto done; 1647 } 1648 1649 ret = 0; 1650 done: 1651 kfree(val); 1652 return ret; 1653 } 1654 1655 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn, 1656 enum cmn_node_type type, 1657 unsigned int eventid) 1658 { 1659 struct arm_cmn_event_attr *e; 1660 enum cmn_model model = arm_cmn_model(cmn); 1661 1662 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) { 1663 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr); 1664 if (e->model & model && e->type == type && e->eventid == eventid) 1665 return e->fsel; 1666 } 1667 return SEL_NONE; 1668 } 1669 1670 1671 static int arm_cmn_event_init(struct perf_event *event) 1672 { 1673 struct arm_cmn *cmn = to_cmn(event->pmu); 1674 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1675 struct arm_cmn_node *dn; 1676 enum cmn_node_type type; 1677 bool bynodeid; 1678 u16 nodeid, eventid; 1679 1680 if (event->attr.type != event->pmu->type) 1681 return -ENOENT; 1682 1683 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 1684 return -EINVAL; 1685 1686 event->cpu = cmn->cpu; 1687 if (event->cpu < 0) 1688 return -EINVAL; 1689 1690 type = CMN_EVENT_TYPE(event); 1691 /* DTC events (i.e. cycles) already have everything they need */ 1692 if (type == CMN_TYPE_DTC) 1693 return arm_cmn_validate_group(cmn, event); 1694 1695 eventid = CMN_EVENT_EVENTID(event); 1696 /* For watchpoints we need the actual XP node here */ 1697 if (type == CMN_TYPE_WP) { 1698 type = CMN_TYPE_XP; 1699 /* ...and we need a "real" direction */ 1700 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN) 1701 return -EINVAL; 1702 /* ...but the DTM may depend on which port we're watching */ 1703 if (cmn->multi_dtm) 1704 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2; 1705 } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) { 1706 hw->wide_sel = true; 1707 } 1708 1709 /* This is sufficiently annoying to recalculate, so cache it */ 1710 hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid); 1711 1712 bynodeid = CMN_EVENT_BYNODEID(event); 1713 nodeid = CMN_EVENT_NODEID(event); 1714 1715 hw->dn = arm_cmn_node(cmn, type); 1716 if (!hw->dn) 1717 return -EINVAL; 1718 1719 memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx)); 1720 for (dn = hw->dn; dn->type == type; dn++) { 1721 if (bynodeid && dn->id != nodeid) { 1722 hw->dn++; 1723 continue; 1724 } 1725 hw->num_dns++; 1726 if (dn->dtc < 0) 1727 memset(hw->dtc_idx, 0, cmn->num_dtcs); 1728 else 1729 hw->dtc_idx[dn->dtc] = 0; 1730 1731 if (bynodeid) 1732 break; 1733 } 1734 1735 if (!hw->num_dns) { 1736 dev_dbg(cmn->dev, "invalid node 0x%x type 0x%x\n", nodeid, type); 1737 return -EINVAL; 1738 } 1739 1740 return arm_cmn_validate_group(cmn, event); 1741 } 1742 1743 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event, 1744 int i) 1745 { 1746 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1747 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1748 1749 while (i--) { 1750 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; 1751 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i); 1752 1753 if (type == CMN_TYPE_WP) 1754 dtm->wp_event[arm_cmn_wp_idx(event)] = -1; 1755 1756 if (hw->filter_sel > SEL_NONE) 1757 hw->dn[i].occupid[hw->filter_sel].count--; 1758 1759 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx); 1760 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 1761 } 1762 memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); 1763 1764 for_each_hw_dtc_idx(hw, j, idx) 1765 cmn->dtc[j].counters[idx] = NULL; 1766 } 1767 1768 static int arm_cmn_event_add(struct perf_event *event, int flags) 1769 { 1770 struct arm_cmn *cmn = to_cmn(event->pmu); 1771 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1772 struct arm_cmn_node *dn; 1773 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1774 unsigned int input_sel, i = 0; 1775 1776 if (type == CMN_TYPE_DTC) { 1777 while (cmn->dtc[i].cycles) 1778 if (++i == cmn->num_dtcs) 1779 return -ENOSPC; 1780 1781 cmn->dtc[i].cycles = event; 1782 hw->dtc_idx[0] = i; 1783 1784 if (flags & PERF_EF_START) 1785 arm_cmn_event_start(event, 0); 1786 return 0; 1787 } 1788 1789 /* Grab a free global counter first... */ 1790 for_each_hw_dtc_idx(hw, j, idx) { 1791 if (j > 0) { 1792 idx = hw->dtc_idx[0]; 1793 } else { 1794 idx = 0; 1795 while (cmn->dtc[j].counters[idx]) 1796 if (++idx == CMN_DT_NUM_COUNTERS) 1797 goto free_dtms; 1798 } 1799 hw->dtc_idx[j] = idx; 1800 } 1801 1802 /* ...then the local counters to feed it. */ 1803 for_each_hw_dn(hw, dn, i) { 1804 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset; 1805 unsigned int dtm_idx, shift, d = 0; 1806 u64 reg; 1807 1808 dtm_idx = 0; 1809 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx)) 1810 if (++dtm_idx == CMN_DTM_NUM_COUNTERS) 1811 goto free_dtms; 1812 1813 if (type == CMN_TYPE_XP) { 1814 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx; 1815 } else if (type == CMN_TYPE_WP) { 1816 int tmp, wp_idx = arm_cmn_wp_idx(event); 1817 u32 cfg = arm_cmn_wp_config(event); 1818 1819 if (dtm->wp_event[wp_idx] >= 0) 1820 goto free_dtms; 1821 1822 tmp = dtm->wp_event[wp_idx ^ 1]; 1823 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) != 1824 CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp])) 1825 goto free_dtms; 1826 1827 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx; 1828 dtm->wp_event[wp_idx] = hw->dtc_idx[d]; 1829 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx)); 1830 } else { 1831 struct arm_cmn_nodeid nid = arm_cmn_nid(dn); 1832 1833 if (cmn->multi_dtm) 1834 nid.port %= 2; 1835 1836 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx + 1837 (nid.port << 4) + (nid.dev << 2); 1838 1839 if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event))) 1840 goto free_dtms; 1841 } 1842 1843 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); 1844 1845 dtm->input_sel[dtm_idx] = input_sel; 1846 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); 1847 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift); 1848 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift; 1849 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx); 1850 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low; 1851 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); 1852 } 1853 1854 /* Go go go! */ 1855 arm_cmn_init_counter(event); 1856 1857 if (flags & PERF_EF_START) 1858 arm_cmn_event_start(event, 0); 1859 1860 return 0; 1861 1862 free_dtms: 1863 arm_cmn_event_clear(cmn, event, i); 1864 return -ENOSPC; 1865 } 1866 1867 static void arm_cmn_event_del(struct perf_event *event, int flags) 1868 { 1869 struct arm_cmn *cmn = to_cmn(event->pmu); 1870 struct arm_cmn_hw_event *hw = to_cmn_hw(event); 1871 enum cmn_node_type type = CMN_EVENT_TYPE(event); 1872 1873 arm_cmn_event_stop(event, PERF_EF_UPDATE); 1874 1875 if (type == CMN_TYPE_DTC) 1876 cmn->dtc[hw->dtc_idx[0]].cycles = NULL; 1877 else 1878 arm_cmn_event_clear(cmn, event, hw->num_dns); 1879 } 1880 1881 /* 1882 * We stop the PMU for both add and read, to avoid skew across DTM counters. 1883 * In theory we could use snapshots to read without stopping, but then it 1884 * becomes a lot trickier to deal with overlow and racing against interrupts, 1885 * plus it seems they don't work properly on some hardware anyway :( 1886 */ 1887 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags) 1888 { 1889 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN); 1890 } 1891 1892 static void arm_cmn_end_txn(struct pmu *pmu) 1893 { 1894 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN); 1895 } 1896 1897 static int arm_cmn_commit_txn(struct pmu *pmu) 1898 { 1899 arm_cmn_end_txn(pmu); 1900 return 0; 1901 } 1902 1903 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu) 1904 { 1905 unsigned int i; 1906 1907 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu); 1908 for (i = 0; i < cmn->num_dtcs; i++) 1909 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu)); 1910 cmn->cpu = cpu; 1911 } 1912 1913 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 1914 { 1915 struct arm_cmn *cmn; 1916 int node; 1917 1918 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 1919 node = dev_to_node(cmn->dev); 1920 if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node) 1921 arm_cmn_migrate(cmn, cpu); 1922 return 0; 1923 } 1924 1925 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node) 1926 { 1927 struct arm_cmn *cmn; 1928 unsigned int target; 1929 int node; 1930 cpumask_t mask; 1931 1932 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node); 1933 if (cpu != cmn->cpu) 1934 return 0; 1935 1936 node = dev_to_node(cmn->dev); 1937 if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) && 1938 cpumask_andnot(&mask, &mask, cpumask_of(cpu))) 1939 target = cpumask_any(&mask); 1940 else 1941 target = cpumask_any_but(cpu_online_mask, cpu); 1942 if (target < nr_cpu_ids) 1943 arm_cmn_migrate(cmn, target); 1944 return 0; 1945 } 1946 1947 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id) 1948 { 1949 struct arm_cmn_dtc *dtc = dev_id; 1950 irqreturn_t ret = IRQ_NONE; 1951 1952 for (;;) { 1953 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR); 1954 u64 delta; 1955 int i; 1956 1957 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) { 1958 if (status & (1U << i)) { 1959 ret = IRQ_HANDLED; 1960 if (WARN_ON(!dtc->counters[i])) 1961 continue; 1962 delta = (u64)arm_cmn_read_counter(dtc, i) << 16; 1963 local64_add(delta, &dtc->counters[i]->count); 1964 } 1965 } 1966 1967 if (status & (1U << CMN_DT_NUM_COUNTERS)) { 1968 ret = IRQ_HANDLED; 1969 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) { 1970 delta = arm_cmn_read_cc(dtc); 1971 local64_add(delta, &dtc->cycles->count); 1972 } 1973 } 1974 1975 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR); 1976 1977 if (!dtc->irq_friend) 1978 return ret; 1979 dtc += dtc->irq_friend; 1980 } 1981 } 1982 1983 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ 1984 static int arm_cmn_init_irqs(struct arm_cmn *cmn) 1985 { 1986 int i, j, irq, err; 1987 1988 for (i = 0; i < cmn->num_dtcs; i++) { 1989 irq = cmn->dtc[i].irq; 1990 for (j = i; j--; ) { 1991 if (cmn->dtc[j].irq == irq) { 1992 cmn->dtc[j].irq_friend = i - j; 1993 goto next; 1994 } 1995 } 1996 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq, 1997 IRQF_NOBALANCING | IRQF_NO_THREAD, 1998 dev_name(cmn->dev), &cmn->dtc[i]); 1999 if (err) 2000 return err; 2001 2002 err = irq_set_affinity(irq, cpumask_of(cmn->cpu)); 2003 if (err) 2004 return err; 2005 next: 2006 ; /* isn't C great? */ 2007 } 2008 return 0; 2009 } 2010 2011 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx) 2012 { 2013 int i; 2014 2015 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); 2016 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN; 2017 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); 2018 for (i = 0; i < 4; i++) { 2019 dtm->wp_event[i] = -1; 2020 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); 2021 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i)); 2022 } 2023 } 2024 2025 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx) 2026 { 2027 struct arm_cmn_dtc *dtc = cmn->dtc + idx; 2028 2029 dtc->base = dn->pmu_base - CMN_PMU_OFFSET; 2030 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx); 2031 if (dtc->irq < 0) 2032 return dtc->irq; 2033 2034 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); 2035 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR); 2036 writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR); 2037 writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR); 2038 2039 return 0; 2040 } 2041 2042 static int arm_cmn_node_cmp(const void *a, const void *b) 2043 { 2044 const struct arm_cmn_node *dna = a, *dnb = b; 2045 int cmp; 2046 2047 cmp = dna->type - dnb->type; 2048 if (!cmp) 2049 cmp = dna->logid - dnb->logid; 2050 return cmp; 2051 } 2052 2053 static int arm_cmn_init_dtcs(struct arm_cmn *cmn) 2054 { 2055 struct arm_cmn_node *dn, *xp; 2056 int dtc_idx = 0; 2057 2058 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL); 2059 if (!cmn->dtc) 2060 return -ENOMEM; 2061 2062 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL); 2063 2064 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP); 2065 2066 if (cmn->part == PART_CMN600 && cmn->num_dtcs > 1) { 2067 /* We do at least know that a DTC's XP must be in that DTC's domain */ 2068 dn = arm_cmn_node(cmn, CMN_TYPE_DTC); 2069 for (int i = 0; i < cmn->num_dtcs; i++) 2070 arm_cmn_node_to_xp(cmn, dn + i)->dtc = i; 2071 } 2072 2073 for (dn = cmn->dns; dn->type; dn++) { 2074 if (dn->type == CMN_TYPE_XP) 2075 continue; 2076 2077 xp = arm_cmn_node_to_xp(cmn, dn); 2078 dn->portid_bits = xp->portid_bits; 2079 dn->deviceid_bits = xp->deviceid_bits; 2080 dn->dtc = xp->dtc; 2081 dn->dtm = xp->dtm; 2082 if (cmn->multi_dtm) 2083 dn->dtm += arm_cmn_nid(dn).port / 2; 2084 2085 if (dn->type == CMN_TYPE_DTC) { 2086 int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++); 2087 2088 if (err) 2089 return err; 2090 } 2091 2092 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ 2093 if (dn->type == CMN_TYPE_RND) 2094 dn->type = CMN_TYPE_RNI; 2095 2096 /* We split the RN-I off already, so let the CCLA part match CCLA events */ 2097 if (dn->type == CMN_TYPE_CCLA_RNI) 2098 dn->type = CMN_TYPE_CCLA; 2099 } 2100 2101 arm_cmn_set_state(cmn, CMN_STATE_DISABLED); 2102 2103 return 0; 2104 } 2105 2106 static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region) 2107 { 2108 int offset = CMN_DTM_UNIT_INFO; 2109 2110 if (cmn->part == PART_CMN650 || cmn->part == PART_CI700) 2111 offset = CMN650_DTM_UNIT_INFO; 2112 2113 return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset)); 2114 } 2115 2116 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node) 2117 { 2118 int level; 2119 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO); 2120 2121 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg); 2122 node->id = FIELD_GET(CMN_NI_NODE_ID, reg); 2123 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg); 2124 2125 node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET; 2126 2127 if (node->type == CMN_TYPE_CFG) 2128 level = 0; 2129 else if (node->type == CMN_TYPE_XP) 2130 level = 1; 2131 else 2132 level = 2; 2133 2134 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n", 2135 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ', 2136 node->type, node->logid, offset); 2137 } 2138 2139 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type) 2140 { 2141 switch (type) { 2142 case CMN_TYPE_HNP: 2143 return CMN_TYPE_HNI; 2144 case CMN_TYPE_CCLA_RNI: 2145 return CMN_TYPE_RNI; 2146 default: 2147 return CMN_TYPE_INVALID; 2148 } 2149 } 2150 2151 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) 2152 { 2153 void __iomem *cfg_region; 2154 struct arm_cmn_node cfg, *dn; 2155 struct arm_cmn_dtm *dtm; 2156 enum cmn_part part; 2157 u16 child_count, child_poff; 2158 u32 xp_offset[CMN_MAX_XPS]; 2159 u64 reg; 2160 int i, j; 2161 size_t sz; 2162 2163 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); 2164 if (cfg.type != CMN_TYPE_CFG) 2165 return -ENODEV; 2166 2167 cfg_region = cmn->base + rgn_offset; 2168 2169 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); 2170 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg); 2171 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; 2172 if (cmn->part && cmn->part != part) 2173 dev_warn(cmn->dev, 2174 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n", 2175 cmn->part, part); 2176 cmn->part = part; 2177 if (!arm_cmn_model(cmn)) 2178 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part); 2179 2180 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23); 2181 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg); 2182 2183 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL); 2184 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN; 2185 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg); 2186 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg); 2187 2188 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1); 2189 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg); 2190 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg); 2191 2192 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO); 2193 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2194 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2195 2196 cmn->num_xps = child_count; 2197 cmn->num_dns = cmn->num_xps; 2198 2199 /* Pass 1: visit the XPs, enumerate their children */ 2200 for (i = 0; i < cmn->num_xps; i++) { 2201 reg = readq_relaxed(cfg_region + child_poff + i * 8); 2202 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR; 2203 2204 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO); 2205 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2206 } 2207 2208 /* 2209 * Some nodes effectively have two separate types, which we'll handle 2210 * by creating one of each internally. For a (very) safe initial upper 2211 * bound, account for double the number of non-XP nodes. 2212 */ 2213 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps, 2214 sizeof(*dn), GFP_KERNEL); 2215 if (!dn) 2216 return -ENOMEM; 2217 2218 /* Initial safe upper bound on DTMs for any possible mesh layout */ 2219 i = cmn->num_xps; 2220 if (cmn->multi_dtm) 2221 i += cmn->num_xps + 1; 2222 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL); 2223 if (!dtm) 2224 return -ENOMEM; 2225 2226 /* Pass 2: now we can actually populate the nodes */ 2227 cmn->dns = dn; 2228 cmn->dtms = dtm; 2229 for (i = 0; i < cmn->num_xps; i++) { 2230 void __iomem *xp_region = cmn->base + xp_offset[i]; 2231 struct arm_cmn_node *xp = dn++; 2232 unsigned int xp_ports = 0; 2233 2234 arm_cmn_init_node_info(cmn, xp_offset[i], xp); 2235 /* 2236 * Thanks to the order in which XP logical IDs seem to be 2237 * assigned, we can handily infer the mesh X dimension by 2238 * looking out for the XP at (0,1) without needing to know 2239 * the exact node ID format, which we can later derive. 2240 */ 2241 if (xp->id == (1 << 3)) 2242 cmn->mesh_x = xp->logid; 2243 2244 if (cmn->part == PART_CMN600) 2245 xp->dtc = -1; 2246 else 2247 xp->dtc = arm_cmn_dtc_domain(cmn, xp_region); 2248 2249 xp->dtm = dtm - cmn->dtms; 2250 arm_cmn_init_dtm(dtm++, xp, 0); 2251 /* 2252 * Keeping track of connected ports will let us filter out 2253 * unnecessary XP events easily, and also infer the per-XP 2254 * part of the node ID format. 2255 */ 2256 for (int p = 0; p < CMN_MAX_PORTS; p++) 2257 if (arm_cmn_device_connect_info(cmn, xp, p)) 2258 xp_ports |= BIT(p); 2259 2260 if (cmn->num_xps == 1) { 2261 xp->portid_bits = 3; 2262 xp->deviceid_bits = 2; 2263 } else if (xp_ports > 0x3) { 2264 xp->portid_bits = 2; 2265 xp->deviceid_bits = 1; 2266 } else { 2267 xp->portid_bits = 1; 2268 xp->deviceid_bits = 2; 2269 } 2270 2271 if (cmn->multi_dtm && (xp_ports > 0x3)) 2272 arm_cmn_init_dtm(dtm++, xp, 1); 2273 if (cmn->multi_dtm && (xp_ports > 0xf)) 2274 arm_cmn_init_dtm(dtm++, xp, 2); 2275 2276 cmn->ports_used |= xp_ports; 2277 2278 reg = readq_relaxed(xp_region + CMN_CHILD_INFO); 2279 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg); 2280 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg); 2281 2282 for (j = 0; j < child_count; j++) { 2283 reg = readq_relaxed(xp_region + child_poff + j * 8); 2284 /* 2285 * Don't even try to touch anything external, since in general 2286 * we haven't a clue how to power up arbitrary CHI requesters. 2287 * As of CMN-600r1 these could only be RN-SAMs or CXLAs, 2288 * neither of which have any PMU events anyway. 2289 * (Actually, CXLAs do seem to have grown some events in r1p2, 2290 * but they don't go to regular XP DTMs, and they depend on 2291 * secure configuration which we can't easily deal with) 2292 */ 2293 if (reg & CMN_CHILD_NODE_EXTERNAL) { 2294 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg); 2295 continue; 2296 } 2297 /* 2298 * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus 2299 * child count larger than the number of valid child pointers. 2300 * A child offset of 0 can only occur on CMN-600; otherwise it 2301 * would imply the root node being its own grandchild, which 2302 * we can safely dismiss in general. 2303 */ 2304 if (reg == 0 && cmn->part != PART_CMN600) { 2305 dev_dbg(cmn->dev, "bogus child pointer?\n"); 2306 continue; 2307 } 2308 2309 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn); 2310 2311 switch (dn->type) { 2312 case CMN_TYPE_DTC: 2313 cmn->num_dtcs++; 2314 dn++; 2315 break; 2316 /* These guys have PMU events */ 2317 case CMN_TYPE_DVM: 2318 case CMN_TYPE_HNI: 2319 case CMN_TYPE_HNF: 2320 case CMN_TYPE_SBSX: 2321 case CMN_TYPE_RNI: 2322 case CMN_TYPE_RND: 2323 case CMN_TYPE_MTSX: 2324 case CMN_TYPE_CXRA: 2325 case CMN_TYPE_CXHA: 2326 case CMN_TYPE_CCRA: 2327 case CMN_TYPE_CCHA: 2328 case CMN_TYPE_HNS: 2329 dn++; 2330 break; 2331 case CMN_TYPE_CCLA: 2332 dn->pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2333 dn++; 2334 break; 2335 /* Nothing to see here */ 2336 case CMN_TYPE_MPAM_S: 2337 case CMN_TYPE_MPAM_NS: 2338 case CMN_TYPE_RNSAM: 2339 case CMN_TYPE_CXLA: 2340 case CMN_TYPE_HNS_MPAM_S: 2341 case CMN_TYPE_HNS_MPAM_NS: 2342 break; 2343 /* 2344 * Split "optimised" combination nodes into separate 2345 * types for the different event sets. Offsetting the 2346 * base address lets us handle the second pmu_event_sel 2347 * register via the normal mechanism later. 2348 */ 2349 case CMN_TYPE_HNP: 2350 case CMN_TYPE_CCLA_RNI: 2351 dn[1] = dn[0]; 2352 dn[0].pmu_base += CMN_CCLA_PMU_EVENT_SEL; 2353 dn[1].type = arm_cmn_subtype(dn->type); 2354 dn += 2; 2355 break; 2356 /* Something has gone horribly wrong */ 2357 default: 2358 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type); 2359 return -ENODEV; 2360 } 2361 } 2362 } 2363 2364 /* Correct for any nodes we added or skipped */ 2365 cmn->num_dns = dn - cmn->dns; 2366 2367 /* Cheeky +1 to help terminate pointer-based iteration later */ 2368 sz = (void *)(dn + 1) - (void *)cmn->dns; 2369 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL); 2370 if (dn) 2371 cmn->dns = dn; 2372 2373 sz = (void *)dtm - (void *)cmn->dtms; 2374 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL); 2375 if (dtm) 2376 cmn->dtms = dtm; 2377 2378 /* 2379 * If mesh_x wasn't set during discovery then we never saw 2380 * an XP at (0,1), thus we must have an Nx1 configuration. 2381 */ 2382 if (!cmn->mesh_x) 2383 cmn->mesh_x = cmn->num_xps; 2384 cmn->mesh_y = cmn->num_xps / cmn->mesh_x; 2385 2386 /* 1x1 config plays havoc with XP event encodings */ 2387 if (cmn->num_xps == 1) 2388 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n"); 2389 2390 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev); 2391 reg = cmn->ports_used; 2392 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n", 2393 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®, 2394 cmn->multi_dtm ? ", multi-DTM" : ""); 2395 2396 return 0; 2397 } 2398 2399 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn) 2400 { 2401 struct resource *cfg, *root; 2402 2403 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2404 if (!cfg) 2405 return -EINVAL; 2406 2407 root = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2408 if (!root) 2409 return -EINVAL; 2410 2411 if (!resource_contains(cfg, root)) 2412 swap(cfg, root); 2413 /* 2414 * Note that devm_ioremap_resource() is dumb and won't let the platform 2415 * device claim cfg when the ACPI companion device has already claimed 2416 * root within it. But since they *are* already both claimed in the 2417 * appropriate name, we don't really need to do it again here anyway. 2418 */ 2419 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg)); 2420 if (!cmn->base) 2421 return -ENOMEM; 2422 2423 return root->start - cfg->start; 2424 } 2425 2426 static int arm_cmn600_of_probe(struct device_node *np) 2427 { 2428 u32 rootnode; 2429 2430 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode; 2431 } 2432 2433 static int arm_cmn_probe(struct platform_device *pdev) 2434 { 2435 struct arm_cmn *cmn; 2436 const char *name; 2437 static atomic_t id; 2438 int err, rootnode, this_id; 2439 2440 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); 2441 if (!cmn) 2442 return -ENOMEM; 2443 2444 cmn->dev = &pdev->dev; 2445 cmn->part = (unsigned long)device_get_match_data(cmn->dev); 2446 platform_set_drvdata(pdev, cmn); 2447 2448 if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) { 2449 rootnode = arm_cmn600_acpi_probe(pdev, cmn); 2450 } else { 2451 rootnode = 0; 2452 cmn->base = devm_platform_ioremap_resource(pdev, 0); 2453 if (IS_ERR(cmn->base)) 2454 return PTR_ERR(cmn->base); 2455 if (cmn->part == PART_CMN600) 2456 rootnode = arm_cmn600_of_probe(pdev->dev.of_node); 2457 } 2458 if (rootnode < 0) 2459 return rootnode; 2460 2461 err = arm_cmn_discover(cmn, rootnode); 2462 if (err) 2463 return err; 2464 2465 err = arm_cmn_init_dtcs(cmn); 2466 if (err) 2467 return err; 2468 2469 err = arm_cmn_init_irqs(cmn); 2470 if (err) 2471 return err; 2472 2473 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev)); 2474 cmn->pmu = (struct pmu) { 2475 .module = THIS_MODULE, 2476 .attr_groups = arm_cmn_attr_groups, 2477 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 2478 .task_ctx_nr = perf_invalid_context, 2479 .pmu_enable = arm_cmn_pmu_enable, 2480 .pmu_disable = arm_cmn_pmu_disable, 2481 .event_init = arm_cmn_event_init, 2482 .add = arm_cmn_event_add, 2483 .del = arm_cmn_event_del, 2484 .start = arm_cmn_event_start, 2485 .stop = arm_cmn_event_stop, 2486 .read = arm_cmn_event_read, 2487 .start_txn = arm_cmn_start_txn, 2488 .commit_txn = arm_cmn_commit_txn, 2489 .cancel_txn = arm_cmn_end_txn, 2490 }; 2491 2492 this_id = atomic_fetch_inc(&id); 2493 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id); 2494 if (!name) 2495 return -ENOMEM; 2496 2497 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node); 2498 if (err) 2499 return err; 2500 2501 err = perf_pmu_register(&cmn->pmu, name, -1); 2502 if (err) 2503 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2504 else 2505 arm_cmn_debugfs_init(cmn, this_id); 2506 2507 return err; 2508 } 2509 2510 static int arm_cmn_remove(struct platform_device *pdev) 2511 { 2512 struct arm_cmn *cmn = platform_get_drvdata(pdev); 2513 2514 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL); 2515 2516 perf_pmu_unregister(&cmn->pmu); 2517 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node); 2518 debugfs_remove(cmn->debug); 2519 return 0; 2520 } 2521 2522 #ifdef CONFIG_OF 2523 static const struct of_device_id arm_cmn_of_match[] = { 2524 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 }, 2525 { .compatible = "arm,cmn-650" }, 2526 { .compatible = "arm,cmn-700" }, 2527 { .compatible = "arm,ci-700" }, 2528 {} 2529 }; 2530 MODULE_DEVICE_TABLE(of, arm_cmn_of_match); 2531 #endif 2532 2533 #ifdef CONFIG_ACPI 2534 static const struct acpi_device_id arm_cmn_acpi_match[] = { 2535 { "ARMHC600", PART_CMN600 }, 2536 { "ARMHC650" }, 2537 { "ARMHC700" }, 2538 {} 2539 }; 2540 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); 2541 #endif 2542 2543 static struct platform_driver arm_cmn_driver = { 2544 .driver = { 2545 .name = "arm-cmn", 2546 .of_match_table = of_match_ptr(arm_cmn_of_match), 2547 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match), 2548 }, 2549 .probe = arm_cmn_probe, 2550 .remove = arm_cmn_remove, 2551 }; 2552 2553 static int __init arm_cmn_init(void) 2554 { 2555 int ret; 2556 2557 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 2558 "perf/arm/cmn:online", 2559 arm_cmn_pmu_online_cpu, 2560 arm_cmn_pmu_offline_cpu); 2561 if (ret < 0) 2562 return ret; 2563 2564 arm_cmn_hp_state = ret; 2565 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL); 2566 2567 ret = platform_driver_register(&arm_cmn_driver); 2568 if (ret) { 2569 cpuhp_remove_multi_state(arm_cmn_hp_state); 2570 debugfs_remove(arm_cmn_debugfs); 2571 } 2572 return ret; 2573 } 2574 2575 static void __exit arm_cmn_exit(void) 2576 { 2577 platform_driver_unregister(&arm_cmn_driver); 2578 cpuhp_remove_multi_state(arm_cmn_hp_state); 2579 debugfs_remove(arm_cmn_debugfs); 2580 } 2581 2582 module_init(arm_cmn_init); 2583 module_exit(arm_cmn_exit); 2584 2585 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>"); 2586 MODULE_DESCRIPTION("Arm CMN-600 PMU driver"); 2587 MODULE_LICENSE("GPL v2"); 2588