1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License version 2 as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * Copyright (C) 2014 ARM Limited 12 */ 13 14 #include <linux/ctype.h> 15 #include <linux/hrtimer.h> 16 #include <linux/idr.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/perf_event.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 25 #define CCN_NUM_XP_PORTS 2 26 #define CCN_NUM_VCS 4 27 #define CCN_NUM_REGIONS 256 28 #define CCN_REGION_SIZE 0x10000 29 30 #define CCN_ALL_OLY_ID 0xff00 31 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0 32 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f 33 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8 34 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f 35 36 #define CCN_MN_ERRINT_STATUS 0x0008 37 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11 38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02 39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20 40 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22 41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04 42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40 43 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44 44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08 45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80 46 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88 47 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0 48 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300 49 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1) 50 51 #define CCN_DT_ACTIVE_DSM 0x0000 52 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8) 53 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff 54 #define CCN_DT_CTL 0x0028 55 #define CCN_DT_CTL__DT_EN (1 << 0) 56 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8) 57 #define CCN_DT_PMCCNTR 0x0140 58 #define CCN_DT_PMCCNTRSR 0x0190 59 #define CCN_DT_PMOVSR 0x0198 60 #define CCN_DT_PMOVSR_CLR 0x01a0 61 #define CCN_DT_PMOVSR_CLR__MASK 0x1f 62 #define CCN_DT_PMCR 0x01a8 63 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6) 64 #define CCN_DT_PMCR__PMU_EN (1 << 0) 65 #define CCN_DT_PMSR 0x01b0 66 #define CCN_DT_PMSR_REQ 0x01b8 67 #define CCN_DT_PMSR_CLR 0x01c0 68 69 #define CCN_HNF_PMU_EVENT_SEL 0x0600 70 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) 71 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf 72 73 #define CCN_XP_DT_CONFIG 0x0300 74 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4) 75 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf 76 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0 77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1 78 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n)) 79 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n)) 80 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n)) 81 #define CCN_XP_DT_INTERFACE_SEL 0x0308 82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8) 83 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1 84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8) 85 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1 86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8) 87 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3 88 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40) 89 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40) 90 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40) 91 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40) 92 #define CCN_XP_DT_CONTROL 0x0370 93 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0) 94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4) 95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf 96 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf 97 #define CCN_XP_PMU_EVENT_SEL 0x0600 98 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7) 99 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f 100 101 #define CCN_SBAS_PMU_EVENT_SEL 0x0600 102 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) 103 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf 104 105 #define CCN_RNI_PMU_EVENT_SEL 0x0600 106 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) 107 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf 108 109 #define CCN_TYPE_MN 0x01 110 #define CCN_TYPE_DT 0x02 111 #define CCN_TYPE_HNF 0x04 112 #define CCN_TYPE_HNI 0x05 113 #define CCN_TYPE_XP 0x08 114 #define CCN_TYPE_SBSX 0x0c 115 #define CCN_TYPE_SBAS 0x10 116 #define CCN_TYPE_RNI_1P 0x14 117 #define CCN_TYPE_RNI_2P 0x15 118 #define CCN_TYPE_RNI_3P 0x16 119 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */ 120 #define CCN_TYPE_RND_2P 0x19 121 #define CCN_TYPE_RND_3P 0x1a 122 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */ 123 124 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */ 125 126 #define CCN_NUM_PMU_EVENTS 4 127 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */ 128 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */ 129 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS 130 131 #define CCN_NUM_PREDEFINED_MASKS 4 132 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0) 133 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1) 134 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2) 135 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3) 136 137 struct arm_ccn_component { 138 void __iomem *base; 139 u32 type; 140 141 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS); 142 union { 143 struct { 144 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS); 145 } xp; 146 }; 147 }; 148 149 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \ 150 struct arm_ccn_dt, pmu), struct arm_ccn, dt) 151 152 struct arm_ccn_dt { 153 int id; 154 void __iomem *base; 155 156 spinlock_t config_lock; 157 158 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1); 159 struct { 160 struct arm_ccn_component *source; 161 struct perf_event *event; 162 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1]; 163 164 struct { 165 u64 l, h; 166 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS]; 167 168 struct hrtimer hrtimer; 169 170 cpumask_t cpu; 171 struct hlist_node node; 172 173 struct pmu pmu; 174 }; 175 176 struct arm_ccn { 177 struct device *dev; 178 void __iomem *base; 179 unsigned int irq; 180 181 unsigned sbas_present:1; 182 unsigned sbsx_present:1; 183 184 int num_nodes; 185 struct arm_ccn_component *node; 186 187 int num_xps; 188 struct arm_ccn_component *xp; 189 190 struct arm_ccn_dt dt; 191 int mn_id; 192 }; 193 194 static int arm_ccn_node_to_xp(int node) 195 { 196 return node / CCN_NUM_XP_PORTS; 197 } 198 199 static int arm_ccn_node_to_xp_port(int node) 200 { 201 return node % CCN_NUM_XP_PORTS; 202 } 203 204 205 /* 206 * Bit shifts and masks in these defines must be kept in sync with 207 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below! 208 */ 209 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff) 210 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff) 211 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff) 212 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff) 213 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3) 214 #define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3) 215 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7) 216 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1) 217 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf) 218 219 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port) 220 { 221 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24)); 222 *config |= (node_xp << 0) | (type << 8) | (port << 24); 223 } 224 225 static ssize_t arm_ccn_pmu_format_show(struct device *dev, 226 struct device_attribute *attr, char *buf) 227 { 228 struct dev_ext_attribute *ea = container_of(attr, 229 struct dev_ext_attribute, attr); 230 231 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var); 232 } 233 234 #define CCN_FORMAT_ATTR(_name, _config) \ 235 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \ 236 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \ 237 NULL), _config } 238 239 static CCN_FORMAT_ATTR(node, "config:0-7"); 240 static CCN_FORMAT_ATTR(xp, "config:0-7"); 241 static CCN_FORMAT_ATTR(type, "config:8-15"); 242 static CCN_FORMAT_ATTR(event, "config:16-23"); 243 static CCN_FORMAT_ATTR(port, "config:24-25"); 244 static CCN_FORMAT_ATTR(bus, "config:24-25"); 245 static CCN_FORMAT_ATTR(vc, "config:26-28"); 246 static CCN_FORMAT_ATTR(dir, "config:29-29"); 247 static CCN_FORMAT_ATTR(mask, "config:30-33"); 248 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62"); 249 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59"); 250 251 static struct attribute *arm_ccn_pmu_format_attrs[] = { 252 &arm_ccn_pmu_format_attr_node.attr.attr, 253 &arm_ccn_pmu_format_attr_xp.attr.attr, 254 &arm_ccn_pmu_format_attr_type.attr.attr, 255 &arm_ccn_pmu_format_attr_event.attr.attr, 256 &arm_ccn_pmu_format_attr_port.attr.attr, 257 &arm_ccn_pmu_format_attr_bus.attr.attr, 258 &arm_ccn_pmu_format_attr_vc.attr.attr, 259 &arm_ccn_pmu_format_attr_dir.attr.attr, 260 &arm_ccn_pmu_format_attr_mask.attr.attr, 261 &arm_ccn_pmu_format_attr_cmp_l.attr.attr, 262 &arm_ccn_pmu_format_attr_cmp_h.attr.attr, 263 NULL 264 }; 265 266 static const struct attribute_group arm_ccn_pmu_format_attr_group = { 267 .name = "format", 268 .attrs = arm_ccn_pmu_format_attrs, 269 }; 270 271 272 struct arm_ccn_pmu_event { 273 struct device_attribute attr; 274 u32 type; 275 u32 event; 276 int num_ports; 277 int num_vcs; 278 const char *def; 279 int mask; 280 }; 281 282 #define CCN_EVENT_ATTR(_name) \ 283 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL) 284 285 /* 286 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on 287 * their ports in XP they are connected to. For the sake of usability they are 288 * explicitly defined here (and translated into a relevant watchpoint in 289 * arm_ccn_pmu_event_init()) so the user can easily request them without deep 290 * knowledge of the flit format. 291 */ 292 293 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \ 294 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \ 295 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \ 296 .def = _def, .mask = _mask, } 297 298 #define CCN_EVENT_HNI(_name, _def, _mask) { \ 299 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \ 300 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ 301 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } 302 303 #define CCN_EVENT_SBSX(_name, _def, _mask) { \ 304 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \ 305 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ 306 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } 307 308 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \ 309 .type = CCN_TYPE_HNF, .event = _event, } 310 311 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \ 312 .type = CCN_TYPE_XP, .event = _event, \ 313 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, } 314 315 /* 316 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending 317 * on configuration. One of them is picked to represent the whole group, 318 * as they all share the same event types. 319 */ 320 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \ 321 .type = CCN_TYPE_RNI_3P, .event = _event, } 322 323 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \ 324 .type = CCN_TYPE_SBAS, .event = _event, } 325 326 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \ 327 .type = CCN_TYPE_CYCLES } 328 329 330 static ssize_t arm_ccn_pmu_event_show(struct device *dev, 331 struct device_attribute *attr, char *buf) 332 { 333 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 334 struct arm_ccn_pmu_event *event = container_of(attr, 335 struct arm_ccn_pmu_event, attr); 336 ssize_t res; 337 338 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type); 339 if (event->event) 340 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x", 341 event->event); 342 if (event->def) 343 res += snprintf(buf + res, PAGE_SIZE - res, ",%s", 344 event->def); 345 if (event->mask) 346 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x", 347 event->mask); 348 349 /* Arguments required by an event */ 350 switch (event->type) { 351 case CCN_TYPE_CYCLES: 352 break; 353 case CCN_TYPE_XP: 354 res += snprintf(buf + res, PAGE_SIZE - res, 355 ",xp=?,vc=?"); 356 if (event->event == CCN_EVENT_WATCHPOINT) 357 res += snprintf(buf + res, PAGE_SIZE - res, 358 ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?"); 359 else 360 res += snprintf(buf + res, PAGE_SIZE - res, 361 ",bus=?"); 362 363 break; 364 case CCN_TYPE_MN: 365 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id); 366 break; 367 default: 368 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?"); 369 break; 370 } 371 372 res += snprintf(buf + res, PAGE_SIZE - res, "\n"); 373 374 return res; 375 } 376 377 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj, 378 struct attribute *attr, int index) 379 { 380 struct device *dev = kobj_to_dev(kobj); 381 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 382 struct device_attribute *dev_attr = container_of(attr, 383 struct device_attribute, attr); 384 struct arm_ccn_pmu_event *event = container_of(dev_attr, 385 struct arm_ccn_pmu_event, attr); 386 387 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present) 388 return 0; 389 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present) 390 return 0; 391 392 return attr->mode; 393 } 394 395 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = { 396 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE), 397 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE), 398 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE), 399 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), 400 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), 401 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), 402 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), 403 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", 404 CCN_IDX_MASK_ORDER), 405 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), 406 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), 407 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), 408 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), 409 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", 410 CCN_IDX_MASK_ORDER), 411 CCN_EVENT_HNF(cache_miss, 0x1), 412 CCN_EVENT_HNF(l3_sf_cache_access, 0x02), 413 CCN_EVENT_HNF(cache_fill, 0x3), 414 CCN_EVENT_HNF(pocq_retry, 0x4), 415 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5), 416 CCN_EVENT_HNF(sf_hit, 0x6), 417 CCN_EVENT_HNF(sf_evictions, 0x7), 418 CCN_EVENT_HNF(snoops_sent, 0x8), 419 CCN_EVENT_HNF(snoops_broadcast, 0x9), 420 CCN_EVENT_HNF(l3_eviction, 0xa), 421 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb), 422 CCN_EVENT_HNF(mc_retries, 0xc), 423 CCN_EVENT_HNF(mc_reqs, 0xd), 424 CCN_EVENT_HNF(qos_hh_retry, 0xe), 425 CCN_EVENT_RNI(rdata_beats_p0, 0x1), 426 CCN_EVENT_RNI(rdata_beats_p1, 0x2), 427 CCN_EVENT_RNI(rdata_beats_p2, 0x3), 428 CCN_EVENT_RNI(rxdat_flits, 0x4), 429 CCN_EVENT_RNI(txdat_flits, 0x5), 430 CCN_EVENT_RNI(txreq_flits, 0x6), 431 CCN_EVENT_RNI(txreq_flits_retried, 0x7), 432 CCN_EVENT_RNI(rrt_full, 0x8), 433 CCN_EVENT_RNI(wrt_full, 0x9), 434 CCN_EVENT_RNI(txreq_flits_replayed, 0xa), 435 CCN_EVENT_XP(upload_starvation, 0x1), 436 CCN_EVENT_XP(download_starvation, 0x2), 437 CCN_EVENT_XP(respin, 0x3), 438 CCN_EVENT_XP(valid_flit, 0x4), 439 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT), 440 CCN_EVENT_SBAS(rdata_beats_p0, 0x1), 441 CCN_EVENT_SBAS(rxdat_flits, 0x4), 442 CCN_EVENT_SBAS(txdat_flits, 0x5), 443 CCN_EVENT_SBAS(txreq_flits, 0x6), 444 CCN_EVENT_SBAS(txreq_flits_retried, 0x7), 445 CCN_EVENT_SBAS(rrt_full, 0x8), 446 CCN_EVENT_SBAS(wrt_full, 0x9), 447 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa), 448 CCN_EVENT_CYCLES(cycles), 449 }; 450 451 /* Populated in arm_ccn_init() */ 452 static struct attribute 453 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1]; 454 455 static const struct attribute_group arm_ccn_pmu_events_attr_group = { 456 .name = "events", 457 .is_visible = arm_ccn_pmu_events_is_visible, 458 .attrs = arm_ccn_pmu_events_attrs, 459 }; 460 461 462 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name) 463 { 464 unsigned long i; 465 466 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1])) 467 return NULL; 468 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a'; 469 470 switch (name[1]) { 471 case 'l': 472 return &ccn->dt.cmp_mask[i].l; 473 case 'h': 474 return &ccn->dt.cmp_mask[i].h; 475 default: 476 return NULL; 477 } 478 } 479 480 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev, 481 struct device_attribute *attr, char *buf) 482 { 483 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 484 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); 485 486 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL; 487 } 488 489 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev, 490 struct device_attribute *attr, const char *buf, size_t count) 491 { 492 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 493 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); 494 int err = -EINVAL; 495 496 if (mask) 497 err = kstrtoull(buf, 0, mask); 498 499 return err ? err : count; 500 } 501 502 #define CCN_CMP_MASK_ATTR(_name) \ 503 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ 504 __ATTR(_name, S_IRUGO | S_IWUSR, \ 505 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store) 506 507 #define CCN_CMP_MASK_ATTR_RO(_name) \ 508 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ 509 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL) 510 511 static CCN_CMP_MASK_ATTR(0l); 512 static CCN_CMP_MASK_ATTR(0h); 513 static CCN_CMP_MASK_ATTR(1l); 514 static CCN_CMP_MASK_ATTR(1h); 515 static CCN_CMP_MASK_ATTR(2l); 516 static CCN_CMP_MASK_ATTR(2h); 517 static CCN_CMP_MASK_ATTR(3l); 518 static CCN_CMP_MASK_ATTR(3h); 519 static CCN_CMP_MASK_ATTR(4l); 520 static CCN_CMP_MASK_ATTR(4h); 521 static CCN_CMP_MASK_ATTR(5l); 522 static CCN_CMP_MASK_ATTR(5h); 523 static CCN_CMP_MASK_ATTR(6l); 524 static CCN_CMP_MASK_ATTR(6h); 525 static CCN_CMP_MASK_ATTR(7l); 526 static CCN_CMP_MASK_ATTR(7h); 527 static CCN_CMP_MASK_ATTR_RO(8l); 528 static CCN_CMP_MASK_ATTR_RO(8h); 529 static CCN_CMP_MASK_ATTR_RO(9l); 530 static CCN_CMP_MASK_ATTR_RO(9h); 531 static CCN_CMP_MASK_ATTR_RO(al); 532 static CCN_CMP_MASK_ATTR_RO(ah); 533 static CCN_CMP_MASK_ATTR_RO(bl); 534 static CCN_CMP_MASK_ATTR_RO(bh); 535 536 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = { 537 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr, 538 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr, 539 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr, 540 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr, 541 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr, 542 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr, 543 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr, 544 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr, 545 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr, 546 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr, 547 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr, 548 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr, 549 NULL 550 }; 551 552 static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { 553 .name = "cmp_mask", 554 .attrs = arm_ccn_pmu_cmp_mask_attrs, 555 }; 556 557 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev, 558 struct device_attribute *attr, char *buf) 559 { 560 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 561 562 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu); 563 } 564 565 static struct device_attribute arm_ccn_pmu_cpumask_attr = 566 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL); 567 568 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = { 569 &arm_ccn_pmu_cpumask_attr.attr, 570 NULL, 571 }; 572 573 static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = { 574 .attrs = arm_ccn_pmu_cpumask_attrs, 575 }; 576 577 /* 578 * Default poll period is 10ms, which is way over the top anyway, 579 * as in the worst case scenario (an event every cycle), with 1GHz 580 * clocked bus, the smallest, 32 bit counter will overflow in 581 * more than 4s. 582 */ 583 static unsigned int arm_ccn_pmu_poll_period_us = 10000; 584 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint, 585 S_IRUGO | S_IWUSR); 586 587 static ktime_t arm_ccn_pmu_timer_period(void) 588 { 589 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000); 590 } 591 592 593 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = { 594 &arm_ccn_pmu_events_attr_group, 595 &arm_ccn_pmu_format_attr_group, 596 &arm_ccn_pmu_cmp_mask_attr_group, 597 &arm_ccn_pmu_cpumask_attr_group, 598 NULL 599 }; 600 601 602 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size) 603 { 604 int bit; 605 606 do { 607 bit = find_first_zero_bit(bitmap, size); 608 if (bit >= size) 609 return -EAGAIN; 610 } while (test_and_set_bit(bit, bitmap)); 611 612 return bit; 613 } 614 615 /* All RN-I and RN-D nodes have identical PMUs */ 616 static int arm_ccn_pmu_type_eq(u32 a, u32 b) 617 { 618 if (a == b) 619 return 1; 620 621 switch (a) { 622 case CCN_TYPE_RNI_1P: 623 case CCN_TYPE_RNI_2P: 624 case CCN_TYPE_RNI_3P: 625 case CCN_TYPE_RND_1P: 626 case CCN_TYPE_RND_2P: 627 case CCN_TYPE_RND_3P: 628 switch (b) { 629 case CCN_TYPE_RNI_1P: 630 case CCN_TYPE_RNI_2P: 631 case CCN_TYPE_RNI_3P: 632 case CCN_TYPE_RND_1P: 633 case CCN_TYPE_RND_2P: 634 case CCN_TYPE_RND_3P: 635 return 1; 636 } 637 break; 638 } 639 640 return 0; 641 } 642 643 static int arm_ccn_pmu_event_alloc(struct perf_event *event) 644 { 645 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 646 struct hw_perf_event *hw = &event->hw; 647 u32 node_xp, type, event_id; 648 struct arm_ccn_component *source; 649 int bit; 650 651 node_xp = CCN_CONFIG_NODE(event->attr.config); 652 type = CCN_CONFIG_TYPE(event->attr.config); 653 event_id = CCN_CONFIG_EVENT(event->attr.config); 654 655 /* Allocate the cycle counter */ 656 if (type == CCN_TYPE_CYCLES) { 657 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER, 658 ccn->dt.pmu_counters_mask)) 659 return -EAGAIN; 660 661 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER; 662 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; 663 664 return 0; 665 } 666 667 /* Allocate an event counter */ 668 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, 669 CCN_NUM_PMU_EVENT_COUNTERS); 670 if (hw->idx < 0) { 671 dev_dbg(ccn->dev, "No more counters available!\n"); 672 return -EAGAIN; 673 } 674 675 if (type == CCN_TYPE_XP) 676 source = &ccn->xp[node_xp]; 677 else 678 source = &ccn->node[node_xp]; 679 ccn->dt.pmu_counters[hw->idx].source = source; 680 681 /* Allocate an event source or a watchpoint */ 682 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT) 683 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask, 684 CCN_NUM_XP_WATCHPOINTS); 685 else 686 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask, 687 CCN_NUM_PMU_EVENTS); 688 if (bit < 0) { 689 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n", 690 node_xp); 691 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); 692 return -EAGAIN; 693 } 694 hw->config_base = bit; 695 696 ccn->dt.pmu_counters[hw->idx].event = event; 697 698 return 0; 699 } 700 701 static void arm_ccn_pmu_event_release(struct perf_event *event) 702 { 703 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 704 struct hw_perf_event *hw = &event->hw; 705 706 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) { 707 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); 708 } else { 709 struct arm_ccn_component *source = 710 ccn->dt.pmu_counters[hw->idx].source; 711 712 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP && 713 CCN_CONFIG_EVENT(event->attr.config) == 714 CCN_EVENT_WATCHPOINT) 715 clear_bit(hw->config_base, source->xp.dt_cmp_mask); 716 else 717 clear_bit(hw->config_base, source->pmu_events_mask); 718 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); 719 } 720 721 ccn->dt.pmu_counters[hw->idx].source = NULL; 722 ccn->dt.pmu_counters[hw->idx].event = NULL; 723 } 724 725 static int arm_ccn_pmu_event_init(struct perf_event *event) 726 { 727 struct arm_ccn *ccn; 728 struct hw_perf_event *hw = &event->hw; 729 u32 node_xp, type, event_id; 730 int valid; 731 int i; 732 struct perf_event *sibling; 733 734 if (event->attr.type != event->pmu->type) 735 return -ENOENT; 736 737 ccn = pmu_to_arm_ccn(event->pmu); 738 739 if (hw->sample_period) { 740 dev_dbg(ccn->dev, "Sampling not supported!\n"); 741 return -EOPNOTSUPP; 742 } 743 744 if (has_branch_stack(event) || event->attr.exclude_user || 745 event->attr.exclude_kernel || event->attr.exclude_hv || 746 event->attr.exclude_idle || event->attr.exclude_host || 747 event->attr.exclude_guest) { 748 dev_dbg(ccn->dev, "Can't exclude execution levels!\n"); 749 return -EINVAL; 750 } 751 752 if (event->cpu < 0) { 753 dev_dbg(ccn->dev, "Can't provide per-task data!\n"); 754 return -EOPNOTSUPP; 755 } 756 /* 757 * Many perf core operations (eg. events rotation) operate on a 758 * single CPU context. This is obvious for CPU PMUs, where one 759 * expects the same sets of events being observed on all CPUs, 760 * but can lead to issues for off-core PMUs, like CCN, where each 761 * event could be theoretically assigned to a different CPU. To 762 * mitigate this, we enforce CPU assignment to one, selected 763 * processor (the one described in the "cpumask" attribute). 764 */ 765 event->cpu = cpumask_first(&ccn->dt.cpu); 766 767 node_xp = CCN_CONFIG_NODE(event->attr.config); 768 type = CCN_CONFIG_TYPE(event->attr.config); 769 event_id = CCN_CONFIG_EVENT(event->attr.config); 770 771 /* Validate node/xp vs topology */ 772 switch (type) { 773 case CCN_TYPE_MN: 774 if (node_xp != ccn->mn_id) { 775 dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp); 776 return -EINVAL; 777 } 778 break; 779 case CCN_TYPE_XP: 780 if (node_xp >= ccn->num_xps) { 781 dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp); 782 return -EINVAL; 783 } 784 break; 785 case CCN_TYPE_CYCLES: 786 break; 787 default: 788 if (node_xp >= ccn->num_nodes) { 789 dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp); 790 return -EINVAL; 791 } 792 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) { 793 dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n", 794 type, node_xp); 795 return -EINVAL; 796 } 797 break; 798 } 799 800 /* Validate event ID vs available for the type */ 801 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid; 802 i++) { 803 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i]; 804 u32 port = CCN_CONFIG_PORT(event->attr.config); 805 u32 vc = CCN_CONFIG_VC(event->attr.config); 806 807 if (!arm_ccn_pmu_type_eq(type, e->type)) 808 continue; 809 if (event_id != e->event) 810 continue; 811 if (e->num_ports && port >= e->num_ports) { 812 dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n", 813 port, node_xp); 814 return -EINVAL; 815 } 816 if (e->num_vcs && vc >= e->num_vcs) { 817 dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n", 818 vc, node_xp); 819 return -EINVAL; 820 } 821 valid = 1; 822 } 823 if (!valid) { 824 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n", 825 event_id, node_xp); 826 return -EINVAL; 827 } 828 829 /* Watchpoint-based event for a node is actually set on XP */ 830 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) { 831 u32 port; 832 833 type = CCN_TYPE_XP; 834 port = arm_ccn_node_to_xp_port(node_xp); 835 node_xp = arm_ccn_node_to_xp(node_xp); 836 837 arm_ccn_pmu_config_set(&event->attr.config, 838 node_xp, type, port); 839 } 840 841 /* 842 * We must NOT create groups containing mixed PMUs, although software 843 * events are acceptable (for example to create a CCN group 844 * periodically read when a hrtimer aka cpu-clock leader triggers). 845 */ 846 if (event->group_leader->pmu != event->pmu && 847 !is_software_event(event->group_leader)) 848 return -EINVAL; 849 850 for_each_sibling_event(sibling, event->group_leader) { 851 if (sibling->pmu != event->pmu && 852 !is_software_event(sibling)) 853 return -EINVAL; 854 } 855 856 return 0; 857 } 858 859 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx) 860 { 861 u64 res; 862 863 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) { 864 #ifdef readq 865 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); 866 #else 867 /* 40 bit counter, can do snapshot and read in two parts */ 868 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); 869 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) 870 ; 871 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); 872 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; 873 res <<= 32; 874 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); 875 #endif 876 } else { 877 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); 878 } 879 880 return res; 881 } 882 883 static void arm_ccn_pmu_event_update(struct perf_event *event) 884 { 885 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 886 struct hw_perf_event *hw = &event->hw; 887 u64 prev_count, new_count, mask; 888 889 do { 890 prev_count = local64_read(&hw->prev_count); 891 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx); 892 } while (local64_xchg(&hw->prev_count, new_count) != prev_count); 893 894 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; 895 896 local64_add((new_count - prev_count) & mask, &event->count); 897 } 898 899 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable) 900 { 901 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 902 struct hw_perf_event *hw = &event->hw; 903 struct arm_ccn_component *xp; 904 u32 val, dt_cfg; 905 906 /* Nothing to do for cycle counter */ 907 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) 908 return; 909 910 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) 911 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)]; 912 else 913 xp = &ccn->xp[arm_ccn_node_to_xp( 914 CCN_CONFIG_NODE(event->attr.config))]; 915 916 if (enable) 917 dt_cfg = hw->event_base; 918 else 919 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH; 920 921 spin_lock(&ccn->dt.config_lock); 922 923 val = readl(xp->base + CCN_XP_DT_CONFIG); 924 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK << 925 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx)); 926 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); 927 writel(val, xp->base + CCN_XP_DT_CONFIG); 928 929 spin_unlock(&ccn->dt.config_lock); 930 } 931 932 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags) 933 { 934 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 935 struct hw_perf_event *hw = &event->hw; 936 937 local64_set(&event->hw.prev_count, 938 arm_ccn_pmu_read_counter(ccn, hw->idx)); 939 hw->state = 0; 940 941 /* Set the DT bus input, engaging the counter */ 942 arm_ccn_pmu_xp_dt_config(event, 1); 943 } 944 945 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags) 946 { 947 struct hw_perf_event *hw = &event->hw; 948 949 /* Disable counting, setting the DT bus to pass-through mode */ 950 arm_ccn_pmu_xp_dt_config(event, 0); 951 952 if (flags & PERF_EF_UPDATE) 953 arm_ccn_pmu_event_update(event); 954 955 hw->state |= PERF_HES_STOPPED; 956 } 957 958 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event) 959 { 960 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 961 struct hw_perf_event *hw = &event->hw; 962 struct arm_ccn_component *source = 963 ccn->dt.pmu_counters[hw->idx].source; 964 unsigned long wp = hw->config_base; 965 u32 val; 966 u64 cmp_l = event->attr.config1; 967 u64 cmp_h = event->attr.config2; 968 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; 969 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; 970 971 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); 972 973 /* Direction (RX/TX), device (port) & virtual channel */ 974 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); 975 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK << 976 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp)); 977 val |= CCN_CONFIG_DIR(event->attr.config) << 978 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp); 979 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK << 980 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp)); 981 val |= CCN_CONFIG_PORT(event->attr.config) << 982 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp); 983 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK << 984 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp)); 985 val |= CCN_CONFIG_VC(event->attr.config) << 986 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp); 987 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); 988 989 /* Comparison values */ 990 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); 991 writel((cmp_l >> 32) & 0x7fffffff, 992 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); 993 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); 994 writel((cmp_h >> 32) & 0x0fffffff, 995 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); 996 997 /* Mask */ 998 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); 999 writel((mask_l >> 32) & 0x7fffffff, 1000 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); 1001 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); 1002 writel((mask_h >> 32) & 0x0fffffff, 1003 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); 1004 } 1005 1006 static void arm_ccn_pmu_xp_event_config(struct perf_event *event) 1007 { 1008 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1009 struct hw_perf_event *hw = &event->hw; 1010 struct arm_ccn_component *source = 1011 ccn->dt.pmu_counters[hw->idx].source; 1012 u32 val, id; 1013 1014 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); 1015 1016 id = (CCN_CONFIG_VC(event->attr.config) << 4) | 1017 (CCN_CONFIG_BUS(event->attr.config) << 3) | 1018 (CCN_CONFIG_EVENT(event->attr.config) << 0); 1019 1020 val = readl(source->base + CCN_XP_PMU_EVENT_SEL); 1021 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK << 1022 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); 1023 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); 1024 writel(val, source->base + CCN_XP_PMU_EVENT_SEL); 1025 } 1026 1027 static void arm_ccn_pmu_node_event_config(struct perf_event *event) 1028 { 1029 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1030 struct hw_perf_event *hw = &event->hw; 1031 struct arm_ccn_component *source = 1032 ccn->dt.pmu_counters[hw->idx].source; 1033 u32 type = CCN_CONFIG_TYPE(event->attr.config); 1034 u32 val, port; 1035 1036 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config)); 1037 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, 1038 hw->config_base); 1039 1040 /* These *_event_sel regs should be identical, but let's make sure... */ 1041 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL); 1042 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL); 1043 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) != 1044 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1)); 1045 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) != 1046 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1)); 1047 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK != 1048 CCN_SBAS_PMU_EVENT_SEL__ID__MASK); 1049 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK != 1050 CCN_RNI_PMU_EVENT_SEL__ID__MASK); 1051 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS && 1052 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P))) 1053 return; 1054 1055 /* Set the event id for the pre-allocated counter */ 1056 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); 1057 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK << 1058 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); 1059 val |= CCN_CONFIG_EVENT(event->attr.config) << 1060 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); 1061 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); 1062 } 1063 1064 static void arm_ccn_pmu_event_config(struct perf_event *event) 1065 { 1066 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1067 struct hw_perf_event *hw = &event->hw; 1068 u32 xp, offset, val; 1069 1070 /* Cycle counter requires no setup */ 1071 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) 1072 return; 1073 1074 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) 1075 xp = CCN_CONFIG_XP(event->attr.config); 1076 else 1077 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config)); 1078 1079 spin_lock(&ccn->dt.config_lock); 1080 1081 /* Set the DT bus "distance" register */ 1082 offset = (hw->idx / 4) * 4; 1083 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); 1084 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK << 1085 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4)); 1086 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); 1087 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); 1088 1089 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) { 1090 if (CCN_CONFIG_EVENT(event->attr.config) == 1091 CCN_EVENT_WATCHPOINT) 1092 arm_ccn_pmu_xp_watchpoint_config(event); 1093 else 1094 arm_ccn_pmu_xp_event_config(event); 1095 } else { 1096 arm_ccn_pmu_node_event_config(event); 1097 } 1098 1099 spin_unlock(&ccn->dt.config_lock); 1100 } 1101 1102 static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn) 1103 { 1104 return bitmap_weight(ccn->dt.pmu_counters_mask, 1105 CCN_NUM_PMU_EVENT_COUNTERS + 1); 1106 } 1107 1108 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags) 1109 { 1110 int err; 1111 struct hw_perf_event *hw = &event->hw; 1112 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1113 1114 err = arm_ccn_pmu_event_alloc(event); 1115 if (err) 1116 return err; 1117 1118 /* 1119 * Pin the timer, so that the overflows are handled by the chosen 1120 * event->cpu (this is the same one as presented in "cpumask" 1121 * attribute). 1122 */ 1123 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1) 1124 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), 1125 HRTIMER_MODE_REL_PINNED); 1126 1127 arm_ccn_pmu_event_config(event); 1128 1129 hw->state = PERF_HES_STOPPED; 1130 1131 if (flags & PERF_EF_START) 1132 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE); 1133 1134 return 0; 1135 } 1136 1137 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags) 1138 { 1139 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1140 1141 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE); 1142 1143 arm_ccn_pmu_event_release(event); 1144 1145 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0) 1146 hrtimer_cancel(&ccn->dt.hrtimer); 1147 } 1148 1149 static void arm_ccn_pmu_event_read(struct perf_event *event) 1150 { 1151 arm_ccn_pmu_event_update(event); 1152 } 1153 1154 static void arm_ccn_pmu_enable(struct pmu *pmu) 1155 { 1156 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); 1157 1158 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); 1159 val |= CCN_DT_PMCR__PMU_EN; 1160 writel(val, ccn->dt.base + CCN_DT_PMCR); 1161 } 1162 1163 static void arm_ccn_pmu_disable(struct pmu *pmu) 1164 { 1165 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); 1166 1167 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); 1168 val &= ~CCN_DT_PMCR__PMU_EN; 1169 writel(val, ccn->dt.base + CCN_DT_PMCR); 1170 } 1171 1172 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) 1173 { 1174 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); 1175 int idx; 1176 1177 if (!pmovsr) 1178 return IRQ_NONE; 1179 1180 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); 1181 1182 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS); 1183 1184 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) { 1185 struct perf_event *event = dt->pmu_counters[idx].event; 1186 int overflowed = pmovsr & BIT(idx); 1187 1188 WARN_ON_ONCE(overflowed && !event && 1189 idx != CCN_IDX_PMU_CYCLE_COUNTER); 1190 1191 if (!event || !overflowed) 1192 continue; 1193 1194 arm_ccn_pmu_event_update(event); 1195 } 1196 1197 return IRQ_HANDLED; 1198 } 1199 1200 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer) 1201 { 1202 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, 1203 hrtimer); 1204 unsigned long flags; 1205 1206 local_irq_save(flags); 1207 arm_ccn_pmu_overflow_handler(dt); 1208 local_irq_restore(flags); 1209 1210 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period()); 1211 return HRTIMER_RESTART; 1212 } 1213 1214 1215 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) 1216 { 1217 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); 1218 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); 1219 unsigned int target; 1220 1221 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) 1222 return 0; 1223 target = cpumask_any_but(cpu_online_mask, cpu); 1224 if (target >= nr_cpu_ids) 1225 return 0; 1226 perf_pmu_migrate_context(&dt->pmu, cpu, target); 1227 cpumask_set_cpu(target, &dt->cpu); 1228 if (ccn->irq) 1229 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0); 1230 return 0; 1231 } 1232 1233 static DEFINE_IDA(arm_ccn_pmu_ida); 1234 1235 static int arm_ccn_pmu_init(struct arm_ccn *ccn) 1236 { 1237 int i; 1238 char *name; 1239 int err; 1240 1241 /* Initialize DT subsystem */ 1242 ccn->dt.base = ccn->base + CCN_REGION_SIZE; 1243 spin_lock_init(&ccn->dt.config_lock); 1244 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); 1245 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); 1246 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN, 1247 ccn->dt.base + CCN_DT_PMCR); 1248 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); 1249 for (i = 0; i < ccn->num_xps; i++) { 1250 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); 1251 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << 1252 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) | 1253 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << 1254 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) | 1255 CCN_XP_DT_CONTROL__DT_ENABLE, 1256 ccn->xp[i].base + CCN_XP_DT_CONTROL); 1257 } 1258 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; 1259 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; 1260 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; 1261 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; 1262 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; 1263 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); 1264 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; 1265 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); 1266 1267 /* Get a convenient /sys/event_source/devices/ name */ 1268 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL); 1269 if (ccn->dt.id == 0) { 1270 name = "ccn"; 1271 } else { 1272 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", 1273 ccn->dt.id); 1274 if (!name) { 1275 err = -ENOMEM; 1276 goto error_choose_name; 1277 } 1278 } 1279 1280 /* Perf driver registration */ 1281 ccn->dt.pmu = (struct pmu) { 1282 .module = THIS_MODULE, 1283 .attr_groups = arm_ccn_pmu_attr_groups, 1284 .task_ctx_nr = perf_invalid_context, 1285 .event_init = arm_ccn_pmu_event_init, 1286 .add = arm_ccn_pmu_event_add, 1287 .del = arm_ccn_pmu_event_del, 1288 .start = arm_ccn_pmu_event_start, 1289 .stop = arm_ccn_pmu_event_stop, 1290 .read = arm_ccn_pmu_event_read, 1291 .pmu_enable = arm_ccn_pmu_enable, 1292 .pmu_disable = arm_ccn_pmu_disable, 1293 }; 1294 1295 /* No overflow interrupt? Have to use a timer instead. */ 1296 if (!ccn->irq) { 1297 dev_info(ccn->dev, "No access to interrupts, using timer.\n"); 1298 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, 1299 HRTIMER_MODE_REL); 1300 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; 1301 } 1302 1303 /* Pick one CPU which we will use to collect data from CCN... */ 1304 cpumask_set_cpu(get_cpu(), &ccn->dt.cpu); 1305 1306 /* Also make sure that the overflow interrupt is handled by this CPU */ 1307 if (ccn->irq) { 1308 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu); 1309 if (err) { 1310 dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); 1311 goto error_set_affinity; 1312 } 1313 } 1314 1315 err = perf_pmu_register(&ccn->dt.pmu, name, -1); 1316 if (err) 1317 goto error_pmu_register; 1318 1319 cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, 1320 &ccn->dt.node); 1321 put_cpu(); 1322 return 0; 1323 1324 error_pmu_register: 1325 error_set_affinity: 1326 put_cpu(); 1327 error_choose_name: 1328 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); 1329 for (i = 0; i < ccn->num_xps; i++) 1330 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); 1331 writel(0, ccn->dt.base + CCN_DT_PMCR); 1332 return err; 1333 } 1334 1335 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn) 1336 { 1337 int i; 1338 1339 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, 1340 &ccn->dt.node); 1341 if (ccn->irq) 1342 irq_set_affinity_hint(ccn->irq, NULL); 1343 for (i = 0; i < ccn->num_xps; i++) 1344 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); 1345 writel(0, ccn->dt.base + CCN_DT_PMCR); 1346 perf_pmu_unregister(&ccn->dt.pmu); 1347 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); 1348 } 1349 1350 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn, 1351 int (*callback)(struct arm_ccn *ccn, int region, 1352 void __iomem *base, u32 type, u32 id)) 1353 { 1354 int region; 1355 1356 for (region = 0; region < CCN_NUM_REGIONS; region++) { 1357 u32 val, type, id; 1358 void __iomem *base; 1359 int err; 1360 1361 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + 1362 4 * (region / 32)); 1363 if (!(val & (1 << (region % 32)))) 1364 continue; 1365 1366 base = ccn->base + region * CCN_REGION_SIZE; 1367 val = readl(base + CCN_ALL_OLY_ID); 1368 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) & 1369 CCN_ALL_OLY_ID__OLY_ID__MASK; 1370 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) & 1371 CCN_ALL_OLY_ID__NODE_ID__MASK; 1372 1373 err = callback(ccn, region, base, type, id); 1374 if (err) 1375 return err; 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region, 1382 void __iomem *base, u32 type, u32 id) 1383 { 1384 1385 if (type == CCN_TYPE_XP && id >= ccn->num_xps) 1386 ccn->num_xps = id + 1; 1387 else if (id >= ccn->num_nodes) 1388 ccn->num_nodes = id + 1; 1389 1390 return 0; 1391 } 1392 1393 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region, 1394 void __iomem *base, u32 type, u32 id) 1395 { 1396 struct arm_ccn_component *component; 1397 1398 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type); 1399 1400 switch (type) { 1401 case CCN_TYPE_MN: 1402 ccn->mn_id = id; 1403 return 0; 1404 case CCN_TYPE_DT: 1405 return 0; 1406 case CCN_TYPE_XP: 1407 component = &ccn->xp[id]; 1408 break; 1409 case CCN_TYPE_SBSX: 1410 ccn->sbsx_present = 1; 1411 component = &ccn->node[id]; 1412 break; 1413 case CCN_TYPE_SBAS: 1414 ccn->sbas_present = 1; 1415 /* Fall-through */ 1416 default: 1417 component = &ccn->node[id]; 1418 break; 1419 } 1420 1421 component->base = base; 1422 component->type = type; 1423 1424 return 0; 1425 } 1426 1427 1428 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn, 1429 const u32 *err_sig_val) 1430 { 1431 /* This should be really handled by firmware... */ 1432 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n", 1433 err_sig_val[5], err_sig_val[4], err_sig_val[3], 1434 err_sig_val[2], err_sig_val[1], err_sig_val[0]); 1435 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n"); 1436 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE, 1437 ccn->base + CCN_MN_ERRINT_STATUS); 1438 1439 return IRQ_HANDLED; 1440 } 1441 1442 1443 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id) 1444 { 1445 irqreturn_t res = IRQ_NONE; 1446 struct arm_ccn *ccn = dev_id; 1447 u32 err_sig_val[6]; 1448 u32 err_or; 1449 int i; 1450 1451 /* PMU overflow is a special case */ 1452 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); 1453 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) { 1454 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT; 1455 res = arm_ccn_pmu_overflow_handler(&ccn->dt); 1456 } 1457 1458 /* Have to read all err_sig_vals to clear them */ 1459 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) { 1460 err_sig_val[i] = readl(ccn->base + 1461 CCN_MN_ERR_SIG_VAL_63_0 + i * 4); 1462 err_or |= err_sig_val[i]; 1463 } 1464 if (err_or) 1465 res |= arm_ccn_error_handler(ccn, err_sig_val); 1466 1467 if (res != IRQ_NONE) 1468 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT, 1469 ccn->base + CCN_MN_ERRINT_STATUS); 1470 1471 return res; 1472 } 1473 1474 1475 static int arm_ccn_probe(struct platform_device *pdev) 1476 { 1477 struct arm_ccn *ccn; 1478 struct resource *res; 1479 unsigned int irq; 1480 int err; 1481 1482 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); 1483 if (!ccn) 1484 return -ENOMEM; 1485 ccn->dev = &pdev->dev; 1486 platform_set_drvdata(pdev, ccn); 1487 1488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1489 ccn->base = devm_ioremap_resource(ccn->dev, res); 1490 if (IS_ERR(ccn->base)) 1491 return PTR_ERR(ccn->base); 1492 1493 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1494 if (!res) 1495 return -EINVAL; 1496 irq = res->start; 1497 1498 /* Check if we can use the interrupt */ 1499 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE, 1500 ccn->base + CCN_MN_ERRINT_STATUS); 1501 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & 1502 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) { 1503 /* Can set 'disable' bits, so can acknowledge interrupts */ 1504 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE, 1505 ccn->base + CCN_MN_ERRINT_STATUS); 1506 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 1507 IRQF_NOBALANCING | IRQF_NO_THREAD, 1508 dev_name(ccn->dev), ccn); 1509 if (err) 1510 return err; 1511 1512 ccn->irq = irq; 1513 } 1514 1515 1516 /* Build topology */ 1517 1518 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num); 1519 if (err) 1520 return err; 1521 1522 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node), 1523 GFP_KERNEL); 1524 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node), 1525 GFP_KERNEL); 1526 if (!ccn->node || !ccn->xp) 1527 return -ENOMEM; 1528 1529 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes); 1530 if (err) 1531 return err; 1532 1533 return arm_ccn_pmu_init(ccn); 1534 } 1535 1536 static int arm_ccn_remove(struct platform_device *pdev) 1537 { 1538 struct arm_ccn *ccn = platform_get_drvdata(pdev); 1539 1540 arm_ccn_pmu_cleanup(ccn); 1541 1542 return 0; 1543 } 1544 1545 static const struct of_device_id arm_ccn_match[] = { 1546 { .compatible = "arm,ccn-502", }, 1547 { .compatible = "arm,ccn-504", }, 1548 {}, 1549 }; 1550 MODULE_DEVICE_TABLE(of, arm_ccn_match); 1551 1552 static struct platform_driver arm_ccn_driver = { 1553 .driver = { 1554 .name = "arm-ccn", 1555 .of_match_table = arm_ccn_match, 1556 }, 1557 .probe = arm_ccn_probe, 1558 .remove = arm_ccn_remove, 1559 }; 1560 1561 static int __init arm_ccn_init(void) 1562 { 1563 int i, ret; 1564 1565 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE, 1566 "perf/arm/ccn:online", NULL, 1567 arm_ccn_pmu_offline_cpu); 1568 if (ret) 1569 return ret; 1570 1571 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++) 1572 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr; 1573 1574 ret = platform_driver_register(&arm_ccn_driver); 1575 if (ret) 1576 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); 1577 return ret; 1578 } 1579 1580 static void __exit arm_ccn_exit(void) 1581 { 1582 platform_driver_unregister(&arm_ccn_driver); 1583 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); 1584 } 1585 1586 module_init(arm_ccn_init); 1587 module_exit(arm_ccn_exit); 1588 1589 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>"); 1590 MODULE_LICENSE("GPL v2"); 1591