1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License version 2 as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * Copyright (C) 2014 ARM Limited 12 */ 13 14 #include <linux/ctype.h> 15 #include <linux/hrtimer.h> 16 #include <linux/idr.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/perf_event.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 24 #define CCN_NUM_XP_PORTS 2 25 #define CCN_NUM_VCS 4 26 #define CCN_NUM_REGIONS 256 27 #define CCN_REGION_SIZE 0x10000 28 29 #define CCN_ALL_OLY_ID 0xff00 30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0 31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f 32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8 33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f 34 35 #define CCN_MN_ERRINT_STATUS 0x0008 36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11 37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02 38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20 39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22 40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04 41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40 42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44 43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08 44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80 45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88 46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0 47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300 48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1) 49 50 #define CCN_DT_ACTIVE_DSM 0x0000 51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8) 52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff 53 #define CCN_DT_CTL 0x0028 54 #define CCN_DT_CTL__DT_EN (1 << 0) 55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8) 56 #define CCN_DT_PMCCNTR 0x0140 57 #define CCN_DT_PMCCNTRSR 0x0190 58 #define CCN_DT_PMOVSR 0x0198 59 #define CCN_DT_PMOVSR_CLR 0x01a0 60 #define CCN_DT_PMOVSR_CLR__MASK 0x1f 61 #define CCN_DT_PMCR 0x01a8 62 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6) 63 #define CCN_DT_PMCR__PMU_EN (1 << 0) 64 #define CCN_DT_PMSR 0x01b0 65 #define CCN_DT_PMSR_REQ 0x01b8 66 #define CCN_DT_PMSR_CLR 0x01c0 67 68 #define CCN_HNF_PMU_EVENT_SEL 0x0600 69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) 70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf 71 72 #define CCN_XP_DT_CONFIG 0x0300 73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4) 74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf 75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0 76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1 77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n)) 78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n)) 79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n)) 80 #define CCN_XP_DT_INTERFACE_SEL 0x0308 81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8) 82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1 83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8) 84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1 85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8) 86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3 87 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40) 88 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40) 89 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40) 90 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40) 91 #define CCN_XP_DT_CONTROL 0x0370 92 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0) 93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4) 94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf 95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf 96 #define CCN_XP_PMU_EVENT_SEL 0x0600 97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7) 98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f 99 100 #define CCN_SBAS_PMU_EVENT_SEL 0x0600 101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) 102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf 103 104 #define CCN_RNI_PMU_EVENT_SEL 0x0600 105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) 106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf 107 108 #define CCN_TYPE_MN 0x01 109 #define CCN_TYPE_DT 0x02 110 #define CCN_TYPE_HNF 0x04 111 #define CCN_TYPE_HNI 0x05 112 #define CCN_TYPE_XP 0x08 113 #define CCN_TYPE_SBSX 0x0c 114 #define CCN_TYPE_SBAS 0x10 115 #define CCN_TYPE_RNI_1P 0x14 116 #define CCN_TYPE_RNI_2P 0x15 117 #define CCN_TYPE_RNI_3P 0x16 118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */ 119 #define CCN_TYPE_RND_2P 0x19 120 #define CCN_TYPE_RND_3P 0x1a 121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */ 122 123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */ 124 125 #define CCN_NUM_PMU_EVENTS 4 126 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */ 127 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */ 128 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS 129 130 #define CCN_NUM_PREDEFINED_MASKS 4 131 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0) 132 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1) 133 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2) 134 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3) 135 136 struct arm_ccn_component { 137 void __iomem *base; 138 u32 type; 139 140 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS); 141 union { 142 struct { 143 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS); 144 } xp; 145 }; 146 }; 147 148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \ 149 struct arm_ccn_dt, pmu), struct arm_ccn, dt) 150 151 struct arm_ccn_dt { 152 int id; 153 void __iomem *base; 154 155 spinlock_t config_lock; 156 157 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1); 158 struct { 159 struct arm_ccn_component *source; 160 struct perf_event *event; 161 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1]; 162 163 struct { 164 u64 l, h; 165 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS]; 166 167 struct hrtimer hrtimer; 168 169 cpumask_t cpu; 170 struct hlist_node node; 171 172 struct pmu pmu; 173 }; 174 175 struct arm_ccn { 176 struct device *dev; 177 void __iomem *base; 178 unsigned int irq; 179 180 unsigned sbas_present:1; 181 unsigned sbsx_present:1; 182 183 int num_nodes; 184 struct arm_ccn_component *node; 185 186 int num_xps; 187 struct arm_ccn_component *xp; 188 189 struct arm_ccn_dt dt; 190 int mn_id; 191 }; 192 193 static int arm_ccn_node_to_xp(int node) 194 { 195 return node / CCN_NUM_XP_PORTS; 196 } 197 198 static int arm_ccn_node_to_xp_port(int node) 199 { 200 return node % CCN_NUM_XP_PORTS; 201 } 202 203 204 /* 205 * Bit shifts and masks in these defines must be kept in sync with 206 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below! 207 */ 208 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff) 209 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff) 210 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff) 211 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff) 212 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3) 213 #define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3) 214 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7) 215 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1) 216 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf) 217 218 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port) 219 { 220 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24)); 221 *config |= (node_xp << 0) | (type << 8) | (port << 24); 222 } 223 224 static ssize_t arm_ccn_pmu_format_show(struct device *dev, 225 struct device_attribute *attr, char *buf) 226 { 227 struct dev_ext_attribute *ea = container_of(attr, 228 struct dev_ext_attribute, attr); 229 230 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var); 231 } 232 233 #define CCN_FORMAT_ATTR(_name, _config) \ 234 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \ 235 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \ 236 NULL), _config } 237 238 static CCN_FORMAT_ATTR(node, "config:0-7"); 239 static CCN_FORMAT_ATTR(xp, "config:0-7"); 240 static CCN_FORMAT_ATTR(type, "config:8-15"); 241 static CCN_FORMAT_ATTR(event, "config:16-23"); 242 static CCN_FORMAT_ATTR(port, "config:24-25"); 243 static CCN_FORMAT_ATTR(bus, "config:24-25"); 244 static CCN_FORMAT_ATTR(vc, "config:26-28"); 245 static CCN_FORMAT_ATTR(dir, "config:29-29"); 246 static CCN_FORMAT_ATTR(mask, "config:30-33"); 247 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62"); 248 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59"); 249 250 static struct attribute *arm_ccn_pmu_format_attrs[] = { 251 &arm_ccn_pmu_format_attr_node.attr.attr, 252 &arm_ccn_pmu_format_attr_xp.attr.attr, 253 &arm_ccn_pmu_format_attr_type.attr.attr, 254 &arm_ccn_pmu_format_attr_event.attr.attr, 255 &arm_ccn_pmu_format_attr_port.attr.attr, 256 &arm_ccn_pmu_format_attr_bus.attr.attr, 257 &arm_ccn_pmu_format_attr_vc.attr.attr, 258 &arm_ccn_pmu_format_attr_dir.attr.attr, 259 &arm_ccn_pmu_format_attr_mask.attr.attr, 260 &arm_ccn_pmu_format_attr_cmp_l.attr.attr, 261 &arm_ccn_pmu_format_attr_cmp_h.attr.attr, 262 NULL 263 }; 264 265 static const struct attribute_group arm_ccn_pmu_format_attr_group = { 266 .name = "format", 267 .attrs = arm_ccn_pmu_format_attrs, 268 }; 269 270 271 struct arm_ccn_pmu_event { 272 struct device_attribute attr; 273 u32 type; 274 u32 event; 275 int num_ports; 276 int num_vcs; 277 const char *def; 278 int mask; 279 }; 280 281 #define CCN_EVENT_ATTR(_name) \ 282 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL) 283 284 /* 285 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on 286 * their ports in XP they are connected to. For the sake of usability they are 287 * explicitly defined here (and translated into a relevant watchpoint in 288 * arm_ccn_pmu_event_init()) so the user can easily request them without deep 289 * knowledge of the flit format. 290 */ 291 292 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \ 293 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \ 294 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \ 295 .def = _def, .mask = _mask, } 296 297 #define CCN_EVENT_HNI(_name, _def, _mask) { \ 298 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \ 299 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ 300 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } 301 302 #define CCN_EVENT_SBSX(_name, _def, _mask) { \ 303 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \ 304 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ 305 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } 306 307 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \ 308 .type = CCN_TYPE_HNF, .event = _event, } 309 310 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \ 311 .type = CCN_TYPE_XP, .event = _event, \ 312 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, } 313 314 /* 315 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending 316 * on configuration. One of them is picked to represent the whole group, 317 * as they all share the same event types. 318 */ 319 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \ 320 .type = CCN_TYPE_RNI_3P, .event = _event, } 321 322 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \ 323 .type = CCN_TYPE_SBAS, .event = _event, } 324 325 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \ 326 .type = CCN_TYPE_CYCLES } 327 328 329 static ssize_t arm_ccn_pmu_event_show(struct device *dev, 330 struct device_attribute *attr, char *buf) 331 { 332 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 333 struct arm_ccn_pmu_event *event = container_of(attr, 334 struct arm_ccn_pmu_event, attr); 335 ssize_t res; 336 337 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type); 338 if (event->event) 339 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x", 340 event->event); 341 if (event->def) 342 res += snprintf(buf + res, PAGE_SIZE - res, ",%s", 343 event->def); 344 if (event->mask) 345 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x", 346 event->mask); 347 348 /* Arguments required by an event */ 349 switch (event->type) { 350 case CCN_TYPE_CYCLES: 351 break; 352 case CCN_TYPE_XP: 353 res += snprintf(buf + res, PAGE_SIZE - res, 354 ",xp=?,vc=?"); 355 if (event->event == CCN_EVENT_WATCHPOINT) 356 res += snprintf(buf + res, PAGE_SIZE - res, 357 ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?"); 358 else 359 res += snprintf(buf + res, PAGE_SIZE - res, 360 ",bus=?"); 361 362 break; 363 case CCN_TYPE_MN: 364 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id); 365 break; 366 default: 367 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?"); 368 break; 369 } 370 371 res += snprintf(buf + res, PAGE_SIZE - res, "\n"); 372 373 return res; 374 } 375 376 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj, 377 struct attribute *attr, int index) 378 { 379 struct device *dev = kobj_to_dev(kobj); 380 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 381 struct device_attribute *dev_attr = container_of(attr, 382 struct device_attribute, attr); 383 struct arm_ccn_pmu_event *event = container_of(dev_attr, 384 struct arm_ccn_pmu_event, attr); 385 386 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present) 387 return 0; 388 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present) 389 return 0; 390 391 return attr->mode; 392 } 393 394 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = { 395 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE), 396 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE), 397 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE), 398 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), 399 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), 400 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), 401 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), 402 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", 403 CCN_IDX_MASK_ORDER), 404 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), 405 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), 406 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), 407 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), 408 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", 409 CCN_IDX_MASK_ORDER), 410 CCN_EVENT_HNF(cache_miss, 0x1), 411 CCN_EVENT_HNF(l3_sf_cache_access, 0x02), 412 CCN_EVENT_HNF(cache_fill, 0x3), 413 CCN_EVENT_HNF(pocq_retry, 0x4), 414 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5), 415 CCN_EVENT_HNF(sf_hit, 0x6), 416 CCN_EVENT_HNF(sf_evictions, 0x7), 417 CCN_EVENT_HNF(snoops_sent, 0x8), 418 CCN_EVENT_HNF(snoops_broadcast, 0x9), 419 CCN_EVENT_HNF(l3_eviction, 0xa), 420 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb), 421 CCN_EVENT_HNF(mc_retries, 0xc), 422 CCN_EVENT_HNF(mc_reqs, 0xd), 423 CCN_EVENT_HNF(qos_hh_retry, 0xe), 424 CCN_EVENT_RNI(rdata_beats_p0, 0x1), 425 CCN_EVENT_RNI(rdata_beats_p1, 0x2), 426 CCN_EVENT_RNI(rdata_beats_p2, 0x3), 427 CCN_EVENT_RNI(rxdat_flits, 0x4), 428 CCN_EVENT_RNI(txdat_flits, 0x5), 429 CCN_EVENT_RNI(txreq_flits, 0x6), 430 CCN_EVENT_RNI(txreq_flits_retried, 0x7), 431 CCN_EVENT_RNI(rrt_full, 0x8), 432 CCN_EVENT_RNI(wrt_full, 0x9), 433 CCN_EVENT_RNI(txreq_flits_replayed, 0xa), 434 CCN_EVENT_XP(upload_starvation, 0x1), 435 CCN_EVENT_XP(download_starvation, 0x2), 436 CCN_EVENT_XP(respin, 0x3), 437 CCN_EVENT_XP(valid_flit, 0x4), 438 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT), 439 CCN_EVENT_SBAS(rdata_beats_p0, 0x1), 440 CCN_EVENT_SBAS(rxdat_flits, 0x4), 441 CCN_EVENT_SBAS(txdat_flits, 0x5), 442 CCN_EVENT_SBAS(txreq_flits, 0x6), 443 CCN_EVENT_SBAS(txreq_flits_retried, 0x7), 444 CCN_EVENT_SBAS(rrt_full, 0x8), 445 CCN_EVENT_SBAS(wrt_full, 0x9), 446 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa), 447 CCN_EVENT_CYCLES(cycles), 448 }; 449 450 /* Populated in arm_ccn_init() */ 451 static struct attribute 452 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1]; 453 454 static const struct attribute_group arm_ccn_pmu_events_attr_group = { 455 .name = "events", 456 .is_visible = arm_ccn_pmu_events_is_visible, 457 .attrs = arm_ccn_pmu_events_attrs, 458 }; 459 460 461 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name) 462 { 463 unsigned long i; 464 465 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1])) 466 return NULL; 467 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a'; 468 469 switch (name[1]) { 470 case 'l': 471 return &ccn->dt.cmp_mask[i].l; 472 case 'h': 473 return &ccn->dt.cmp_mask[i].h; 474 default: 475 return NULL; 476 } 477 } 478 479 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev, 480 struct device_attribute *attr, char *buf) 481 { 482 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 483 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); 484 485 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL; 486 } 487 488 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev, 489 struct device_attribute *attr, const char *buf, size_t count) 490 { 491 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 492 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); 493 int err = -EINVAL; 494 495 if (mask) 496 err = kstrtoull(buf, 0, mask); 497 498 return err ? err : count; 499 } 500 501 #define CCN_CMP_MASK_ATTR(_name) \ 502 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ 503 __ATTR(_name, S_IRUGO | S_IWUSR, \ 504 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store) 505 506 #define CCN_CMP_MASK_ATTR_RO(_name) \ 507 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ 508 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL) 509 510 static CCN_CMP_MASK_ATTR(0l); 511 static CCN_CMP_MASK_ATTR(0h); 512 static CCN_CMP_MASK_ATTR(1l); 513 static CCN_CMP_MASK_ATTR(1h); 514 static CCN_CMP_MASK_ATTR(2l); 515 static CCN_CMP_MASK_ATTR(2h); 516 static CCN_CMP_MASK_ATTR(3l); 517 static CCN_CMP_MASK_ATTR(3h); 518 static CCN_CMP_MASK_ATTR(4l); 519 static CCN_CMP_MASK_ATTR(4h); 520 static CCN_CMP_MASK_ATTR(5l); 521 static CCN_CMP_MASK_ATTR(5h); 522 static CCN_CMP_MASK_ATTR(6l); 523 static CCN_CMP_MASK_ATTR(6h); 524 static CCN_CMP_MASK_ATTR(7l); 525 static CCN_CMP_MASK_ATTR(7h); 526 static CCN_CMP_MASK_ATTR_RO(8l); 527 static CCN_CMP_MASK_ATTR_RO(8h); 528 static CCN_CMP_MASK_ATTR_RO(9l); 529 static CCN_CMP_MASK_ATTR_RO(9h); 530 static CCN_CMP_MASK_ATTR_RO(al); 531 static CCN_CMP_MASK_ATTR_RO(ah); 532 static CCN_CMP_MASK_ATTR_RO(bl); 533 static CCN_CMP_MASK_ATTR_RO(bh); 534 535 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = { 536 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr, 537 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr, 538 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr, 539 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr, 540 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr, 541 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr, 542 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr, 543 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr, 544 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr, 545 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr, 546 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr, 547 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr, 548 NULL 549 }; 550 551 static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { 552 .name = "cmp_mask", 553 .attrs = arm_ccn_pmu_cmp_mask_attrs, 554 }; 555 556 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev, 557 struct device_attribute *attr, char *buf) 558 { 559 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); 560 561 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu); 562 } 563 564 static struct device_attribute arm_ccn_pmu_cpumask_attr = 565 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL); 566 567 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = { 568 &arm_ccn_pmu_cpumask_attr.attr, 569 NULL, 570 }; 571 572 static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = { 573 .attrs = arm_ccn_pmu_cpumask_attrs, 574 }; 575 576 /* 577 * Default poll period is 10ms, which is way over the top anyway, 578 * as in the worst case scenario (an event every cycle), with 1GHz 579 * clocked bus, the smallest, 32 bit counter will overflow in 580 * more than 4s. 581 */ 582 static unsigned int arm_ccn_pmu_poll_period_us = 10000; 583 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint, 584 S_IRUGO | S_IWUSR); 585 586 static ktime_t arm_ccn_pmu_timer_period(void) 587 { 588 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000); 589 } 590 591 592 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = { 593 &arm_ccn_pmu_events_attr_group, 594 &arm_ccn_pmu_format_attr_group, 595 &arm_ccn_pmu_cmp_mask_attr_group, 596 &arm_ccn_pmu_cpumask_attr_group, 597 NULL 598 }; 599 600 601 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size) 602 { 603 int bit; 604 605 do { 606 bit = find_first_zero_bit(bitmap, size); 607 if (bit >= size) 608 return -EAGAIN; 609 } while (test_and_set_bit(bit, bitmap)); 610 611 return bit; 612 } 613 614 /* All RN-I and RN-D nodes have identical PMUs */ 615 static int arm_ccn_pmu_type_eq(u32 a, u32 b) 616 { 617 if (a == b) 618 return 1; 619 620 switch (a) { 621 case CCN_TYPE_RNI_1P: 622 case CCN_TYPE_RNI_2P: 623 case CCN_TYPE_RNI_3P: 624 case CCN_TYPE_RND_1P: 625 case CCN_TYPE_RND_2P: 626 case CCN_TYPE_RND_3P: 627 switch (b) { 628 case CCN_TYPE_RNI_1P: 629 case CCN_TYPE_RNI_2P: 630 case CCN_TYPE_RNI_3P: 631 case CCN_TYPE_RND_1P: 632 case CCN_TYPE_RND_2P: 633 case CCN_TYPE_RND_3P: 634 return 1; 635 } 636 break; 637 } 638 639 return 0; 640 } 641 642 static int arm_ccn_pmu_event_alloc(struct perf_event *event) 643 { 644 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 645 struct hw_perf_event *hw = &event->hw; 646 u32 node_xp, type, event_id; 647 struct arm_ccn_component *source; 648 int bit; 649 650 node_xp = CCN_CONFIG_NODE(event->attr.config); 651 type = CCN_CONFIG_TYPE(event->attr.config); 652 event_id = CCN_CONFIG_EVENT(event->attr.config); 653 654 /* Allocate the cycle counter */ 655 if (type == CCN_TYPE_CYCLES) { 656 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER, 657 ccn->dt.pmu_counters_mask)) 658 return -EAGAIN; 659 660 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER; 661 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; 662 663 return 0; 664 } 665 666 /* Allocate an event counter */ 667 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, 668 CCN_NUM_PMU_EVENT_COUNTERS); 669 if (hw->idx < 0) { 670 dev_dbg(ccn->dev, "No more counters available!\n"); 671 return -EAGAIN; 672 } 673 674 if (type == CCN_TYPE_XP) 675 source = &ccn->xp[node_xp]; 676 else 677 source = &ccn->node[node_xp]; 678 ccn->dt.pmu_counters[hw->idx].source = source; 679 680 /* Allocate an event source or a watchpoint */ 681 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT) 682 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask, 683 CCN_NUM_XP_WATCHPOINTS); 684 else 685 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask, 686 CCN_NUM_PMU_EVENTS); 687 if (bit < 0) { 688 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n", 689 node_xp); 690 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); 691 return -EAGAIN; 692 } 693 hw->config_base = bit; 694 695 ccn->dt.pmu_counters[hw->idx].event = event; 696 697 return 0; 698 } 699 700 static void arm_ccn_pmu_event_release(struct perf_event *event) 701 { 702 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 703 struct hw_perf_event *hw = &event->hw; 704 705 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) { 706 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); 707 } else { 708 struct arm_ccn_component *source = 709 ccn->dt.pmu_counters[hw->idx].source; 710 711 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP && 712 CCN_CONFIG_EVENT(event->attr.config) == 713 CCN_EVENT_WATCHPOINT) 714 clear_bit(hw->config_base, source->xp.dt_cmp_mask); 715 else 716 clear_bit(hw->config_base, source->pmu_events_mask); 717 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); 718 } 719 720 ccn->dt.pmu_counters[hw->idx].source = NULL; 721 ccn->dt.pmu_counters[hw->idx].event = NULL; 722 } 723 724 static int arm_ccn_pmu_event_init(struct perf_event *event) 725 { 726 struct arm_ccn *ccn; 727 struct hw_perf_event *hw = &event->hw; 728 u32 node_xp, type, event_id; 729 int valid; 730 int i; 731 struct perf_event *sibling; 732 733 if (event->attr.type != event->pmu->type) 734 return -ENOENT; 735 736 ccn = pmu_to_arm_ccn(event->pmu); 737 738 if (hw->sample_period) { 739 dev_warn(ccn->dev, "Sampling not supported!\n"); 740 return -EOPNOTSUPP; 741 } 742 743 if (has_branch_stack(event) || event->attr.exclude_user || 744 event->attr.exclude_kernel || event->attr.exclude_hv || 745 event->attr.exclude_idle || event->attr.exclude_host || 746 event->attr.exclude_guest) { 747 dev_warn(ccn->dev, "Can't exclude execution levels!\n"); 748 return -EINVAL; 749 } 750 751 if (event->cpu < 0) { 752 dev_warn(ccn->dev, "Can't provide per-task data!\n"); 753 return -EOPNOTSUPP; 754 } 755 /* 756 * Many perf core operations (eg. events rotation) operate on a 757 * single CPU context. This is obvious for CPU PMUs, where one 758 * expects the same sets of events being observed on all CPUs, 759 * but can lead to issues for off-core PMUs, like CCN, where each 760 * event could be theoretically assigned to a different CPU. To 761 * mitigate this, we enforce CPU assignment to one, selected 762 * processor (the one described in the "cpumask" attribute). 763 */ 764 event->cpu = cpumask_first(&ccn->dt.cpu); 765 766 node_xp = CCN_CONFIG_NODE(event->attr.config); 767 type = CCN_CONFIG_TYPE(event->attr.config); 768 event_id = CCN_CONFIG_EVENT(event->attr.config); 769 770 /* Validate node/xp vs topology */ 771 switch (type) { 772 case CCN_TYPE_MN: 773 if (node_xp != ccn->mn_id) { 774 dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp); 775 return -EINVAL; 776 } 777 break; 778 case CCN_TYPE_XP: 779 if (node_xp >= ccn->num_xps) { 780 dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp); 781 return -EINVAL; 782 } 783 break; 784 case CCN_TYPE_CYCLES: 785 break; 786 default: 787 if (node_xp >= ccn->num_nodes) { 788 dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp); 789 return -EINVAL; 790 } 791 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) { 792 dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n", 793 type, node_xp); 794 return -EINVAL; 795 } 796 break; 797 } 798 799 /* Validate event ID vs available for the type */ 800 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid; 801 i++) { 802 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i]; 803 u32 port = CCN_CONFIG_PORT(event->attr.config); 804 u32 vc = CCN_CONFIG_VC(event->attr.config); 805 806 if (!arm_ccn_pmu_type_eq(type, e->type)) 807 continue; 808 if (event_id != e->event) 809 continue; 810 if (e->num_ports && port >= e->num_ports) { 811 dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n", 812 port, node_xp); 813 return -EINVAL; 814 } 815 if (e->num_vcs && vc >= e->num_vcs) { 816 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n", 817 vc, node_xp); 818 return -EINVAL; 819 } 820 valid = 1; 821 } 822 if (!valid) { 823 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n", 824 event_id, node_xp); 825 return -EINVAL; 826 } 827 828 /* Watchpoint-based event for a node is actually set on XP */ 829 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) { 830 u32 port; 831 832 type = CCN_TYPE_XP; 833 port = arm_ccn_node_to_xp_port(node_xp); 834 node_xp = arm_ccn_node_to_xp(node_xp); 835 836 arm_ccn_pmu_config_set(&event->attr.config, 837 node_xp, type, port); 838 } 839 840 /* 841 * We must NOT create groups containing mixed PMUs, although software 842 * events are acceptable (for example to create a CCN group 843 * periodically read when a hrtimer aka cpu-clock leader triggers). 844 */ 845 if (event->group_leader->pmu != event->pmu && 846 !is_software_event(event->group_leader)) 847 return -EINVAL; 848 849 for_each_sibling_event(sibling, event->group_leader) { 850 if (sibling->pmu != event->pmu && 851 !is_software_event(sibling)) 852 return -EINVAL; 853 } 854 855 return 0; 856 } 857 858 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx) 859 { 860 u64 res; 861 862 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) { 863 #ifdef readq 864 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); 865 #else 866 /* 40 bit counter, can do snapshot and read in two parts */ 867 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); 868 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) 869 ; 870 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); 871 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; 872 res <<= 32; 873 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); 874 #endif 875 } else { 876 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); 877 } 878 879 return res; 880 } 881 882 static void arm_ccn_pmu_event_update(struct perf_event *event) 883 { 884 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 885 struct hw_perf_event *hw = &event->hw; 886 u64 prev_count, new_count, mask; 887 888 do { 889 prev_count = local64_read(&hw->prev_count); 890 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx); 891 } while (local64_xchg(&hw->prev_count, new_count) != prev_count); 892 893 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; 894 895 local64_add((new_count - prev_count) & mask, &event->count); 896 } 897 898 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable) 899 { 900 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 901 struct hw_perf_event *hw = &event->hw; 902 struct arm_ccn_component *xp; 903 u32 val, dt_cfg; 904 905 /* Nothing to do for cycle counter */ 906 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) 907 return; 908 909 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) 910 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)]; 911 else 912 xp = &ccn->xp[arm_ccn_node_to_xp( 913 CCN_CONFIG_NODE(event->attr.config))]; 914 915 if (enable) 916 dt_cfg = hw->event_base; 917 else 918 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH; 919 920 spin_lock(&ccn->dt.config_lock); 921 922 val = readl(xp->base + CCN_XP_DT_CONFIG); 923 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK << 924 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx)); 925 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); 926 writel(val, xp->base + CCN_XP_DT_CONFIG); 927 928 spin_unlock(&ccn->dt.config_lock); 929 } 930 931 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags) 932 { 933 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 934 struct hw_perf_event *hw = &event->hw; 935 936 local64_set(&event->hw.prev_count, 937 arm_ccn_pmu_read_counter(ccn, hw->idx)); 938 hw->state = 0; 939 940 /* Set the DT bus input, engaging the counter */ 941 arm_ccn_pmu_xp_dt_config(event, 1); 942 } 943 944 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags) 945 { 946 struct hw_perf_event *hw = &event->hw; 947 948 /* Disable counting, setting the DT bus to pass-through mode */ 949 arm_ccn_pmu_xp_dt_config(event, 0); 950 951 if (flags & PERF_EF_UPDATE) 952 arm_ccn_pmu_event_update(event); 953 954 hw->state |= PERF_HES_STOPPED; 955 } 956 957 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event) 958 { 959 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 960 struct hw_perf_event *hw = &event->hw; 961 struct arm_ccn_component *source = 962 ccn->dt.pmu_counters[hw->idx].source; 963 unsigned long wp = hw->config_base; 964 u32 val; 965 u64 cmp_l = event->attr.config1; 966 u64 cmp_h = event->attr.config2; 967 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; 968 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; 969 970 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); 971 972 /* Direction (RX/TX), device (port) & virtual channel */ 973 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); 974 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK << 975 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp)); 976 val |= CCN_CONFIG_DIR(event->attr.config) << 977 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp); 978 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK << 979 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp)); 980 val |= CCN_CONFIG_PORT(event->attr.config) << 981 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp); 982 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK << 983 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp)); 984 val |= CCN_CONFIG_VC(event->attr.config) << 985 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp); 986 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); 987 988 /* Comparison values */ 989 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); 990 writel((cmp_l >> 32) & 0x7fffffff, 991 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); 992 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); 993 writel((cmp_h >> 32) & 0x0fffffff, 994 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); 995 996 /* Mask */ 997 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); 998 writel((mask_l >> 32) & 0x7fffffff, 999 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); 1000 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); 1001 writel((mask_h >> 32) & 0x0fffffff, 1002 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); 1003 } 1004 1005 static void arm_ccn_pmu_xp_event_config(struct perf_event *event) 1006 { 1007 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1008 struct hw_perf_event *hw = &event->hw; 1009 struct arm_ccn_component *source = 1010 ccn->dt.pmu_counters[hw->idx].source; 1011 u32 val, id; 1012 1013 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); 1014 1015 id = (CCN_CONFIG_VC(event->attr.config) << 4) | 1016 (CCN_CONFIG_BUS(event->attr.config) << 3) | 1017 (CCN_CONFIG_EVENT(event->attr.config) << 0); 1018 1019 val = readl(source->base + CCN_XP_PMU_EVENT_SEL); 1020 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK << 1021 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); 1022 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); 1023 writel(val, source->base + CCN_XP_PMU_EVENT_SEL); 1024 } 1025 1026 static void arm_ccn_pmu_node_event_config(struct perf_event *event) 1027 { 1028 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1029 struct hw_perf_event *hw = &event->hw; 1030 struct arm_ccn_component *source = 1031 ccn->dt.pmu_counters[hw->idx].source; 1032 u32 type = CCN_CONFIG_TYPE(event->attr.config); 1033 u32 val, port; 1034 1035 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config)); 1036 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, 1037 hw->config_base); 1038 1039 /* These *_event_sel regs should be identical, but let's make sure... */ 1040 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL); 1041 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL); 1042 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) != 1043 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1)); 1044 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) != 1045 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1)); 1046 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK != 1047 CCN_SBAS_PMU_EVENT_SEL__ID__MASK); 1048 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK != 1049 CCN_RNI_PMU_EVENT_SEL__ID__MASK); 1050 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS && 1051 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P))) 1052 return; 1053 1054 /* Set the event id for the pre-allocated counter */ 1055 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); 1056 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK << 1057 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); 1058 val |= CCN_CONFIG_EVENT(event->attr.config) << 1059 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); 1060 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); 1061 } 1062 1063 static void arm_ccn_pmu_event_config(struct perf_event *event) 1064 { 1065 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1066 struct hw_perf_event *hw = &event->hw; 1067 u32 xp, offset, val; 1068 1069 /* Cycle counter requires no setup */ 1070 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) 1071 return; 1072 1073 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) 1074 xp = CCN_CONFIG_XP(event->attr.config); 1075 else 1076 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config)); 1077 1078 spin_lock(&ccn->dt.config_lock); 1079 1080 /* Set the DT bus "distance" register */ 1081 offset = (hw->idx / 4) * 4; 1082 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); 1083 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK << 1084 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4)); 1085 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); 1086 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); 1087 1088 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) { 1089 if (CCN_CONFIG_EVENT(event->attr.config) == 1090 CCN_EVENT_WATCHPOINT) 1091 arm_ccn_pmu_xp_watchpoint_config(event); 1092 else 1093 arm_ccn_pmu_xp_event_config(event); 1094 } else { 1095 arm_ccn_pmu_node_event_config(event); 1096 } 1097 1098 spin_unlock(&ccn->dt.config_lock); 1099 } 1100 1101 static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn) 1102 { 1103 return bitmap_weight(ccn->dt.pmu_counters_mask, 1104 CCN_NUM_PMU_EVENT_COUNTERS + 1); 1105 } 1106 1107 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags) 1108 { 1109 int err; 1110 struct hw_perf_event *hw = &event->hw; 1111 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1112 1113 err = arm_ccn_pmu_event_alloc(event); 1114 if (err) 1115 return err; 1116 1117 /* 1118 * Pin the timer, so that the overflows are handled by the chosen 1119 * event->cpu (this is the same one as presented in "cpumask" 1120 * attribute). 1121 */ 1122 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1) 1123 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), 1124 HRTIMER_MODE_REL_PINNED); 1125 1126 arm_ccn_pmu_event_config(event); 1127 1128 hw->state = PERF_HES_STOPPED; 1129 1130 if (flags & PERF_EF_START) 1131 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE); 1132 1133 return 0; 1134 } 1135 1136 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags) 1137 { 1138 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); 1139 1140 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE); 1141 1142 arm_ccn_pmu_event_release(event); 1143 1144 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0) 1145 hrtimer_cancel(&ccn->dt.hrtimer); 1146 } 1147 1148 static void arm_ccn_pmu_event_read(struct perf_event *event) 1149 { 1150 arm_ccn_pmu_event_update(event); 1151 } 1152 1153 static void arm_ccn_pmu_enable(struct pmu *pmu) 1154 { 1155 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); 1156 1157 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); 1158 val |= CCN_DT_PMCR__PMU_EN; 1159 writel(val, ccn->dt.base + CCN_DT_PMCR); 1160 } 1161 1162 static void arm_ccn_pmu_disable(struct pmu *pmu) 1163 { 1164 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); 1165 1166 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); 1167 val &= ~CCN_DT_PMCR__PMU_EN; 1168 writel(val, ccn->dt.base + CCN_DT_PMCR); 1169 } 1170 1171 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) 1172 { 1173 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); 1174 int idx; 1175 1176 if (!pmovsr) 1177 return IRQ_NONE; 1178 1179 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); 1180 1181 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS); 1182 1183 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) { 1184 struct perf_event *event = dt->pmu_counters[idx].event; 1185 int overflowed = pmovsr & BIT(idx); 1186 1187 WARN_ON_ONCE(overflowed && !event && 1188 idx != CCN_IDX_PMU_CYCLE_COUNTER); 1189 1190 if (!event || !overflowed) 1191 continue; 1192 1193 arm_ccn_pmu_event_update(event); 1194 } 1195 1196 return IRQ_HANDLED; 1197 } 1198 1199 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer) 1200 { 1201 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, 1202 hrtimer); 1203 unsigned long flags; 1204 1205 local_irq_save(flags); 1206 arm_ccn_pmu_overflow_handler(dt); 1207 local_irq_restore(flags); 1208 1209 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period()); 1210 return HRTIMER_RESTART; 1211 } 1212 1213 1214 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) 1215 { 1216 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); 1217 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); 1218 unsigned int target; 1219 1220 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) 1221 return 0; 1222 target = cpumask_any_but(cpu_online_mask, cpu); 1223 if (target >= nr_cpu_ids) 1224 return 0; 1225 perf_pmu_migrate_context(&dt->pmu, cpu, target); 1226 cpumask_set_cpu(target, &dt->cpu); 1227 if (ccn->irq) 1228 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0); 1229 return 0; 1230 } 1231 1232 static DEFINE_IDA(arm_ccn_pmu_ida); 1233 1234 static int arm_ccn_pmu_init(struct arm_ccn *ccn) 1235 { 1236 int i; 1237 char *name; 1238 int err; 1239 1240 /* Initialize DT subsystem */ 1241 ccn->dt.base = ccn->base + CCN_REGION_SIZE; 1242 spin_lock_init(&ccn->dt.config_lock); 1243 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); 1244 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); 1245 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN, 1246 ccn->dt.base + CCN_DT_PMCR); 1247 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); 1248 for (i = 0; i < ccn->num_xps; i++) { 1249 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); 1250 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << 1251 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) | 1252 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << 1253 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) | 1254 CCN_XP_DT_CONTROL__DT_ENABLE, 1255 ccn->xp[i].base + CCN_XP_DT_CONTROL); 1256 } 1257 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; 1258 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; 1259 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; 1260 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; 1261 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; 1262 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); 1263 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; 1264 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); 1265 1266 /* Get a convenient /sys/event_source/devices/ name */ 1267 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL); 1268 if (ccn->dt.id == 0) { 1269 name = "ccn"; 1270 } else { 1271 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", 1272 ccn->dt.id); 1273 if (!name) { 1274 err = -ENOMEM; 1275 goto error_choose_name; 1276 } 1277 } 1278 1279 /* Perf driver registration */ 1280 ccn->dt.pmu = (struct pmu) { 1281 .module = THIS_MODULE, 1282 .attr_groups = arm_ccn_pmu_attr_groups, 1283 .task_ctx_nr = perf_invalid_context, 1284 .event_init = arm_ccn_pmu_event_init, 1285 .add = arm_ccn_pmu_event_add, 1286 .del = arm_ccn_pmu_event_del, 1287 .start = arm_ccn_pmu_event_start, 1288 .stop = arm_ccn_pmu_event_stop, 1289 .read = arm_ccn_pmu_event_read, 1290 .pmu_enable = arm_ccn_pmu_enable, 1291 .pmu_disable = arm_ccn_pmu_disable, 1292 }; 1293 1294 /* No overflow interrupt? Have to use a timer instead. */ 1295 if (!ccn->irq) { 1296 dev_info(ccn->dev, "No access to interrupts, using timer.\n"); 1297 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, 1298 HRTIMER_MODE_REL); 1299 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; 1300 } 1301 1302 /* Pick one CPU which we will use to collect data from CCN... */ 1303 cpumask_set_cpu(get_cpu(), &ccn->dt.cpu); 1304 1305 /* Also make sure that the overflow interrupt is handled by this CPU */ 1306 if (ccn->irq) { 1307 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu); 1308 if (err) { 1309 dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); 1310 goto error_set_affinity; 1311 } 1312 } 1313 1314 err = perf_pmu_register(&ccn->dt.pmu, name, -1); 1315 if (err) 1316 goto error_pmu_register; 1317 1318 cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, 1319 &ccn->dt.node); 1320 put_cpu(); 1321 return 0; 1322 1323 error_pmu_register: 1324 error_set_affinity: 1325 put_cpu(); 1326 error_choose_name: 1327 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); 1328 for (i = 0; i < ccn->num_xps; i++) 1329 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); 1330 writel(0, ccn->dt.base + CCN_DT_PMCR); 1331 return err; 1332 } 1333 1334 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn) 1335 { 1336 int i; 1337 1338 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, 1339 &ccn->dt.node); 1340 if (ccn->irq) 1341 irq_set_affinity_hint(ccn->irq, NULL); 1342 for (i = 0; i < ccn->num_xps; i++) 1343 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); 1344 writel(0, ccn->dt.base + CCN_DT_PMCR); 1345 perf_pmu_unregister(&ccn->dt.pmu); 1346 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); 1347 } 1348 1349 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn, 1350 int (*callback)(struct arm_ccn *ccn, int region, 1351 void __iomem *base, u32 type, u32 id)) 1352 { 1353 int region; 1354 1355 for (region = 0; region < CCN_NUM_REGIONS; region++) { 1356 u32 val, type, id; 1357 void __iomem *base; 1358 int err; 1359 1360 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + 1361 4 * (region / 32)); 1362 if (!(val & (1 << (region % 32)))) 1363 continue; 1364 1365 base = ccn->base + region * CCN_REGION_SIZE; 1366 val = readl(base + CCN_ALL_OLY_ID); 1367 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) & 1368 CCN_ALL_OLY_ID__OLY_ID__MASK; 1369 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) & 1370 CCN_ALL_OLY_ID__NODE_ID__MASK; 1371 1372 err = callback(ccn, region, base, type, id); 1373 if (err) 1374 return err; 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region, 1381 void __iomem *base, u32 type, u32 id) 1382 { 1383 1384 if (type == CCN_TYPE_XP && id >= ccn->num_xps) 1385 ccn->num_xps = id + 1; 1386 else if (id >= ccn->num_nodes) 1387 ccn->num_nodes = id + 1; 1388 1389 return 0; 1390 } 1391 1392 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region, 1393 void __iomem *base, u32 type, u32 id) 1394 { 1395 struct arm_ccn_component *component; 1396 1397 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type); 1398 1399 switch (type) { 1400 case CCN_TYPE_MN: 1401 ccn->mn_id = id; 1402 return 0; 1403 case CCN_TYPE_DT: 1404 return 0; 1405 case CCN_TYPE_XP: 1406 component = &ccn->xp[id]; 1407 break; 1408 case CCN_TYPE_SBSX: 1409 ccn->sbsx_present = 1; 1410 component = &ccn->node[id]; 1411 break; 1412 case CCN_TYPE_SBAS: 1413 ccn->sbas_present = 1; 1414 /* Fall-through */ 1415 default: 1416 component = &ccn->node[id]; 1417 break; 1418 } 1419 1420 component->base = base; 1421 component->type = type; 1422 1423 return 0; 1424 } 1425 1426 1427 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn, 1428 const u32 *err_sig_val) 1429 { 1430 /* This should be really handled by firmware... */ 1431 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n", 1432 err_sig_val[5], err_sig_val[4], err_sig_val[3], 1433 err_sig_val[2], err_sig_val[1], err_sig_val[0]); 1434 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n"); 1435 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE, 1436 ccn->base + CCN_MN_ERRINT_STATUS); 1437 1438 return IRQ_HANDLED; 1439 } 1440 1441 1442 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id) 1443 { 1444 irqreturn_t res = IRQ_NONE; 1445 struct arm_ccn *ccn = dev_id; 1446 u32 err_sig_val[6]; 1447 u32 err_or; 1448 int i; 1449 1450 /* PMU overflow is a special case */ 1451 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); 1452 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) { 1453 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT; 1454 res = arm_ccn_pmu_overflow_handler(&ccn->dt); 1455 } 1456 1457 /* Have to read all err_sig_vals to clear them */ 1458 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) { 1459 err_sig_val[i] = readl(ccn->base + 1460 CCN_MN_ERR_SIG_VAL_63_0 + i * 4); 1461 err_or |= err_sig_val[i]; 1462 } 1463 if (err_or) 1464 res |= arm_ccn_error_handler(ccn, err_sig_val); 1465 1466 if (res != IRQ_NONE) 1467 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT, 1468 ccn->base + CCN_MN_ERRINT_STATUS); 1469 1470 return res; 1471 } 1472 1473 1474 static int arm_ccn_probe(struct platform_device *pdev) 1475 { 1476 struct arm_ccn *ccn; 1477 struct resource *res; 1478 unsigned int irq; 1479 int err; 1480 1481 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); 1482 if (!ccn) 1483 return -ENOMEM; 1484 ccn->dev = &pdev->dev; 1485 platform_set_drvdata(pdev, ccn); 1486 1487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1488 if (!res) 1489 return -EINVAL; 1490 1491 if (!devm_request_mem_region(ccn->dev, res->start, 1492 resource_size(res), pdev->name)) 1493 return -EBUSY; 1494 1495 ccn->base = devm_ioremap(ccn->dev, res->start, 1496 resource_size(res)); 1497 if (!ccn->base) 1498 return -EFAULT; 1499 1500 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1501 if (!res) 1502 return -EINVAL; 1503 irq = res->start; 1504 1505 /* Check if we can use the interrupt */ 1506 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE, 1507 ccn->base + CCN_MN_ERRINT_STATUS); 1508 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & 1509 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) { 1510 /* Can set 'disable' bits, so can acknowledge interrupts */ 1511 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE, 1512 ccn->base + CCN_MN_ERRINT_STATUS); 1513 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 1514 IRQF_NOBALANCING | IRQF_NO_THREAD, 1515 dev_name(ccn->dev), ccn); 1516 if (err) 1517 return err; 1518 1519 ccn->irq = irq; 1520 } 1521 1522 1523 /* Build topology */ 1524 1525 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num); 1526 if (err) 1527 return err; 1528 1529 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node), 1530 GFP_KERNEL); 1531 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node), 1532 GFP_KERNEL); 1533 if (!ccn->node || !ccn->xp) 1534 return -ENOMEM; 1535 1536 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes); 1537 if (err) 1538 return err; 1539 1540 return arm_ccn_pmu_init(ccn); 1541 } 1542 1543 static int arm_ccn_remove(struct platform_device *pdev) 1544 { 1545 struct arm_ccn *ccn = platform_get_drvdata(pdev); 1546 1547 arm_ccn_pmu_cleanup(ccn); 1548 1549 return 0; 1550 } 1551 1552 static const struct of_device_id arm_ccn_match[] = { 1553 { .compatible = "arm,ccn-502", }, 1554 { .compatible = "arm,ccn-504", }, 1555 {}, 1556 }; 1557 MODULE_DEVICE_TABLE(of, arm_ccn_match); 1558 1559 static struct platform_driver arm_ccn_driver = { 1560 .driver = { 1561 .name = "arm-ccn", 1562 .of_match_table = arm_ccn_match, 1563 }, 1564 .probe = arm_ccn_probe, 1565 .remove = arm_ccn_remove, 1566 }; 1567 1568 static int __init arm_ccn_init(void) 1569 { 1570 int i, ret; 1571 1572 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE, 1573 "perf/arm/ccn:online", NULL, 1574 arm_ccn_pmu_offline_cpu); 1575 if (ret) 1576 return ret; 1577 1578 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++) 1579 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr; 1580 1581 ret = platform_driver_register(&arm_ccn_driver); 1582 if (ret) 1583 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); 1584 return ret; 1585 } 1586 1587 static void __exit arm_ccn_exit(void) 1588 { 1589 platform_driver_unregister(&arm_ccn_driver); 1590 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); 1591 } 1592 1593 module_init(arm_ccn_init); 1594 module_exit(arm_ccn_exit); 1595 1596 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>"); 1597 MODULE_LICENSE("GPL"); 1598