1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Performance Monitor Drivers 4# 5 6menu "Performance monitor support" 7 depends on PERF_EVENTS 8 9config ARM_CCI_PMU 10 tristate "ARM CCI PMU driver" 11 depends on (ARM && CPU_V7) || ARM64 12 select ARM_CCI 13 help 14 Support for PMU events monitoring on the ARM CCI (Cache Coherent 15 Interconnect) family of products. 16 17 If compiled as a module, it will be called arm-cci. 18 19config ARM_CCI400_PMU 20 bool "support CCI-400" 21 default y 22 depends on ARM_CCI_PMU 23 select ARM_CCI400_COMMON 24 help 25 CCI-400 provides 4 independent event counters counting events related 26 to the connected slave/master interfaces, plus a cycle counter. 27 28config ARM_CCI5xx_PMU 29 bool "support CCI-500/CCI-550" 30 default y 31 depends on ARM_CCI_PMU 32 help 33 CCI-500/CCI-550 both provide 8 independent event counters, which can 34 count events pertaining to the slave/master interfaces as well as the 35 internal events to the CCI. 36 37config ARM_CCN 38 tristate "ARM CCN driver support" 39 depends on ARM || ARM64 || COMPILE_TEST 40 help 41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 42 interconnect. 43 44config ARM_CMN 45 tristate "Arm CMN-600 PMU support" 46 depends on ARM64 || COMPILE_TEST 47 help 48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 49 Network interconnect. 50 51config ARM_PMU 52 depends on ARM || ARM64 53 bool "ARM PMU framework" 54 default y 55 help 56 Say y if you want to use CPU performance monitors on ARM-based 57 systems. 58 59config RISCV_PMU 60 depends on RISCV 61 bool "RISC-V PMU framework" 62 default y 63 help 64 Say y if you want to use CPU performance monitors on RISCV-based 65 systems. This provides the core PMU framework that abstracts common 66 PMU functionalities in a core library so that different PMU drivers 67 can reuse it. 68 69config RISCV_PMU_LEGACY 70 depends on RISCV_PMU 71 bool "RISC-V legacy PMU implementation" 72 default y 73 help 74 Say y if you want to use the legacy CPU performance monitor 75 implementation on RISC-V based systems. This only allows counting 76 of cycle/instruction counter and doesn't support counter overflow, 77 or programmable counters. It will be removed in future. 78 79config RISCV_PMU_SBI 80 depends on RISCV_PMU && RISCV_SBI 81 bool "RISC-V PMU based on SBI PMU extension" 82 default y 83 help 84 Say y if you want to use the CPU performance monitor 85 using SBI PMU extension on RISC-V based systems. This option provides 86 full perf feature support i.e. counter overflow, privilege mode 87 filtering, counter configuration. 88 89config ARM_PMU_ACPI 90 depends on ARM_PMU && ACPI 91 def_bool y 92 93config ARM_SMMU_V3_PMU 94 tristate "ARM SMMUv3 Performance Monitors Extension" 95 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) 96 depends on GENERIC_MSI_IRQ 97 help 98 Provides support for the ARM SMMUv3 Performance Monitor Counter 99 Groups (PMCG), which provide monitoring of transactions passing 100 through the SMMU and allow the resulting information to be filtered 101 based on the Stream ID of the corresponding master. 102 103config ARM_PMUV3 104 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64) 105 bool "ARM PMUv3 support" if !ARM64 106 default ARM64 107 help 108 Say y if you want to use the ARM performance monitor unit (PMU) 109 version 3. The PMUv3 is the CPU performance monitors on ARMv8 110 (aarch32 and aarch64) systems that implement the PMUv3 111 architecture. 112 113config ARM_DSU_PMU 114 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 115 depends on ARM64 116 help 117 Provides support for performance monitor unit in ARM DynamIQ Shared 118 Unit (DSU). The DSU integrates one or more cores with an L3 memory 119 system, control logic. The PMU allows counting various events related 120 to DSU. 121 122config FSL_IMX8_DDR_PMU 123 tristate "Freescale i.MX8 DDR perf monitor" 124 depends on ARCH_MXC || COMPILE_TEST 125 help 126 Provides support for the DDR performance monitor in i.MX8, which 127 can give information about memory throughput and other related 128 events. 129 130config FSL_IMX9_DDR_PMU 131 tristate "Freescale i.MX9 DDR perf monitor" 132 depends on ARCH_MXC 133 help 134 Provides support for the DDR performance monitor in i.MX9, which 135 can give information about memory throughput and other related 136 events. 137 138config QCOM_L2_PMU 139 bool "Qualcomm Technologies L2-cache PMU" 140 depends on ARCH_QCOM && ARM64 && ACPI 141 select QCOM_KRYO_L2_ACCESSORS 142 help 143 Provides support for the L2 cache performance monitor unit (PMU) 144 in Qualcomm Technologies processors. 145 Adds the L2 cache PMU into the perf events subsystem for 146 monitoring L2 cache events. 147 148config QCOM_L3_PMU 149 bool "Qualcomm Technologies L3-cache PMU" 150 depends on ARCH_QCOM && ARM64 && ACPI 151 select QCOM_IRQ_COMBINER 152 help 153 Provides support for the L3 cache performance monitor unit (PMU) 154 in Qualcomm Technologies processors. 155 Adds the L3 cache PMU into the perf events subsystem for 156 monitoring L3 cache events. 157 158config THUNDERX2_PMU 159 tristate "Cavium ThunderX2 SoC PMU UNCORE" 160 depends on ARCH_THUNDER2 || COMPILE_TEST 161 depends on NUMA && ACPI 162 default m 163 help 164 Provides support for ThunderX2 UNCORE events. 165 The SoC has PMU support in its L3 cache controller (L3C) and 166 in the DDR4 Memory Controller (DMC). 167 168config XGENE_PMU 169 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 170 bool "APM X-Gene SoC PMU" 171 default n 172 help 173 Say y if you want to use APM X-Gene SoC performance monitors. 174 175config ARM_SPE_PMU 176 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 177 depends on ARM64 178 help 179 Enable perf support for the ARMv8.2 Statistical Profiling 180 Extension, which provides periodic sampling of operations in 181 the CPU pipeline and reports this via the perf AUX interface. 182 183config ARM_DMC620_PMU 184 tristate "Enable PMU support for the ARM DMC-620 memory controller" 185 depends on (ARM64 && ACPI) || COMPILE_TEST 186 help 187 Support for PMU events monitoring on the ARM DMC-620 memory 188 controller. 189 190config MARVELL_CN10K_TAD_PMU 191 tristate "Marvell CN10K LLC-TAD PMU" 192 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 193 help 194 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 195 performance monitors on CN10K family silicons. 196 197config APPLE_M1_CPU_PMU 198 bool "Apple M1 CPU PMU support" 199 depends on ARM_PMU && ARCH_APPLE 200 help 201 Provides support for the non-architectural CPU PMUs present on 202 the Apple M1 SoCs and derivatives. 203 204config ALIBABA_UNCORE_DRW_PMU 205 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 206 depends on (ARM64 && ACPI) || COMPILE_TEST 207 help 208 Support for Driveway PMU events monitoring on Yitian 710 DDR 209 Sub-system. 210 211source "drivers/perf/hisilicon/Kconfig" 212 213config MARVELL_CN10K_DDR_PMU 214 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support" 215 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 216 help 217 Enable perf support for Marvell DDR Performance monitoring 218 event on CN10K platform. 219 220source "drivers/perf/arm_cspmu/Kconfig" 221 222source "drivers/perf/amlogic/Kconfig" 223 224config CXL_PMU 225 tristate "CXL Performance Monitoring Unit" 226 depends on CXL_BUS 227 help 228 Support performance monitoring as defined in CXL rev 3.0 229 section 13.2: Performance Monitoring. CXL components may have 230 one or more CXL Performance Monitoring Units (CPMUs). 231 232 Say 'y/m' to enable a driver that will attach to performance 233 monitoring units and provide standard perf based interfaces. 234 235 If unsure say 'm'. 236 237endmenu 238