1# 2# Performance Monitor Drivers 3# 4 5menu "Performance monitor support" 6 depends on PERF_EVENTS 7 8config ARM_CCI_PMU 9 tristate "ARM CCI PMU driver" 10 depends on (ARM && CPU_V7) || ARM64 11 select ARM_CCI 12 help 13 Support for PMU events monitoring on the ARM CCI (Cache Coherent 14 Interconnect) family of products. 15 16 If compiled as a module, it will be called arm-cci. 17 18config ARM_CCI400_PMU 19 bool "support CCI-400" 20 default y 21 depends on ARM_CCI_PMU 22 select ARM_CCI400_COMMON 23 help 24 CCI-400 provides 4 independent event counters counting events related 25 to the connected slave/master interfaces, plus a cycle counter. 26 27config ARM_CCI5xx_PMU 28 bool "support CCI-500/CCI-550" 29 default y 30 depends on ARM_CCI_PMU 31 help 32 CCI-500/CCI-550 both provide 8 independent event counters, which can 33 count events pertaining to the slave/master interfaces as well as the 34 internal events to the CCI. 35 36config ARM_CCN 37 tristate "ARM CCN driver support" 38 depends on ARM || ARM64 39 help 40 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 41 interconnect. 42 43config ARM_PMU 44 depends on ARM || ARM64 45 bool "ARM PMU framework" 46 default y 47 help 48 Say y if you want to use CPU performance monitors on ARM-based 49 systems. 50 51config ARM_PMU_ACPI 52 depends on ARM_PMU && ACPI 53 def_bool y 54 55config ARM_SMMU_V3_PMU 56 tristate "ARM SMMUv3 Performance Monitors Extension" 57 depends on ARM64 && ACPI && ARM_SMMU_V3 58 help 59 Provides support for the ARM SMMUv3 Performance Monitor Counter 60 Groups (PMCG), which provide monitoring of transactions passing 61 through the SMMU and allow the resulting information to be filtered 62 based on the Stream ID of the corresponding master. 63 64config ARM_DSU_PMU 65 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 66 depends on ARM64 67 help 68 Provides support for performance monitor unit in ARM DynamIQ Shared 69 Unit (DSU). The DSU integrates one or more cores with an L3 memory 70 system, control logic. The PMU allows counting various events related 71 to DSU. 72 73config HISI_PMU 74 bool "HiSilicon SoC PMU" 75 depends on ARM64 && ACPI 76 help 77 Support for HiSilicon SoC uncore performance monitoring 78 unit (PMU), such as: L3C, HHA and DDRC. 79 80config QCOM_L2_PMU 81 bool "Qualcomm Technologies L2-cache PMU" 82 depends on ARCH_QCOM && ARM64 && ACPI 83 help 84 Provides support for the L2 cache performance monitor unit (PMU) 85 in Qualcomm Technologies processors. 86 Adds the L2 cache PMU into the perf events subsystem for 87 monitoring L2 cache events. 88 89config QCOM_L3_PMU 90 bool "Qualcomm Technologies L3-cache PMU" 91 depends on ARCH_QCOM && ARM64 && ACPI 92 select QCOM_IRQ_COMBINER 93 help 94 Provides support for the L3 cache performance monitor unit (PMU) 95 in Qualcomm Technologies processors. 96 Adds the L3 cache PMU into the perf events subsystem for 97 monitoring L3 cache events. 98 99config THUNDERX2_PMU 100 tristate "Cavium ThunderX2 SoC PMU UNCORE" 101 depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA 102 default m 103 help 104 Provides support for ThunderX2 UNCORE events. 105 The SoC has PMU support in its L3 cache controller (L3C) and 106 in the DDR4 Memory Controller (DMC). 107 108config XGENE_PMU 109 depends on ARCH_XGENE 110 bool "APM X-Gene SoC PMU" 111 default n 112 help 113 Say y if you want to use APM X-Gene SoC performance monitors. 114 115config ARM_SPE_PMU 116 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 117 depends on ARM64 118 help 119 Enable perf support for the ARMv8.2 Statistical Profiling 120 Extension, which provides periodic sampling of operations in 121 the CPU pipeline and reports this via the perf AUX interface. 122 123endmenu 124