xref: /openbmc/linux/drivers/perf/Kconfig (revision a90bb65a) 
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Performance Monitor Drivers
4#
5
6menu "Performance monitor support"
7	depends on PERF_EVENTS
8
9config ARM_CCI_PMU
10	tristate "ARM CCI PMU driver"
11	depends on (ARM && CPU_V7) || ARM64
12	select ARM_CCI
13	help
14	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
15	  Interconnect) family of products.
16
17	  If compiled as a module, it will be called arm-cci.
18
19config ARM_CCI400_PMU
20	bool "support CCI-400"
21	default y
22	depends on ARM_CCI_PMU
23	select ARM_CCI400_COMMON
24	help
25	  CCI-400 provides 4 independent event counters counting events related
26	  to the connected slave/master interfaces, plus a cycle counter.
27
28config ARM_CCI5xx_PMU
29	bool "support CCI-500/CCI-550"
30	default y
31	depends on ARM_CCI_PMU
32	help
33	  CCI-500/CCI-550 both provide 8 independent event counters, which can
34	  count events pertaining to the slave/master interfaces as well as the
35	  internal events to the CCI.
36
37config ARM_CCN
38	tristate "ARM CCN driver support"
39	depends on ARM || ARM64 || COMPILE_TEST
40	help
41	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
42	  interconnect.
43
44config ARM_CMN
45	tristate "Arm CMN-600 PMU support"
46	depends on ARM64 || COMPILE_TEST
47	help
48	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
49	  Network interconnect.
50
51config ARM_PMU
52	depends on ARM || ARM64
53	bool "ARM PMU framework"
54	default y
55	help
56	  Say y if you want to use CPU performance monitors on ARM-based
57	  systems.
58
59config RISCV_PMU
60	depends on RISCV
61	bool "RISC-V PMU framework"
62	default y
63	help
64	  Say y if you want to use CPU performance monitors on RISCV-based
65	  systems. This provides the core PMU framework that abstracts common
66	  PMU functionalities in a core library so that different PMU drivers
67	  can reuse it.
68
69config RISCV_PMU_LEGACY
70	depends on RISCV_PMU
71	bool "RISC-V legacy PMU implementation"
72	default y
73	help
74	  Say y if you want to use the legacy CPU performance monitor
75	  implementation on RISC-V based systems. This only allows counting
76	  of cycle/instruction counter and doesn't support counter overflow,
77	  or programmable counters. It will be removed in future.
78
79config RISCV_PMU_SBI
80	depends on RISCV_PMU && RISCV_SBI
81	bool "RISC-V PMU based on SBI PMU extension"
82	default y
83	help
84	  Say y if you want to use the CPU performance monitor
85	  using SBI PMU extension on RISC-V based systems. This option provides
86	  full perf feature support i.e. counter overflow, privilege mode
87	  filtering, counter configuration.
88
89config ARM_PMU_ACPI
90	depends on ARM_PMU && ACPI
91	def_bool y
92
93config ARM_SMMU_V3_PMU
94	 tristate "ARM SMMUv3 Performance Monitors Extension"
95	 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
96	 depends on GENERIC_MSI_IRQ_DOMAIN
97	   help
98	   Provides support for the ARM SMMUv3 Performance Monitor Counter
99	   Groups (PMCG), which provide monitoring of transactions passing
100	   through the SMMU and allow the resulting information to be filtered
101	   based on the Stream ID of the corresponding master.
102
103config ARM_DSU_PMU
104	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
105	depends on ARM64
106	  help
107	  Provides support for performance monitor unit in ARM DynamIQ Shared
108	  Unit (DSU). The DSU integrates one or more cores with an L3 memory
109	  system, control logic. The PMU allows counting various events related
110	  to DSU.
111
112config FSL_IMX8_DDR_PMU
113	tristate "Freescale i.MX8 DDR perf monitor"
114	depends on ARCH_MXC || COMPILE_TEST
115	  help
116	  Provides support for the DDR performance monitor in i.MX8, which
117	  can give information about memory throughput and other related
118	  events.
119
120config QCOM_L2_PMU
121	bool "Qualcomm Technologies L2-cache PMU"
122	depends on ARCH_QCOM && ARM64 && ACPI
123	select QCOM_KRYO_L2_ACCESSORS
124	  help
125	  Provides support for the L2 cache performance monitor unit (PMU)
126	  in Qualcomm Technologies processors.
127	  Adds the L2 cache PMU into the perf events subsystem for
128	  monitoring L2 cache events.
129
130config QCOM_L3_PMU
131	bool "Qualcomm Technologies L3-cache PMU"
132	depends on ARCH_QCOM && ARM64 && ACPI
133	select QCOM_IRQ_COMBINER
134	help
135	   Provides support for the L3 cache performance monitor unit (PMU)
136	   in Qualcomm Technologies processors.
137	   Adds the L3 cache PMU into the perf events subsystem for
138	   monitoring L3 cache events.
139
140config THUNDERX2_PMU
141	tristate "Cavium ThunderX2 SoC PMU UNCORE"
142	depends on ARCH_THUNDER2 || COMPILE_TEST
143	depends on NUMA && ACPI
144	default m
145	help
146	   Provides support for ThunderX2 UNCORE events.
147	   The SoC has PMU support in its L3 cache controller (L3C) and
148	   in the DDR4 Memory Controller (DMC).
149
150config XGENE_PMU
151        depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
152        bool "APM X-Gene SoC PMU"
153        default n
154        help
155          Say y if you want to use APM X-Gene SoC performance monitors.
156
157config ARM_SPE_PMU
158	tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
159	depends on ARM64
160	help
161	  Enable perf support for the ARMv8.2 Statistical Profiling
162	  Extension, which provides periodic sampling of operations in
163	  the CPU pipeline and reports this via the perf AUX interface.
164
165config ARM_DMC620_PMU
166	tristate "Enable PMU support for the ARM DMC-620 memory controller"
167	depends on (ARM64 && ACPI) || COMPILE_TEST
168	help
169	  Support for PMU events monitoring on the ARM DMC-620 memory
170	  controller.
171
172config MARVELL_CN10K_TAD_PMU
173	tristate "Marvell CN10K LLC-TAD PMU"
174	depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
175	help
176	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
177	  performance monitors on CN10K family silicons.
178
179config APPLE_M1_CPU_PMU
180	bool "Apple M1 CPU PMU support"
181	depends on ARM_PMU && ARCH_APPLE
182	help
183	  Provides support for the non-architectural CPU PMUs present on
184	  the Apple M1 SoCs and derivatives.
185
186source "drivers/perf/hisilicon/Kconfig"
187
188config MARVELL_CN10K_DDR_PMU
189	tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
190	depends on ARM64 || (COMPILE_TEST && 64BIT)
191	help
192	  Enable perf support for Marvell DDR Performance monitoring
193	  event on CN10K platform.
194
195endmenu
196