1# 2# Performance Monitor Drivers 3# 4 5menu "Performance monitor support" 6 depends on PERF_EVENTS 7 8config ARM_CCI_PMU 9 bool 10 select ARM_CCI 11 12config ARM_CCI400_PMU 13 bool "ARM CCI400 PMU support" 14 depends on (ARM && CPU_V7) || ARM64 15 select ARM_CCI400_COMMON 16 select ARM_CCI_PMU 17 help 18 Support for PMU events monitoring on the ARM CCI-400 (cache coherent 19 interconnect). CCI-400 supports counting events related to the 20 connected slave/master interfaces. 21 22config ARM_CCI5xx_PMU 23 bool "ARM CCI-500/CCI-550 PMU support" 24 depends on (ARM && CPU_V7) || ARM64 25 select ARM_CCI_PMU 26 help 27 Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache 28 coherent interconnects. Both of them provide 8 independent event counters, 29 which can count events pertaining to the slave/master interfaces as well 30 as the internal events to the CCI. 31 32 If unsure, say Y 33 34config ARM_CCN 35 tristate "ARM CCN driver support" 36 depends on ARM || ARM64 37 help 38 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 39 interconnect. 40 41config ARM_PMU 42 depends on ARM || ARM64 43 bool "ARM PMU framework" 44 default y 45 help 46 Say y if you want to use CPU performance monitors on ARM-based 47 systems. 48 49config ARM_PMU_ACPI 50 depends on ARM_PMU && ACPI 51 def_bool y 52 53config ARM_DSU_PMU 54 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 55 depends on ARM64 56 help 57 Provides support for performance monitor unit in ARM DynamIQ Shared 58 Unit (DSU). The DSU integrates one or more cores with an L3 memory 59 system, control logic. The PMU allows counting various events related 60 to DSU. 61 62config HISI_PMU 63 bool "HiSilicon SoC PMU" 64 depends on ARM64 && ACPI 65 help 66 Support for HiSilicon SoC uncore performance monitoring 67 unit (PMU), such as: L3C, HHA and DDRC. 68 69config QCOM_L2_PMU 70 bool "Qualcomm Technologies L2-cache PMU" 71 depends on ARCH_QCOM && ARM64 && ACPI 72 help 73 Provides support for the L2 cache performance monitor unit (PMU) 74 in Qualcomm Technologies processors. 75 Adds the L2 cache PMU into the perf events subsystem for 76 monitoring L2 cache events. 77 78config QCOM_L3_PMU 79 bool "Qualcomm Technologies L3-cache PMU" 80 depends on ARCH_QCOM && ARM64 && ACPI 81 select QCOM_IRQ_COMBINER 82 help 83 Provides support for the L3 cache performance monitor unit (PMU) 84 in Qualcomm Technologies processors. 85 Adds the L3 cache PMU into the perf events subsystem for 86 monitoring L3 cache events. 87 88config XGENE_PMU 89 depends on ARCH_XGENE 90 bool "APM X-Gene SoC PMU" 91 default n 92 help 93 Say y if you want to use APM X-Gene SoC performance monitors. 94 95config ARM_SPE_PMU 96 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 97 depends on PERF_EVENTS && ARM64 98 help 99 Enable perf support for the ARMv8.2 Statistical Profiling 100 Extension, which provides periodic sampling of operations in 101 the CPU pipeline and reports this via the perf AUX interface. 102 103endmenu 104