1*ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2fa8ad788SMark Rutland# 3fa8ad788SMark Rutland# Performance Monitor Drivers 4fa8ad788SMark Rutland# 5fa8ad788SMark Rutland 6fa8ad788SMark Rutlandmenu "Performance monitor support" 7bddb9b68SMark Rutland depends on PERF_EVENTS 8fa8ad788SMark Rutland 93de6be7aSRobin Murphyconfig ARM_CCI_PMU 108b0c93c2SRobin Murphy tristate "ARM CCI PMU driver" 118b0c93c2SRobin Murphy depends on (ARM && CPU_V7) || ARM64 123de6be7aSRobin Murphy select ARM_CCI 138b0c93c2SRobin Murphy help 148b0c93c2SRobin Murphy Support for PMU events monitoring on the ARM CCI (Cache Coherent 158b0c93c2SRobin Murphy Interconnect) family of products. 168b0c93c2SRobin Murphy 178b0c93c2SRobin Murphy If compiled as a module, it will be called arm-cci. 183de6be7aSRobin Murphy 193de6be7aSRobin Murphyconfig ARM_CCI400_PMU 208b0c93c2SRobin Murphy bool "support CCI-400" 218b0c93c2SRobin Murphy default y 228b0c93c2SRobin Murphy depends on ARM_CCI_PMU 233de6be7aSRobin Murphy select ARM_CCI400_COMMON 243de6be7aSRobin Murphy help 258b0c93c2SRobin Murphy CCI-400 provides 4 independent event counters counting events related 268b0c93c2SRobin Murphy to the connected slave/master interfaces, plus a cycle counter. 273de6be7aSRobin Murphy 283de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 298b0c93c2SRobin Murphy bool "support CCI-500/CCI-550" 308b0c93c2SRobin Murphy default y 318b0c93c2SRobin Murphy depends on ARM_CCI_PMU 323de6be7aSRobin Murphy help 338b0c93c2SRobin Murphy CCI-500/CCI-550 both provide 8 independent event counters, which can 348b0c93c2SRobin Murphy count events pertaining to the slave/master interfaces as well as the 358b0c93c2SRobin Murphy internal events to the CCI. 363de6be7aSRobin Murphy 371888d3ddSRobin Murphyconfig ARM_CCN 381888d3ddSRobin Murphy tristate "ARM CCN driver support" 391888d3ddSRobin Murphy depends on ARM || ARM64 401888d3ddSRobin Murphy help 411888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 421888d3ddSRobin Murphy interconnect. 431888d3ddSRobin Murphy 44fa8ad788SMark Rutlandconfig ARM_PMU 45bddb9b68SMark Rutland depends on ARM || ARM64 46fa8ad788SMark Rutland bool "ARM PMU framework" 47fa8ad788SMark Rutland default y 48fa8ad788SMark Rutland help 49fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 50fa8ad788SMark Rutland systems. 51fa8ad788SMark Rutland 5245736a72SMark Rutlandconfig ARM_PMU_ACPI 5345736a72SMark Rutland depends on ARM_PMU && ACPI 5445736a72SMark Rutland def_bool y 5545736a72SMark Rutland 567d839b4bSNeil Leederconfig ARM_SMMU_V3_PMU 577d839b4bSNeil Leeder tristate "ARM SMMUv3 Performance Monitors Extension" 587d839b4bSNeil Leeder depends on ARM64 && ACPI && ARM_SMMU_V3 597d839b4bSNeil Leeder help 607d839b4bSNeil Leeder Provides support for the ARM SMMUv3 Performance Monitor Counter 617d839b4bSNeil Leeder Groups (PMCG), which provide monitoring of transactions passing 627d839b4bSNeil Leeder through the SMMU and allow the resulting information to be filtered 637d839b4bSNeil Leeder based on the Stream ID of the corresponding master. 647d839b4bSNeil Leeder 657520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 667520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 677520fa99SSuzuki K Poulose depends on ARM64 687520fa99SSuzuki K Poulose help 697520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 707520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 717520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 727520fa99SSuzuki K Poulose to DSU. 737520fa99SSuzuki K Poulose 746ce4ef94SShaokun Zhangconfig HISI_PMU 756ce4ef94SShaokun Zhang bool "HiSilicon SoC PMU" 766ce4ef94SShaokun Zhang depends on ARM64 && ACPI 776ce4ef94SShaokun Zhang help 786ce4ef94SShaokun Zhang Support for HiSilicon SoC uncore performance monitoring 796ce4ef94SShaokun Zhang unit (PMU), such as: L3C, HHA and DDRC. 806ce4ef94SShaokun Zhang 8121bdbb71SNeil Leederconfig QCOM_L2_PMU 8221bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 83bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 8421bdbb71SNeil Leeder help 8521bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 8621bdbb71SNeil Leeder in Qualcomm Technologies processors. 8721bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 8821bdbb71SNeil Leeder monitoring L2 cache events. 8921bdbb71SNeil Leeder 903071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 913071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 92bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 933071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 943071f13dSAgustin Vega-Frias help 953071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 963071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 973071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 983071f13dSAgustin Vega-Frias monitoring L3 cache events. 993071f13dSAgustin Vega-Frias 10069c32972SKulkarni, Ganapatraoconfig THUNDERX2_PMU 10169c32972SKulkarni, Ganapatrao tristate "Cavium ThunderX2 SoC PMU UNCORE" 10269c32972SKulkarni, Ganapatrao depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA 10369c32972SKulkarni, Ganapatrao default m 10469c32972SKulkarni, Ganapatrao help 10569c32972SKulkarni, Ganapatrao Provides support for ThunderX2 UNCORE events. 10669c32972SKulkarni, Ganapatrao The SoC has PMU support in its L3 cache controller (L3C) and 10769c32972SKulkarni, Ganapatrao in the DDR4 Memory Controller (DMC). 10869c32972SKulkarni, Ganapatrao 109832c927dSTai Nguyenconfig XGENE_PMU 110bddb9b68SMark Rutland depends on ARCH_XGENE 111832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 112832c927dSTai Nguyen default n 113832c927dSTai Nguyen help 114832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 115832c927dSTai Nguyen 116d5d9696bSWill Deaconconfig ARM_SPE_PMU 117d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 118b89205bdSJohn Garry depends on ARM64 119d5d9696bSWill Deacon help 120d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 121d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 122d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 123d5d9696bSWill Deacon 124fa8ad788SMark Rutlandendmenu 125