1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2fa8ad788SMark Rutland# 3fa8ad788SMark Rutland# Performance Monitor Drivers 4fa8ad788SMark Rutland# 5fa8ad788SMark Rutland 6fa8ad788SMark Rutlandmenu "Performance monitor support" 7bddb9b68SMark Rutland depends on PERF_EVENTS 8fa8ad788SMark Rutland 93de6be7aSRobin Murphyconfig ARM_CCI_PMU 108b0c93c2SRobin Murphy tristate "ARM CCI PMU driver" 118b0c93c2SRobin Murphy depends on (ARM && CPU_V7) || ARM64 123de6be7aSRobin Murphy select ARM_CCI 138b0c93c2SRobin Murphy help 148b0c93c2SRobin Murphy Support for PMU events monitoring on the ARM CCI (Cache Coherent 158b0c93c2SRobin Murphy Interconnect) family of products. 168b0c93c2SRobin Murphy 178b0c93c2SRobin Murphy If compiled as a module, it will be called arm-cci. 183de6be7aSRobin Murphy 193de6be7aSRobin Murphyconfig ARM_CCI400_PMU 208b0c93c2SRobin Murphy bool "support CCI-400" 218b0c93c2SRobin Murphy default y 228b0c93c2SRobin Murphy depends on ARM_CCI_PMU 233de6be7aSRobin Murphy select ARM_CCI400_COMMON 243de6be7aSRobin Murphy help 258b0c93c2SRobin Murphy CCI-400 provides 4 independent event counters counting events related 268b0c93c2SRobin Murphy to the connected slave/master interfaces, plus a cycle counter. 273de6be7aSRobin Murphy 283de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 298b0c93c2SRobin Murphy bool "support CCI-500/CCI-550" 308b0c93c2SRobin Murphy default y 318b0c93c2SRobin Murphy depends on ARM_CCI_PMU 323de6be7aSRobin Murphy help 338b0c93c2SRobin Murphy CCI-500/CCI-550 both provide 8 independent event counters, which can 348b0c93c2SRobin Murphy count events pertaining to the slave/master interfaces as well as the 358b0c93c2SRobin Murphy internal events to the CCI. 363de6be7aSRobin Murphy 371888d3ddSRobin Murphyconfig ARM_CCN 381888d3ddSRobin Murphy tristate "ARM CCN driver support" 39e656972bSJohn Garry depends on ARM || ARM64 || COMPILE_TEST 401888d3ddSRobin Murphy help 411888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 421888d3ddSRobin Murphy interconnect. 431888d3ddSRobin Murphy 440ba64770SRobin Murphyconfig ARM_CMN 450ba64770SRobin Murphy tristate "Arm CMN-600 PMU support" 4682d8ea4bSRobin Murphy depends on ARM64 || COMPILE_TEST 470ba64770SRobin Murphy help 480ba64770SRobin Murphy Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 490ba64770SRobin Murphy Network interconnect. 500ba64770SRobin Murphy 51fa8ad788SMark Rutlandconfig ARM_PMU 52bddb9b68SMark Rutland depends on ARM || ARM64 53fa8ad788SMark Rutland bool "ARM PMU framework" 54fa8ad788SMark Rutland default y 55fa8ad788SMark Rutland help 56fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 57fa8ad788SMark Rutland systems. 58fa8ad788SMark Rutland 59f5bfa23fSAtish Patraconfig RISCV_PMU 60f5bfa23fSAtish Patra depends on RISCV 61f5bfa23fSAtish Patra bool "RISC-V PMU framework" 62f5bfa23fSAtish Patra default y 63f5bfa23fSAtish Patra help 64f5bfa23fSAtish Patra Say y if you want to use CPU performance monitors on RISCV-based 65f5bfa23fSAtish Patra systems. This provides the core PMU framework that abstracts common 66f5bfa23fSAtish Patra PMU functionalities in a core library so that different PMU drivers 67f5bfa23fSAtish Patra can reuse it. 68f5bfa23fSAtish Patra 699b3e150eSAtish Patraconfig RISCV_PMU_LEGACY 709b3e150eSAtish Patra depends on RISCV_PMU 719b3e150eSAtish Patra bool "RISC-V legacy PMU implementation" 729b3e150eSAtish Patra default y 739b3e150eSAtish Patra help 749b3e150eSAtish Patra Say y if you want to use the legacy CPU performance monitor 759b3e150eSAtish Patra implementation on RISC-V based systems. This only allows counting 769b3e150eSAtish Patra of cycle/instruction counter and doesn't support counter overflow, 779b3e150eSAtish Patra or programmable counters. It will be removed in future. 789b3e150eSAtish Patra 79*e9991434SAtish Patraconfig RISCV_PMU_SBI 80*e9991434SAtish Patra depends on RISCV_PMU && RISCV_SBI 81*e9991434SAtish Patra bool "RISC-V PMU based on SBI PMU extension" 82*e9991434SAtish Patra default y 83*e9991434SAtish Patra help 84*e9991434SAtish Patra Say y if you want to use the CPU performance monitor 85*e9991434SAtish Patra using SBI PMU extension on RISC-V based systems. This option provides 86*e9991434SAtish Patra full perf feature support i.e. counter overflow, privilege mode 87*e9991434SAtish Patra filtering, counter configuration. 88*e9991434SAtish Patra 8945736a72SMark Rutlandconfig ARM_PMU_ACPI 9045736a72SMark Rutland depends on ARM_PMU && ACPI 9145736a72SMark Rutland def_bool y 9245736a72SMark Rutland 937d839b4bSNeil Leederconfig ARM_SMMU_V3_PMU 947d839b4bSNeil Leeder tristate "ARM SMMUv3 Performance Monitors Extension" 95e656972bSJohn Garry depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) 96e656972bSJohn Garry depends on GENERIC_MSI_IRQ_DOMAIN 977d839b4bSNeil Leeder help 987d839b4bSNeil Leeder Provides support for the ARM SMMUv3 Performance Monitor Counter 997d839b4bSNeil Leeder Groups (PMCG), which provide monitoring of transactions passing 1007d839b4bSNeil Leeder through the SMMU and allow the resulting information to be filtered 1017d839b4bSNeil Leeder based on the Stream ID of the corresponding master. 1027d839b4bSNeil Leeder 1037520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 1047520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 1057520fa99SSuzuki K Poulose depends on ARM64 1067520fa99SSuzuki K Poulose help 1077520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 1087520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 1097520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 1107520fa99SSuzuki K Poulose to DSU. 1117520fa99SSuzuki K Poulose 1129a66d36cSFrank Liconfig FSL_IMX8_DDR_PMU 1139a66d36cSFrank Li tristate "Freescale i.MX8 DDR perf monitor" 114e656972bSJohn Garry depends on ARCH_MXC || COMPILE_TEST 1159a66d36cSFrank Li help 1169a66d36cSFrank Li Provides support for the DDR performance monitor in i.MX8, which 1179a66d36cSFrank Li can give information about memory throughput and other related 1189a66d36cSFrank Li events. 1199a66d36cSFrank Li 12021bdbb71SNeil Leederconfig QCOM_L2_PMU 12121bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 122bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1236d0efeb1SIlia Lin select QCOM_KRYO_L2_ACCESSORS 12421bdbb71SNeil Leeder help 12521bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 12621bdbb71SNeil Leeder in Qualcomm Technologies processors. 12721bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 12821bdbb71SNeil Leeder monitoring L2 cache events. 12921bdbb71SNeil Leeder 1303071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 1313071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 132bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1333071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 1343071f13dSAgustin Vega-Frias help 1353071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 1363071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 1373071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 1383071f13dSAgustin Vega-Frias monitoring L3 cache events. 1393071f13dSAgustin Vega-Frias 14069c32972SKulkarni, Ganapatraoconfig THUNDERX2_PMU 14169c32972SKulkarni, Ganapatrao tristate "Cavium ThunderX2 SoC PMU UNCORE" 142e656972bSJohn Garry depends on ARCH_THUNDER2 || COMPILE_TEST 143e656972bSJohn Garry depends on NUMA && ACPI 14469c32972SKulkarni, Ganapatrao default m 14569c32972SKulkarni, Ganapatrao help 14669c32972SKulkarni, Ganapatrao Provides support for ThunderX2 UNCORE events. 14769c32972SKulkarni, Ganapatrao The SoC has PMU support in its L3 cache controller (L3C) and 14869c32972SKulkarni, Ganapatrao in the DDR4 Memory Controller (DMC). 14969c32972SKulkarni, Ganapatrao 150832c927dSTai Nguyenconfig XGENE_PMU 151e656972bSJohn Garry depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 152832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 153832c927dSTai Nguyen default n 154832c927dSTai Nguyen help 155832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 156832c927dSTai Nguyen 157d5d9696bSWill Deaconconfig ARM_SPE_PMU 158d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 159b89205bdSJohn Garry depends on ARM64 160d5d9696bSWill Deacon help 161d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 162d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 163d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 164d5d9696bSWill Deacon 16553c218daSTuan Phanconfig ARM_DMC620_PMU 16653c218daSTuan Phan tristate "Enable PMU support for the ARM DMC-620 memory controller" 16753c218daSTuan Phan depends on (ARM64 && ACPI) || COMPILE_TEST 16853c218daSTuan Phan help 16953c218daSTuan Phan Support for PMU events monitoring on the ARM DMC-620 memory 17053c218daSTuan Phan controller. 17153c218daSTuan Phan 172036a7584SBhaskara Budiredlaconfig MARVELL_CN10K_TAD_PMU 173036a7584SBhaskara Budiredla tristate "Marvell CN10K LLC-TAD PMU" 174036a7584SBhaskara Budiredla depends on ARM64 || (COMPILE_TEST && 64BIT) 175036a7584SBhaskara Budiredla help 176036a7584SBhaskara Budiredla Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 177036a7584SBhaskara Budiredla performance monitors on CN10K family silicons. 178036a7584SBhaskara Budiredla 17997807325SZhou Wangsource "drivers/perf/hisilicon/Kconfig" 18097807325SZhou Wang 181fa8ad788SMark Rutlandendmenu 182