1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2fa8ad788SMark Rutland# 3fa8ad788SMark Rutland# Performance Monitor Drivers 4fa8ad788SMark Rutland# 5fa8ad788SMark Rutland 6fa8ad788SMark Rutlandmenu "Performance monitor support" 7bddb9b68SMark Rutland depends on PERF_EVENTS 8fa8ad788SMark Rutland 93de6be7aSRobin Murphyconfig ARM_CCI_PMU 108b0c93c2SRobin Murphy tristate "ARM CCI PMU driver" 118b0c93c2SRobin Murphy depends on (ARM && CPU_V7) || ARM64 123de6be7aSRobin Murphy select ARM_CCI 138b0c93c2SRobin Murphy help 148b0c93c2SRobin Murphy Support for PMU events monitoring on the ARM CCI (Cache Coherent 158b0c93c2SRobin Murphy Interconnect) family of products. 168b0c93c2SRobin Murphy 178b0c93c2SRobin Murphy If compiled as a module, it will be called arm-cci. 183de6be7aSRobin Murphy 193de6be7aSRobin Murphyconfig ARM_CCI400_PMU 208b0c93c2SRobin Murphy bool "support CCI-400" 218b0c93c2SRobin Murphy default y 228b0c93c2SRobin Murphy depends on ARM_CCI_PMU 233de6be7aSRobin Murphy select ARM_CCI400_COMMON 243de6be7aSRobin Murphy help 258b0c93c2SRobin Murphy CCI-400 provides 4 independent event counters counting events related 268b0c93c2SRobin Murphy to the connected slave/master interfaces, plus a cycle counter. 273de6be7aSRobin Murphy 283de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 298b0c93c2SRobin Murphy bool "support CCI-500/CCI-550" 308b0c93c2SRobin Murphy default y 318b0c93c2SRobin Murphy depends on ARM_CCI_PMU 323de6be7aSRobin Murphy help 338b0c93c2SRobin Murphy CCI-500/CCI-550 both provide 8 independent event counters, which can 348b0c93c2SRobin Murphy count events pertaining to the slave/master interfaces as well as the 358b0c93c2SRobin Murphy internal events to the CCI. 363de6be7aSRobin Murphy 371888d3ddSRobin Murphyconfig ARM_CCN 381888d3ddSRobin Murphy tristate "ARM CCN driver support" 39e656972bSJohn Garry depends on ARM || ARM64 || COMPILE_TEST 401888d3ddSRobin Murphy help 411888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 421888d3ddSRobin Murphy interconnect. 431888d3ddSRobin Murphy 440ba64770SRobin Murphyconfig ARM_CMN 450ba64770SRobin Murphy tristate "Arm CMN-600 PMU support" 4682d8ea4bSRobin Murphy depends on ARM64 || COMPILE_TEST 470ba64770SRobin Murphy help 480ba64770SRobin Murphy Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 490ba64770SRobin Murphy Network interconnect. 500ba64770SRobin Murphy 51fa8ad788SMark Rutlandconfig ARM_PMU 52bddb9b68SMark Rutland depends on ARM || ARM64 53fa8ad788SMark Rutland bool "ARM PMU framework" 54fa8ad788SMark Rutland default y 55fa8ad788SMark Rutland help 56fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 57fa8ad788SMark Rutland systems. 58fa8ad788SMark Rutland 5945736a72SMark Rutlandconfig ARM_PMU_ACPI 6045736a72SMark Rutland depends on ARM_PMU && ACPI 6145736a72SMark Rutland def_bool y 6245736a72SMark Rutland 637d839b4bSNeil Leederconfig ARM_SMMU_V3_PMU 647d839b4bSNeil Leeder tristate "ARM SMMUv3 Performance Monitors Extension" 65e656972bSJohn Garry depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) 66e656972bSJohn Garry depends on GENERIC_MSI_IRQ_DOMAIN 677d839b4bSNeil Leeder help 687d839b4bSNeil Leeder Provides support for the ARM SMMUv3 Performance Monitor Counter 697d839b4bSNeil Leeder Groups (PMCG), which provide monitoring of transactions passing 707d839b4bSNeil Leeder through the SMMU and allow the resulting information to be filtered 717d839b4bSNeil Leeder based on the Stream ID of the corresponding master. 727d839b4bSNeil Leeder 737520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 747520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 757520fa99SSuzuki K Poulose depends on ARM64 767520fa99SSuzuki K Poulose help 777520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 787520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 797520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 807520fa99SSuzuki K Poulose to DSU. 817520fa99SSuzuki K Poulose 829a66d36cSFrank Liconfig FSL_IMX8_DDR_PMU 839a66d36cSFrank Li tristate "Freescale i.MX8 DDR perf monitor" 84e656972bSJohn Garry depends on ARCH_MXC || COMPILE_TEST 859a66d36cSFrank Li help 869a66d36cSFrank Li Provides support for the DDR performance monitor in i.MX8, which 879a66d36cSFrank Li can give information about memory throughput and other related 889a66d36cSFrank Li events. 899a66d36cSFrank Li 9021bdbb71SNeil Leederconfig QCOM_L2_PMU 9121bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 92bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 936d0efeb1SIlia Lin select QCOM_KRYO_L2_ACCESSORS 9421bdbb71SNeil Leeder help 9521bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 9621bdbb71SNeil Leeder in Qualcomm Technologies processors. 9721bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 9821bdbb71SNeil Leeder monitoring L2 cache events. 9921bdbb71SNeil Leeder 1003071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 1013071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 102bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1033071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 1043071f13dSAgustin Vega-Frias help 1053071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 1063071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 1073071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 1083071f13dSAgustin Vega-Frias monitoring L3 cache events. 1093071f13dSAgustin Vega-Frias 11069c32972SKulkarni, Ganapatraoconfig THUNDERX2_PMU 11169c32972SKulkarni, Ganapatrao tristate "Cavium ThunderX2 SoC PMU UNCORE" 112e656972bSJohn Garry depends on ARCH_THUNDER2 || COMPILE_TEST 113e656972bSJohn Garry depends on NUMA && ACPI 11469c32972SKulkarni, Ganapatrao default m 11569c32972SKulkarni, Ganapatrao help 11669c32972SKulkarni, Ganapatrao Provides support for ThunderX2 UNCORE events. 11769c32972SKulkarni, Ganapatrao The SoC has PMU support in its L3 cache controller (L3C) and 11869c32972SKulkarni, Ganapatrao in the DDR4 Memory Controller (DMC). 11969c32972SKulkarni, Ganapatrao 120832c927dSTai Nguyenconfig XGENE_PMU 121e656972bSJohn Garry depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 122832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 123832c927dSTai Nguyen default n 124832c927dSTai Nguyen help 125832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 126832c927dSTai Nguyen 127d5d9696bSWill Deaconconfig ARM_SPE_PMU 128d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 129b89205bdSJohn Garry depends on ARM64 130d5d9696bSWill Deacon help 131d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 132d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 133d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 134d5d9696bSWill Deacon 13553c218daSTuan Phanconfig ARM_DMC620_PMU 13653c218daSTuan Phan tristate "Enable PMU support for the ARM DMC-620 memory controller" 13753c218daSTuan Phan depends on (ARM64 && ACPI) || COMPILE_TEST 13853c218daSTuan Phan help 13953c218daSTuan Phan Support for PMU events monitoring on the ARM DMC-620 memory 14053c218daSTuan Phan controller. 14153c218daSTuan Phan 142036a7584SBhaskara Budiredlaconfig MARVELL_CN10K_TAD_PMU 143036a7584SBhaskara Budiredla tristate "Marvell CN10K LLC-TAD PMU" 144*e564518bSGeert Uytterhoeven depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 145036a7584SBhaskara Budiredla help 146036a7584SBhaskara Budiredla Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 147036a7584SBhaskara Budiredla performance monitors on CN10K family silicons. 148036a7584SBhaskara Budiredla 14997807325SZhou Wangsource "drivers/perf/hisilicon/Kconfig" 15097807325SZhou Wang 151fa8ad788SMark Rutlandendmenu 152