1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2fa8ad788SMark Rutland# 3fa8ad788SMark Rutland# Performance Monitor Drivers 4fa8ad788SMark Rutland# 5fa8ad788SMark Rutland 6fa8ad788SMark Rutlandmenu "Performance monitor support" 7bddb9b68SMark Rutland depends on PERF_EVENTS 8fa8ad788SMark Rutland 93de6be7aSRobin Murphyconfig ARM_CCI_PMU 108b0c93c2SRobin Murphy tristate "ARM CCI PMU driver" 118b0c93c2SRobin Murphy depends on (ARM && CPU_V7) || ARM64 123de6be7aSRobin Murphy select ARM_CCI 138b0c93c2SRobin Murphy help 148b0c93c2SRobin Murphy Support for PMU events monitoring on the ARM CCI (Cache Coherent 158b0c93c2SRobin Murphy Interconnect) family of products. 168b0c93c2SRobin Murphy 178b0c93c2SRobin Murphy If compiled as a module, it will be called arm-cci. 183de6be7aSRobin Murphy 193de6be7aSRobin Murphyconfig ARM_CCI400_PMU 208b0c93c2SRobin Murphy bool "support CCI-400" 218b0c93c2SRobin Murphy default y 228b0c93c2SRobin Murphy depends on ARM_CCI_PMU 233de6be7aSRobin Murphy select ARM_CCI400_COMMON 243de6be7aSRobin Murphy help 258b0c93c2SRobin Murphy CCI-400 provides 4 independent event counters counting events related 268b0c93c2SRobin Murphy to the connected slave/master interfaces, plus a cycle counter. 273de6be7aSRobin Murphy 283de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 298b0c93c2SRobin Murphy bool "support CCI-500/CCI-550" 308b0c93c2SRobin Murphy default y 318b0c93c2SRobin Murphy depends on ARM_CCI_PMU 323de6be7aSRobin Murphy help 338b0c93c2SRobin Murphy CCI-500/CCI-550 both provide 8 independent event counters, which can 348b0c93c2SRobin Murphy count events pertaining to the slave/master interfaces as well as the 358b0c93c2SRobin Murphy internal events to the CCI. 363de6be7aSRobin Murphy 371888d3ddSRobin Murphyconfig ARM_CCN 381888d3ddSRobin Murphy tristate "ARM CCN driver support" 39e656972bSJohn Garry depends on ARM || ARM64 || COMPILE_TEST 401888d3ddSRobin Murphy help 411888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 421888d3ddSRobin Murphy interconnect. 431888d3ddSRobin Murphy 440ba64770SRobin Murphyconfig ARM_CMN 450ba64770SRobin Murphy tristate "Arm CMN-600 PMU support" 4682d8ea4bSRobin Murphy depends on ARM64 || COMPILE_TEST 470ba64770SRobin Murphy help 480ba64770SRobin Murphy Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 490ba64770SRobin Murphy Network interconnect. 500ba64770SRobin Murphy 51fa8ad788SMark Rutlandconfig ARM_PMU 52bddb9b68SMark Rutland depends on ARM || ARM64 53fa8ad788SMark Rutland bool "ARM PMU framework" 54fa8ad788SMark Rutland default y 55fa8ad788SMark Rutland help 56fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 57fa8ad788SMark Rutland systems. 58fa8ad788SMark Rutland 59f5bfa23fSAtish Patraconfig RISCV_PMU 60f5bfa23fSAtish Patra depends on RISCV 61f5bfa23fSAtish Patra bool "RISC-V PMU framework" 62f5bfa23fSAtish Patra default y 63f5bfa23fSAtish Patra help 64f5bfa23fSAtish Patra Say y if you want to use CPU performance monitors on RISCV-based 65f5bfa23fSAtish Patra systems. This provides the core PMU framework that abstracts common 66f5bfa23fSAtish Patra PMU functionalities in a core library so that different PMU drivers 67f5bfa23fSAtish Patra can reuse it. 68f5bfa23fSAtish Patra 69*9b3e150eSAtish Patraconfig RISCV_PMU_LEGACY 70*9b3e150eSAtish Patra depends on RISCV_PMU 71*9b3e150eSAtish Patra bool "RISC-V legacy PMU implementation" 72*9b3e150eSAtish Patra default y 73*9b3e150eSAtish Patra help 74*9b3e150eSAtish Patra Say y if you want to use the legacy CPU performance monitor 75*9b3e150eSAtish Patra implementation on RISC-V based systems. This only allows counting 76*9b3e150eSAtish Patra of cycle/instruction counter and doesn't support counter overflow, 77*9b3e150eSAtish Patra or programmable counters. It will be removed in future. 78*9b3e150eSAtish Patra 7945736a72SMark Rutlandconfig ARM_PMU_ACPI 8045736a72SMark Rutland depends on ARM_PMU && ACPI 8145736a72SMark Rutland def_bool y 8245736a72SMark Rutland 837d839b4bSNeil Leederconfig ARM_SMMU_V3_PMU 847d839b4bSNeil Leeder tristate "ARM SMMUv3 Performance Monitors Extension" 85e656972bSJohn Garry depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) 86e656972bSJohn Garry depends on GENERIC_MSI_IRQ_DOMAIN 877d839b4bSNeil Leeder help 887d839b4bSNeil Leeder Provides support for the ARM SMMUv3 Performance Monitor Counter 897d839b4bSNeil Leeder Groups (PMCG), which provide monitoring of transactions passing 907d839b4bSNeil Leeder through the SMMU and allow the resulting information to be filtered 917d839b4bSNeil Leeder based on the Stream ID of the corresponding master. 927d839b4bSNeil Leeder 937520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 947520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 957520fa99SSuzuki K Poulose depends on ARM64 967520fa99SSuzuki K Poulose help 977520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 987520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 997520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 1007520fa99SSuzuki K Poulose to DSU. 1017520fa99SSuzuki K Poulose 1029a66d36cSFrank Liconfig FSL_IMX8_DDR_PMU 1039a66d36cSFrank Li tristate "Freescale i.MX8 DDR perf monitor" 104e656972bSJohn Garry depends on ARCH_MXC || COMPILE_TEST 1059a66d36cSFrank Li help 1069a66d36cSFrank Li Provides support for the DDR performance monitor in i.MX8, which 1079a66d36cSFrank Li can give information about memory throughput and other related 1089a66d36cSFrank Li events. 1099a66d36cSFrank Li 11021bdbb71SNeil Leederconfig QCOM_L2_PMU 11121bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 112bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1136d0efeb1SIlia Lin select QCOM_KRYO_L2_ACCESSORS 11421bdbb71SNeil Leeder help 11521bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 11621bdbb71SNeil Leeder in Qualcomm Technologies processors. 11721bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 11821bdbb71SNeil Leeder monitoring L2 cache events. 11921bdbb71SNeil Leeder 1203071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 1213071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 122bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1233071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 1243071f13dSAgustin Vega-Frias help 1253071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 1263071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 1273071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 1283071f13dSAgustin Vega-Frias monitoring L3 cache events. 1293071f13dSAgustin Vega-Frias 13069c32972SKulkarni, Ganapatraoconfig THUNDERX2_PMU 13169c32972SKulkarni, Ganapatrao tristate "Cavium ThunderX2 SoC PMU UNCORE" 132e656972bSJohn Garry depends on ARCH_THUNDER2 || COMPILE_TEST 133e656972bSJohn Garry depends on NUMA && ACPI 13469c32972SKulkarni, Ganapatrao default m 13569c32972SKulkarni, Ganapatrao help 13669c32972SKulkarni, Ganapatrao Provides support for ThunderX2 UNCORE events. 13769c32972SKulkarni, Ganapatrao The SoC has PMU support in its L3 cache controller (L3C) and 13869c32972SKulkarni, Ganapatrao in the DDR4 Memory Controller (DMC). 13969c32972SKulkarni, Ganapatrao 140832c927dSTai Nguyenconfig XGENE_PMU 141e656972bSJohn Garry depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 142832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 143832c927dSTai Nguyen default n 144832c927dSTai Nguyen help 145832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 146832c927dSTai Nguyen 147d5d9696bSWill Deaconconfig ARM_SPE_PMU 148d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 149b89205bdSJohn Garry depends on ARM64 150d5d9696bSWill Deacon help 151d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 152d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 153d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 154d5d9696bSWill Deacon 15553c218daSTuan Phanconfig ARM_DMC620_PMU 15653c218daSTuan Phan tristate "Enable PMU support for the ARM DMC-620 memory controller" 15753c218daSTuan Phan depends on (ARM64 && ACPI) || COMPILE_TEST 15853c218daSTuan Phan help 15953c218daSTuan Phan Support for PMU events monitoring on the ARM DMC-620 memory 16053c218daSTuan Phan controller. 16153c218daSTuan Phan 162036a7584SBhaskara Budiredlaconfig MARVELL_CN10K_TAD_PMU 163036a7584SBhaskara Budiredla tristate "Marvell CN10K LLC-TAD PMU" 164036a7584SBhaskara Budiredla depends on ARM64 || (COMPILE_TEST && 64BIT) 165036a7584SBhaskara Budiredla help 166036a7584SBhaskara Budiredla Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 167036a7584SBhaskara Budiredla performance monitors on CN10K family silicons. 168036a7584SBhaskara Budiredla 16997807325SZhou Wangsource "drivers/perf/hisilicon/Kconfig" 17097807325SZhou Wang 171fa8ad788SMark Rutlandendmenu 172