1fa8ad788SMark Rutland# 2fa8ad788SMark Rutland# Performance Monitor Drivers 3fa8ad788SMark Rutland# 4fa8ad788SMark Rutland 5fa8ad788SMark Rutlandmenu "Performance monitor support" 6bddb9b68SMark Rutland depends on PERF_EVENTS 7fa8ad788SMark Rutland 8fa8ad788SMark Rutlandconfig ARM_PMU 9bddb9b68SMark Rutland depends on ARM || ARM64 10fa8ad788SMark Rutland bool "ARM PMU framework" 11fa8ad788SMark Rutland default y 12fa8ad788SMark Rutland help 13fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 14fa8ad788SMark Rutland systems. 15fa8ad788SMark Rutland 1645736a72SMark Rutlandconfig ARM_PMU_ACPI 1745736a72SMark Rutland depends on ARM_PMU && ACPI 1845736a72SMark Rutland def_bool y 1945736a72SMark Rutland 20*7520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 21*7520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 22*7520fa99SSuzuki K Poulose depends on ARM64 23*7520fa99SSuzuki K Poulose help 24*7520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 25*7520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 26*7520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 27*7520fa99SSuzuki K Poulose to DSU. 28*7520fa99SSuzuki K Poulose 296ce4ef94SShaokun Zhangconfig HISI_PMU 306ce4ef94SShaokun Zhang bool "HiSilicon SoC PMU" 316ce4ef94SShaokun Zhang depends on ARM64 && ACPI 326ce4ef94SShaokun Zhang help 336ce4ef94SShaokun Zhang Support for HiSilicon SoC uncore performance monitoring 346ce4ef94SShaokun Zhang unit (PMU), such as: L3C, HHA and DDRC. 356ce4ef94SShaokun Zhang 3621bdbb71SNeil Leederconfig QCOM_L2_PMU 3721bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 38bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 3921bdbb71SNeil Leeder help 4021bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 4121bdbb71SNeil Leeder in Qualcomm Technologies processors. 4221bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 4321bdbb71SNeil Leeder monitoring L2 cache events. 4421bdbb71SNeil Leeder 453071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 463071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 47bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 483071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 493071f13dSAgustin Vega-Frias help 503071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 513071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 523071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 533071f13dSAgustin Vega-Frias monitoring L3 cache events. 543071f13dSAgustin Vega-Frias 55832c927dSTai Nguyenconfig XGENE_PMU 56bddb9b68SMark Rutland depends on ARCH_XGENE 57832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 58832c927dSTai Nguyen default n 59832c927dSTai Nguyen help 60832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 61832c927dSTai Nguyen 62d5d9696bSWill Deaconconfig ARM_SPE_PMU 63d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 64d5d9696bSWill Deacon depends on PERF_EVENTS && ARM64 65d5d9696bSWill Deacon help 66d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 67d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 68d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 69d5d9696bSWill Deacon 70fa8ad788SMark Rutlandendmenu 71