1fa8ad788SMark Rutland# 2fa8ad788SMark Rutland# Performance Monitor Drivers 3fa8ad788SMark Rutland# 4fa8ad788SMark Rutland 5fa8ad788SMark Rutlandmenu "Performance monitor support" 6bddb9b68SMark Rutland depends on PERF_EVENTS 7fa8ad788SMark Rutland 8fa8ad788SMark Rutlandconfig ARM_PMU 9bddb9b68SMark Rutland depends on ARM || ARM64 10fa8ad788SMark Rutland bool "ARM PMU framework" 11fa8ad788SMark Rutland default y 12fa8ad788SMark Rutland help 13fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 14fa8ad788SMark Rutland systems. 15fa8ad788SMark Rutland 1645736a72SMark Rutlandconfig ARM_PMU_ACPI 1745736a72SMark Rutland depends on ARM_PMU && ACPI 1845736a72SMark Rutland def_bool y 1945736a72SMark Rutland 20*6ce4ef94SShaokun Zhangconfig HISI_PMU 21*6ce4ef94SShaokun Zhang bool "HiSilicon SoC PMU" 22*6ce4ef94SShaokun Zhang depends on ARM64 && ACPI 23*6ce4ef94SShaokun Zhang help 24*6ce4ef94SShaokun Zhang Support for HiSilicon SoC uncore performance monitoring 25*6ce4ef94SShaokun Zhang unit (PMU), such as: L3C, HHA and DDRC. 26*6ce4ef94SShaokun Zhang 2721bdbb71SNeil Leederconfig QCOM_L2_PMU 2821bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 29bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 3021bdbb71SNeil Leeder help 3121bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 3221bdbb71SNeil Leeder in Qualcomm Technologies processors. 3321bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 3421bdbb71SNeil Leeder monitoring L2 cache events. 3521bdbb71SNeil Leeder 363071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 373071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 38bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 393071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 403071f13dSAgustin Vega-Frias help 413071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 423071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 433071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 443071f13dSAgustin Vega-Frias monitoring L3 cache events. 453071f13dSAgustin Vega-Frias 46832c927dSTai Nguyenconfig XGENE_PMU 47bddb9b68SMark Rutland depends on ARCH_XGENE 48832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 49832c927dSTai Nguyen default n 50832c927dSTai Nguyen help 51832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 52832c927dSTai Nguyen 53d5d9696bSWill Deaconconfig ARM_SPE_PMU 54d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 55d5d9696bSWill Deacon depends on PERF_EVENTS && ARM64 56d5d9696bSWill Deacon help 57d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 58d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 59d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 60d5d9696bSWill Deacon 61fa8ad788SMark Rutlandendmenu 62