1fa8ad788SMark Rutland# 2fa8ad788SMark Rutland# Performance Monitor Drivers 3fa8ad788SMark Rutland# 4fa8ad788SMark Rutland 5fa8ad788SMark Rutlandmenu "Performance monitor support" 6bddb9b68SMark Rutland depends on PERF_EVENTS 7fa8ad788SMark Rutland 83de6be7aSRobin Murphyconfig ARM_CCI_PMU 98b0c93c2SRobin Murphy tristate "ARM CCI PMU driver" 108b0c93c2SRobin Murphy depends on (ARM && CPU_V7) || ARM64 113de6be7aSRobin Murphy select ARM_CCI 128b0c93c2SRobin Murphy help 138b0c93c2SRobin Murphy Support for PMU events monitoring on the ARM CCI (Cache Coherent 148b0c93c2SRobin Murphy Interconnect) family of products. 158b0c93c2SRobin Murphy 168b0c93c2SRobin Murphy If compiled as a module, it will be called arm-cci. 173de6be7aSRobin Murphy 183de6be7aSRobin Murphyconfig ARM_CCI400_PMU 198b0c93c2SRobin Murphy bool "support CCI-400" 208b0c93c2SRobin Murphy default y 218b0c93c2SRobin Murphy depends on ARM_CCI_PMU 223de6be7aSRobin Murphy select ARM_CCI400_COMMON 233de6be7aSRobin Murphy help 248b0c93c2SRobin Murphy CCI-400 provides 4 independent event counters counting events related 258b0c93c2SRobin Murphy to the connected slave/master interfaces, plus a cycle counter. 263de6be7aSRobin Murphy 273de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 288b0c93c2SRobin Murphy bool "support CCI-500/CCI-550" 298b0c93c2SRobin Murphy default y 308b0c93c2SRobin Murphy depends on ARM_CCI_PMU 313de6be7aSRobin Murphy help 328b0c93c2SRobin Murphy CCI-500/CCI-550 both provide 8 independent event counters, which can 338b0c93c2SRobin Murphy count events pertaining to the slave/master interfaces as well as the 348b0c93c2SRobin Murphy internal events to the CCI. 353de6be7aSRobin Murphy 361888d3ddSRobin Murphyconfig ARM_CCN 371888d3ddSRobin Murphy tristate "ARM CCN driver support" 381888d3ddSRobin Murphy depends on ARM || ARM64 391888d3ddSRobin Murphy help 401888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 411888d3ddSRobin Murphy interconnect. 421888d3ddSRobin Murphy 43fa8ad788SMark Rutlandconfig ARM_PMU 44bddb9b68SMark Rutland depends on ARM || ARM64 45fa8ad788SMark Rutland bool "ARM PMU framework" 46fa8ad788SMark Rutland default y 47fa8ad788SMark Rutland help 48fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 49fa8ad788SMark Rutland systems. 50fa8ad788SMark Rutland 5145736a72SMark Rutlandconfig ARM_PMU_ACPI 5245736a72SMark Rutland depends on ARM_PMU && ACPI 5345736a72SMark Rutland def_bool y 5445736a72SMark Rutland 557520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 567520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 577520fa99SSuzuki K Poulose depends on ARM64 587520fa99SSuzuki K Poulose help 597520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 607520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 617520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 627520fa99SSuzuki K Poulose to DSU. 637520fa99SSuzuki K Poulose 646ce4ef94SShaokun Zhangconfig HISI_PMU 656ce4ef94SShaokun Zhang bool "HiSilicon SoC PMU" 666ce4ef94SShaokun Zhang depends on ARM64 && ACPI 676ce4ef94SShaokun Zhang help 686ce4ef94SShaokun Zhang Support for HiSilicon SoC uncore performance monitoring 696ce4ef94SShaokun Zhang unit (PMU), such as: L3C, HHA and DDRC. 706ce4ef94SShaokun Zhang 7121bdbb71SNeil Leederconfig QCOM_L2_PMU 7221bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 73bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 7421bdbb71SNeil Leeder help 7521bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 7621bdbb71SNeil Leeder in Qualcomm Technologies processors. 7721bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 7821bdbb71SNeil Leeder monitoring L2 cache events. 7921bdbb71SNeil Leeder 803071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 813071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 82bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 833071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 843071f13dSAgustin Vega-Frias help 853071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 863071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 873071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 883071f13dSAgustin Vega-Frias monitoring L3 cache events. 893071f13dSAgustin Vega-Frias 9069c32972SKulkarni, Ganapatraoconfig THUNDERX2_PMU 9169c32972SKulkarni, Ganapatrao tristate "Cavium ThunderX2 SoC PMU UNCORE" 9269c32972SKulkarni, Ganapatrao depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA 9369c32972SKulkarni, Ganapatrao default m 9469c32972SKulkarni, Ganapatrao help 9569c32972SKulkarni, Ganapatrao Provides support for ThunderX2 UNCORE events. 9669c32972SKulkarni, Ganapatrao The SoC has PMU support in its L3 cache controller (L3C) and 9769c32972SKulkarni, Ganapatrao in the DDR4 Memory Controller (DMC). 9869c32972SKulkarni, Ganapatrao 99832c927dSTai Nguyenconfig XGENE_PMU 100bddb9b68SMark Rutland depends on ARCH_XGENE 101832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 102832c927dSTai Nguyen default n 103832c927dSTai Nguyen help 104832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 105832c927dSTai Nguyen 106d5d9696bSWill Deaconconfig ARM_SPE_PMU 107d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 108b89205bdSJohn Garry depends on ARM64 109d5d9696bSWill Deacon help 110d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 111d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 112d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 113d5d9696bSWill Deacon 114fa8ad788SMark Rutlandendmenu 115