1fa8ad788SMark Rutland# 2fa8ad788SMark Rutland# Performance Monitor Drivers 3fa8ad788SMark Rutland# 4fa8ad788SMark Rutland 5fa8ad788SMark Rutlandmenu "Performance monitor support" 6bddb9b68SMark Rutland depends on PERF_EVENTS 7fa8ad788SMark Rutland 8*3de6be7aSRobin Murphyconfig ARM_CCI_PMU 9*3de6be7aSRobin Murphy bool 10*3de6be7aSRobin Murphy select ARM_CCI 11*3de6be7aSRobin Murphy 12*3de6be7aSRobin Murphyconfig ARM_CCI400_PMU 13*3de6be7aSRobin Murphy bool "ARM CCI400 PMU support" 14*3de6be7aSRobin Murphy depends on (ARM && CPU_V7) || ARM64 15*3de6be7aSRobin Murphy select ARM_CCI400_COMMON 16*3de6be7aSRobin Murphy select ARM_CCI_PMU 17*3de6be7aSRobin Murphy help 18*3de6be7aSRobin Murphy Support for PMU events monitoring on the ARM CCI-400 (cache coherent 19*3de6be7aSRobin Murphy interconnect). CCI-400 supports counting events related to the 20*3de6be7aSRobin Murphy connected slave/master interfaces. 21*3de6be7aSRobin Murphy 22*3de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 23*3de6be7aSRobin Murphy bool "ARM CCI-500/CCI-550 PMU support" 24*3de6be7aSRobin Murphy depends on (ARM && CPU_V7) || ARM64 25*3de6be7aSRobin Murphy select ARM_CCI_PMU 26*3de6be7aSRobin Murphy help 27*3de6be7aSRobin Murphy Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache 28*3de6be7aSRobin Murphy coherent interconnects. Both of them provide 8 independent event counters, 29*3de6be7aSRobin Murphy which can count events pertaining to the slave/master interfaces as well 30*3de6be7aSRobin Murphy as the internal events to the CCI. 31*3de6be7aSRobin Murphy 32*3de6be7aSRobin Murphy If unsure, say Y 33*3de6be7aSRobin Murphy 341888d3ddSRobin Murphyconfig ARM_CCN 351888d3ddSRobin Murphy tristate "ARM CCN driver support" 361888d3ddSRobin Murphy depends on ARM || ARM64 371888d3ddSRobin Murphy help 381888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 391888d3ddSRobin Murphy interconnect. 401888d3ddSRobin Murphy 41fa8ad788SMark Rutlandconfig ARM_PMU 42bddb9b68SMark Rutland depends on ARM || ARM64 43fa8ad788SMark Rutland bool "ARM PMU framework" 44fa8ad788SMark Rutland default y 45fa8ad788SMark Rutland help 46fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 47fa8ad788SMark Rutland systems. 48fa8ad788SMark Rutland 4945736a72SMark Rutlandconfig ARM_PMU_ACPI 5045736a72SMark Rutland depends on ARM_PMU && ACPI 5145736a72SMark Rutland def_bool y 5245736a72SMark Rutland 537520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 547520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 557520fa99SSuzuki K Poulose depends on ARM64 567520fa99SSuzuki K Poulose help 577520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 587520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 597520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 607520fa99SSuzuki K Poulose to DSU. 617520fa99SSuzuki K Poulose 626ce4ef94SShaokun Zhangconfig HISI_PMU 636ce4ef94SShaokun Zhang bool "HiSilicon SoC PMU" 646ce4ef94SShaokun Zhang depends on ARM64 && ACPI 656ce4ef94SShaokun Zhang help 666ce4ef94SShaokun Zhang Support for HiSilicon SoC uncore performance monitoring 676ce4ef94SShaokun Zhang unit (PMU), such as: L3C, HHA and DDRC. 686ce4ef94SShaokun Zhang 6921bdbb71SNeil Leederconfig QCOM_L2_PMU 7021bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 71bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 7221bdbb71SNeil Leeder help 7321bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 7421bdbb71SNeil Leeder in Qualcomm Technologies processors. 7521bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 7621bdbb71SNeil Leeder monitoring L2 cache events. 7721bdbb71SNeil Leeder 783071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 793071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 80bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 813071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 823071f13dSAgustin Vega-Frias help 833071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 843071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 853071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 863071f13dSAgustin Vega-Frias monitoring L3 cache events. 873071f13dSAgustin Vega-Frias 88832c927dSTai Nguyenconfig XGENE_PMU 89bddb9b68SMark Rutland depends on ARCH_XGENE 90832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 91832c927dSTai Nguyen default n 92832c927dSTai Nguyen help 93832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 94832c927dSTai Nguyen 95d5d9696bSWill Deaconconfig ARM_SPE_PMU 96d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 97d5d9696bSWill Deacon depends on PERF_EVENTS && ARM64 98d5d9696bSWill Deacon help 99d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 100d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 101d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 102d5d9696bSWill Deacon 103fa8ad788SMark Rutlandendmenu 104