1fa8ad788SMark Rutland# 2fa8ad788SMark Rutland# Performance Monitor Drivers 3fa8ad788SMark Rutland# 4fa8ad788SMark Rutland 5fa8ad788SMark Rutlandmenu "Performance monitor support" 6bddb9b68SMark Rutland depends on PERF_EVENTS 7fa8ad788SMark Rutland 81888d3ddSRobin Murphyconfig ARM_CCN 91888d3ddSRobin Murphy tristate "ARM CCN driver support" 101888d3ddSRobin Murphy depends on ARM || ARM64 111888d3ddSRobin Murphy help 121888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 131888d3ddSRobin Murphy interconnect. 141888d3ddSRobin Murphy 15fa8ad788SMark Rutlandconfig ARM_PMU 16bddb9b68SMark Rutland depends on ARM || ARM64 17fa8ad788SMark Rutland bool "ARM PMU framework" 18fa8ad788SMark Rutland default y 19fa8ad788SMark Rutland help 20fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 21fa8ad788SMark Rutland systems. 22fa8ad788SMark Rutland 2345736a72SMark Rutlandconfig ARM_PMU_ACPI 2445736a72SMark Rutland depends on ARM_PMU && ACPI 2545736a72SMark Rutland def_bool y 2645736a72SMark Rutland 277520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 287520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 297520fa99SSuzuki K Poulose depends on ARM64 307520fa99SSuzuki K Poulose help 317520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 327520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 337520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 347520fa99SSuzuki K Poulose to DSU. 357520fa99SSuzuki K Poulose 366ce4ef94SShaokun Zhangconfig HISI_PMU 376ce4ef94SShaokun Zhang bool "HiSilicon SoC PMU" 386ce4ef94SShaokun Zhang depends on ARM64 && ACPI 396ce4ef94SShaokun Zhang help 406ce4ef94SShaokun Zhang Support for HiSilicon SoC uncore performance monitoring 416ce4ef94SShaokun Zhang unit (PMU), such as: L3C, HHA and DDRC. 426ce4ef94SShaokun Zhang 4321bdbb71SNeil Leederconfig QCOM_L2_PMU 4421bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 45bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 4621bdbb71SNeil Leeder help 4721bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 4821bdbb71SNeil Leeder in Qualcomm Technologies processors. 4921bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 5021bdbb71SNeil Leeder monitoring L2 cache events. 5121bdbb71SNeil Leeder 523071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 533071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 54bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 553071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 563071f13dSAgustin Vega-Frias help 573071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 583071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 593071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 603071f13dSAgustin Vega-Frias monitoring L3 cache events. 613071f13dSAgustin Vega-Frias 62832c927dSTai Nguyenconfig XGENE_PMU 63bddb9b68SMark Rutland depends on ARCH_XGENE 64832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 65832c927dSTai Nguyen default n 66832c927dSTai Nguyen help 67832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 68832c927dSTai Nguyen 69d5d9696bSWill Deaconconfig ARM_SPE_PMU 70d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 71d5d9696bSWill Deacon depends on PERF_EVENTS && ARM64 72d5d9696bSWill Deacon help 73d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 74d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 75d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 76d5d9696bSWill Deacon 77fa8ad788SMark Rutlandendmenu 78