1 /* 2 * tcic.h 1.13 1999/10/25 20:03:34 3 * 4 * The contents of this file are subject to the Mozilla Public License 5 * Version 1.1 (the "License"); you may not use this file except in 6 * compliance with the License. You may obtain a copy of the License 7 * at http://www.mozilla.org/MPL/ 8 * 9 * Software distributed under the License is distributed on an "AS IS" 10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See 11 * the License for the specific language governing rights and 12 * limitations under the License. 13 * 14 * The initial developer of the original code is David A. Hinds 15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 17 * 18 * Alternatively, the contents of this file may be used under the 19 * terms of the GNU General Public License version 2 (the "GPL"), in which 20 * case the provisions of the GPL are applicable instead of the 21 * above. If you wish to allow the use of your version of this file 22 * only under the terms of the GPL and not to allow others to use 23 * your version of this file under the MPL, indicate your decision by 24 * deleting the provisions above and replace them with the notice and 25 * other provisions required by the GPL. If you do not delete the 26 * provisions above, a recipient may use your version of this file 27 * under either the MPL or the GPL. 28 */ 29 30 #ifndef _LINUX_TCIC_H 31 #define _LINUX_TCIC_H 32 33 #define TCIC_BASE 0x240 34 35 /* offsets of registers from TCIC_BASE */ 36 #define TCIC_DATA 0x00 37 #define TCIC_ADDR 0x02 38 #define TCIC_SCTRL 0x06 39 #define TCIC_SSTAT 0x07 40 #define TCIC_MODE 0x08 41 #define TCIC_PWR 0x09 42 #define TCIC_EDC 0x0A 43 #define TCIC_ICSR 0x0C 44 #define TCIC_IENA 0x0D 45 #define TCIC_AUX 0x0E 46 47 #define TCIC_SS_SHFT 12 48 #define TCIC_SS_MASK 0x7000 49 50 /* Flags for TCIC_ADDR */ 51 #define TCIC_ADR2_REG 0x8000 52 #define TCIC_ADR2_INDREG 0x0800 53 54 #define TCIC_ADDR_REG 0x80000000 55 #define TCIC_ADDR_SS_SHFT (TCIC_SS_SHFT+16) 56 #define TCIC_ADDR_SS_MASK (TCIC_SS_MASK<<16) 57 #define TCIC_ADDR_INDREG 0x08000000 58 #define TCIC_ADDR_IO 0x04000000 59 #define TCIC_ADDR_MASK 0x03ffffff 60 61 /* Flags for TCIC_SCTRL */ 62 #define TCIC_SCTRL_ENA 0x01 63 #define TCIC_SCTRL_INCMODE 0x18 64 #define TCIC_SCTRL_INCMODE_HOLD 0x00 65 #define TCIC_SCTRL_INCMODE_WORD 0x08 66 #define TCIC_SCTRL_INCMODE_REG 0x10 67 #define TCIC_SCTRL_INCMODE_AUTO 0x18 68 #define TCIC_SCTRL_EDCSUM 0x20 69 #define TCIC_SCTRL_RESET 0x80 70 71 /* Flags for TCIC_SSTAT */ 72 #define TCIC_SSTAT_6US 0x01 73 #define TCIC_SSTAT_10US 0x02 74 #define TCIC_SSTAT_PROGTIME 0x04 75 #define TCIC_SSTAT_LBAT1 0x08 76 #define TCIC_SSTAT_LBAT2 0x10 77 #define TCIC_SSTAT_RDY 0x20 /* Inverted */ 78 #define TCIC_SSTAT_WP 0x40 79 #define TCIC_SSTAT_CD 0x80 /* Card detect */ 80 81 /* Flags for TCIC_MODE */ 82 #define TCIC_MODE_PGMMASK 0x1f 83 #define TCIC_MODE_NORMAL 0x00 84 #define TCIC_MODE_PGMWR 0x01 85 #define TCIC_MODE_PGMRD 0x02 86 #define TCIC_MODE_PGMCE 0x04 87 #define TCIC_MODE_PGMDBW 0x08 88 #define TCIC_MODE_PGMWORD 0x10 89 #define TCIC_MODE_AUXSEL_MASK 0xe0 90 91 /* Registers accessed through TCIC_AUX, by setting TCIC_MODE */ 92 #define TCIC_AUX_TCTL (0<<5) 93 #define TCIC_AUX_PCTL (1<<5) 94 #define TCIC_AUX_WCTL (2<<5) 95 #define TCIC_AUX_EXTERN (3<<5) 96 #define TCIC_AUX_PDATA (4<<5) 97 #define TCIC_AUX_SYSCFG (5<<5) 98 #define TCIC_AUX_ILOCK (6<<5) 99 #define TCIC_AUX_TEST (7<<5) 100 101 /* Flags for TCIC_PWR */ 102 #define TCIC_PWR_VCC(sock) (0x01<<(sock)) 103 #define TCIC_PWR_VCC_MASK 0x03 104 #define TCIC_PWR_VPP(sock) (0x08<<(sock)) 105 #define TCIC_PWR_VPP_MASK 0x18 106 #define TCIC_PWR_CLIMENA 0x40 107 #define TCIC_PWR_CLIMSTAT 0x80 108 109 /* Flags for TCIC_ICSR */ 110 #define TCIC_ICSR_CLEAR 0x01 111 #define TCIC_ICSR_SET 0x02 112 #define TCIC_ICSR_JAM (TCIC_ICSR_CLEAR|TCIC_ICSR_SET) 113 #define TCIC_ICSR_STOPCPU 0x04 114 #define TCIC_ICSR_ILOCK 0x08 115 #define TCIC_ICSR_PROGTIME 0x10 116 #define TCIC_ICSR_ERR 0x20 117 #define TCIC_ICSR_CDCHG 0x40 118 #define TCIC_ICSR_IOCHK 0x80 119 120 /* Flags for TCIC_IENA */ 121 #define TCIC_IENA_CFG_MASK 0x03 122 #define TCIC_IENA_CFG_OFF 0x00 /* disabled */ 123 #define TCIC_IENA_CFG_OD 0x01 /* active low, open drain */ 124 #define TCIC_IENA_CFG_LOW 0x02 /* active low, totem pole */ 125 #define TCIC_IENA_CFG_HIGH 0x03 /* active high, totem pole */ 126 #define TCIC_IENA_ILOCK 0x08 127 #define TCIC_IENA_PROGTIME 0x10 128 #define TCIC_IENA_ERR 0x20 /* overcurrent or iochk */ 129 #define TCIC_IENA_CDCHG 0x40 130 131 /* Flags for TCIC_AUX_WCTL */ 132 #define TCIC_WAIT_COUNT_MASK 0x001f 133 #define TCIC_WAIT_ASYNC 0x0020 134 #define TCIC_WAIT_SENSE 0x0040 135 #define TCIC_WAIT_SRC 0x0080 136 #define TCIC_WCTL_WR 0x0100 137 #define TCIC_WCTL_RD 0x0200 138 #define TCIC_WCTL_CE 0x0400 139 #define TCIC_WCTL_LLBAT1 0x0800 140 #define TCIC_WCTL_LLBAT2 0x1000 141 #define TCIC_WCTL_LRDY 0x2000 142 #define TCIC_WCTL_LWP 0x4000 143 #define TCIC_WCTL_LCD 0x8000 144 145 /* Flags for TCIC_AUX_SYSCFG */ 146 #define TCIC_SYSCFG_IRQ_MASK 0x000f 147 #define TCIC_SYSCFG_MCSFULL 0x0010 148 #define TCIC_SYSCFG_IO1723 0x0020 149 #define TCIC_SYSCFG_MCSXB 0x0040 150 #define TCIC_SYSCFG_ICSXB 0x0080 151 #define TCIC_SYSCFG_NOPDN 0x0100 152 #define TCIC_SYSCFG_MPSEL_SHFT 9 153 #define TCIC_SYSCFG_MPSEL_MASK 0x0e00 154 #define TCIC_SYSCFG_MPSENSE 0x2000 155 #define TCIC_SYSCFG_AUTOBUSY 0x4000 156 #define TCIC_SYSCFG_ACC 0x8000 157 158 #define TCIC_ILOCK_OUT 0x01 159 #define TCIC_ILOCK_SENSE 0x02 160 #define TCIC_ILOCK_CRESET 0x04 161 #define TCIC_ILOCK_CRESENA 0x08 162 #define TCIC_ILOCK_CWAIT 0x10 163 #define TCIC_ILOCK_CWAITSNS 0x20 164 #define TCIC_ILOCK_HOLD_MASK 0xc0 165 #define TCIC_ILOCK_HOLD_CCLK 0xc0 166 167 #define TCIC_ILOCKTEST_ID_SH 8 168 #define TCIC_ILOCKTEST_ID_MASK 0x7f00 169 #define TCIC_ILOCKTEST_MCIC_1 0x8000 170 171 #define TCIC_ID_DB86082 0x02 172 #define TCIC_ID_DB86082A 0x03 173 #define TCIC_ID_DB86084 0x04 174 #define TCIC_ID_DB86084A 0x08 175 #define TCIC_ID_DB86072 0x15 176 #define TCIC_ID_DB86184 0x14 177 #define TCIC_ID_DB86082B 0x17 178 179 #define TCIC_TEST_DIAG 0x8000 180 181 /* 182 * Indirectly addressed registers 183 */ 184 185 #define TCIC_SCF1(sock) ((sock)<<3) 186 #define TCIC_SCF2(sock) (((sock)<<3)+2) 187 188 /* Flags for SCF1 */ 189 #define TCIC_SCF1_IRQ_MASK 0x000f 190 #define TCIC_SCF1_IRQ_OFF 0x0000 191 #define TCIC_SCF1_IRQOC 0x0010 192 #define TCIC_SCF1_PCVT 0x0020 193 #define TCIC_SCF1_IRDY 0x0040 194 #define TCIC_SCF1_ATA 0x0080 195 #define TCIC_SCF1_DMA_SHIFT 8 196 #define TCIC_SCF1_DMA_MASK 0x0700 197 #define TCIC_SCF1_DMA_OFF 0 198 #define TCIC_SCF1_DREQ2 2 199 #define TCIC_SCF1_IOSTS 0x0800 200 #define TCIC_SCF1_SPKR 0x1000 201 #define TCIC_SCF1_FINPACK 0x2000 202 #define TCIC_SCF1_DELWR 0x4000 203 #define TCIC_SCF1_HD7IDE 0x8000 204 205 /* Flags for SCF2 */ 206 #define TCIC_SCF2_RI 0x0001 207 #define TCIC_SCF2_IDBR 0x0002 208 #define TCIC_SCF2_MDBR 0x0004 209 #define TCIC_SCF2_MLBAT1 0x0008 210 #define TCIC_SCF2_MLBAT2 0x0010 211 #define TCIC_SCF2_MRDY 0x0020 212 #define TCIC_SCF2_MWP 0x0040 213 #define TCIC_SCF2_MCD 0x0080 214 #define TCIC_SCF2_MALL 0x00f8 215 216 /* Indirect addresses for memory window registers */ 217 #define TCIC_MWIN(sock,map) (0x100+(((map)+((sock)<<2))<<3)) 218 #define TCIC_MBASE_X 2 219 #define TCIC_MMAP_X 4 220 #define TCIC_MCTL_X 6 221 222 #define TCIC_MBASE_4K_BIT 0x4000 223 #define TCIC_MBASE_HA_SHFT 12 224 #define TCIC_MBASE_HA_MASK 0x0fff 225 226 #define TCIC_MMAP_REG 0x8000 227 #define TCIC_MMAP_CA_SHFT 12 228 #define TCIC_MMAP_CA_MASK 0x3fff 229 230 #define TCIC_MCTL_WSCNT_MASK 0x001f 231 #define TCIC_MCTL_WCLK 0x0020 232 #define TCIC_MCTL_WCLK_CCLK 0x0000 233 #define TCIC_MCTL_WCLK_BCLK 0x0020 234 #define TCIC_MCTL_QUIET 0x0040 235 #define TCIC_MCTL_WP 0x0080 236 #define TCIC_MCTL_ACC 0x0100 237 #define TCIC_MCTL_KE 0x0200 238 #define TCIC_MCTL_EDC 0x0400 239 #define TCIC_MCTL_B8 0x0800 240 #define TCIC_MCTL_SS_SHFT TCIC_SS_SHFT 241 #define TCIC_MCTL_SS_MASK TCIC_SS_MASK 242 #define TCIC_MCTL_ENA 0x8000 243 244 /* Indirect addresses for I/O window registers */ 245 #define TCIC_IWIN(sock,map) (0x200+(((map)+((sock)<<1))<<2)) 246 #define TCIC_IBASE_X 0 247 #define TCIC_ICTL_X 2 248 249 #define TCIC_ICTL_WSCNT_MASK TCIC_MCTL_WSCNT_MASK 250 #define TCIC_ICTL_QUIET TCIC_MCTL_QUIET 251 #define TCIC_ICTL_1K 0x0080 252 #define TCIC_ICTL_PASS16 0x0100 253 #define TCIC_ICTL_ACC TCIC_MCTL_ACC 254 #define TCIC_ICTL_TINY 0x0200 255 #define TCIC_ICTL_B16 0x0400 256 #define TCIC_ICTL_B8 TCIC_MCTL_B8 257 #define TCIC_ICTL_BW_MASK (TCIC_ICTL_B16|TCIC_ICTL_B8) 258 #define TCIC_ICTL_BW_DYN 0 259 #define TCIC_ICTL_BW_8 TCIC_ICTL_B8 260 #define TCIC_ICTL_BW_16 TCIC_ICTL_B16 261 #define TCIC_ICTL_BW_ATA (TCIC_ICTL_B16|TCIC_ICTL_B8) 262 #define TCIC_ICTL_SS_SHFT TCIC_SS_SHFT 263 #define TCIC_ICTL_SS_MASK TCIC_SS_MASK 264 #define TCIC_ICTL_ENA TCIC_MCTL_ENA 265 266 #endif /* _LINUX_TCIC_H */ 267