xref: /openbmc/linux/drivers/pcmcia/pxa2xx_base.c (revision b6dcefde) 
1 /*======================================================================
2 
3   Device driver for the PCMCIA control functionality of PXA2xx
4   microprocessors.
5 
6     The contents of this file may be used under the
7     terms of the GNU Public License version 2 (the "GPL")
8 
9     (c) Ian Molton (spyro@f2s.com) 2003
10     (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
11 
12     derived from sa11xx_base.c
13 
14      Portions created by John G. Dorsey are
15      Copyright (C) 1999 John G. Dorsey.
16 
17   ======================================================================*/
18 
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/cpufreq.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
26 
27 #include <mach/hardware.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30 #include <asm/system.h>
31 #include <mach/pxa2xx-regs.h>
32 #include <asm/mach-types.h>
33 
34 #include <pcmcia/cs_types.h>
35 #include <pcmcia/ss.h>
36 #include <pcmcia/cistpl.h>
37 
38 #include "soc_common.h"
39 #include "pxa2xx_base.h"
40 
41 /*
42  * Personal Computer Memory Card International Association (PCMCIA) sockets
43  */
44 
45 #define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
46 #define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
47 #define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
48 #define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
49 #define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */
50 
51 #define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
52 #define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
53 #define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
54 #define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
55 
56 #define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
57 #define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
58 #define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
59 #define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
60 
61 #define _PCMCIA(Nb)			/* PCMCIA [0..1]                   */ \
62 			(0x20000000 + (Nb) * PCMCIASp)
63 #define _PCMCIAIO(Nb)	_PCMCIA(Nb)	/* PCMCIA I/O [0..1]               */
64 #define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]         */ \
65 			(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
66 #define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]            */ \
67 			(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
68 
69 #define _PCMCIA0	_PCMCIA(0)	/* PCMCIA 0                        */
70 #define _PCMCIA0IO	_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
71 #define _PCMCIA0Attr	_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
72 #define _PCMCIA0Mem	_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */
73 
74 #define _PCMCIA1	_PCMCIA(1)	/* PCMCIA 1                        */
75 #define _PCMCIA1IO	_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
76 #define _PCMCIA1Attr	_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
77 #define _PCMCIA1Mem	_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */
78 
79 
80 #define MCXX_SETUP_MASK     (0x7f)
81 #define MCXX_ASST_MASK      (0x1f)
82 #define MCXX_HOLD_MASK      (0x3f)
83 #define MCXX_SETUP_SHIFT    (0)
84 #define MCXX_ASST_SHIFT     (7)
85 #define MCXX_HOLD_SHIFT     (14)
86 
87 static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
88 				     u_int mem_clk_10khz)
89 {
90 	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
91 	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
92 }
93 
94 static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
95 				     u_int mem_clk_10khz)
96 {
97 	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
98 	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
99 }
100 
101 static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
102 				      u_int mem_clk_10khz)
103 {
104 	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
105 	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
106 }
107 
108 /* This function returns the (approximate) command assertion period, in
109  * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
110  */
111 static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
112 					   u_int pcmcia_mcxx_asst)
113 {
114 	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
115 }
116 
117 static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
118 {
119 	MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock)
120 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
121 		| ((pxa2xx_mcxx_asst(speed, clock)
122 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
123 		| ((pxa2xx_mcxx_hold(speed, clock)
124 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
125 
126 	return 0;
127 }
128 
129 static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
130 {
131 	MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock)
132 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
133 		| ((pxa2xx_mcxx_asst(speed, clock)
134 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
135 		| ((pxa2xx_mcxx_hold(speed, clock)
136 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
137 
138 	return 0;
139 }
140 
141 static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
142 {
143 	MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock)
144 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
145 		| ((pxa2xx_mcxx_asst(speed, clock)
146 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
147 		| ((pxa2xx_mcxx_hold(speed, clock)
148 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
149 
150 	return 0;
151 }
152 
153 static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
154 {
155 	struct soc_pcmcia_timing timing;
156 	int sock = skt->nr;
157 
158 	soc_common_pcmcia_get_timing(skt, &timing);
159 
160 	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
161 	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
162 	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
163 
164 	return 0;
165 }
166 
167 static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
168 {
169 	unsigned int clk = get_memclk_frequency_10khz();
170 	return pxa2xx_pcmcia_set_mcxx(skt, clk);
171 }
172 
173 #ifdef CONFIG_CPU_FREQ
174 
175 static int
176 pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
177 			       unsigned long val,
178 			       struct cpufreq_freqs *freqs)
179 {
180 #warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
181 	switch (val) {
182 	case CPUFREQ_PRECHANGE:
183 		if (freqs->new > freqs->old) {
184 			debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
185 			       "pre-updating\n",
186 			       freqs->new / 1000, (freqs->new / 100) % 10,
187 			       freqs->old / 1000, (freqs->old / 100) % 10);
188 			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
189 		}
190 		break;
191 
192 	case CPUFREQ_POSTCHANGE:
193 		if (freqs->new < freqs->old) {
194 			debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
195 			       "post-updating\n",
196 			       freqs->new / 1000, (freqs->new / 100) % 10,
197 			       freqs->old / 1000, (freqs->old / 100) % 10);
198 			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
199 		}
200 		break;
201 	}
202 	return 0;
203 }
204 #endif
205 
206 static void pxa2xx_configure_sockets(struct device *dev)
207 {
208 	struct pcmcia_low_level *ops = dev->platform_data;
209 
210 	/*
211 	 * We have at least one socket, so set MECR:CIT
212 	 * (Card Is There)
213 	 */
214 	MECR |= MECR_CIT;
215 
216 	/* Set MECR:NOS (Number Of Sockets) */
217 	if ((ops->first + ops->nr) > 1 ||
218 	    machine_is_viper() || machine_is_arcom_zeus())
219 		MECR |= MECR_NOS;
220 	else
221 		MECR &= ~MECR_NOS;
222 }
223 
224 static const char *skt_names[] = {
225 	"PCMCIA socket 0",
226 	"PCMCIA socket 1",
227 };
228 
229 #define SKT_DEV_INFO_SIZE(n) \
230 	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
231 
232 int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
233 {
234 	skt->res_skt.start = _PCMCIA(skt->nr);
235 	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
236 	skt->res_skt.name = skt_names[skt->nr];
237 	skt->res_skt.flags = IORESOURCE_MEM;
238 
239 	skt->res_io.start = _PCMCIAIO(skt->nr);
240 	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
241 	skt->res_io.name = "io";
242 	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
243 
244 	skt->res_mem.start = _PCMCIAMem(skt->nr);
245 	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
246 	skt->res_mem.name = "memory";
247 	skt->res_mem.flags = IORESOURCE_MEM;
248 
249 	skt->res_attr.start = _PCMCIAAttr(skt->nr);
250 	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
251 	skt->res_attr.name = "attribute";
252 	skt->res_attr.flags = IORESOURCE_MEM;
253 
254 	return soc_pcmcia_add_one(skt);
255 }
256 EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
257 
258 void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
259 {
260 	/* Provide our PXA2xx specific timing routines. */
261 	ops->set_timing  = pxa2xx_pcmcia_set_timing;
262 #ifdef CONFIG_CPU_FREQ
263 	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
264 #endif
265 }
266 EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
267 
268 static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
269 {
270 	int i, ret = 0;
271 	struct pcmcia_low_level *ops;
272 	struct skt_dev_info *sinfo;
273 	struct soc_pcmcia_socket *skt;
274 
275 	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
276 	if (!ops)
277 		return -ENODEV;
278 
279 	pxa2xx_drv_pcmcia_ops(ops);
280 
281 	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
282 	if (!sinfo)
283 		return -ENOMEM;
284 
285 	sinfo->nskt = ops->nr;
286 
287 	/* Initialize processor specific parameters */
288 	for (i = 0; i < ops->nr; i++) {
289 		skt = &sinfo->skt[i];
290 
291 		skt->nr = ops->first + i;
292 		skt->ops = ops;
293 		skt->socket.owner = ops->owner;
294 		skt->socket.dev.parent = &dev->dev;
295 		skt->socket.pci_irq = NO_IRQ;
296 
297 		ret = pxa2xx_drv_pcmcia_add_one(skt);
298 		if (ret)
299 			break;
300 	}
301 
302 	if (ret) {
303 		while (--i >= 0)
304 			soc_pcmcia_remove_one(&sinfo->skt[i]);
305 		kfree(sinfo);
306 	} else {
307 		pxa2xx_configure_sockets(&dev->dev);
308 		dev_set_drvdata(&dev->dev, sinfo);
309 	}
310 
311 	return ret;
312 }
313 
314 static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
315 {
316 	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
317 	int i;
318 
319 	platform_set_drvdata(dev, NULL);
320 
321 	for (i = 0; i < sinfo->nskt; i++)
322 		soc_pcmcia_remove_one(&sinfo->skt[i]);
323 
324 	kfree(sinfo);
325 	return 0;
326 }
327 
328 static int pxa2xx_drv_pcmcia_suspend(struct device *dev)
329 {
330 	return pcmcia_socket_dev_suspend(dev);
331 }
332 
333 static int pxa2xx_drv_pcmcia_resume(struct device *dev)
334 {
335 	pxa2xx_configure_sockets(dev);
336 	return pcmcia_socket_dev_resume(dev);
337 }
338 
339 static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
340 	.suspend	= pxa2xx_drv_pcmcia_suspend,
341 	.resume		= pxa2xx_drv_pcmcia_resume,
342 };
343 
344 static struct platform_driver pxa2xx_pcmcia_driver = {
345 	.probe		= pxa2xx_drv_pcmcia_probe,
346 	.remove		= pxa2xx_drv_pcmcia_remove,
347 	.driver		= {
348 		.name	= "pxa2xx-pcmcia",
349 		.owner	= THIS_MODULE,
350 		.pm	= &pxa2xx_drv_pcmcia_pm_ops,
351 	},
352 };
353 
354 static int __init pxa2xx_pcmcia_init(void)
355 {
356 	return platform_driver_register(&pxa2xx_pcmcia_driver);
357 }
358 
359 static void __exit pxa2xx_pcmcia_exit(void)
360 {
361 	platform_driver_unregister(&pxa2xx_pcmcia_driver);
362 }
363 
364 fs_initcall(pxa2xx_pcmcia_init);
365 module_exit(pxa2xx_pcmcia_exit);
366 
367 MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
368 MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
369 MODULE_LICENSE("GPL");
370 MODULE_ALIAS("platform:pxa2xx-pcmcia");
371