1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Intel I82092AA PCI-PCMCIA bridge. 4 * 5 * (C) 2001 Red Hat, Inc. 6 * 7 * Author: Arjan Van De Ven <arjanv@redhat.com> 8 * Loosly based on i82365.c from the pcmcia-cs package 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/workqueue.h> 16 #include <linux/interrupt.h> 17 #include <linux/device.h> 18 19 #include <pcmcia/ss.h> 20 21 #include <asm/io.h> 22 23 #include "i82092aa.h" 24 #include "i82365.h" 25 26 MODULE_LICENSE("GPL"); 27 28 /* PCI core routines */ 29 static const struct pci_device_id i82092aa_pci_ids[] = { 30 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) }, 31 { } 32 }; 33 MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); 34 35 static struct pci_driver i82092aa_pci_driver = { 36 .name = "i82092aa", 37 .id_table = i82092aa_pci_ids, 38 .probe = i82092aa_pci_probe, 39 .remove = i82092aa_pci_remove, 40 }; 41 42 43 /* the pccard structure and its functions */ 44 static struct pccard_operations i82092aa_operations = { 45 .init = i82092aa_init, 46 .get_status = i82092aa_get_status, 47 .set_socket = i82092aa_set_socket, 48 .set_io_map = i82092aa_set_io_map, 49 .set_mem_map = i82092aa_set_mem_map, 50 }; 51 52 /* The card can do up to 4 sockets, allocate a structure for each of them */ 53 54 struct socket_info { 55 int number; 56 int card_state; 57 /* 0 = no socket, 58 * 1 = empty socket, 59 * 2 = card but not initialized, 60 * 3 = operational card 61 */ 62 unsigned int io_base; /* base io address of the socket */ 63 64 struct pcmcia_socket socket; 65 struct pci_dev *dev; /* The PCI device for the socket */ 66 }; 67 68 #define MAX_SOCKETS 4 69 static struct socket_info sockets[MAX_SOCKETS]; 70 static int socket_count; /* shortcut */ 71 72 73 static int i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 74 { 75 unsigned char configbyte; 76 int i, ret; 77 78 enter("i82092aa_pci_probe"); 79 80 if ((ret = pci_enable_device(dev))) 81 return ret; 82 83 pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ 84 switch (configbyte&6) { 85 case 0: 86 socket_count = 2; 87 break; 88 case 2: 89 socket_count = 1; 90 break; 91 case 4: 92 case 6: 93 socket_count = 4; 94 break; 95 96 default: 97 dev_err(&dev->dev, 98 "Oops, you did something we didn't think of.\n"); 99 ret = -EIO; 100 goto err_out_disable; 101 } 102 dev_info(&dev->dev, "configured as a %d socket device.\n", 103 socket_count); 104 105 if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { 106 ret = -EBUSY; 107 goto err_out_disable; 108 } 109 110 for (i = 0; i < socket_count; i++) { 111 sockets[i].card_state = 1; /* 1 = present but empty */ 112 sockets[i].io_base = pci_resource_start(dev, 0); 113 sockets[i].socket.features |= SS_CAP_PCCARD; 114 sockets[i].socket.map_size = 0x1000; 115 sockets[i].socket.irq_mask = 0; 116 sockets[i].socket.pci_irq = dev->irq; 117 sockets[i].socket.cb_dev = dev; 118 sockets[i].socket.owner = THIS_MODULE; 119 120 sockets[i].number = i; 121 122 if (card_present(i)) { 123 sockets[i].card_state = 3; 124 dev_dbg(&dev->dev, "slot %i is occupied\n", i); 125 } else { 126 dev_dbg(&dev->dev, "slot %i is vacant\n", i); 127 } 128 } 129 130 /* Now, specifiy that all interrupts are to be done as PCI interrupts */ 131 configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ 132 pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ 133 134 /* Register the interrupt handler */ 135 dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq); 136 if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { 137 dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n", 138 dev->irq); 139 goto err_out_free_res; 140 } 141 142 for (i = 0; i < socket_count; i++) { 143 sockets[i].socket.dev.parent = &dev->dev; 144 sockets[i].socket.ops = &i82092aa_operations; 145 sockets[i].socket.resource_ops = &pccard_nonstatic_ops; 146 ret = pcmcia_register_socket(&sockets[i].socket); 147 if (ret) 148 goto err_out_free_sockets; 149 } 150 151 leave("i82092aa_pci_probe"); 152 return 0; 153 154 err_out_free_sockets: 155 if (i) { 156 for (i--; i >= 0; i--) 157 pcmcia_unregister_socket(&sockets[i].socket); 158 } 159 free_irq(dev->irq, i82092aa_interrupt); 160 err_out_free_res: 161 release_region(pci_resource_start(dev, 0), 2); 162 err_out_disable: 163 pci_disable_device(dev); 164 return ret; 165 } 166 167 static void i82092aa_pci_remove(struct pci_dev *dev) 168 { 169 int i; 170 171 enter("i82092aa_pci_remove"); 172 173 free_irq(dev->irq, i82092aa_interrupt); 174 175 for (i = 0; i < socket_count; i++) 176 pcmcia_unregister_socket(&sockets[i].socket); 177 178 leave("i82092aa_pci_remove"); 179 } 180 181 static DEFINE_SPINLOCK(port_lock); 182 183 /* basic value read/write functions */ 184 185 static unsigned char indirect_read(int socket, unsigned short reg) 186 { 187 unsigned short int port; 188 unsigned char val; 189 unsigned long flags; 190 spin_lock_irqsave(&port_lock, flags); 191 reg += socket * 0x40; 192 port = sockets[socket].io_base; 193 outb(reg, port); 194 val = inb(port+1); 195 spin_unlock_irqrestore(&port_lock, flags); 196 return val; 197 } 198 199 #if 0 200 static unsigned short indirect_read16(int socket, unsigned short reg) 201 { 202 unsigned short int port; 203 unsigned short tmp; 204 unsigned long flags; 205 spin_lock_irqsave(&port_lock, flags); 206 reg = reg + socket * 0x40; 207 port = sockets[socket].io_base; 208 outb(reg, port); 209 tmp = inb(port+1); 210 reg++; 211 outb(reg, port); 212 tmp = tmp | (inb(port+1)<<8); 213 spin_unlock_irqrestore(&port_lock, flags); 214 return tmp; 215 } 216 #endif 217 218 static void indirect_write(int socket, unsigned short reg, unsigned char value) 219 { 220 unsigned short int port; 221 unsigned long flags; 222 spin_lock_irqsave(&port_lock, flags); 223 reg = reg + socket * 0x40; 224 port = sockets[socket].io_base; 225 outb(reg, port); 226 outb(value, port+1); 227 spin_unlock_irqrestore(&port_lock, flags); 228 } 229 230 static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) 231 { 232 unsigned short int port; 233 unsigned char val; 234 unsigned long flags; 235 spin_lock_irqsave(&port_lock, flags); 236 reg = reg + socket * 0x40; 237 port = sockets[socket].io_base; 238 outb(reg, port); 239 val = inb(port+1); 240 val |= mask; 241 outb(reg, port); 242 outb(val, port+1); 243 spin_unlock_irqrestore(&port_lock, flags); 244 } 245 246 247 static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) 248 { 249 unsigned short int port; 250 unsigned char val; 251 unsigned long flags; 252 spin_lock_irqsave(&port_lock, flags); 253 reg = reg + socket * 0x40; 254 port = sockets[socket].io_base; 255 outb(reg, port); 256 val = inb(port+1); 257 val &= ~mask; 258 outb(reg, port); 259 outb(val, port+1); 260 spin_unlock_irqrestore(&port_lock, flags); 261 } 262 263 static void indirect_write16(int socket, unsigned short reg, unsigned short value) 264 { 265 unsigned short int port; 266 unsigned char val; 267 unsigned long flags; 268 spin_lock_irqsave(&port_lock, flags); 269 reg = reg + socket * 0x40; 270 port = sockets[socket].io_base; 271 272 outb(reg, port); 273 val = value & 255; 274 outb(val, port+1); 275 276 reg++; 277 278 outb(reg, port); 279 val = value>>8; 280 outb(val, port+1); 281 spin_unlock_irqrestore(&port_lock, flags); 282 } 283 284 /* simple helper functions */ 285 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ 286 static int cycle_time = 120; 287 288 static int to_cycles(int ns) 289 { 290 if (cycle_time != 0) 291 return ns/cycle_time; 292 else 293 return 0; 294 } 295 296 297 /* Interrupt handler functionality */ 298 299 static irqreturn_t i82092aa_interrupt(int irq, void *dev) 300 { 301 int i; 302 int loopcount = 0; 303 int handled = 0; 304 305 unsigned int events, active = 0; 306 307 /* enter("i82092aa_interrupt");*/ 308 309 while (1) { 310 loopcount++; 311 if (loopcount > 20) { 312 pr_err("i82092aa: infinite eventloop in interrupt\n"); 313 break; 314 } 315 316 active = 0; 317 318 for (i = 0; i < socket_count; i++) { 319 int csc; 320 if (sockets[i].card_state == 0) /* Inactive socket, should not happen */ 321 continue; 322 323 csc = indirect_read(i, I365_CSC); /* card status change register */ 324 325 if (csc == 0) /* no events on this socket */ 326 continue; 327 handled = 1; 328 events = 0; 329 330 if (csc & I365_CSC_DETECT) { 331 events |= SS_DETECT; 332 dev_info(&sockets[i].dev->dev, 333 "Card detected in socket %i!\n", i); 334 } 335 336 if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) { 337 /* For IO/CARDS, bit 0 means "read the card" */ 338 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; 339 } else { 340 /* Check for battery/ready events */ 341 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; 342 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; 343 events |= (csc & I365_CSC_READY) ? SS_READY : 0; 344 } 345 346 if (events) 347 pcmcia_parse_events(&sockets[i].socket, events); 348 active |= events; 349 } 350 351 if (active == 0) /* no more events to handle */ 352 break; 353 } 354 return IRQ_RETVAL(handled); 355 /* leave("i82092aa_interrupt");*/ 356 } 357 358 359 360 /* socket functions */ 361 362 static int card_present(int socketno) 363 { 364 unsigned int val; 365 enter("card_present"); 366 367 if ((socketno < 0) || (socketno >= MAX_SOCKETS)) 368 return 0; 369 if (sockets[socketno].io_base == 0) 370 return 0; 371 372 373 val = indirect_read(socketno, 1); /* Interface status register */ 374 if ((val&12) == 12) { 375 leave("card_present 1"); 376 return 1; 377 } 378 379 leave("card_present 0"); 380 return 0; 381 } 382 383 static void set_bridge_state(int sock) 384 { 385 enter("set_bridge_state"); 386 indirect_write(sock, I365_GBLCTL, 0x00); 387 indirect_write(sock, I365_GENCTL, 0x00); 388 389 indirect_setbit(sock, I365_INTCTL, 0x08); 390 leave("set_bridge_state"); 391 } 392 393 394 static int i82092aa_init(struct pcmcia_socket *sock) 395 { 396 int i; 397 struct resource res = { .start = 0, .end = 0x0fff }; 398 pccard_io_map io = { 0, 0, 0, 0, 1 }; 399 pccard_mem_map mem = { .res = &res, }; 400 401 enter("i82092aa_init"); 402 403 for (i = 0; i < 2; i++) { 404 io.map = i; 405 i82092aa_set_io_map(sock, &io); 406 } 407 for (i = 0; i < 5; i++) { 408 mem.map = i; 409 i82092aa_set_mem_map(sock, &mem); 410 } 411 412 leave("i82092aa_init"); 413 return 0; 414 } 415 416 static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) 417 { 418 unsigned int sock = container_of(socket, struct socket_info, socket)->number; 419 unsigned int status; 420 421 enter("i82092aa_get_status"); 422 423 status = indirect_read(sock, I365_STATUS); /* Interface Status Register */ 424 *value = 0; 425 426 if ((status & I365_CS_DETECT) == I365_CS_DETECT) 427 *value |= SS_DETECT; 428 429 /* IO cards have a different meaning of bits 0,1 */ 430 /* Also notice the inverse-logic on the bits */ 431 if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { 432 /* IO card */ 433 if (!(status & I365_CS_STSCHG)) 434 *value |= SS_STSCHG; 435 } else { /* non I/O card */ 436 if (!(status & I365_CS_BVD1)) 437 *value |= SS_BATDEAD; 438 if (!(status & I365_CS_BVD2)) 439 *value |= SS_BATWARN; 440 } 441 442 if (status & I365_CS_WRPROT) 443 (*value) |= SS_WRPROT; /* card is write protected */ 444 445 if (status & I365_CS_READY) 446 (*value) |= SS_READY; /* card is not busy */ 447 448 if (status & I365_CS_POWERON) 449 (*value) |= SS_POWERON; /* power is applied to the card */ 450 451 leave("i82092aa_get_status"); 452 return 0; 453 } 454 455 456 static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) 457 { 458 struct socket_info *sock_info = container_of(socket, struct socket_info, 459 socket); 460 unsigned int sock = sock_info->number; 461 unsigned char reg; 462 463 enter("i82092aa_set_socket"); 464 465 /* First, set the global controller options */ 466 467 set_bridge_state(sock); 468 469 /* Values for the IGENC register */ 470 471 reg = 0; 472 if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ 473 reg = reg | I365_PC_RESET; 474 if (state->flags & SS_IOCARD) 475 reg = reg | I365_PC_IOCARD; 476 477 indirect_write(sock, I365_INTCTL, reg); /* IGENC, Interrupt and General Control Register */ 478 479 /* Power registers */ 480 481 reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ 482 483 if (state->flags & SS_PWR_AUTO) { 484 dev_info(&sock_info->dev->dev, "Auto power\n"); 485 reg |= I365_PWR_AUTO; /* automatic power mngmnt */ 486 } 487 if (state->flags & SS_OUTPUT_ENA) { 488 dev_info(&sock_info->dev->dev, "Power Enabled\n"); 489 reg |= I365_PWR_OUT; /* enable power */ 490 } 491 492 switch (state->Vcc) { 493 case 0: 494 break; 495 case 50: 496 dev_info(&sock_info->dev->dev, 497 "setting voltage to Vcc to 5V on socket %i\n", 498 sock); 499 reg |= I365_VCC_5V; 500 break; 501 default: 502 dev_err(&sock_info->dev->dev, 503 "%s called with invalid VCC power value: %i", 504 __func__, state->Vcc); 505 leave("i82092aa_set_socket"); 506 return -EINVAL; 507 } 508 509 switch (state->Vpp) { 510 case 0: 511 dev_info(&sock_info->dev->dev, 512 "not setting Vpp on socket %i\n", sock); 513 break; 514 case 50: 515 dev_info(&sock_info->dev->dev, 516 "setting Vpp to 5.0 for socket %i\n", sock); 517 reg |= I365_VPP1_5V | I365_VPP2_5V; 518 break; 519 case 120: 520 dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n"); 521 reg |= I365_VPP1_12V | I365_VPP2_12V; 522 break; 523 default: 524 dev_err(&sock_info->dev->dev, 525 "%s called with invalid VPP power value: %i", 526 __func__, state->Vcc); 527 leave("i82092aa_set_socket"); 528 return -EINVAL; 529 } 530 531 if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */ 532 indirect_write(sock, I365_POWER, reg); 533 534 /* Enable specific interrupt events */ 535 536 reg = 0x00; 537 if (state->csc_mask & SS_DETECT) 538 reg |= I365_CSC_DETECT; 539 if (state->flags & SS_IOCARD) { 540 if (state->csc_mask & SS_STSCHG) 541 reg |= I365_CSC_STSCHG; 542 } else { 543 if (state->csc_mask & SS_BATDEAD) 544 reg |= I365_CSC_BVD1; 545 if (state->csc_mask & SS_BATWARN) 546 reg |= I365_CSC_BVD2; 547 if (state->csc_mask & SS_READY) 548 reg |= I365_CSC_READY; 549 550 } 551 552 /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ 553 554 indirect_write(sock, I365_CSCINT, reg); 555 (void)indirect_read(sock, I365_CSC); 556 557 leave("i82092aa_set_socket"); 558 return 0; 559 } 560 561 static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) 562 { 563 struct socket_info *sock_info = container_of(socket, struct socket_info, 564 socket); 565 unsigned int sock = sock_info->number; 566 unsigned char map, ioctl; 567 568 enter("i82092aa_set_io_map"); 569 570 map = io->map; 571 572 /* Check error conditions */ 573 if (map > 1) { 574 leave("i82092aa_set_io_map with invalid map"); 575 return -EINVAL; 576 } 577 if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)) { 578 leave("i82092aa_set_io_map with invalid io"); 579 return -EINVAL; 580 } 581 582 /* Turn off the window before changing anything */ 583 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) 584 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 585 586 /* write the new values */ 587 indirect_write16(sock, I365_IO(map)+I365_W_START, io->start); 588 indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop); 589 590 ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map); 591 592 if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) 593 ioctl |= I365_IOCTL_16BIT(map); 594 595 indirect_write(sock, I365_IOCTL, ioctl); 596 597 /* Turn the window back on if needed */ 598 if (io->flags & MAP_ACTIVE) 599 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 600 601 leave("i82092aa_set_io_map"); 602 return 0; 603 } 604 605 static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) 606 { 607 struct socket_info *sock_info = container_of(socket, struct socket_info, socket); 608 unsigned int sock = sock_info->number; 609 struct pci_bus_region region; 610 unsigned short base, i; 611 unsigned char map; 612 613 enter("i82092aa_set_mem_map"); 614 615 pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res); 616 617 map = mem->map; 618 if (map > 4) { 619 leave("i82092aa_set_mem_map: invalid map"); 620 return -EINVAL; 621 } 622 623 624 if ((mem->card_start > 0x3ffffff) || (region.start > region.end) || 625 (mem->speed > 1000)) { 626 leave("i82092aa_set_mem_map: invalid address / speed"); 627 dev_err(&sock_info->dev->dev, 628 "invalid mem map for socket %i: %llx to %llx with a " 629 "start of %x\n", 630 sock, 631 (unsigned long long)region.start, 632 (unsigned long long)region.end, 633 mem->card_start); 634 return -EINVAL; 635 } 636 637 /* Turn off the window before changing anything */ 638 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) 639 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 640 641 /* write the start address */ 642 base = I365_MEM(map); 643 i = (region.start >> 12) & 0x0fff; 644 if (mem->flags & MAP_16BIT) 645 i |= I365_MEM_16BIT; 646 if (mem->flags & MAP_0WS) 647 i |= I365_MEM_0WS; 648 indirect_write16(sock, base+I365_W_START, i); 649 650 /* write the stop address */ 651 652 i = (region.end >> 12) & 0x0fff; 653 switch (to_cycles(mem->speed)) { 654 case 0: 655 break; 656 case 1: 657 i |= I365_MEM_WS0; 658 break; 659 case 2: 660 i |= I365_MEM_WS1; 661 break; 662 default: 663 i |= I365_MEM_WS1 | I365_MEM_WS0; 664 break; 665 } 666 667 indirect_write16(sock, base+I365_W_STOP, i); 668 669 /* card start */ 670 671 i = ((mem->card_start - region.start) >> 12) & 0x3fff; 672 if (mem->flags & MAP_WRPROT) 673 i |= I365_MEM_WRPROT; 674 if (mem->flags & MAP_ATTRIB) 675 i |= I365_MEM_REG; 676 indirect_write16(sock, base+I365_W_OFF, i); 677 678 /* Enable the window if necessary */ 679 if (mem->flags & MAP_ACTIVE) 680 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 681 682 leave("i82092aa_set_mem_map"); 683 return 0; 684 } 685 686 static int i82092aa_module_init(void) 687 { 688 return pci_register_driver(&i82092aa_pci_driver); 689 } 690 691 static void i82092aa_module_exit(void) 692 { 693 enter("i82092aa_module_exit"); 694 pci_unregister_driver(&i82092aa_pci_driver); 695 if (sockets[0].io_base > 0) 696 release_region(sockets[0].io_base, 2); 697 leave("i82092aa_module_exit"); 698 } 699 700 module_init(i82092aa_module_init); 701 module_exit(i82092aa_module_exit); 702 703