1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Intel I82092AA PCI-PCMCIA bridge. 4 * 5 * (C) 2001 Red Hat, Inc. 6 * 7 * Author: Arjan Van De Ven <arjanv@redhat.com> 8 * Loosly based on i82365.c from the pcmcia-cs package 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/workqueue.h> 16 #include <linux/interrupt.h> 17 #include <linux/device.h> 18 19 #include <pcmcia/ss.h> 20 21 #include <asm/io.h> 22 23 #include "i82092aa.h" 24 #include "i82365.h" 25 26 MODULE_LICENSE("GPL"); 27 28 /* PCI core routines */ 29 static const struct pci_device_id i82092aa_pci_ids[] = { 30 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) }, 31 { } 32 }; 33 MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); 34 35 static struct pci_driver i82092aa_pci_driver = { 36 .name = "i82092aa", 37 .id_table = i82092aa_pci_ids, 38 .probe = i82092aa_pci_probe, 39 .remove = i82092aa_pci_remove, 40 }; 41 42 43 /* the pccard structure and its functions */ 44 static struct pccard_operations i82092aa_operations = { 45 .init = i82092aa_init, 46 .get_status = i82092aa_get_status, 47 .set_socket = i82092aa_set_socket, 48 .set_io_map = i82092aa_set_io_map, 49 .set_mem_map = i82092aa_set_mem_map, 50 }; 51 52 /* The card can do up to 4 sockets, allocate a structure for each of them */ 53 54 struct socket_info { 55 int number; 56 int card_state; 57 /* 0 = no socket, 58 * 1 = empty socket, 59 * 2 = card but not initialized, 60 * 3 = operational card 61 */ 62 unsigned int io_base; /* base io address of the socket */ 63 64 struct pcmcia_socket socket; 65 struct pci_dev *dev; /* The PCI device for the socket */ 66 }; 67 68 #define MAX_SOCKETS 4 69 static struct socket_info sockets[MAX_SOCKETS]; 70 static int socket_count; /* shortcut */ 71 72 73 static int i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 74 { 75 unsigned char configbyte; 76 int i, ret; 77 78 enter("i82092aa_pci_probe"); 79 80 if ((ret = pci_enable_device(dev))) 81 return ret; 82 83 pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ 84 switch (configbyte&6) { 85 case 0: 86 socket_count = 2; 87 break; 88 case 2: 89 socket_count = 1; 90 break; 91 case 4: 92 case 6: 93 socket_count = 4; 94 break; 95 96 default: 97 dev_err(&dev->dev, 98 "Oops, you did something we didn't think of.\n"); 99 ret = -EIO; 100 goto err_out_disable; 101 } 102 dev_info(&dev->dev, "configured as a %d socket device.\n", 103 socket_count); 104 105 if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { 106 ret = -EBUSY; 107 goto err_out_disable; 108 } 109 110 for (i = 0; i < socket_count; i++) { 111 sockets[i].card_state = 1; /* 1 = present but empty */ 112 sockets[i].io_base = pci_resource_start(dev, 0); 113 sockets[i].socket.features |= SS_CAP_PCCARD; 114 sockets[i].socket.map_size = 0x1000; 115 sockets[i].socket.irq_mask = 0; 116 sockets[i].socket.pci_irq = dev->irq; 117 sockets[i].socket.cb_dev = dev; 118 sockets[i].socket.owner = THIS_MODULE; 119 120 sockets[i].number = i; 121 122 if (card_present(i)) { 123 sockets[i].card_state = 3; 124 dev_dbg(&dev->dev, "slot %i is occupied\n", i); 125 } else { 126 dev_dbg(&dev->dev, "slot %i is vacant\n", i); 127 } 128 } 129 130 /* Now, specifiy that all interrupts are to be done as PCI interrupts */ 131 configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ 132 pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ 133 134 /* Register the interrupt handler */ 135 dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq); 136 if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { 137 dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n", 138 dev->irq); 139 goto err_out_free_res; 140 } 141 142 for (i = 0; i < socket_count; i++) { 143 sockets[i].socket.dev.parent = &dev->dev; 144 sockets[i].socket.ops = &i82092aa_operations; 145 sockets[i].socket.resource_ops = &pccard_nonstatic_ops; 146 ret = pcmcia_register_socket(&sockets[i].socket); 147 if (ret) 148 goto err_out_free_sockets; 149 } 150 151 leave("i82092aa_pci_probe"); 152 return 0; 153 154 err_out_free_sockets: 155 if (i) { 156 for (i--; i >= 0; i--) 157 pcmcia_unregister_socket(&sockets[i].socket); 158 } 159 free_irq(dev->irq, i82092aa_interrupt); 160 err_out_free_res: 161 release_region(pci_resource_start(dev, 0), 2); 162 err_out_disable: 163 pci_disable_device(dev); 164 return ret; 165 } 166 167 static void i82092aa_pci_remove(struct pci_dev *dev) 168 { 169 int i; 170 171 enter("i82092aa_pci_remove"); 172 173 free_irq(dev->irq, i82092aa_interrupt); 174 175 for (i = 0; i < socket_count; i++) 176 pcmcia_unregister_socket(&sockets[i].socket); 177 178 leave("i82092aa_pci_remove"); 179 } 180 181 static DEFINE_SPINLOCK(port_lock); 182 183 /* basic value read/write functions */ 184 185 static unsigned char indirect_read(int socket, unsigned short reg) 186 { 187 unsigned short int port; 188 unsigned char val; 189 unsigned long flags; 190 191 spin_lock_irqsave(&port_lock, flags); 192 reg += socket * 0x40; 193 port = sockets[socket].io_base; 194 outb(reg, port); 195 val = inb(port+1); 196 spin_unlock_irqrestore(&port_lock, flags); 197 return val; 198 } 199 200 #if 0 201 static unsigned short indirect_read16(int socket, unsigned short reg) 202 { 203 unsigned short int port; 204 unsigned short tmp; 205 unsigned long flags; 206 207 spin_lock_irqsave(&port_lock, flags); 208 reg = reg + socket * 0x40; 209 port = sockets[socket].io_base; 210 outb(reg, port); 211 tmp = inb(port+1); 212 reg++; 213 outb(reg, port); 214 tmp = tmp | (inb(port+1)<<8); 215 spin_unlock_irqrestore(&port_lock, flags); 216 return tmp; 217 } 218 #endif 219 220 static void indirect_write(int socket, unsigned short reg, unsigned char value) 221 { 222 unsigned short int port; 223 unsigned long flags; 224 225 spin_lock_irqsave(&port_lock, flags); 226 reg = reg + socket * 0x40; 227 port = sockets[socket].io_base; 228 outb(reg, port); 229 outb(value, port+1); 230 spin_unlock_irqrestore(&port_lock, flags); 231 } 232 233 static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) 234 { 235 unsigned short int port; 236 unsigned char val; 237 unsigned long flags; 238 239 spin_lock_irqsave(&port_lock, flags); 240 reg = reg + socket * 0x40; 241 port = sockets[socket].io_base; 242 outb(reg, port); 243 val = inb(port+1); 244 val |= mask; 245 outb(reg, port); 246 outb(val, port+1); 247 spin_unlock_irqrestore(&port_lock, flags); 248 } 249 250 251 static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) 252 { 253 unsigned short int port; 254 unsigned char val; 255 unsigned long flags; 256 257 spin_lock_irqsave(&port_lock, flags); 258 reg = reg + socket * 0x40; 259 port = sockets[socket].io_base; 260 outb(reg, port); 261 val = inb(port+1); 262 val &= ~mask; 263 outb(reg, port); 264 outb(val, port+1); 265 spin_unlock_irqrestore(&port_lock, flags); 266 } 267 268 static void indirect_write16(int socket, unsigned short reg, unsigned short value) 269 { 270 unsigned short int port; 271 unsigned char val; 272 unsigned long flags; 273 274 spin_lock_irqsave(&port_lock, flags); 275 reg = reg + socket * 0x40; 276 port = sockets[socket].io_base; 277 278 outb(reg, port); 279 val = value & 255; 280 outb(val, port+1); 281 282 reg++; 283 284 outb(reg, port); 285 val = value>>8; 286 outb(val, port+1); 287 spin_unlock_irqrestore(&port_lock, flags); 288 } 289 290 /* simple helper functions */ 291 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ 292 static int cycle_time = 120; 293 294 static int to_cycles(int ns) 295 { 296 if (cycle_time != 0) 297 return ns/cycle_time; 298 else 299 return 0; 300 } 301 302 303 /* Interrupt handler functionality */ 304 305 static irqreturn_t i82092aa_interrupt(int irq, void *dev) 306 { 307 int i; 308 int loopcount = 0; 309 int handled = 0; 310 311 unsigned int events, active = 0; 312 313 /* enter("i82092aa_interrupt");*/ 314 315 while (1) { 316 loopcount++; 317 if (loopcount > 20) { 318 pr_err("i82092aa: infinite eventloop in interrupt\n"); 319 break; 320 } 321 322 active = 0; 323 324 for (i = 0; i < socket_count; i++) { 325 int csc; 326 327 if (sockets[i].card_state == 0) /* Inactive socket, should not happen */ 328 continue; 329 330 csc = indirect_read(i, I365_CSC); /* card status change register */ 331 332 if (csc == 0) /* no events on this socket */ 333 continue; 334 handled = 1; 335 events = 0; 336 337 if (csc & I365_CSC_DETECT) { 338 events |= SS_DETECT; 339 dev_info(&sockets[i].dev->dev, 340 "Card detected in socket %i!\n", i); 341 } 342 343 if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) { 344 /* For IO/CARDS, bit 0 means "read the card" */ 345 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; 346 } else { 347 /* Check for battery/ready events */ 348 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; 349 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; 350 events |= (csc & I365_CSC_READY) ? SS_READY : 0; 351 } 352 353 if (events) 354 pcmcia_parse_events(&sockets[i].socket, events); 355 active |= events; 356 } 357 358 if (active == 0) /* no more events to handle */ 359 break; 360 } 361 return IRQ_RETVAL(handled); 362 /* leave("i82092aa_interrupt");*/ 363 } 364 365 366 367 /* socket functions */ 368 369 static int card_present(int socketno) 370 { 371 unsigned int val; 372 373 enter("card_present"); 374 375 if ((socketno < 0) || (socketno >= MAX_SOCKETS)) 376 return 0; 377 if (sockets[socketno].io_base == 0) 378 return 0; 379 380 381 val = indirect_read(socketno, 1); /* Interface status register */ 382 if ((val&12) == 12) { 383 leave("card_present 1"); 384 return 1; 385 } 386 387 leave("card_present 0"); 388 return 0; 389 } 390 391 static void set_bridge_state(int sock) 392 { 393 enter("set_bridge_state"); 394 indirect_write(sock, I365_GBLCTL, 0x00); 395 indirect_write(sock, I365_GENCTL, 0x00); 396 397 indirect_setbit(sock, I365_INTCTL, 0x08); 398 leave("set_bridge_state"); 399 } 400 401 402 static int i82092aa_init(struct pcmcia_socket *sock) 403 { 404 int i; 405 struct resource res = { .start = 0, .end = 0x0fff }; 406 pccard_io_map io = { 0, 0, 0, 0, 1 }; 407 pccard_mem_map mem = { .res = &res, }; 408 409 enter("i82092aa_init"); 410 411 for (i = 0; i < 2; i++) { 412 io.map = i; 413 i82092aa_set_io_map(sock, &io); 414 } 415 for (i = 0; i < 5; i++) { 416 mem.map = i; 417 i82092aa_set_mem_map(sock, &mem); 418 } 419 420 leave("i82092aa_init"); 421 return 0; 422 } 423 424 static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) 425 { 426 unsigned int sock = container_of(socket, struct socket_info, socket)->number; 427 unsigned int status; 428 429 enter("i82092aa_get_status"); 430 431 status = indirect_read(sock, I365_STATUS); /* Interface Status Register */ 432 *value = 0; 433 434 if ((status & I365_CS_DETECT) == I365_CS_DETECT) 435 *value |= SS_DETECT; 436 437 /* IO cards have a different meaning of bits 0,1 */ 438 /* Also notice the inverse-logic on the bits */ 439 if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { 440 /* IO card */ 441 if (!(status & I365_CS_STSCHG)) 442 *value |= SS_STSCHG; 443 } else { /* non I/O card */ 444 if (!(status & I365_CS_BVD1)) 445 *value |= SS_BATDEAD; 446 if (!(status & I365_CS_BVD2)) 447 *value |= SS_BATWARN; 448 } 449 450 if (status & I365_CS_WRPROT) 451 (*value) |= SS_WRPROT; /* card is write protected */ 452 453 if (status & I365_CS_READY) 454 (*value) |= SS_READY; /* card is not busy */ 455 456 if (status & I365_CS_POWERON) 457 (*value) |= SS_POWERON; /* power is applied to the card */ 458 459 leave("i82092aa_get_status"); 460 return 0; 461 } 462 463 464 static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) 465 { 466 struct socket_info *sock_info = container_of(socket, struct socket_info, 467 socket); 468 unsigned int sock = sock_info->number; 469 unsigned char reg; 470 471 enter("i82092aa_set_socket"); 472 473 /* First, set the global controller options */ 474 475 set_bridge_state(sock); 476 477 /* Values for the IGENC register */ 478 479 reg = 0; 480 if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ 481 reg = reg | I365_PC_RESET; 482 if (state->flags & SS_IOCARD) 483 reg = reg | I365_PC_IOCARD; 484 485 indirect_write(sock, I365_INTCTL, reg); /* IGENC, Interrupt and General Control Register */ 486 487 /* Power registers */ 488 489 reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ 490 491 if (state->flags & SS_PWR_AUTO) { 492 dev_info(&sock_info->dev->dev, "Auto power\n"); 493 reg |= I365_PWR_AUTO; /* automatic power mngmnt */ 494 } 495 if (state->flags & SS_OUTPUT_ENA) { 496 dev_info(&sock_info->dev->dev, "Power Enabled\n"); 497 reg |= I365_PWR_OUT; /* enable power */ 498 } 499 500 switch (state->Vcc) { 501 case 0: 502 break; 503 case 50: 504 dev_info(&sock_info->dev->dev, 505 "setting voltage to Vcc to 5V on socket %i\n", 506 sock); 507 reg |= I365_VCC_5V; 508 break; 509 default: 510 dev_err(&sock_info->dev->dev, 511 "%s called with invalid VCC power value: %i", 512 __func__, state->Vcc); 513 leave("i82092aa_set_socket"); 514 return -EINVAL; 515 } 516 517 switch (state->Vpp) { 518 case 0: 519 dev_info(&sock_info->dev->dev, 520 "not setting Vpp on socket %i\n", sock); 521 break; 522 case 50: 523 dev_info(&sock_info->dev->dev, 524 "setting Vpp to 5.0 for socket %i\n", sock); 525 reg |= I365_VPP1_5V | I365_VPP2_5V; 526 break; 527 case 120: 528 dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n"); 529 reg |= I365_VPP1_12V | I365_VPP2_12V; 530 break; 531 default: 532 dev_err(&sock_info->dev->dev, 533 "%s called with invalid VPP power value: %i", 534 __func__, state->Vcc); 535 leave("i82092aa_set_socket"); 536 return -EINVAL; 537 } 538 539 if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */ 540 indirect_write(sock, I365_POWER, reg); 541 542 /* Enable specific interrupt events */ 543 544 reg = 0x00; 545 if (state->csc_mask & SS_DETECT) 546 reg |= I365_CSC_DETECT; 547 if (state->flags & SS_IOCARD) { 548 if (state->csc_mask & SS_STSCHG) 549 reg |= I365_CSC_STSCHG; 550 } else { 551 if (state->csc_mask & SS_BATDEAD) 552 reg |= I365_CSC_BVD1; 553 if (state->csc_mask & SS_BATWARN) 554 reg |= I365_CSC_BVD2; 555 if (state->csc_mask & SS_READY) 556 reg |= I365_CSC_READY; 557 558 } 559 560 /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ 561 562 indirect_write(sock, I365_CSCINT, reg); 563 (void)indirect_read(sock, I365_CSC); 564 565 leave("i82092aa_set_socket"); 566 return 0; 567 } 568 569 static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) 570 { 571 struct socket_info *sock_info = container_of(socket, struct socket_info, 572 socket); 573 unsigned int sock = sock_info->number; 574 unsigned char map, ioctl; 575 576 enter("i82092aa_set_io_map"); 577 578 map = io->map; 579 580 /* Check error conditions */ 581 if (map > 1) { 582 leave("i82092aa_set_io_map with invalid map"); 583 return -EINVAL; 584 } 585 if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)) { 586 leave("i82092aa_set_io_map with invalid io"); 587 return -EINVAL; 588 } 589 590 /* Turn off the window before changing anything */ 591 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) 592 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 593 594 /* write the new values */ 595 indirect_write16(sock, I365_IO(map)+I365_W_START, io->start); 596 indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop); 597 598 ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map); 599 600 if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) 601 ioctl |= I365_IOCTL_16BIT(map); 602 603 indirect_write(sock, I365_IOCTL, ioctl); 604 605 /* Turn the window back on if needed */ 606 if (io->flags & MAP_ACTIVE) 607 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 608 609 leave("i82092aa_set_io_map"); 610 return 0; 611 } 612 613 static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) 614 { 615 struct socket_info *sock_info = container_of(socket, struct socket_info, socket); 616 unsigned int sock = sock_info->number; 617 struct pci_bus_region region; 618 unsigned short base, i; 619 unsigned char map; 620 621 enter("i82092aa_set_mem_map"); 622 623 pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res); 624 625 map = mem->map; 626 if (map > 4) { 627 leave("i82092aa_set_mem_map: invalid map"); 628 return -EINVAL; 629 } 630 631 632 if ((mem->card_start > 0x3ffffff) || (region.start > region.end) || 633 (mem->speed > 1000)) { 634 leave("i82092aa_set_mem_map: invalid address / speed"); 635 dev_err(&sock_info->dev->dev, 636 "invalid mem map for socket %i: %llx to %llx with a " 637 "start of %x\n", 638 sock, 639 (unsigned long long)region.start, 640 (unsigned long long)region.end, 641 mem->card_start); 642 return -EINVAL; 643 } 644 645 /* Turn off the window before changing anything */ 646 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) 647 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 648 649 /* write the start address */ 650 base = I365_MEM(map); 651 i = (region.start >> 12) & 0x0fff; 652 if (mem->flags & MAP_16BIT) 653 i |= I365_MEM_16BIT; 654 if (mem->flags & MAP_0WS) 655 i |= I365_MEM_0WS; 656 indirect_write16(sock, base+I365_W_START, i); 657 658 /* write the stop address */ 659 660 i = (region.end >> 12) & 0x0fff; 661 switch (to_cycles(mem->speed)) { 662 case 0: 663 break; 664 case 1: 665 i |= I365_MEM_WS0; 666 break; 667 case 2: 668 i |= I365_MEM_WS1; 669 break; 670 default: 671 i |= I365_MEM_WS1 | I365_MEM_WS0; 672 break; 673 } 674 675 indirect_write16(sock, base+I365_W_STOP, i); 676 677 /* card start */ 678 679 i = ((mem->card_start - region.start) >> 12) & 0x3fff; 680 if (mem->flags & MAP_WRPROT) 681 i |= I365_MEM_WRPROT; 682 if (mem->flags & MAP_ATTRIB) 683 i |= I365_MEM_REG; 684 indirect_write16(sock, base+I365_W_OFF, i); 685 686 /* Enable the window if necessary */ 687 if (mem->flags & MAP_ACTIVE) 688 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 689 690 leave("i82092aa_set_mem_map"); 691 return 0; 692 } 693 694 static int i82092aa_module_init(void) 695 { 696 return pci_register_driver(&i82092aa_pci_driver); 697 } 698 699 static void i82092aa_module_exit(void) 700 { 701 enter("i82092aa_module_exit"); 702 pci_unregister_driver(&i82092aa_pci_driver); 703 if (sockets[0].io_base > 0) 704 release_region(sockets[0].io_base, 2); 705 leave("i82092aa_module_exit"); 706 } 707 708 module_init(i82092aa_module_init); 709 module_exit(i82092aa_module_exit); 710 711