1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Intel I82092AA PCI-PCMCIA bridge. 4 * 5 * (C) 2001 Red Hat, Inc. 6 * 7 * Author: Arjan Van De Ven <arjanv@redhat.com> 8 * Loosly based on i82365.c from the pcmcia-cs package 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/workqueue.h> 16 #include <linux/interrupt.h> 17 #include <linux/device.h> 18 19 #include <pcmcia/ss.h> 20 21 #include <asm/io.h> 22 23 #include "i82092aa.h" 24 #include "i82365.h" 25 26 MODULE_LICENSE("GPL"); 27 28 /* PCI core routines */ 29 static const struct pci_device_id i82092aa_pci_ids[] = { 30 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) }, 31 { } 32 }; 33 MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); 34 35 static struct pci_driver i82092aa_pci_driver = { 36 .name = "i82092aa", 37 .id_table = i82092aa_pci_ids, 38 .probe = i82092aa_pci_probe, 39 .remove = i82092aa_pci_remove, 40 }; 41 42 43 /* the pccard structure and its functions */ 44 static struct pccard_operations i82092aa_operations = { 45 .init = i82092aa_init, 46 .get_status = i82092aa_get_status, 47 .set_socket = i82092aa_set_socket, 48 .set_io_map = i82092aa_set_io_map, 49 .set_mem_map = i82092aa_set_mem_map, 50 }; 51 52 /* The card can do up to 4 sockets, allocate a structure for each of them */ 53 54 struct socket_info { 55 int number; 56 int card_state; 57 /* 0 = no socket, 58 * 1 = empty socket, 59 * 2 = card but not initialized, 60 * 3 = operational card 61 */ 62 unsigned int io_base; /* base io address of the socket */ 63 64 struct pcmcia_socket socket; 65 struct pci_dev *dev; /* The PCI device for the socket */ 66 }; 67 68 #define MAX_SOCKETS 4 69 static struct socket_info sockets[MAX_SOCKETS]; 70 static int socket_count; /* shortcut */ 71 72 73 static int i82092aa_pci_probe(struct pci_dev *dev, 74 const struct pci_device_id *id) 75 { 76 unsigned char configbyte; 77 int i, ret; 78 79 enter("i82092aa_pci_probe"); 80 81 ret = pci_enable_device(dev); 82 if (ret) 83 return ret; 84 85 /* PCI Configuration Control */ 86 pci_read_config_byte(dev, 0x40, &configbyte); 87 88 switch (configbyte&6) { 89 case 0: 90 socket_count = 2; 91 break; 92 case 2: 93 socket_count = 1; 94 break; 95 case 4: 96 case 6: 97 socket_count = 4; 98 break; 99 100 default: 101 dev_err(&dev->dev, 102 "Oops, you did something we didn't think of.\n"); 103 ret = -EIO; 104 goto err_out_disable; 105 } 106 dev_info(&dev->dev, "configured as a %d socket device.\n", 107 socket_count); 108 109 if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { 110 ret = -EBUSY; 111 goto err_out_disable; 112 } 113 114 for (i = 0; i < socket_count; i++) { 115 sockets[i].card_state = 1; /* 1 = present but empty */ 116 sockets[i].io_base = pci_resource_start(dev, 0); 117 sockets[i].socket.features |= SS_CAP_PCCARD; 118 sockets[i].socket.map_size = 0x1000; 119 sockets[i].socket.irq_mask = 0; 120 sockets[i].socket.pci_irq = dev->irq; 121 sockets[i].socket.cb_dev = dev; 122 sockets[i].socket.owner = THIS_MODULE; 123 124 sockets[i].number = i; 125 126 if (card_present(i)) { 127 sockets[i].card_state = 3; 128 dev_dbg(&dev->dev, "slot %i is occupied\n", i); 129 } else { 130 dev_dbg(&dev->dev, "slot %i is vacant\n", i); 131 } 132 } 133 134 /* Now, specifiy that all interrupts are to be done as PCI interrupts 135 * bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt 136 */ 137 configbyte = 0xFF; 138 139 /* PCI Interrupt Routing Register */ 140 pci_write_config_byte(dev, 0x50, configbyte); 141 142 /* Register the interrupt handler */ 143 dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq); 144 ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, 145 "i82092aa", i82092aa_interrupt); 146 if (ret) { 147 dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n", 148 dev->irq); 149 goto err_out_free_res; 150 } 151 152 for (i = 0; i < socket_count; i++) { 153 sockets[i].socket.dev.parent = &dev->dev; 154 sockets[i].socket.ops = &i82092aa_operations; 155 sockets[i].socket.resource_ops = &pccard_nonstatic_ops; 156 ret = pcmcia_register_socket(&sockets[i].socket); 157 if (ret) 158 goto err_out_free_sockets; 159 } 160 161 leave("i82092aa_pci_probe"); 162 return 0; 163 164 err_out_free_sockets: 165 if (i) { 166 for (i--; i >= 0; i--) 167 pcmcia_unregister_socket(&sockets[i].socket); 168 } 169 free_irq(dev->irq, i82092aa_interrupt); 170 err_out_free_res: 171 release_region(pci_resource_start(dev, 0), 2); 172 err_out_disable: 173 pci_disable_device(dev); 174 return ret; 175 } 176 177 static void i82092aa_pci_remove(struct pci_dev *dev) 178 { 179 int i; 180 181 enter("i82092aa_pci_remove"); 182 183 free_irq(dev->irq, i82092aa_interrupt); 184 185 for (i = 0; i < socket_count; i++) 186 pcmcia_unregister_socket(&sockets[i].socket); 187 188 leave("i82092aa_pci_remove"); 189 } 190 191 static DEFINE_SPINLOCK(port_lock); 192 193 /* basic value read/write functions */ 194 195 static unsigned char indirect_read(int socket, unsigned short reg) 196 { 197 unsigned short int port; 198 unsigned char val; 199 unsigned long flags; 200 201 spin_lock_irqsave(&port_lock, flags); 202 reg += socket * 0x40; 203 port = sockets[socket].io_base; 204 outb(reg, port); 205 val = inb(port+1); 206 spin_unlock_irqrestore(&port_lock, flags); 207 return val; 208 } 209 210 #if 0 211 static unsigned short indirect_read16(int socket, unsigned short reg) 212 { 213 unsigned short int port; 214 unsigned short tmp; 215 unsigned long flags; 216 217 spin_lock_irqsave(&port_lock, flags); 218 reg = reg + socket * 0x40; 219 port = sockets[socket].io_base; 220 outb(reg, port); 221 tmp = inb(port+1); 222 reg++; 223 outb(reg, port); 224 tmp = tmp | (inb(port+1)<<8); 225 spin_unlock_irqrestore(&port_lock, flags); 226 return tmp; 227 } 228 #endif 229 230 static void indirect_write(int socket, unsigned short reg, unsigned char value) 231 { 232 unsigned short int port; 233 unsigned long flags; 234 235 spin_lock_irqsave(&port_lock, flags); 236 reg = reg + socket * 0x40; 237 port = sockets[socket].io_base; 238 outb(reg, port); 239 outb(value, port+1); 240 spin_unlock_irqrestore(&port_lock, flags); 241 } 242 243 static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) 244 { 245 unsigned short int port; 246 unsigned char val; 247 unsigned long flags; 248 249 spin_lock_irqsave(&port_lock, flags); 250 reg = reg + socket * 0x40; 251 port = sockets[socket].io_base; 252 outb(reg, port); 253 val = inb(port+1); 254 val |= mask; 255 outb(reg, port); 256 outb(val, port+1); 257 spin_unlock_irqrestore(&port_lock, flags); 258 } 259 260 261 static void indirect_resetbit(int socket, 262 unsigned short reg, unsigned char mask) 263 { 264 unsigned short int port; 265 unsigned char val; 266 unsigned long flags; 267 268 spin_lock_irqsave(&port_lock, flags); 269 reg = reg + socket * 0x40; 270 port = sockets[socket].io_base; 271 outb(reg, port); 272 val = inb(port+1); 273 val &= ~mask; 274 outb(reg, port); 275 outb(val, port+1); 276 spin_unlock_irqrestore(&port_lock, flags); 277 } 278 279 static void indirect_write16(int socket, 280 unsigned short reg, unsigned short value) 281 { 282 unsigned short int port; 283 unsigned char val; 284 unsigned long flags; 285 286 spin_lock_irqsave(&port_lock, flags); 287 reg = reg + socket * 0x40; 288 port = sockets[socket].io_base; 289 290 outb(reg, port); 291 val = value & 255; 292 outb(val, port+1); 293 294 reg++; 295 296 outb(reg, port); 297 val = value>>8; 298 outb(val, port+1); 299 spin_unlock_irqrestore(&port_lock, flags); 300 } 301 302 /* simple helper functions */ 303 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ 304 static int cycle_time = 120; 305 306 static int to_cycles(int ns) 307 { 308 if (cycle_time != 0) 309 return ns/cycle_time; 310 else 311 return 0; 312 } 313 314 315 /* Interrupt handler functionality */ 316 317 static irqreturn_t i82092aa_interrupt(int irq, void *dev) 318 { 319 int i; 320 int loopcount = 0; 321 int handled = 0; 322 323 unsigned int events, active = 0; 324 325 /* enter("i82092aa_interrupt");*/ 326 327 while (1) { 328 loopcount++; 329 if (loopcount > 20) { 330 pr_err("i82092aa: infinite eventloop in interrupt\n"); 331 break; 332 } 333 334 active = 0; 335 336 for (i = 0; i < socket_count; i++) { 337 int csc; 338 339 /* Inactive socket, should not happen */ 340 if (sockets[i].card_state == 0) 341 continue; 342 343 /* card status change register */ 344 csc = indirect_read(i, I365_CSC); 345 346 if (csc == 0) /* no events on this socket */ 347 continue; 348 handled = 1; 349 events = 0; 350 351 if (csc & I365_CSC_DETECT) { 352 events |= SS_DETECT; 353 dev_info(&sockets[i].dev->dev, 354 "Card detected in socket %i!\n", i); 355 } 356 357 if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) { 358 /* For IO/CARDS, bit 0 means "read the card" */ 359 if (csc & I365_CSC_STSCHG) 360 events |= SS_STSCHG; 361 } else { 362 /* Check for battery/ready events */ 363 if (csc & I365_CSC_BVD1) 364 events |= SS_BATDEAD; 365 if (csc & I365_CSC_BVD2) 366 events |= SS_BATWARN; 367 if (csc & I365_CSC_READY) 368 events |= SS_READY; 369 } 370 371 if (events) 372 pcmcia_parse_events(&sockets[i].socket, events); 373 active |= events; 374 } 375 376 if (active == 0) /* no more events to handle */ 377 break; 378 } 379 return IRQ_RETVAL(handled); 380 /* leave("i82092aa_interrupt");*/ 381 } 382 383 384 385 /* socket functions */ 386 387 static int card_present(int socketno) 388 { 389 unsigned int val; 390 391 enter("card_present"); 392 393 if ((socketno < 0) || (socketno >= MAX_SOCKETS)) 394 return 0; 395 if (sockets[socketno].io_base == 0) 396 return 0; 397 398 399 val = indirect_read(socketno, 1); /* Interface status register */ 400 if ((val&12) == 12) { 401 leave("card_present 1"); 402 return 1; 403 } 404 405 leave("card_present 0"); 406 return 0; 407 } 408 409 static void set_bridge_state(int sock) 410 { 411 enter("set_bridge_state"); 412 indirect_write(sock, I365_GBLCTL, 0x00); 413 indirect_write(sock, I365_GENCTL, 0x00); 414 415 indirect_setbit(sock, I365_INTCTL, 0x08); 416 leave("set_bridge_state"); 417 } 418 419 420 static int i82092aa_init(struct pcmcia_socket *sock) 421 { 422 int i; 423 struct resource res = { .start = 0, .end = 0x0fff }; 424 pccard_io_map io = { 0, 0, 0, 0, 1 }; 425 pccard_mem_map mem = { .res = &res, }; 426 427 enter("i82092aa_init"); 428 429 for (i = 0; i < 2; i++) { 430 io.map = i; 431 i82092aa_set_io_map(sock, &io); 432 } 433 for (i = 0; i < 5; i++) { 434 mem.map = i; 435 i82092aa_set_mem_map(sock, &mem); 436 } 437 438 leave("i82092aa_init"); 439 return 0; 440 } 441 442 static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) 443 { 444 unsigned int sock = container_of(socket, 445 struct socket_info, socket)->number; 446 unsigned int status; 447 448 enter("i82092aa_get_status"); 449 450 /* Interface Status Register */ 451 status = indirect_read(sock, I365_STATUS); 452 453 *value = 0; 454 455 if ((status & I365_CS_DETECT) == I365_CS_DETECT) 456 *value |= SS_DETECT; 457 458 /* IO cards have a different meaning of bits 0,1 */ 459 /* Also notice the inverse-logic on the bits */ 460 if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { 461 /* IO card */ 462 if (!(status & I365_CS_STSCHG)) 463 *value |= SS_STSCHG; 464 } else { /* non I/O card */ 465 if (!(status & I365_CS_BVD1)) 466 *value |= SS_BATDEAD; 467 if (!(status & I365_CS_BVD2)) 468 *value |= SS_BATWARN; 469 } 470 471 if (status & I365_CS_WRPROT) 472 (*value) |= SS_WRPROT; /* card is write protected */ 473 474 if (status & I365_CS_READY) 475 (*value) |= SS_READY; /* card is not busy */ 476 477 if (status & I365_CS_POWERON) 478 (*value) |= SS_POWERON; /* power is applied to the card */ 479 480 leave("i82092aa_get_status"); 481 return 0; 482 } 483 484 485 static int i82092aa_set_socket(struct pcmcia_socket *socket, 486 socket_state_t *state) 487 { 488 struct socket_info *sock_info = container_of(socket, struct socket_info, 489 socket); 490 unsigned int sock = sock_info->number; 491 unsigned char reg; 492 493 enter("i82092aa_set_socket"); 494 495 /* First, set the global controller options */ 496 497 set_bridge_state(sock); 498 499 /* Values for the IGENC register */ 500 501 reg = 0; 502 503 /* The reset bit has "inverse" logic */ 504 if (!(state->flags & SS_RESET)) 505 reg = reg | I365_PC_RESET; 506 if (state->flags & SS_IOCARD) 507 reg = reg | I365_PC_IOCARD; 508 509 /* IGENC, Interrupt and General Control Register */ 510 indirect_write(sock, I365_INTCTL, reg); 511 512 /* Power registers */ 513 514 reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ 515 516 if (state->flags & SS_PWR_AUTO) { 517 dev_info(&sock_info->dev->dev, "Auto power\n"); 518 reg |= I365_PWR_AUTO; /* automatic power mngmnt */ 519 } 520 if (state->flags & SS_OUTPUT_ENA) { 521 dev_info(&sock_info->dev->dev, "Power Enabled\n"); 522 reg |= I365_PWR_OUT; /* enable power */ 523 } 524 525 switch (state->Vcc) { 526 case 0: 527 break; 528 case 50: 529 dev_info(&sock_info->dev->dev, 530 "setting voltage to Vcc to 5V on socket %i\n", 531 sock); 532 reg |= I365_VCC_5V; 533 break; 534 default: 535 dev_err(&sock_info->dev->dev, 536 "%s called with invalid VCC power value: %i", 537 __func__, state->Vcc); 538 leave("i82092aa_set_socket"); 539 return -EINVAL; 540 } 541 542 switch (state->Vpp) { 543 case 0: 544 dev_info(&sock_info->dev->dev, 545 "not setting Vpp on socket %i\n", sock); 546 break; 547 case 50: 548 dev_info(&sock_info->dev->dev, 549 "setting Vpp to 5.0 for socket %i\n", sock); 550 reg |= I365_VPP1_5V | I365_VPP2_5V; 551 break; 552 case 120: 553 dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n"); 554 reg |= I365_VPP1_12V | I365_VPP2_12V; 555 break; 556 default: 557 dev_err(&sock_info->dev->dev, 558 "%s called with invalid VPP power value: %i", 559 __func__, state->Vcc); 560 leave("i82092aa_set_socket"); 561 return -EINVAL; 562 } 563 564 if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */ 565 indirect_write(sock, I365_POWER, reg); 566 567 /* Enable specific interrupt events */ 568 569 reg = 0x00; 570 if (state->csc_mask & SS_DETECT) 571 reg |= I365_CSC_DETECT; 572 if (state->flags & SS_IOCARD) { 573 if (state->csc_mask & SS_STSCHG) 574 reg |= I365_CSC_STSCHG; 575 } else { 576 if (state->csc_mask & SS_BATDEAD) 577 reg |= I365_CSC_BVD1; 578 if (state->csc_mask & SS_BATWARN) 579 reg |= I365_CSC_BVD2; 580 if (state->csc_mask & SS_READY) 581 reg |= I365_CSC_READY; 582 583 } 584 585 /* now write the value and clear the (probably bogus) pending stuff 586 * by doing a dummy read 587 */ 588 589 indirect_write(sock, I365_CSCINT, reg); 590 (void)indirect_read(sock, I365_CSC); 591 592 leave("i82092aa_set_socket"); 593 return 0; 594 } 595 596 static int i82092aa_set_io_map(struct pcmcia_socket *socket, 597 struct pccard_io_map *io) 598 { 599 struct socket_info *sock_info = container_of(socket, struct socket_info, 600 socket); 601 unsigned int sock = sock_info->number; 602 unsigned char map, ioctl; 603 604 enter("i82092aa_set_io_map"); 605 606 map = io->map; 607 608 /* Check error conditions */ 609 if (map > 1) { 610 leave("i82092aa_set_io_map with invalid map"); 611 return -EINVAL; 612 } 613 if ((io->start > 0xffff) || (io->stop > 0xffff) 614 || (io->stop < io->start)) { 615 leave("i82092aa_set_io_map with invalid io"); 616 return -EINVAL; 617 } 618 619 /* Turn off the window before changing anything */ 620 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) 621 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 622 623 /* write the new values */ 624 indirect_write16(sock, I365_IO(map)+I365_W_START, io->start); 625 indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop); 626 627 ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map); 628 629 if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) 630 ioctl |= I365_IOCTL_16BIT(map); 631 632 indirect_write(sock, I365_IOCTL, ioctl); 633 634 /* Turn the window back on if needed */ 635 if (io->flags & MAP_ACTIVE) 636 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 637 638 leave("i82092aa_set_io_map"); 639 return 0; 640 } 641 642 static int i82092aa_set_mem_map(struct pcmcia_socket *socket, 643 struct pccard_mem_map *mem) 644 { 645 struct socket_info *sock_info = container_of(socket, struct socket_info, 646 socket); 647 unsigned int sock = sock_info->number; 648 struct pci_bus_region region; 649 unsigned short base, i; 650 unsigned char map; 651 652 enter("i82092aa_set_mem_map"); 653 654 pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res); 655 656 map = mem->map; 657 if (map > 4) { 658 leave("i82092aa_set_mem_map: invalid map"); 659 return -EINVAL; 660 } 661 662 663 if ((mem->card_start > 0x3ffffff) || (region.start > region.end) || 664 (mem->speed > 1000)) { 665 leave("i82092aa_set_mem_map: invalid address / speed"); 666 dev_err(&sock_info->dev->dev, 667 "invalid mem map for socket %i: %llx to %llx with a start of %x\n", 668 sock, 669 (unsigned long long)region.start, 670 (unsigned long long)region.end, 671 mem->card_start); 672 return -EINVAL; 673 } 674 675 /* Turn off the window before changing anything */ 676 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) 677 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 678 679 /* write the start address */ 680 base = I365_MEM(map); 681 i = (region.start >> 12) & 0x0fff; 682 if (mem->flags & MAP_16BIT) 683 i |= I365_MEM_16BIT; 684 if (mem->flags & MAP_0WS) 685 i |= I365_MEM_0WS; 686 indirect_write16(sock, base+I365_W_START, i); 687 688 /* write the stop address */ 689 690 i = (region.end >> 12) & 0x0fff; 691 switch (to_cycles(mem->speed)) { 692 case 0: 693 break; 694 case 1: 695 i |= I365_MEM_WS0; 696 break; 697 case 2: 698 i |= I365_MEM_WS1; 699 break; 700 default: 701 i |= I365_MEM_WS1 | I365_MEM_WS0; 702 break; 703 } 704 705 indirect_write16(sock, base+I365_W_STOP, i); 706 707 /* card start */ 708 709 i = ((mem->card_start - region.start) >> 12) & 0x3fff; 710 if (mem->flags & MAP_WRPROT) 711 i |= I365_MEM_WRPROT; 712 if (mem->flags & MAP_ATTRIB) 713 i |= I365_MEM_REG; 714 indirect_write16(sock, base+I365_W_OFF, i); 715 716 /* Enable the window if necessary */ 717 if (mem->flags & MAP_ACTIVE) 718 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 719 720 leave("i82092aa_set_mem_map"); 721 return 0; 722 } 723 724 static int i82092aa_module_init(void) 725 { 726 return pci_register_driver(&i82092aa_pci_driver); 727 } 728 729 static void i82092aa_module_exit(void) 730 { 731 enter("i82092aa_module_exit"); 732 pci_unregister_driver(&i82092aa_pci_driver); 733 if (sockets[0].io_base > 0) 734 release_region(sockets[0].io_base, 2); 735 leave("i82092aa_module_exit"); 736 } 737 738 module_init(i82092aa_module_init); 739 module_exit(i82092aa_module_exit); 740 741