1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/pci.h> 20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include <linux/dmi.h> 25 #include <linux/ioport.h> 26 #include <linux/sched.h> 27 #include <linux/ktime.h> 28 #include <linux/mm.h> 29 #include <linux/nvme.h> 30 #include <linux/platform_data/x86/apple.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/suspend.h> 33 #include <linux/switchtec.h> 34 #include "pci.h" 35 36 /* 37 * Retrain the link of a downstream PCIe port by hand if necessary. 38 * 39 * This is needed at least where a downstream port of the ASMedia ASM2824 40 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 41 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 42 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 43 * board. 44 * 45 * In such a configuration the switches are supposed to negotiate the link 46 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 47 * continues switching between the two speeds indefinitely and the data 48 * link layer never reaches the active state, with link training reported 49 * repeatedly active ~84% of the time. Forcing the target link speed to 50 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 51 * each other correctly however. And more interestingly retraining with a 52 * higher target link speed afterwards lets the two successfully negotiate 53 * 5.0GT/s. 54 * 55 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 56 * Link Active status bit and in the failed link training scenario it will 57 * be off along with the Link Bandwidth Management Status indicating that 58 * hardware has changed the link speed or width in an attempt to correct 59 * unreliable link operation. For a port that has been left unconnected 60 * both bits will be clear. So use this information to detect the problem 61 * rather than polling the Link Training bit and watching out for flips or 62 * at least the active status. 63 * 64 * Since the exact nature of the problem isn't known and in principle this 65 * could trigger where an ASM2824 device is downstream rather upstream, 66 * apply this erratum workaround to any downstream ports as long as they 67 * support Link Active reporting and have the Link Control 2 register. 68 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 69 * request a retrain and wait 200ms for the data link to go up. 70 * 71 * If this turns out successful and we know by the Vendor:Device ID it is 72 * safe to do so, then lift the restriction, letting the devices negotiate 73 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 74 * firmware may have already arranged and lift it with ports that already 75 * report their data link being up. 76 * 77 * Return TRUE if the link has been successfully retrained, otherwise FALSE. 78 */ 79 bool pcie_failed_link_retrain(struct pci_dev *dev) 80 { 81 static const struct pci_device_id ids[] = { 82 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 83 {} 84 }; 85 u16 lnksta, lnkctl2; 86 87 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 88 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 89 return false; 90 91 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 92 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 93 if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) == 94 PCI_EXP_LNKSTA_LBMS) { 95 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 96 97 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 98 lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT; 99 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 100 101 if (pcie_retrain_link(dev, false)) { 102 pci_info(dev, "retraining failed\n"); 103 return false; 104 } 105 106 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 107 } 108 109 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 110 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 111 pci_match_id(ids, dev)) { 112 u32 lnkcap; 113 114 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 115 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 116 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 117 lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS; 118 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 119 120 if (pcie_retrain_link(dev, false)) { 121 pci_info(dev, "retraining failed\n"); 122 return false; 123 } 124 } 125 126 return true; 127 } 128 129 static ktime_t fixup_debug_start(struct pci_dev *dev, 130 void (*fn)(struct pci_dev *dev)) 131 { 132 if (initcall_debug) 133 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 134 135 return ktime_get(); 136 } 137 138 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 139 void (*fn)(struct pci_dev *dev)) 140 { 141 ktime_t delta, rettime; 142 unsigned long long duration; 143 144 rettime = ktime_get(); 145 delta = ktime_sub(rettime, calltime); 146 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 147 if (initcall_debug || duration > 10000) 148 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 149 } 150 151 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 152 struct pci_fixup *end) 153 { 154 ktime_t calltime; 155 156 for (; f < end; f++) 157 if ((f->class == (u32) (dev->class >> f->class_shift) || 158 f->class == (u32) PCI_ANY_ID) && 159 (f->vendor == dev->vendor || 160 f->vendor == (u16) PCI_ANY_ID) && 161 (f->device == dev->device || 162 f->device == (u16) PCI_ANY_ID)) { 163 void (*hook)(struct pci_dev *dev); 164 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 165 hook = offset_to_ptr(&f->hook_offset); 166 #else 167 hook = f->hook; 168 #endif 169 calltime = fixup_debug_start(dev, hook); 170 hook(dev); 171 fixup_debug_report(dev, calltime, hook); 172 } 173 } 174 175 extern struct pci_fixup __start_pci_fixups_early[]; 176 extern struct pci_fixup __end_pci_fixups_early[]; 177 extern struct pci_fixup __start_pci_fixups_header[]; 178 extern struct pci_fixup __end_pci_fixups_header[]; 179 extern struct pci_fixup __start_pci_fixups_final[]; 180 extern struct pci_fixup __end_pci_fixups_final[]; 181 extern struct pci_fixup __start_pci_fixups_enable[]; 182 extern struct pci_fixup __end_pci_fixups_enable[]; 183 extern struct pci_fixup __start_pci_fixups_resume[]; 184 extern struct pci_fixup __end_pci_fixups_resume[]; 185 extern struct pci_fixup __start_pci_fixups_resume_early[]; 186 extern struct pci_fixup __end_pci_fixups_resume_early[]; 187 extern struct pci_fixup __start_pci_fixups_suspend[]; 188 extern struct pci_fixup __end_pci_fixups_suspend[]; 189 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 190 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 191 192 static bool pci_apply_fixup_final_quirks; 193 194 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 195 { 196 struct pci_fixup *start, *end; 197 198 switch (pass) { 199 case pci_fixup_early: 200 start = __start_pci_fixups_early; 201 end = __end_pci_fixups_early; 202 break; 203 204 case pci_fixup_header: 205 start = __start_pci_fixups_header; 206 end = __end_pci_fixups_header; 207 break; 208 209 case pci_fixup_final: 210 if (!pci_apply_fixup_final_quirks) 211 return; 212 start = __start_pci_fixups_final; 213 end = __end_pci_fixups_final; 214 break; 215 216 case pci_fixup_enable: 217 start = __start_pci_fixups_enable; 218 end = __end_pci_fixups_enable; 219 break; 220 221 case pci_fixup_resume: 222 start = __start_pci_fixups_resume; 223 end = __end_pci_fixups_resume; 224 break; 225 226 case pci_fixup_resume_early: 227 start = __start_pci_fixups_resume_early; 228 end = __end_pci_fixups_resume_early; 229 break; 230 231 case pci_fixup_suspend: 232 start = __start_pci_fixups_suspend; 233 end = __end_pci_fixups_suspend; 234 break; 235 236 case pci_fixup_suspend_late: 237 start = __start_pci_fixups_suspend_late; 238 end = __end_pci_fixups_suspend_late; 239 break; 240 241 default: 242 /* stupid compiler warning, you would think with an enum... */ 243 return; 244 } 245 pci_do_fixups(dev, start, end); 246 } 247 EXPORT_SYMBOL(pci_fixup_device); 248 249 static int __init pci_apply_final_quirks(void) 250 { 251 struct pci_dev *dev = NULL; 252 u8 cls = 0; 253 u8 tmp; 254 255 if (pci_cache_line_size) 256 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 257 258 pci_apply_fixup_final_quirks = true; 259 for_each_pci_dev(dev) { 260 pci_fixup_device(pci_fixup_final, dev); 261 /* 262 * If arch hasn't set it explicitly yet, use the CLS 263 * value shared by all PCI devices. If there's a 264 * mismatch, fall back to the default value. 265 */ 266 if (!pci_cache_line_size) { 267 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 268 if (!cls) 269 cls = tmp; 270 if (!tmp || cls == tmp) 271 continue; 272 273 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 274 cls << 2, tmp << 2, 275 pci_dfl_cache_line_size << 2); 276 pci_cache_line_size = pci_dfl_cache_line_size; 277 } 278 } 279 280 if (!pci_cache_line_size) { 281 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 282 pci_dfl_cache_line_size << 2); 283 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 284 } 285 286 return 0; 287 } 288 fs_initcall_sync(pci_apply_final_quirks); 289 290 /* 291 * Decoding should be disabled for a PCI device during BAR sizing to avoid 292 * conflict. But doing so may cause problems on host bridge and perhaps other 293 * key system devices. For devices that need to have mmio decoding always-on, 294 * we need to set the dev->mmio_always_on bit. 295 */ 296 static void quirk_mmio_always_on(struct pci_dev *dev) 297 { 298 dev->mmio_always_on = 1; 299 } 300 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 301 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 302 303 /* 304 * The Mellanox Tavor device gives false positive parity errors. Disable 305 * parity error reporting. 306 */ 307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 309 310 /* 311 * Deal with broken BIOSes that neglect to enable passive release, 312 * which can cause problems in combination with the 82441FX/PPro MTRRs 313 */ 314 static void quirk_passive_release(struct pci_dev *dev) 315 { 316 struct pci_dev *d = NULL; 317 unsigned char dlc; 318 319 /* 320 * We have to make sure a particular bit is set in the PIIX3 321 * ISA bridge, so we have to go out and find it. 322 */ 323 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 324 pci_read_config_byte(d, 0x82, &dlc); 325 if (!(dlc & 1<<1)) { 326 pci_info(d, "PIIX3: Enabling Passive Release\n"); 327 dlc |= 1<<1; 328 pci_write_config_byte(d, 0x82, dlc); 329 } 330 } 331 } 332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 333 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 334 335 #ifdef CONFIG_X86_32 336 /* 337 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 338 * workaround but VIA don't answer queries. If you happen to have good 339 * contacts at VIA ask them for me please -- Alan 340 * 341 * This appears to be BIOS not version dependent. So presumably there is a 342 * chipset level fix. 343 */ 344 static void quirk_isa_dma_hangs(struct pci_dev *dev) 345 { 346 if (!isa_dma_bridge_buggy) { 347 isa_dma_bridge_buggy = 1; 348 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 349 } 350 } 351 /* 352 * It's not totally clear which chipsets are the problematic ones. We know 353 * 82C586 and 82C596 variants are affected. 354 */ 355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 362 #endif 363 364 #ifdef CONFIG_HAS_IOPORT 365 /* 366 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 367 * for some HT machines to use C4 w/o hanging. 368 */ 369 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 370 { 371 u32 pmbase; 372 u16 pm1a; 373 374 pci_read_config_dword(dev, 0x40, &pmbase); 375 pmbase = pmbase & 0xff80; 376 pm1a = inw(pmbase); 377 378 if (pm1a & 0x10) { 379 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 380 outw(0x10, pmbase); 381 } 382 } 383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 384 #endif 385 386 /* Chipsets where PCI->PCI transfers vanish or hang */ 387 static void quirk_nopcipci(struct pci_dev *dev) 388 { 389 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 390 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 391 pci_pci_problems |= PCIPCI_FAIL; 392 } 393 } 394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 396 397 static void quirk_nopciamd(struct pci_dev *dev) 398 { 399 u8 rev; 400 pci_read_config_byte(dev, 0x08, &rev); 401 if (rev == 0x13) { 402 /* Erratum 24 */ 403 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 404 pci_pci_problems |= PCIAGP_FAIL; 405 } 406 } 407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 408 409 /* Triton requires workarounds to be used by the drivers */ 410 static void quirk_triton(struct pci_dev *dev) 411 { 412 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 413 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 414 pci_pci_problems |= PCIPCI_TRITON; 415 } 416 } 417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 421 422 /* 423 * VIA Apollo KT133 needs PCI latency patch 424 * Made according to a Windows driver-based patch by George E. Breese; 425 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 426 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 427 * which Mr Breese based his work. 428 * 429 * Updated based on further information from the site and also on 430 * information provided by VIA 431 */ 432 static void quirk_vialatency(struct pci_dev *dev) 433 { 434 struct pci_dev *p; 435 u8 busarb; 436 437 /* 438 * Ok, we have a potential problem chipset here. Now see if we have 439 * a buggy southbridge. 440 */ 441 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 442 if (p != NULL) { 443 444 /* 445 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 446 * thanks Dan Hollis. 447 * Check for buggy part revisions 448 */ 449 if (p->revision < 0x40 || p->revision > 0x42) 450 goto exit; 451 } else { 452 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 453 if (p == NULL) /* No problem parts */ 454 goto exit; 455 456 /* Check for buggy part revisions */ 457 if (p->revision < 0x10 || p->revision > 0x12) 458 goto exit; 459 } 460 461 /* 462 * Ok we have the problem. Now set the PCI master grant to occur 463 * every master grant. The apparent bug is that under high PCI load 464 * (quite common in Linux of course) you can get data loss when the 465 * CPU is held off the bus for 3 bus master requests. This happens 466 * to include the IDE controllers.... 467 * 468 * VIA only apply this fix when an SB Live! is present but under 469 * both Linux and Windows this isn't enough, and we have seen 470 * corruption without SB Live! but with things like 3 UDMA IDE 471 * controllers. So we ignore that bit of the VIA recommendation.. 472 */ 473 pci_read_config_byte(dev, 0x76, &busarb); 474 475 /* 476 * Set bit 4 and bit 5 of byte 76 to 0x01 477 * "Master priority rotation on every PCI master grant" 478 */ 479 busarb &= ~(1<<5); 480 busarb |= (1<<4); 481 pci_write_config_byte(dev, 0x76, busarb); 482 pci_info(dev, "Applying VIA southbridge workaround\n"); 483 exit: 484 pci_dev_put(p); 485 } 486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 489 /* Must restore this on a resume from RAM */ 490 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 491 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 492 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 493 494 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 495 static void quirk_viaetbf(struct pci_dev *dev) 496 { 497 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 498 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 499 pci_pci_problems |= PCIPCI_VIAETBF; 500 } 501 } 502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 503 504 static void quirk_vsfx(struct pci_dev *dev) 505 { 506 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 507 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 508 pci_pci_problems |= PCIPCI_VSFX; 509 } 510 } 511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 512 513 /* 514 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 515 * space. Latency must be set to 0xA and Triton workaround applied too. 516 * [Info kindly provided by ALi] 517 */ 518 static void quirk_alimagik(struct pci_dev *dev) 519 { 520 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 521 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 522 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 523 } 524 } 525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 527 528 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 529 static void quirk_natoma(struct pci_dev *dev) 530 { 531 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 532 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 533 pci_pci_problems |= PCIPCI_NATOMA; 534 } 535 } 536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 542 543 /* 544 * This chip can cause PCI parity errors if config register 0xA0 is read 545 * while DMAs are occurring. 546 */ 547 static void quirk_citrine(struct pci_dev *dev) 548 { 549 dev->cfg_size = 0xA0; 550 } 551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 552 553 /* 554 * This chip can cause bus lockups if config addresses above 0x600 555 * are read or written. 556 */ 557 static void quirk_nfp6000(struct pci_dev *dev) 558 { 559 dev->cfg_size = 0x600; 560 } 561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 565 566 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 567 static void quirk_extend_bar_to_page(struct pci_dev *dev) 568 { 569 int i; 570 571 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 572 struct resource *r = &dev->resource[i]; 573 574 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 575 r->end = PAGE_SIZE - 1; 576 r->start = 0; 577 r->flags |= IORESOURCE_UNSET; 578 pci_info(dev, "expanded BAR %d to page size: %pR\n", 579 i, r); 580 } 581 } 582 } 583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 584 585 /* 586 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 587 * If it's needed, re-allocate the region. 588 */ 589 static void quirk_s3_64M(struct pci_dev *dev) 590 { 591 struct resource *r = &dev->resource[0]; 592 593 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 594 r->flags |= IORESOURCE_UNSET; 595 r->start = 0; 596 r->end = 0x3ffffff; 597 } 598 } 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 601 602 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 603 const char *name) 604 { 605 u32 region; 606 struct pci_bus_region bus_region; 607 struct resource *res = dev->resource + pos; 608 609 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 610 611 if (!region) 612 return; 613 614 res->name = pci_name(dev); 615 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 616 res->flags |= 617 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 618 region &= ~(size - 1); 619 620 /* Convert from PCI bus to resource space */ 621 bus_region.start = region; 622 bus_region.end = region + size - 1; 623 pcibios_bus_to_resource(dev->bus, res, &bus_region); 624 625 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 626 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 627 } 628 629 /* 630 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 631 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 632 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 633 * (which conflicts w/ BAR1's memory range). 634 * 635 * CS553x's ISA PCI BARs may also be read-only (ref: 636 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 637 */ 638 static void quirk_cs5536_vsa(struct pci_dev *dev) 639 { 640 static char *name = "CS5536 ISA bridge"; 641 642 if (pci_resource_len(dev, 0) != 8) { 643 quirk_io(dev, 0, 8, name); /* SMB */ 644 quirk_io(dev, 1, 256, name); /* GPIO */ 645 quirk_io(dev, 2, 64, name); /* MFGPT */ 646 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 647 name); 648 } 649 } 650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 651 652 static void quirk_io_region(struct pci_dev *dev, int port, 653 unsigned int size, int nr, const char *name) 654 { 655 u16 region; 656 struct pci_bus_region bus_region; 657 struct resource *res = dev->resource + nr; 658 659 pci_read_config_word(dev, port, ®ion); 660 region &= ~(size - 1); 661 662 if (!region) 663 return; 664 665 res->name = pci_name(dev); 666 res->flags = IORESOURCE_IO; 667 668 /* Convert from PCI bus to resource space */ 669 bus_region.start = region; 670 bus_region.end = region + size - 1; 671 pcibios_bus_to_resource(dev->bus, res, &bus_region); 672 673 if (!pci_claim_resource(dev, nr)) 674 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 675 } 676 677 /* 678 * ATI Northbridge setups MCE the processor if you even read somewhere 679 * between 0x3b0->0x3bb or read 0x3d3 680 */ 681 static void quirk_ati_exploding_mce(struct pci_dev *dev) 682 { 683 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 684 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 685 request_region(0x3b0, 0x0C, "RadeonIGP"); 686 request_region(0x3d3, 0x01, "RadeonIGP"); 687 } 688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 689 690 /* 691 * In the AMD NL platform, this device ([1022:7912]) has a class code of 692 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 693 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 694 * 695 * But the dwc3 driver is a more specific driver for this device, and we'd 696 * prefer to use it instead of xhci. To prevent xhci from claiming the 697 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 698 * defines as "USB device (not host controller)". The dwc3 driver can then 699 * claim it based on its Vendor and Device ID. 700 */ 701 static void quirk_amd_dwc_class(struct pci_dev *pdev) 702 { 703 u32 class = pdev->class; 704 705 /* Use "USB Device (not host controller)" class */ 706 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 707 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 708 class, pdev->class); 709 } 710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 711 quirk_amd_dwc_class); 712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 713 quirk_amd_dwc_class); 714 715 /* 716 * Synopsys USB 3.x host HAPS platform has a class code of 717 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 718 * devices should use dwc3-haps driver. Change these devices' class code to 719 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 720 * them. 721 */ 722 static void quirk_synopsys_haps(struct pci_dev *pdev) 723 { 724 u32 class = pdev->class; 725 726 switch (pdev->device) { 727 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 728 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 729 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 730 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 731 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 732 class, pdev->class); 733 break; 734 } 735 } 736 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 737 PCI_CLASS_SERIAL_USB_XHCI, 0, 738 quirk_synopsys_haps); 739 740 /* 741 * Let's make the southbridge information explicit instead of having to 742 * worry about people probing the ACPI areas, for example.. (Yes, it 743 * happens, and if you read the wrong ACPI register it will put the machine 744 * to sleep with no way of waking it up again. Bummer). 745 * 746 * ALI M7101: Two IO regions pointed to by words at 747 * 0xE0 (64 bytes of ACPI registers) 748 * 0xE2 (32 bytes of SMB registers) 749 */ 750 static void quirk_ali7101_acpi(struct pci_dev *dev) 751 { 752 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 753 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 754 } 755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 756 757 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 758 { 759 u32 devres; 760 u32 mask, size, base; 761 762 pci_read_config_dword(dev, port, &devres); 763 if ((devres & enable) != enable) 764 return; 765 mask = (devres >> 16) & 15; 766 base = devres & 0xffff; 767 size = 16; 768 for (;;) { 769 unsigned int bit = size >> 1; 770 if ((bit & mask) == bit) 771 break; 772 size = bit; 773 } 774 /* 775 * For now we only print it out. Eventually we'll want to 776 * reserve it (at least if it's in the 0x1000+ range), but 777 * let's get enough confirmation reports first. 778 */ 779 base &= -size; 780 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 781 } 782 783 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 784 { 785 u32 devres; 786 u32 mask, size, base; 787 788 pci_read_config_dword(dev, port, &devres); 789 if ((devres & enable) != enable) 790 return; 791 base = devres & 0xffff0000; 792 mask = (devres & 0x3f) << 16; 793 size = 128 << 16; 794 for (;;) { 795 unsigned int bit = size >> 1; 796 if ((bit & mask) == bit) 797 break; 798 size = bit; 799 } 800 801 /* 802 * For now we only print it out. Eventually we'll want to 803 * reserve it, but let's get enough confirmation reports first. 804 */ 805 base &= -size; 806 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 807 } 808 809 /* 810 * PIIX4 ACPI: Two IO regions pointed to by longwords at 811 * 0x40 (64 bytes of ACPI registers) 812 * 0x90 (16 bytes of SMB registers) 813 * and a few strange programmable PIIX4 device resources. 814 */ 815 static void quirk_piix4_acpi(struct pci_dev *dev) 816 { 817 u32 res_a; 818 819 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 820 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 821 822 /* Device resource A has enables for some of the other ones */ 823 pci_read_config_dword(dev, 0x5c, &res_a); 824 825 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 826 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 827 828 /* Device resource D is just bitfields for static resources */ 829 830 /* Device 12 enabled? */ 831 if (res_a & (1 << 29)) { 832 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 833 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 834 } 835 /* Device 13 enabled? */ 836 if (res_a & (1 << 30)) { 837 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 838 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 839 } 840 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 841 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 842 } 843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 845 846 #define ICH_PMBASE 0x40 847 #define ICH_ACPI_CNTL 0x44 848 #define ICH4_ACPI_EN 0x10 849 #define ICH6_ACPI_EN 0x80 850 #define ICH4_GPIOBASE 0x58 851 #define ICH4_GPIO_CNTL 0x5c 852 #define ICH4_GPIO_EN 0x10 853 #define ICH6_GPIOBASE 0x48 854 #define ICH6_GPIO_CNTL 0x4c 855 #define ICH6_GPIO_EN 0x10 856 857 /* 858 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 859 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 860 * 0x58 (64 bytes of GPIO I/O space) 861 */ 862 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 863 { 864 u8 enable; 865 866 /* 867 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 868 * with low legacy (and fixed) ports. We don't know the decoding 869 * priority and can't tell whether the legacy device or the one created 870 * here is really at that address. This happens on boards with broken 871 * BIOSes. 872 */ 873 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 874 if (enable & ICH4_ACPI_EN) 875 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 876 "ICH4 ACPI/GPIO/TCO"); 877 878 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 879 if (enable & ICH4_GPIO_EN) 880 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 881 "ICH4 GPIO"); 882 } 883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 893 894 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 895 { 896 u8 enable; 897 898 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 899 if (enable & ICH6_ACPI_EN) 900 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 901 "ICH6 ACPI/GPIO/TCO"); 902 903 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 904 if (enable & ICH6_GPIO_EN) 905 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 906 "ICH6 GPIO"); 907 } 908 909 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 910 const char *name, int dynsize) 911 { 912 u32 val; 913 u32 size, base; 914 915 pci_read_config_dword(dev, reg, &val); 916 917 /* Enabled? */ 918 if (!(val & 1)) 919 return; 920 base = val & 0xfffc; 921 if (dynsize) { 922 /* 923 * This is not correct. It is 16, 32 or 64 bytes depending on 924 * register D31:F0:ADh bits 5:4. 925 * 926 * But this gets us at least _part_ of it. 927 */ 928 size = 16; 929 } else { 930 size = 128; 931 } 932 base &= ~(size-1); 933 934 /* 935 * Just print it out for now. We should reserve it after more 936 * debugging. 937 */ 938 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 939 } 940 941 static void quirk_ich6_lpc(struct pci_dev *dev) 942 { 943 /* Shared ACPI/GPIO decode with all ICH6+ */ 944 ich6_lpc_acpi_gpio(dev); 945 946 /* ICH6-specific generic IO decode */ 947 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 948 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 949 } 950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 952 953 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 954 const char *name) 955 { 956 u32 val; 957 u32 mask, base; 958 959 pci_read_config_dword(dev, reg, &val); 960 961 /* Enabled? */ 962 if (!(val & 1)) 963 return; 964 965 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 966 base = val & 0xfffc; 967 mask = (val >> 16) & 0xfc; 968 mask |= 3; 969 970 /* 971 * Just print it out for now. We should reserve it after more 972 * debugging. 973 */ 974 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 975 } 976 977 /* ICH7-10 has the same common LPC generic IO decode registers */ 978 static void quirk_ich7_lpc(struct pci_dev *dev) 979 { 980 /* We share the common ACPI/GPIO decode with ICH6 */ 981 ich6_lpc_acpi_gpio(dev); 982 983 /* And have 4 ICH7+ generic decodes */ 984 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 985 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 986 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 987 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 988 } 989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1002 1003 /* 1004 * VIA ACPI: One IO region pointed to by longword at 1005 * 0x48 or 0x20 (256 bytes of ACPI registers) 1006 */ 1007 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1008 { 1009 if (dev->revision & 0x10) 1010 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1011 "vt82c586 ACPI"); 1012 } 1013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1014 1015 /* 1016 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1017 * 0x48 (256 bytes of ACPI registers) 1018 * 0x70 (128 bytes of hardware monitoring register) 1019 * 0x90 (16 bytes of SMB registers) 1020 */ 1021 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1022 { 1023 quirk_vt82c586_acpi(dev); 1024 1025 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1026 "vt82c686 HW-mon"); 1027 1028 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1029 } 1030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1031 1032 /* 1033 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1034 * 0x88 (128 bytes of power management registers) 1035 * 0xd0 (16 bytes of SMB registers) 1036 */ 1037 static void quirk_vt8235_acpi(struct pci_dev *dev) 1038 { 1039 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1040 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1041 } 1042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1043 1044 /* 1045 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1046 * back-to-back: Disable fast back-to-back on the secondary bus segment 1047 */ 1048 static void quirk_xio2000a(struct pci_dev *dev) 1049 { 1050 struct pci_dev *pdev; 1051 u16 command; 1052 1053 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1054 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1055 pci_read_config_word(pdev, PCI_COMMAND, &command); 1056 if (command & PCI_COMMAND_FAST_BACK) 1057 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1058 } 1059 } 1060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1061 quirk_xio2000a); 1062 1063 #ifdef CONFIG_X86_IO_APIC 1064 1065 #include <asm/io_apic.h> 1066 1067 /* 1068 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1069 * devices to the external APIC. 1070 * 1071 * TODO: When we have device-specific interrupt routers, this code will go 1072 * away from quirks. 1073 */ 1074 static void quirk_via_ioapic(struct pci_dev *dev) 1075 { 1076 u8 tmp; 1077 1078 if (nr_ioapics < 1) 1079 tmp = 0; /* nothing routed to external APIC */ 1080 else 1081 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1082 1083 pci_info(dev, "%s VIA external APIC routing\n", 1084 tmp ? "Enabling" : "Disabling"); 1085 1086 /* Offset 0x58: External APIC IRQ output control */ 1087 pci_write_config_byte(dev, 0x58, tmp); 1088 } 1089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1090 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1091 1092 /* 1093 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1094 * This leads to doubled level interrupt rates. 1095 * Set this bit to get rid of cycle wastage. 1096 * Otherwise uncritical. 1097 */ 1098 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1099 { 1100 u8 misc_control2; 1101 #define BYPASS_APIC_DEASSERT 8 1102 1103 pci_read_config_byte(dev, 0x5B, &misc_control2); 1104 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1105 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1106 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1107 } 1108 } 1109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1110 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1111 1112 /* 1113 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1114 * We check all revs >= B0 (yet not in the pre production!) as the bug 1115 * is currently marked NoFix 1116 * 1117 * We have multiple reports of hangs with this chipset that went away with 1118 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1119 * of course. However the advice is demonstrably good even if so. 1120 */ 1121 static void quirk_amd_ioapic(struct pci_dev *dev) 1122 { 1123 if (dev->revision >= 0x02) { 1124 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1125 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1126 } 1127 } 1128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1129 #endif /* CONFIG_X86_IO_APIC */ 1130 1131 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1132 1133 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1134 { 1135 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1136 if (dev->subsystem_device == 0xa118) 1137 dev->sriov->link = dev->devfn; 1138 } 1139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1140 #endif 1141 1142 /* 1143 * Some settings of MMRBC can lead to data corruption so block changes. 1144 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1145 */ 1146 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1147 { 1148 if (dev->subordinate && dev->revision <= 0x12) { 1149 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1150 dev->revision); 1151 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1152 } 1153 } 1154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1155 1156 /* 1157 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1158 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1159 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1160 * of the ACPI SCI interrupt is only done for convenience. 1161 * -jgarzik 1162 */ 1163 static void quirk_via_acpi(struct pci_dev *d) 1164 { 1165 u8 irq; 1166 1167 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1168 pci_read_config_byte(d, 0x42, &irq); 1169 irq &= 0xf; 1170 if (irq && (irq != 2)) 1171 d->irq = irq; 1172 } 1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1175 1176 /* VIA bridges which have VLink */ 1177 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1178 1179 static void quirk_via_bridge(struct pci_dev *dev) 1180 { 1181 /* See what bridge we have and find the device ranges */ 1182 switch (dev->device) { 1183 case PCI_DEVICE_ID_VIA_82C686: 1184 /* 1185 * The VT82C686 is special; it attaches to PCI and can have 1186 * any device number. All its subdevices are functions of 1187 * that single device. 1188 */ 1189 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1190 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1191 break; 1192 case PCI_DEVICE_ID_VIA_8237: 1193 case PCI_DEVICE_ID_VIA_8237A: 1194 via_vlink_dev_lo = 15; 1195 break; 1196 case PCI_DEVICE_ID_VIA_8235: 1197 via_vlink_dev_lo = 16; 1198 break; 1199 case PCI_DEVICE_ID_VIA_8231: 1200 case PCI_DEVICE_ID_VIA_8233_0: 1201 case PCI_DEVICE_ID_VIA_8233A: 1202 case PCI_DEVICE_ID_VIA_8233C_0: 1203 via_vlink_dev_lo = 17; 1204 break; 1205 } 1206 } 1207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1215 1216 /* 1217 * quirk_via_vlink - VIA VLink IRQ number update 1218 * @dev: PCI device 1219 * 1220 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1221 * the IRQ line register which usually is not relevant for PCI cards, is 1222 * actually written so that interrupts get sent to the right place. 1223 * 1224 * We only do this on systems where a VIA south bridge was detected, and 1225 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1226 */ 1227 static void quirk_via_vlink(struct pci_dev *dev) 1228 { 1229 u8 irq, new_irq; 1230 1231 /* Check if we have VLink at all */ 1232 if (via_vlink_dev_lo == -1) 1233 return; 1234 1235 new_irq = dev->irq; 1236 1237 /* Don't quirk interrupts outside the legacy IRQ range */ 1238 if (!new_irq || new_irq > 15) 1239 return; 1240 1241 /* Internal device ? */ 1242 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1243 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1244 return; 1245 1246 /* 1247 * This is an internal VLink device on a PIC interrupt. The BIOS 1248 * ought to have set this but may not have, so we redo it. 1249 */ 1250 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1251 if (new_irq != irq) { 1252 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1253 irq, new_irq); 1254 udelay(15); /* unknown if delay really needed */ 1255 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1256 } 1257 } 1258 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1259 1260 /* 1261 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1262 * of VT82C597 for backward compatibility. We need to switch it off to be 1263 * able to recognize the real type of the chip. 1264 */ 1265 static void quirk_vt82c598_id(struct pci_dev *dev) 1266 { 1267 pci_write_config_byte(dev, 0xfc, 0); 1268 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1269 } 1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1271 1272 /* 1273 * CardBus controllers have a legacy base address that enables them to 1274 * respond as i82365 pcmcia controllers. We don't want them to do this 1275 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1276 * driver does not (and should not) handle CardBus. 1277 */ 1278 static void quirk_cardbus_legacy(struct pci_dev *dev) 1279 { 1280 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1281 } 1282 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1283 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1284 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1285 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1286 1287 /* 1288 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1289 * what the designers were smoking but let's not inhale... 1290 * 1291 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1292 * turn it off! 1293 */ 1294 static void quirk_amd_ordering(struct pci_dev *dev) 1295 { 1296 u32 pcic; 1297 pci_read_config_dword(dev, 0x4C, &pcic); 1298 if ((pcic & 6) != 6) { 1299 pcic |= 6; 1300 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1301 pci_write_config_dword(dev, 0x4C, pcic); 1302 pci_read_config_dword(dev, 0x84, &pcic); 1303 pcic |= (1 << 23); /* Required in this mode */ 1304 pci_write_config_dword(dev, 0x84, pcic); 1305 } 1306 } 1307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1308 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1309 1310 /* 1311 * DreamWorks-provided workaround for Dunord I-3000 problem 1312 * 1313 * This card decodes and responds to addresses not apparently assigned to 1314 * it. We force a larger allocation to ensure that nothing gets put too 1315 * close to it. 1316 */ 1317 static void quirk_dunord(struct pci_dev *dev) 1318 { 1319 struct resource *r = &dev->resource[1]; 1320 1321 r->flags |= IORESOURCE_UNSET; 1322 r->start = 0; 1323 r->end = 0xffffff; 1324 } 1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1326 1327 /* 1328 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1329 * decoding (transparent), and does indicate this in the ProgIf. 1330 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1331 */ 1332 static void quirk_transparent_bridge(struct pci_dev *dev) 1333 { 1334 dev->transparent = 1; 1335 } 1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1338 1339 /* 1340 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1341 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1342 * found at http://www.national.com/analog for info on what these bits do. 1343 * <christer@weinigel.se> 1344 */ 1345 static void quirk_mediagx_master(struct pci_dev *dev) 1346 { 1347 u8 reg; 1348 1349 pci_read_config_byte(dev, 0x41, ®); 1350 if (reg & 2) { 1351 reg &= ~2; 1352 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1353 reg); 1354 pci_write_config_byte(dev, 0x41, reg); 1355 } 1356 } 1357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1358 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1359 1360 /* 1361 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1362 * in the odd case it is not the results are corruption hence the presence 1363 * of a Linux check. 1364 */ 1365 static void quirk_disable_pxb(struct pci_dev *pdev) 1366 { 1367 u16 config; 1368 1369 if (pdev->revision != 0x04) /* Only C0 requires this */ 1370 return; 1371 pci_read_config_word(pdev, 0x40, &config); 1372 if (config & (1<<6)) { 1373 config &= ~(1<<6); 1374 pci_write_config_word(pdev, 0x40, config); 1375 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1376 } 1377 } 1378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1379 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1380 1381 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1382 { 1383 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1384 u8 tmp; 1385 1386 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1387 if (tmp == 0x01) { 1388 pci_read_config_byte(pdev, 0x40, &tmp); 1389 pci_write_config_byte(pdev, 0x40, tmp|1); 1390 pci_write_config_byte(pdev, 0x9, 1); 1391 pci_write_config_byte(pdev, 0xa, 6); 1392 pci_write_config_byte(pdev, 0x40, tmp); 1393 1394 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1395 pci_info(pdev, "set SATA to AHCI mode\n"); 1396 } 1397 } 1398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1399 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1401 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1403 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1405 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1406 1407 /* Serverworks CSB5 IDE does not fully support native mode */ 1408 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1409 { 1410 u8 prog; 1411 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1412 if (prog & 5) { 1413 prog &= ~5; 1414 pdev->class &= ~5; 1415 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1416 /* PCI layer will sort out resources */ 1417 } 1418 } 1419 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1420 1421 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1422 static void quirk_ide_samemode(struct pci_dev *pdev) 1423 { 1424 u8 prog; 1425 1426 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1427 1428 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1429 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1430 prog &= ~5; 1431 pdev->class &= ~5; 1432 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1433 } 1434 } 1435 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1436 1437 /* Some ATA devices break if put into D3 */ 1438 static void quirk_no_ata_d3(struct pci_dev *pdev) 1439 { 1440 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1441 } 1442 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1443 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1444 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1445 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1446 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1447 /* ALi loses some register settings that we cannot then restore */ 1448 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1449 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1450 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1451 occur when mode detecting */ 1452 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1453 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1454 1455 /* 1456 * This was originally an Alpha-specific thing, but it really fits here. 1457 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1458 */ 1459 static void quirk_eisa_bridge(struct pci_dev *dev) 1460 { 1461 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1462 } 1463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1464 1465 /* 1466 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1467 * is not activated. The myth is that Asus said that they do not want the 1468 * users to be irritated by just another PCI Device in the Win98 device 1469 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1470 * package 2.7.0 for details) 1471 * 1472 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1473 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1474 * becomes necessary to do this tweak in two steps -- the chosen trigger 1475 * is either the Host bridge (preferred) or on-board VGA controller. 1476 * 1477 * Note that we used to unhide the SMBus that way on Toshiba laptops 1478 * (Satellite A40 and Tecra M2) but then found that the thermal management 1479 * was done by SMM code, which could cause unsynchronized concurrent 1480 * accesses to the SMBus registers, with potentially bad effects. Thus you 1481 * should be very careful when adding new entries: if SMM is accessing the 1482 * Intel SMBus, this is a very good reason to leave it hidden. 1483 * 1484 * Likewise, many recent laptops use ACPI for thermal management. If the 1485 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1486 * natively, and keeping the SMBus hidden is the right thing to do. If you 1487 * are about to add an entry in the table below, please first disassemble 1488 * the DSDT and double-check that there is no code accessing the SMBus. 1489 */ 1490 static int asus_hides_smbus; 1491 1492 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1493 { 1494 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1495 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1496 switch (dev->subsystem_device) { 1497 case 0x8025: /* P4B-LX */ 1498 case 0x8070: /* P4B */ 1499 case 0x8088: /* P4B533 */ 1500 case 0x1626: /* L3C notebook */ 1501 asus_hides_smbus = 1; 1502 } 1503 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1504 switch (dev->subsystem_device) { 1505 case 0x80b1: /* P4GE-V */ 1506 case 0x80b2: /* P4PE */ 1507 case 0x8093: /* P4B533-V */ 1508 asus_hides_smbus = 1; 1509 } 1510 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1511 switch (dev->subsystem_device) { 1512 case 0x8030: /* P4T533 */ 1513 asus_hides_smbus = 1; 1514 } 1515 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1516 switch (dev->subsystem_device) { 1517 case 0x8070: /* P4G8X Deluxe */ 1518 asus_hides_smbus = 1; 1519 } 1520 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1521 switch (dev->subsystem_device) { 1522 case 0x80c9: /* PU-DLS */ 1523 asus_hides_smbus = 1; 1524 } 1525 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1526 switch (dev->subsystem_device) { 1527 case 0x1751: /* M2N notebook */ 1528 case 0x1821: /* M5N notebook */ 1529 case 0x1897: /* A6L notebook */ 1530 asus_hides_smbus = 1; 1531 } 1532 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1533 switch (dev->subsystem_device) { 1534 case 0x184b: /* W1N notebook */ 1535 case 0x186a: /* M6Ne notebook */ 1536 asus_hides_smbus = 1; 1537 } 1538 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1539 switch (dev->subsystem_device) { 1540 case 0x80f2: /* P4P800-X */ 1541 asus_hides_smbus = 1; 1542 } 1543 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1544 switch (dev->subsystem_device) { 1545 case 0x1882: /* M6V notebook */ 1546 case 0x1977: /* A6VA notebook */ 1547 asus_hides_smbus = 1; 1548 } 1549 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1550 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1551 switch (dev->subsystem_device) { 1552 case 0x088C: /* HP Compaq nc8000 */ 1553 case 0x0890: /* HP Compaq nc6000 */ 1554 asus_hides_smbus = 1; 1555 } 1556 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1557 switch (dev->subsystem_device) { 1558 case 0x12bc: /* HP D330L */ 1559 case 0x12bd: /* HP D530 */ 1560 case 0x006a: /* HP Compaq nx9500 */ 1561 asus_hides_smbus = 1; 1562 } 1563 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1564 switch (dev->subsystem_device) { 1565 case 0x12bf: /* HP xw4100 */ 1566 asus_hides_smbus = 1; 1567 } 1568 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1569 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1570 switch (dev->subsystem_device) { 1571 case 0xC00C: /* Samsung P35 notebook */ 1572 asus_hides_smbus = 1; 1573 } 1574 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1575 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1576 switch (dev->subsystem_device) { 1577 case 0x0058: /* Compaq Evo N620c */ 1578 asus_hides_smbus = 1; 1579 } 1580 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1581 switch (dev->subsystem_device) { 1582 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1583 /* Motherboard doesn't have Host bridge 1584 * subvendor/subdevice IDs, therefore checking 1585 * its on-board VGA controller */ 1586 asus_hides_smbus = 1; 1587 } 1588 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1589 switch (dev->subsystem_device) { 1590 case 0x00b8: /* Compaq Evo D510 CMT */ 1591 case 0x00b9: /* Compaq Evo D510 SFF */ 1592 case 0x00ba: /* Compaq Evo D510 USDT */ 1593 /* Motherboard doesn't have Host bridge 1594 * subvendor/subdevice IDs and on-board VGA 1595 * controller is disabled if an AGP card is 1596 * inserted, therefore checking USB UHCI 1597 * Controller #1 */ 1598 asus_hides_smbus = 1; 1599 } 1600 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1601 switch (dev->subsystem_device) { 1602 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1603 /* Motherboard doesn't have host bridge 1604 * subvendor/subdevice IDs, therefore checking 1605 * its on-board VGA controller */ 1606 asus_hides_smbus = 1; 1607 } 1608 } 1609 } 1610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1620 1621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1624 1625 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1626 { 1627 u16 val; 1628 1629 if (likely(!asus_hides_smbus)) 1630 return; 1631 1632 pci_read_config_word(dev, 0xF2, &val); 1633 if (val & 0x8) { 1634 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1635 pci_read_config_word(dev, 0xF2, &val); 1636 if (val & 0x8) 1637 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1638 val); 1639 else 1640 pci_info(dev, "Enabled i801 SMBus device\n"); 1641 } 1642 } 1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1650 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1651 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1652 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1653 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1654 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1655 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1656 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1657 1658 /* It appears we just have one such device. If not, we have a warning */ 1659 static void __iomem *asus_rcba_base; 1660 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1661 { 1662 u32 rcba; 1663 1664 if (likely(!asus_hides_smbus)) 1665 return; 1666 WARN_ON(asus_rcba_base); 1667 1668 pci_read_config_dword(dev, 0xF0, &rcba); 1669 /* use bits 31:14, 16 kB aligned */ 1670 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1671 if (asus_rcba_base == NULL) 1672 return; 1673 } 1674 1675 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1676 { 1677 u32 val; 1678 1679 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1680 return; 1681 1682 /* read the Function Disable register, dword mode only */ 1683 val = readl(asus_rcba_base + 0x3418); 1684 1685 /* enable the SMBus device */ 1686 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1687 } 1688 1689 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1690 { 1691 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1692 return; 1693 1694 iounmap(asus_rcba_base); 1695 asus_rcba_base = NULL; 1696 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1697 } 1698 1699 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1700 { 1701 asus_hides_smbus_lpc_ich6_suspend(dev); 1702 asus_hides_smbus_lpc_ich6_resume_early(dev); 1703 asus_hides_smbus_lpc_ich6_resume(dev); 1704 } 1705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1706 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1707 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1708 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1709 1710 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1711 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1712 { 1713 u8 val = 0; 1714 pci_read_config_byte(dev, 0x77, &val); 1715 if (val & 0x10) { 1716 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1717 pci_write_config_byte(dev, 0x77, val & ~0x10); 1718 } 1719 } 1720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1724 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1725 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1726 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1727 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1728 1729 /* 1730 * ... This is further complicated by the fact that some SiS96x south 1731 * bridges pretend to be 85C503/5513 instead. In that case see if we 1732 * spotted a compatible north bridge to make sure. 1733 * (pci_find_device() doesn't work yet) 1734 * 1735 * We can also enable the sis96x bit in the discovery register.. 1736 */ 1737 #define SIS_DETECT_REGISTER 0x40 1738 1739 static void quirk_sis_503(struct pci_dev *dev) 1740 { 1741 u8 reg; 1742 u16 devid; 1743 1744 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1745 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1746 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1747 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1748 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1749 return; 1750 } 1751 1752 /* 1753 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1754 * it has already been processed. (Depends on link order, which is 1755 * apparently not guaranteed) 1756 */ 1757 dev->device = devid; 1758 quirk_sis_96x_smbus(dev); 1759 } 1760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1761 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1762 1763 /* 1764 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1765 * and MC97 modem controller are disabled when a second PCI soundcard is 1766 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1767 * -- bjd 1768 */ 1769 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1770 { 1771 u8 val; 1772 int asus_hides_ac97 = 0; 1773 1774 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1775 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1776 asus_hides_ac97 = 1; 1777 } 1778 1779 if (!asus_hides_ac97) 1780 return; 1781 1782 pci_read_config_byte(dev, 0x50, &val); 1783 if (val & 0xc0) { 1784 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1785 pci_read_config_byte(dev, 0x50, &val); 1786 if (val & 0xc0) 1787 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1788 val); 1789 else 1790 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1791 } 1792 } 1793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1794 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1795 1796 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1797 1798 /* 1799 * If we are using libata we can drive this chip properly but must do this 1800 * early on to make the additional device appear during the PCI scanning. 1801 */ 1802 static void quirk_jmicron_ata(struct pci_dev *pdev) 1803 { 1804 u32 conf1, conf5, class; 1805 u8 hdr; 1806 1807 /* Only poke fn 0 */ 1808 if (PCI_FUNC(pdev->devfn)) 1809 return; 1810 1811 pci_read_config_dword(pdev, 0x40, &conf1); 1812 pci_read_config_dword(pdev, 0x80, &conf5); 1813 1814 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1815 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1816 1817 switch (pdev->device) { 1818 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1819 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1820 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1821 /* The controller should be in single function ahci mode */ 1822 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1823 break; 1824 1825 case PCI_DEVICE_ID_JMICRON_JMB365: 1826 case PCI_DEVICE_ID_JMICRON_JMB366: 1827 /* Redirect IDE second PATA port to the right spot */ 1828 conf5 |= (1 << 24); 1829 fallthrough; 1830 case PCI_DEVICE_ID_JMICRON_JMB361: 1831 case PCI_DEVICE_ID_JMICRON_JMB363: 1832 case PCI_DEVICE_ID_JMICRON_JMB369: 1833 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1834 /* Set the class codes correctly and then direct IDE 0 */ 1835 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1836 break; 1837 1838 case PCI_DEVICE_ID_JMICRON_JMB368: 1839 /* The controller should be in single function IDE mode */ 1840 conf1 |= 0x00C00000; /* Set 22, 23 */ 1841 break; 1842 } 1843 1844 pci_write_config_dword(pdev, 0x40, conf1); 1845 pci_write_config_dword(pdev, 0x80, conf5); 1846 1847 /* Update pdev accordingly */ 1848 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1849 pdev->hdr_type = hdr & 0x7f; 1850 pdev->multifunction = !!(hdr & 0x80); 1851 1852 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1853 pdev->class = class >> 8; 1854 } 1855 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1858 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1860 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1861 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1862 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1863 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1864 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1865 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1866 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1867 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1868 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1869 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1870 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1871 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1872 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1873 1874 #endif 1875 1876 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1877 { 1878 if (dev->multifunction) { 1879 device_disable_async_suspend(&dev->dev); 1880 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1881 } 1882 } 1883 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1884 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1887 1888 #ifdef CONFIG_X86_IO_APIC 1889 static void quirk_alder_ioapic(struct pci_dev *pdev) 1890 { 1891 int i; 1892 1893 if ((pdev->class >> 8) != 0xff00) 1894 return; 1895 1896 /* 1897 * The first BAR is the location of the IO-APIC... we must 1898 * not touch this (and it's already covered by the fixmap), so 1899 * forcibly insert it into the resource tree. 1900 */ 1901 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1902 insert_resource(&iomem_resource, &pdev->resource[0]); 1903 1904 /* 1905 * The next five BARs all seem to be rubbish, so just clean 1906 * them out. 1907 */ 1908 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1909 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1910 } 1911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1912 #endif 1913 1914 static void quirk_no_msi(struct pci_dev *dev) 1915 { 1916 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1917 dev->no_msi = 1; 1918 } 1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1922 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1923 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1925 1926 static void quirk_pcie_mch(struct pci_dev *pdev) 1927 { 1928 pdev->no_msi = 1; 1929 } 1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1932 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1933 1934 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1935 1936 /* 1937 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1938 * actually on the AMBA bus. These fake PCI devices can support SVA via 1939 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1940 * 1941 * Normally stalling must not be enabled for PCI devices, since it would 1942 * break the PCI requirement for free-flowing writes and may lead to 1943 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1944 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1945 * even when a "PCI" device turns out to be a regular old SoC device 1946 * dressed up as a RCiEP and normal rules don't apply. 1947 */ 1948 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1949 { 1950 struct property_entry properties[] = { 1951 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1952 {}, 1953 }; 1954 1955 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1956 return; 1957 1958 pdev->pasid_no_tlp = 1; 1959 1960 /* 1961 * Set the dma-can-stall property on ACPI platforms. Device tree 1962 * can set it directly. 1963 */ 1964 if (!pdev->dev.of_node && 1965 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1966 pci_warn(pdev, "could not add stall property"); 1967 } 1968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1974 1975 /* 1976 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1977 * together on certain PXH-based systems. 1978 */ 1979 static void quirk_pcie_pxh(struct pci_dev *dev) 1980 { 1981 dev->no_msi = 1; 1982 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1983 } 1984 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1985 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1986 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1987 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1988 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1989 1990 /* 1991 * Some Intel PCI Express chipsets have trouble with downstream device 1992 * power management. 1993 */ 1994 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1995 { 1996 pci_pm_d3hot_delay = 120; 1997 dev->no_d1d2 = 1; 1998 } 1999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2020 2021 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2022 { 2023 if (dev->d3hot_delay >= delay) 2024 return; 2025 2026 dev->d3hot_delay = delay; 2027 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2028 dev->d3hot_delay); 2029 } 2030 2031 static void quirk_radeon_pm(struct pci_dev *dev) 2032 { 2033 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2034 dev->subsystem_device == 0x00e2) 2035 quirk_d3hot_delay(dev, 20); 2036 } 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2038 2039 /* 2040 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2041 * reset is performed too soon after transition to D0, extend d3hot_delay 2042 * to previous effective default for all NVIDIA HDA controllers. 2043 */ 2044 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2045 { 2046 quirk_d3hot_delay(dev, 20); 2047 } 2048 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2049 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2050 quirk_nvidia_hda_pm); 2051 2052 /* 2053 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2054 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2055 * 2056 * The kernel attempts to transition these devices to D3cold, but that seems 2057 * to be ineffective on the platforms in question; the PCI device appears to 2058 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2059 * extended delay in order to succeed. 2060 */ 2061 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2062 { 2063 quirk_d3hot_delay(dev, 20); 2064 } 2065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2068 2069 #ifdef CONFIG_X86_IO_APIC 2070 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2071 { 2072 noioapicreroute = 1; 2073 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2074 2075 return 0; 2076 } 2077 2078 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2079 /* 2080 * Systems to exclude from boot interrupt reroute quirks 2081 */ 2082 { 2083 .callback = dmi_disable_ioapicreroute, 2084 .ident = "ASUSTek Computer INC. M2N-LR", 2085 .matches = { 2086 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2087 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2088 }, 2089 }, 2090 {} 2091 }; 2092 2093 /* 2094 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2095 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2096 * that a PCI device's interrupt handler is installed on the boot interrupt 2097 * line instead. 2098 */ 2099 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2100 { 2101 dmi_check_system(boot_interrupt_dmi_table); 2102 if (noioapicquirk || noioapicreroute) 2103 return; 2104 2105 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2106 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2107 dev->vendor, dev->device); 2108 } 2109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2117 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2118 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2119 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2120 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2121 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2122 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2123 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2124 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2125 2126 /* 2127 * On some chipsets we can disable the generation of legacy INTx boot 2128 * interrupts. 2129 */ 2130 2131 /* 2132 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2133 * 300641-004US, section 5.7.3. 2134 * 2135 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2136 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2137 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2138 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2139 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2140 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2141 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2142 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2143 * Core IO on Xeon Scalable, see Intel order no 610950. 2144 */ 2145 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2146 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2147 2148 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2149 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2150 2151 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2152 { 2153 u16 pci_config_word; 2154 u32 pci_config_dword; 2155 2156 if (noioapicquirk) 2157 return; 2158 2159 switch (dev->device) { 2160 case PCI_DEVICE_ID_INTEL_ESB_10: 2161 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2162 &pci_config_word); 2163 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2164 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2165 pci_config_word); 2166 break; 2167 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2168 case 0x0e28: /* Xeon E5/E7 V2 */ 2169 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2170 case 0x6f28: /* Xeon D-1500 */ 2171 case 0x2034: /* Xeon Scalable Family */ 2172 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2173 &pci_config_dword); 2174 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2175 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2176 pci_config_dword); 2177 break; 2178 default: 2179 return; 2180 } 2181 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2182 dev->vendor, dev->device); 2183 } 2184 /* 2185 * Device 29 Func 5 Device IDs of IO-APIC 2186 * containing ABAR—APIC1 Alternate Base Address Register 2187 */ 2188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2189 quirk_disable_intel_boot_interrupt); 2190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2191 quirk_disable_intel_boot_interrupt); 2192 2193 /* 2194 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2195 * containing Coherent Interface Protocol Interrupt Control 2196 * 2197 * Device IDs obtained from volume 2 datasheets of commented 2198 * families above. 2199 */ 2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2201 quirk_disable_intel_boot_interrupt); 2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2203 quirk_disable_intel_boot_interrupt); 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2205 quirk_disable_intel_boot_interrupt); 2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2207 quirk_disable_intel_boot_interrupt); 2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2209 quirk_disable_intel_boot_interrupt); 2210 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2211 quirk_disable_intel_boot_interrupt); 2212 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2213 quirk_disable_intel_boot_interrupt); 2214 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2215 quirk_disable_intel_boot_interrupt); 2216 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2217 quirk_disable_intel_boot_interrupt); 2218 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2219 quirk_disable_intel_boot_interrupt); 2220 2221 /* Disable boot interrupts on HT-1000 */ 2222 #define BC_HT1000_FEATURE_REG 0x64 2223 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2224 #define BC_HT1000_MAP_IDX 0xC00 2225 #define BC_HT1000_MAP_DATA 0xC01 2226 2227 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2228 { 2229 u32 pci_config_dword; 2230 u8 irq; 2231 2232 if (noioapicquirk) 2233 return; 2234 2235 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2236 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2237 BC_HT1000_PIC_REGS_ENABLE); 2238 2239 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2240 outb(irq, BC_HT1000_MAP_IDX); 2241 outb(0x00, BC_HT1000_MAP_DATA); 2242 } 2243 2244 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2245 2246 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2247 dev->vendor, dev->device); 2248 } 2249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2250 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2251 2252 /* Disable boot interrupts on AMD and ATI chipsets */ 2253 2254 /* 2255 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2256 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2257 * (due to an erratum). 2258 */ 2259 #define AMD_813X_MISC 0x40 2260 #define AMD_813X_NOIOAMODE (1<<0) 2261 #define AMD_813X_REV_B1 0x12 2262 #define AMD_813X_REV_B2 0x13 2263 2264 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2265 { 2266 u32 pci_config_dword; 2267 2268 if (noioapicquirk) 2269 return; 2270 if ((dev->revision == AMD_813X_REV_B1) || 2271 (dev->revision == AMD_813X_REV_B2)) 2272 return; 2273 2274 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2275 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2276 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2277 2278 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2279 dev->vendor, dev->device); 2280 } 2281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2282 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2284 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2285 2286 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2287 2288 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2289 { 2290 u16 pci_config_word; 2291 2292 if (noioapicquirk) 2293 return; 2294 2295 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2296 if (!pci_config_word) { 2297 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2298 dev->vendor, dev->device); 2299 return; 2300 } 2301 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2302 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2303 dev->vendor, dev->device); 2304 } 2305 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2306 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2307 #endif /* CONFIG_X86_IO_APIC */ 2308 2309 /* 2310 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2311 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2312 * Re-allocate the region if needed... 2313 */ 2314 static void quirk_tc86c001_ide(struct pci_dev *dev) 2315 { 2316 struct resource *r = &dev->resource[0]; 2317 2318 if (r->start & 0x8) { 2319 r->flags |= IORESOURCE_UNSET; 2320 r->start = 0; 2321 r->end = 0xf; 2322 } 2323 } 2324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2325 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2326 quirk_tc86c001_ide); 2327 2328 /* 2329 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2330 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2331 * being read correctly if bit 7 of the base address is set. 2332 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2333 * Re-allocate the regions to a 256-byte boundary if necessary. 2334 */ 2335 static void quirk_plx_pci9050(struct pci_dev *dev) 2336 { 2337 unsigned int bar; 2338 2339 /* Fixed in revision 2 (PCI 9052). */ 2340 if (dev->revision >= 2) 2341 return; 2342 for (bar = 0; bar <= 1; bar++) 2343 if (pci_resource_len(dev, bar) == 0x80 && 2344 (pci_resource_start(dev, bar) & 0x80)) { 2345 struct resource *r = &dev->resource[bar]; 2346 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2347 bar); 2348 r->flags |= IORESOURCE_UNSET; 2349 r->start = 0; 2350 r->end = 0xff; 2351 } 2352 } 2353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2354 quirk_plx_pci9050); 2355 /* 2356 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2357 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2358 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2359 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2360 * 2361 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2362 * driver. 2363 */ 2364 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2365 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2366 2367 static void quirk_netmos(struct pci_dev *dev) 2368 { 2369 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2370 unsigned int num_serial = dev->subsystem_device & 0xf; 2371 2372 /* 2373 * These Netmos parts are multiport serial devices with optional 2374 * parallel ports. Even when parallel ports are present, they 2375 * are identified as class SERIAL, which means the serial driver 2376 * will claim them. To prevent this, mark them as class OTHER. 2377 * These combo devices should be claimed by parport_serial. 2378 * 2379 * The subdevice ID is of the form 0x00PS, where <P> is the number 2380 * of parallel ports and <S> is the number of serial ports. 2381 */ 2382 switch (dev->device) { 2383 case PCI_DEVICE_ID_NETMOS_9835: 2384 /* Well, this rule doesn't hold for the following 9835 device */ 2385 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2386 dev->subsystem_device == 0x0299) 2387 return; 2388 fallthrough; 2389 case PCI_DEVICE_ID_NETMOS_9735: 2390 case PCI_DEVICE_ID_NETMOS_9745: 2391 case PCI_DEVICE_ID_NETMOS_9845: 2392 case PCI_DEVICE_ID_NETMOS_9855: 2393 if (num_parallel) { 2394 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2395 dev->device, num_parallel, num_serial); 2396 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2397 (dev->class & 0xff); 2398 } 2399 } 2400 } 2401 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2402 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2403 2404 static void quirk_e100_interrupt(struct pci_dev *dev) 2405 { 2406 u16 command, pmcsr; 2407 u8 __iomem *csr; 2408 u8 cmd_hi; 2409 2410 switch (dev->device) { 2411 /* PCI IDs taken from drivers/net/e100.c */ 2412 case 0x1029: 2413 case 0x1030 ... 0x1034: 2414 case 0x1038 ... 0x103E: 2415 case 0x1050 ... 0x1057: 2416 case 0x1059: 2417 case 0x1064 ... 0x106B: 2418 case 0x1091 ... 0x1095: 2419 case 0x1209: 2420 case 0x1229: 2421 case 0x2449: 2422 case 0x2459: 2423 case 0x245D: 2424 case 0x27DC: 2425 break; 2426 default: 2427 return; 2428 } 2429 2430 /* 2431 * Some firmware hands off the e100 with interrupts enabled, 2432 * which can cause a flood of interrupts if packets are 2433 * received before the driver attaches to the device. So 2434 * disable all e100 interrupts here. The driver will 2435 * re-enable them when it's ready. 2436 */ 2437 pci_read_config_word(dev, PCI_COMMAND, &command); 2438 2439 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2440 return; 2441 2442 /* 2443 * Check that the device is in the D0 power state. If it's not, 2444 * there is no point to look any further. 2445 */ 2446 if (dev->pm_cap) { 2447 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2448 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2449 return; 2450 } 2451 2452 /* Convert from PCI bus to resource space. */ 2453 csr = ioremap(pci_resource_start(dev, 0), 8); 2454 if (!csr) { 2455 pci_warn(dev, "Can't map e100 registers\n"); 2456 return; 2457 } 2458 2459 cmd_hi = readb(csr + 3); 2460 if (cmd_hi == 0) { 2461 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2462 writeb(1, csr + 3); 2463 } 2464 2465 iounmap(csr); 2466 } 2467 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2468 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2469 2470 /* 2471 * The 82575 and 82598 may experience data corruption issues when transitioning 2472 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2473 */ 2474 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2475 { 2476 pci_info(dev, "Disabling L0s\n"); 2477 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2478 } 2479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2489 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2493 2494 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2495 { 2496 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2497 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2498 } 2499 2500 /* 2501 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2502 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2503 * disable both L0s and L1 for now to be safe. 2504 */ 2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2506 2507 /* 2508 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2509 * Link bit cleared after starting the link retrain process to allow this 2510 * process to finish. 2511 * 2512 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2513 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2514 */ 2515 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2516 { 2517 dev->clear_retrain_link = 1; 2518 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2519 } 2520 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2521 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2522 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2523 2524 static void fixup_rev1_53c810(struct pci_dev *dev) 2525 { 2526 u32 class = dev->class; 2527 2528 /* 2529 * rev 1 ncr53c810 chips don't set the class at all which means 2530 * they don't get their resources remapped. Fix that here. 2531 */ 2532 if (class) 2533 return; 2534 2535 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2536 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2537 class, dev->class); 2538 } 2539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2540 2541 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2542 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2543 { 2544 u16 en1k; 2545 2546 pci_read_config_word(dev, 0x40, &en1k); 2547 2548 if (en1k & 0x200) { 2549 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2550 dev->io_window_1k = 1; 2551 } 2552 } 2553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2554 2555 /* 2556 * Under some circumstances, AER is not linked with extended capabilities. 2557 * Force it to be linked by setting the corresponding control bit in the 2558 * config space. 2559 */ 2560 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2561 { 2562 uint8_t b; 2563 2564 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2565 if (!(b & 0x20)) { 2566 pci_write_config_byte(dev, 0xf41, b | 0x20); 2567 pci_info(dev, "Linking AER extended capability\n"); 2568 } 2569 } 2570 } 2571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2572 quirk_nvidia_ck804_pcie_aer_ext_cap); 2573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2574 quirk_nvidia_ck804_pcie_aer_ext_cap); 2575 2576 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2577 { 2578 /* 2579 * Disable PCI Bus Parking and PCI Master read caching on CX700 2580 * which causes unspecified timing errors with a VT6212L on the PCI 2581 * bus leading to USB2.0 packet loss. 2582 * 2583 * This quirk is only enabled if a second (on the external PCI bus) 2584 * VT6212L is found -- the CX700 core itself also contains a USB 2585 * host controller with the same PCI ID as the VT6212L. 2586 */ 2587 2588 /* Count VT6212L instances */ 2589 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2590 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2591 uint8_t b; 2592 2593 /* 2594 * p should contain the first (internal) VT6212L -- see if we have 2595 * an external one by searching again. 2596 */ 2597 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2598 if (!p) 2599 return; 2600 pci_dev_put(p); 2601 2602 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2603 if (b & 0x40) { 2604 /* Turn off PCI Bus Parking */ 2605 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2606 2607 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2608 } 2609 } 2610 2611 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2612 if (b != 0) { 2613 /* Turn off PCI Master read caching */ 2614 pci_write_config_byte(dev, 0x72, 0x0); 2615 2616 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2617 pci_write_config_byte(dev, 0x75, 0x1); 2618 2619 /* Disable "Read FIFO Timer" */ 2620 pci_write_config_byte(dev, 0x77, 0x0); 2621 2622 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2623 } 2624 } 2625 } 2626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2627 2628 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2629 { 2630 u32 rev; 2631 2632 pci_read_config_dword(dev, 0xf4, &rev); 2633 2634 /* Only CAP the MRRS if the device is a 5719 A0 */ 2635 if (rev == 0x05719000) { 2636 int readrq = pcie_get_readrq(dev); 2637 if (readrq > 2048) 2638 pcie_set_readrq(dev, 2048); 2639 } 2640 } 2641 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2642 PCI_DEVICE_ID_TIGON3_5719, 2643 quirk_brcm_5719_limit_mrrs); 2644 2645 /* 2646 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2647 * hide device 6 which configures the overflow device access containing the 2648 * DRBs - this is where we expose device 6. 2649 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2650 */ 2651 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2652 { 2653 u8 reg; 2654 2655 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2656 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2657 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2658 } 2659 } 2660 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2661 quirk_unhide_mch_dev6); 2662 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2663 quirk_unhide_mch_dev6); 2664 2665 #ifdef CONFIG_PCI_MSI 2666 /* 2667 * Some chipsets do not support MSI. We cannot easily rely on setting 2668 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2669 * other buses controlled by the chipset even if Linux is not aware of it. 2670 * Instead of setting the flag on all buses in the machine, simply disable 2671 * MSI globally. 2672 */ 2673 static void quirk_disable_all_msi(struct pci_dev *dev) 2674 { 2675 pci_no_msi(); 2676 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2677 } 2678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2687 2688 /* Disable MSI on chipsets that are known to not support it */ 2689 static void quirk_disable_msi(struct pci_dev *dev) 2690 { 2691 if (dev->subordinate) { 2692 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2693 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2694 } 2695 } 2696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2699 2700 /* 2701 * The APC bridge device in AMD 780 family northbridges has some random 2702 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2703 * we use the possible vendor/device IDs of the host bridge for the 2704 * declared quirk, and search for the APC bridge by slot number. 2705 */ 2706 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2707 { 2708 struct pci_dev *apc_bridge; 2709 2710 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2711 if (apc_bridge) { 2712 if (apc_bridge->device == 0x9602) 2713 quirk_disable_msi(apc_bridge); 2714 pci_dev_put(apc_bridge); 2715 } 2716 } 2717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2719 2720 /* 2721 * Go through the list of HyperTransport capabilities and return 1 if a HT 2722 * MSI capability is found and enabled. 2723 */ 2724 static int msi_ht_cap_enabled(struct pci_dev *dev) 2725 { 2726 int pos, ttl = PCI_FIND_CAP_TTL; 2727 2728 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2729 while (pos && ttl--) { 2730 u8 flags; 2731 2732 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2733 &flags) == 0) { 2734 pci_info(dev, "Found %s HT MSI Mapping\n", 2735 flags & HT_MSI_FLAGS_ENABLE ? 2736 "enabled" : "disabled"); 2737 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2738 } 2739 2740 pos = pci_find_next_ht_capability(dev, pos, 2741 HT_CAPTYPE_MSI_MAPPING); 2742 } 2743 return 0; 2744 } 2745 2746 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2747 static void quirk_msi_ht_cap(struct pci_dev *dev) 2748 { 2749 if (!msi_ht_cap_enabled(dev)) 2750 quirk_disable_msi(dev); 2751 } 2752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2753 quirk_msi_ht_cap); 2754 2755 /* 2756 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2757 * if the MSI capability is set in any of these mappings. 2758 */ 2759 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2760 { 2761 struct pci_dev *pdev; 2762 2763 /* 2764 * Check HT MSI cap on this chipset and the root one. A single one 2765 * having MSI is enough to be sure that MSI is supported. 2766 */ 2767 pdev = pci_get_slot(dev->bus, 0); 2768 if (!pdev) 2769 return; 2770 if (!msi_ht_cap_enabled(pdev)) 2771 quirk_msi_ht_cap(dev); 2772 pci_dev_put(pdev); 2773 } 2774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2775 quirk_nvidia_ck804_msi_ht_cap); 2776 2777 /* Force enable MSI mapping capability on HT bridges */ 2778 static void ht_enable_msi_mapping(struct pci_dev *dev) 2779 { 2780 int pos, ttl = PCI_FIND_CAP_TTL; 2781 2782 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2783 while (pos && ttl--) { 2784 u8 flags; 2785 2786 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2787 &flags) == 0) { 2788 pci_info(dev, "Enabling HT MSI Mapping\n"); 2789 2790 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2791 flags | HT_MSI_FLAGS_ENABLE); 2792 } 2793 pos = pci_find_next_ht_capability(dev, pos, 2794 HT_CAPTYPE_MSI_MAPPING); 2795 } 2796 } 2797 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2798 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2799 ht_enable_msi_mapping); 2800 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2801 ht_enable_msi_mapping); 2802 2803 /* 2804 * The P5N32-SLI motherboards from Asus have a problem with MSI 2805 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2806 * also affects other devices. As for now, turn off MSI for this device. 2807 */ 2808 static void nvenet_msi_disable(struct pci_dev *dev) 2809 { 2810 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2811 2812 if (board_name && 2813 (strstr(board_name, "P5N32-SLI PREMIUM") || 2814 strstr(board_name, "P5N32-E SLI"))) { 2815 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2816 dev->no_msi = 1; 2817 } 2818 } 2819 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2820 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2821 nvenet_msi_disable); 2822 2823 /* 2824 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2825 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2826 * interrupts for PME and AER events; instead only INTx interrupts are 2827 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2828 * for other events, since PCIe specification doesn't support using a mix of 2829 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2830 * service drivers registering their respective ISRs for MSIs. 2831 */ 2832 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2833 { 2834 dev->no_msi = 1; 2835 } 2836 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2837 PCI_CLASS_BRIDGE_PCI, 8, 2838 pci_quirk_nvidia_tegra_disable_rp_msi); 2839 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2840 PCI_CLASS_BRIDGE_PCI, 8, 2841 pci_quirk_nvidia_tegra_disable_rp_msi); 2842 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2843 PCI_CLASS_BRIDGE_PCI, 8, 2844 pci_quirk_nvidia_tegra_disable_rp_msi); 2845 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2846 PCI_CLASS_BRIDGE_PCI, 8, 2847 pci_quirk_nvidia_tegra_disable_rp_msi); 2848 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2849 PCI_CLASS_BRIDGE_PCI, 8, 2850 pci_quirk_nvidia_tegra_disable_rp_msi); 2851 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2852 PCI_CLASS_BRIDGE_PCI, 8, 2853 pci_quirk_nvidia_tegra_disable_rp_msi); 2854 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2855 PCI_CLASS_BRIDGE_PCI, 8, 2856 pci_quirk_nvidia_tegra_disable_rp_msi); 2857 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2858 PCI_CLASS_BRIDGE_PCI, 8, 2859 pci_quirk_nvidia_tegra_disable_rp_msi); 2860 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2861 PCI_CLASS_BRIDGE_PCI, 8, 2862 pci_quirk_nvidia_tegra_disable_rp_msi); 2863 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2864 PCI_CLASS_BRIDGE_PCI, 8, 2865 pci_quirk_nvidia_tegra_disable_rp_msi); 2866 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2867 PCI_CLASS_BRIDGE_PCI, 8, 2868 pci_quirk_nvidia_tegra_disable_rp_msi); 2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2870 PCI_CLASS_BRIDGE_PCI, 8, 2871 pci_quirk_nvidia_tegra_disable_rp_msi); 2872 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2873 PCI_CLASS_BRIDGE_PCI, 8, 2874 pci_quirk_nvidia_tegra_disable_rp_msi); 2875 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2876 PCI_CLASS_BRIDGE_PCI, 8, 2877 pci_quirk_nvidia_tegra_disable_rp_msi); 2878 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2879 PCI_CLASS_BRIDGE_PCI, 8, 2880 pci_quirk_nvidia_tegra_disable_rp_msi); 2881 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2882 PCI_CLASS_BRIDGE_PCI, 8, 2883 pci_quirk_nvidia_tegra_disable_rp_msi); 2884 2885 /* 2886 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2887 * config register. This register controls the routing of legacy 2888 * interrupts from devices that route through the MCP55. If this register 2889 * is misprogrammed, interrupts are only sent to the BSP, unlike 2890 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2891 * having this register set properly prevents kdump from booting up 2892 * properly, so let's make sure that we have it set correctly. 2893 * Note that this is an undocumented register. 2894 */ 2895 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2896 { 2897 u32 cfg; 2898 2899 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2900 return; 2901 2902 pci_read_config_dword(dev, 0x74, &cfg); 2903 2904 if (cfg & ((1 << 2) | (1 << 15))) { 2905 pr_info("Rewriting IRQ routing register on MCP55\n"); 2906 cfg &= ~((1 << 2) | (1 << 15)); 2907 pci_write_config_dword(dev, 0x74, cfg); 2908 } 2909 } 2910 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2911 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2912 nvbridge_check_legacy_irq_routing); 2913 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2914 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2915 nvbridge_check_legacy_irq_routing); 2916 2917 static int ht_check_msi_mapping(struct pci_dev *dev) 2918 { 2919 int pos, ttl = PCI_FIND_CAP_TTL; 2920 int found = 0; 2921 2922 /* Check if there is HT MSI cap or enabled on this device */ 2923 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2924 while (pos && ttl--) { 2925 u8 flags; 2926 2927 if (found < 1) 2928 found = 1; 2929 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2930 &flags) == 0) { 2931 if (flags & HT_MSI_FLAGS_ENABLE) { 2932 if (found < 2) { 2933 found = 2; 2934 break; 2935 } 2936 } 2937 } 2938 pos = pci_find_next_ht_capability(dev, pos, 2939 HT_CAPTYPE_MSI_MAPPING); 2940 } 2941 2942 return found; 2943 } 2944 2945 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2946 { 2947 struct pci_dev *dev; 2948 int pos; 2949 int i, dev_no; 2950 int found = 0; 2951 2952 dev_no = host_bridge->devfn >> 3; 2953 for (i = dev_no + 1; i < 0x20; i++) { 2954 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2955 if (!dev) 2956 continue; 2957 2958 /* found next host bridge? */ 2959 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2960 if (pos != 0) { 2961 pci_dev_put(dev); 2962 break; 2963 } 2964 2965 if (ht_check_msi_mapping(dev)) { 2966 found = 1; 2967 pci_dev_put(dev); 2968 break; 2969 } 2970 pci_dev_put(dev); 2971 } 2972 2973 return found; 2974 } 2975 2976 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2977 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2978 2979 static int is_end_of_ht_chain(struct pci_dev *dev) 2980 { 2981 int pos, ctrl_off; 2982 int end = 0; 2983 u16 flags, ctrl; 2984 2985 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2986 2987 if (!pos) 2988 goto out; 2989 2990 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2991 2992 ctrl_off = ((flags >> 10) & 1) ? 2993 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2994 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2995 2996 if (ctrl & (1 << 6)) 2997 end = 1; 2998 2999 out: 3000 return end; 3001 } 3002 3003 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3004 { 3005 struct pci_dev *host_bridge; 3006 int pos; 3007 int i, dev_no; 3008 int found = 0; 3009 3010 dev_no = dev->devfn >> 3; 3011 for (i = dev_no; i >= 0; i--) { 3012 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3013 if (!host_bridge) 3014 continue; 3015 3016 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3017 if (pos != 0) { 3018 found = 1; 3019 break; 3020 } 3021 pci_dev_put(host_bridge); 3022 } 3023 3024 if (!found) 3025 return; 3026 3027 /* don't enable end_device/host_bridge with leaf directly here */ 3028 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3029 host_bridge_with_leaf(host_bridge)) 3030 goto out; 3031 3032 /* root did that ! */ 3033 if (msi_ht_cap_enabled(host_bridge)) 3034 goto out; 3035 3036 ht_enable_msi_mapping(dev); 3037 3038 out: 3039 pci_dev_put(host_bridge); 3040 } 3041 3042 static void ht_disable_msi_mapping(struct pci_dev *dev) 3043 { 3044 int pos, ttl = PCI_FIND_CAP_TTL; 3045 3046 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3047 while (pos && ttl--) { 3048 u8 flags; 3049 3050 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3051 &flags) == 0) { 3052 pci_info(dev, "Disabling HT MSI Mapping\n"); 3053 3054 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3055 flags & ~HT_MSI_FLAGS_ENABLE); 3056 } 3057 pos = pci_find_next_ht_capability(dev, pos, 3058 HT_CAPTYPE_MSI_MAPPING); 3059 } 3060 } 3061 3062 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3063 { 3064 struct pci_dev *host_bridge; 3065 int pos; 3066 int found; 3067 3068 if (!pci_msi_enabled()) 3069 return; 3070 3071 /* check if there is HT MSI cap or enabled on this device */ 3072 found = ht_check_msi_mapping(dev); 3073 3074 /* no HT MSI CAP */ 3075 if (found == 0) 3076 return; 3077 3078 /* 3079 * HT MSI mapping should be disabled on devices that are below 3080 * a non-HyperTransport host bridge. Locate the host bridge. 3081 */ 3082 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3083 PCI_DEVFN(0, 0)); 3084 if (host_bridge == NULL) { 3085 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3086 return; 3087 } 3088 3089 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3090 if (pos != 0) { 3091 /* Host bridge is to HT */ 3092 if (found == 1) { 3093 /* it is not enabled, try to enable it */ 3094 if (all) 3095 ht_enable_msi_mapping(dev); 3096 else 3097 nv_ht_enable_msi_mapping(dev); 3098 } 3099 goto out; 3100 } 3101 3102 /* HT MSI is not enabled */ 3103 if (found == 1) 3104 goto out; 3105 3106 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3107 ht_disable_msi_mapping(dev); 3108 3109 out: 3110 pci_dev_put(host_bridge); 3111 } 3112 3113 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3114 { 3115 return __nv_msi_ht_cap_quirk(dev, 1); 3116 } 3117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3119 3120 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3121 { 3122 return __nv_msi_ht_cap_quirk(dev, 0); 3123 } 3124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3125 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3126 3127 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3128 { 3129 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3130 } 3131 3132 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3133 { 3134 struct pci_dev *p; 3135 3136 /* 3137 * SB700 MSI issue will be fixed at HW level from revision A21; 3138 * we need check PCI REVISION ID of SMBus controller to get SB700 3139 * revision. 3140 */ 3141 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3142 NULL); 3143 if (!p) 3144 return; 3145 3146 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3147 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3148 pci_dev_put(p); 3149 } 3150 3151 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3152 { 3153 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3154 if (dev->revision < 0x18) { 3155 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3156 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3157 } 3158 } 3159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3160 PCI_DEVICE_ID_TIGON3_5780, 3161 quirk_msi_intx_disable_bug); 3162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3163 PCI_DEVICE_ID_TIGON3_5780S, 3164 quirk_msi_intx_disable_bug); 3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3166 PCI_DEVICE_ID_TIGON3_5714, 3167 quirk_msi_intx_disable_bug); 3168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3169 PCI_DEVICE_ID_TIGON3_5714S, 3170 quirk_msi_intx_disable_bug); 3171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3172 PCI_DEVICE_ID_TIGON3_5715, 3173 quirk_msi_intx_disable_bug); 3174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3175 PCI_DEVICE_ID_TIGON3_5715S, 3176 quirk_msi_intx_disable_bug); 3177 3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3179 quirk_msi_intx_disable_ati_bug); 3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3181 quirk_msi_intx_disable_ati_bug); 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3183 quirk_msi_intx_disable_ati_bug); 3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3185 quirk_msi_intx_disable_ati_bug); 3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3187 quirk_msi_intx_disable_ati_bug); 3188 3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3190 quirk_msi_intx_disable_bug); 3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3192 quirk_msi_intx_disable_bug); 3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3194 quirk_msi_intx_disable_bug); 3195 3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3197 quirk_msi_intx_disable_bug); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3199 quirk_msi_intx_disable_bug); 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3201 quirk_msi_intx_disable_bug); 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3203 quirk_msi_intx_disable_bug); 3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3205 quirk_msi_intx_disable_bug); 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3207 quirk_msi_intx_disable_bug); 3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3209 quirk_msi_intx_disable_qca_bug); 3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3211 quirk_msi_intx_disable_qca_bug); 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3213 quirk_msi_intx_disable_qca_bug); 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3215 quirk_msi_intx_disable_qca_bug); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3217 quirk_msi_intx_disable_qca_bug); 3218 3219 /* 3220 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3221 * should be disabled on platforms where the device (mistakenly) advertises it. 3222 * 3223 * Notice that this quirk also disables MSI (which may work, but hasn't been 3224 * tested), since currently there is no standard way to disable only MSI-X. 3225 * 3226 * The 0031 device id is reused for other non Root Port device types, 3227 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3228 */ 3229 static void quirk_al_msi_disable(struct pci_dev *dev) 3230 { 3231 dev->no_msi = 1; 3232 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3233 } 3234 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3235 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3236 #endif /* CONFIG_PCI_MSI */ 3237 3238 /* 3239 * Allow manual resource allocation for PCI hotplug bridges via 3240 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3241 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3242 * allocate resources when hotplug device is inserted and PCI bus is 3243 * rescanned. 3244 */ 3245 static void quirk_hotplug_bridge(struct pci_dev *dev) 3246 { 3247 dev->is_hotplug_bridge = 1; 3248 } 3249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3250 3251 /* 3252 * This is a quirk for the Ricoh MMC controller found as a part of some 3253 * multifunction chips. 3254 * 3255 * This is very similar and based on the ricoh_mmc driver written by 3256 * Philip Langdale. Thank you for these magic sequences. 3257 * 3258 * These chips implement the four main memory card controllers (SD, MMC, 3259 * MS, xD) and one or both of CardBus or FireWire. 3260 * 3261 * It happens that they implement SD and MMC support as separate 3262 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3263 * cards but the chip detects MMC cards in hardware and directs them to the 3264 * MMC controller - so the SDHCI driver never sees them. 3265 * 3266 * To get around this, we must disable the useless MMC controller. At that 3267 * point, the SDHCI controller will start seeing them. It seems to be the 3268 * case that the relevant PCI registers to deactivate the MMC controller 3269 * live on PCI function 0, which might be the CardBus controller or the 3270 * FireWire controller, depending on the particular chip in question 3271 * 3272 * This has to be done early, because as soon as we disable the MMC controller 3273 * other PCI functions shift up one level, e.g. function #2 becomes function 3274 * #1, and this will confuse the PCI core. 3275 */ 3276 #ifdef CONFIG_MMC_RICOH_MMC 3277 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3278 { 3279 u8 write_enable; 3280 u8 write_target; 3281 u8 disable; 3282 3283 /* 3284 * Disable via CardBus interface 3285 * 3286 * This must be done via function #0 3287 */ 3288 if (PCI_FUNC(dev->devfn)) 3289 return; 3290 3291 pci_read_config_byte(dev, 0xB7, &disable); 3292 if (disable & 0x02) 3293 return; 3294 3295 pci_read_config_byte(dev, 0x8E, &write_enable); 3296 pci_write_config_byte(dev, 0x8E, 0xAA); 3297 pci_read_config_byte(dev, 0x8D, &write_target); 3298 pci_write_config_byte(dev, 0x8D, 0xB7); 3299 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3300 pci_write_config_byte(dev, 0x8E, write_enable); 3301 pci_write_config_byte(dev, 0x8D, write_target); 3302 3303 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3304 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3305 } 3306 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3308 3309 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3310 { 3311 u8 write_enable; 3312 u8 disable; 3313 3314 /* 3315 * Disable via FireWire interface 3316 * 3317 * This must be done via function #0 3318 */ 3319 if (PCI_FUNC(dev->devfn)) 3320 return; 3321 /* 3322 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3323 * certain types of SD/MMC cards. Lowering the SD base clock 3324 * frequency from 200Mhz to 50Mhz fixes this issue. 3325 * 3326 * 0x150 - SD2.0 mode enable for changing base clock 3327 * frequency to 50Mhz 3328 * 0xe1 - Base clock frequency 3329 * 0x32 - 50Mhz new clock frequency 3330 * 0xf9 - Key register for 0x150 3331 * 0xfc - key register for 0xe1 3332 */ 3333 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3334 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3335 pci_write_config_byte(dev, 0xf9, 0xfc); 3336 pci_write_config_byte(dev, 0x150, 0x10); 3337 pci_write_config_byte(dev, 0xf9, 0x00); 3338 pci_write_config_byte(dev, 0xfc, 0x01); 3339 pci_write_config_byte(dev, 0xe1, 0x32); 3340 pci_write_config_byte(dev, 0xfc, 0x00); 3341 3342 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3343 } 3344 3345 pci_read_config_byte(dev, 0xCB, &disable); 3346 3347 if (disable & 0x02) 3348 return; 3349 3350 pci_read_config_byte(dev, 0xCA, &write_enable); 3351 pci_write_config_byte(dev, 0xCA, 0x57); 3352 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3353 pci_write_config_byte(dev, 0xCA, write_enable); 3354 3355 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3356 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3357 3358 } 3359 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3360 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3361 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3362 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3363 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3364 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3365 #endif /*CONFIG_MMC_RICOH_MMC*/ 3366 3367 #ifdef CONFIG_DMAR_TABLE 3368 #define VTUNCERRMSK_REG 0x1ac 3369 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3370 /* 3371 * This is a quirk for masking VT-d spec-defined errors to platform error 3372 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3373 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3374 * on the RAS config settings of the platform) when a VT-d fault happens. 3375 * The resulting SMI caused the system to hang. 3376 * 3377 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3378 * need to report the same error through other channels. 3379 */ 3380 static void vtd_mask_spec_errors(struct pci_dev *dev) 3381 { 3382 u32 word; 3383 3384 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3385 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3386 } 3387 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3388 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3389 #endif 3390 3391 static void fixup_ti816x_class(struct pci_dev *dev) 3392 { 3393 u32 class = dev->class; 3394 3395 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3396 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3397 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3398 class, dev->class); 3399 } 3400 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3401 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3402 3403 /* 3404 * Some PCIe devices do not work reliably with the claimed maximum 3405 * payload size supported. 3406 */ 3407 static void fixup_mpss_256(struct pci_dev *dev) 3408 { 3409 dev->pcie_mpss = 1; /* 256 bytes */ 3410 } 3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3412 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3413 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3414 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3415 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3416 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3417 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3418 3419 /* 3420 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3421 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3422 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3423 * until all of the devices are discovered and buses walked, read completion 3424 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3425 * it is possible to hotplug a device with MPS of 256B. 3426 */ 3427 static void quirk_intel_mc_errata(struct pci_dev *dev) 3428 { 3429 int err; 3430 u16 rcc; 3431 3432 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3433 pcie_bus_config == PCIE_BUS_DEFAULT) 3434 return; 3435 3436 /* 3437 * Intel erratum specifies bits to change but does not say what 3438 * they are. Keeping them magical until such time as the registers 3439 * and values can be explained. 3440 */ 3441 err = pci_read_config_word(dev, 0x48, &rcc); 3442 if (err) { 3443 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3444 return; 3445 } 3446 3447 if (!(rcc & (1 << 10))) 3448 return; 3449 3450 rcc &= ~(1 << 10); 3451 3452 err = pci_write_config_word(dev, 0x48, rcc); 3453 if (err) { 3454 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3455 return; 3456 } 3457 3458 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3459 } 3460 /* Intel 5000 series memory controllers and ports 2-7 */ 3461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3475 /* Intel 5100 series memory controllers and ports 2-7 */ 3476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3487 3488 /* 3489 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3490 * To work around this, query the size it should be configured to by the 3491 * device and modify the resource end to correspond to this new size. 3492 */ 3493 static void quirk_intel_ntb(struct pci_dev *dev) 3494 { 3495 int rc; 3496 u8 val; 3497 3498 rc = pci_read_config_byte(dev, 0x00D0, &val); 3499 if (rc) 3500 return; 3501 3502 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3503 3504 rc = pci_read_config_byte(dev, 0x00D1, &val); 3505 if (rc) 3506 return; 3507 3508 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3509 } 3510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3512 3513 /* 3514 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3515 * though no one is handling them (e.g., if the i915 driver is never 3516 * loaded). Additionally the interrupt destination is not set up properly 3517 * and the interrupt ends up -somewhere-. 3518 * 3519 * These spurious interrupts are "sticky" and the kernel disables the 3520 * (shared) interrupt line after 100,000+ generated interrupts. 3521 * 3522 * Fix it by disabling the still enabled interrupts. This resolves crashes 3523 * often seen on monitor unplug. 3524 */ 3525 #define I915_DEIER_REG 0x4400c 3526 static void disable_igfx_irq(struct pci_dev *dev) 3527 { 3528 void __iomem *regs = pci_iomap(dev, 0, 0); 3529 if (regs == NULL) { 3530 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3531 return; 3532 } 3533 3534 /* Check if any interrupt line is still enabled */ 3535 if (readl(regs + I915_DEIER_REG) != 0) { 3536 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3537 3538 writel(0, regs + I915_DEIER_REG); 3539 } 3540 3541 pci_iounmap(dev, regs); 3542 } 3543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3550 3551 /* 3552 * PCI devices which are on Intel chips can skip the 10ms delay 3553 * before entering D3 mode. 3554 */ 3555 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3556 { 3557 dev->d3hot_delay = 0; 3558 } 3559 /* C600 Series devices do not need 10ms d3hot_delay */ 3560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3563 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3575 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3585 3586 /* 3587 * Some devices may pass our check in pci_intx_mask_supported() if 3588 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3589 * support this feature. 3590 */ 3591 static void quirk_broken_intx_masking(struct pci_dev *dev) 3592 { 3593 dev->broken_intx_masking = 1; 3594 } 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3596 quirk_broken_intx_masking); 3597 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3598 quirk_broken_intx_masking); 3599 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3600 quirk_broken_intx_masking); 3601 3602 /* 3603 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3604 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3605 * 3606 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3607 */ 3608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3609 quirk_broken_intx_masking); 3610 3611 /* 3612 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3613 * DisINTx can be set but the interrupt status bit is non-functional. 3614 */ 3615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3631 3632 static u16 mellanox_broken_intx_devs[] = { 3633 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3634 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3635 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3636 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3637 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3638 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3639 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3640 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3641 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3642 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3643 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3644 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3645 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3646 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3647 }; 3648 3649 #define CONNECTX_4_CURR_MAX_MINOR 99 3650 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3651 3652 /* 3653 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3654 * If so, don't mark it as broken. 3655 * FW minor > 99 means older FW version format and no INTx masking support. 3656 * FW minor < 14 means new FW version format and no INTx masking support. 3657 */ 3658 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3659 { 3660 __be32 __iomem *fw_ver; 3661 u16 fw_major; 3662 u16 fw_minor; 3663 u16 fw_subminor; 3664 u32 fw_maj_min; 3665 u32 fw_sub_min; 3666 int i; 3667 3668 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3669 if (pdev->device == mellanox_broken_intx_devs[i]) { 3670 pdev->broken_intx_masking = 1; 3671 return; 3672 } 3673 } 3674 3675 /* 3676 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3677 * support so shouldn't be checked further 3678 */ 3679 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3680 return; 3681 3682 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3683 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3684 return; 3685 3686 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3687 if (pci_enable_device_mem(pdev)) { 3688 pci_warn(pdev, "Can't enable device memory\n"); 3689 return; 3690 } 3691 3692 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3693 if (!fw_ver) { 3694 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3695 goto out; 3696 } 3697 3698 /* Reading from resource space should be 32b aligned */ 3699 fw_maj_min = ioread32be(fw_ver); 3700 fw_sub_min = ioread32be(fw_ver + 1); 3701 fw_major = fw_maj_min & 0xffff; 3702 fw_minor = fw_maj_min >> 16; 3703 fw_subminor = fw_sub_min & 0xffff; 3704 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3705 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3706 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3707 fw_major, fw_minor, fw_subminor, pdev->device == 3708 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3709 pdev->broken_intx_masking = 1; 3710 } 3711 3712 iounmap(fw_ver); 3713 3714 out: 3715 pci_disable_device(pdev); 3716 } 3717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3718 mellanox_check_broken_intx_masking); 3719 3720 static void quirk_no_bus_reset(struct pci_dev *dev) 3721 { 3722 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3723 } 3724 3725 /* 3726 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3727 * prevented for those affected devices. 3728 */ 3729 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3730 { 3731 if ((dev->device & 0xffc0) == 0x2340) 3732 quirk_no_bus_reset(dev); 3733 } 3734 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3735 quirk_nvidia_no_bus_reset); 3736 3737 /* 3738 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3739 * The device will throw a Link Down error on AER-capable systems and 3740 * regardless of AER, config space of the device is never accessible again 3741 * and typically causes the system to hang or reset when access is attempted. 3742 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3743 */ 3744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3750 3751 /* 3752 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3753 * reset when used with certain child devices. After the reset, config 3754 * accesses to the child may fail. 3755 */ 3756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3757 3758 /* 3759 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3760 * automatically disables LTSSM when Secondary Bus Reset is received and 3761 * the device stops working. Prevent bus reset for these devices. With 3762 * this change, the device can be assigned to VMs with VFIO, but it will 3763 * leak state between VMs. Reference 3764 * https://e2e.ti.com/support/processors/f/791/t/954382 3765 */ 3766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3767 3768 static void quirk_no_pm_reset(struct pci_dev *dev) 3769 { 3770 /* 3771 * We can't do a bus reset on root bus devices, but an ineffective 3772 * PM reset may be better than nothing. 3773 */ 3774 if (!pci_is_root_bus(dev->bus)) 3775 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3776 } 3777 3778 /* 3779 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3780 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3781 * to have no effect on the device: it retains the framebuffer contents and 3782 * monitor sync. Advertising this support makes other layers, like VFIO, 3783 * assume pci_reset_function() is viable for this device. Mark it as 3784 * unavailable to skip it when testing reset methods. 3785 */ 3786 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3787 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3788 3789 /* 3790 * Thunderbolt controllers with broken MSI hotplug signaling: 3791 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3792 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3793 */ 3794 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3795 { 3796 if (pdev->is_hotplug_bridge && 3797 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3798 pdev->revision <= 1)) 3799 pdev->no_msi = 1; 3800 } 3801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3802 quirk_thunderbolt_hotplug_msi); 3803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3804 quirk_thunderbolt_hotplug_msi); 3805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3806 quirk_thunderbolt_hotplug_msi); 3807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3808 quirk_thunderbolt_hotplug_msi); 3809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3810 quirk_thunderbolt_hotplug_msi); 3811 3812 #ifdef CONFIG_ACPI 3813 /* 3814 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3815 * 3816 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3817 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3818 * be present after resume if a device was plugged in before suspend. 3819 * 3820 * The Thunderbolt controller consists of a PCIe switch with downstream 3821 * bridges leading to the NHI and to the tunnel PCI bridges. 3822 * 3823 * This quirk cuts power to the whole chip. Therefore we have to apply it 3824 * during suspend_noirq of the upstream bridge. 3825 * 3826 * Power is automagically restored before resume. No action is needed. 3827 */ 3828 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3829 { 3830 acpi_handle bridge, SXIO, SXFP, SXLV; 3831 3832 if (!x86_apple_machine) 3833 return; 3834 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3835 return; 3836 3837 /* 3838 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3839 * We don't know how to turn it back on again, but firmware does, 3840 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3841 * firmware. 3842 */ 3843 if (!pm_suspend_via_firmware()) 3844 return; 3845 3846 bridge = ACPI_HANDLE(&dev->dev); 3847 if (!bridge) 3848 return; 3849 3850 /* 3851 * SXIO and SXLV are present only on machines requiring this quirk. 3852 * Thunderbolt bridges in external devices might have the same 3853 * device ID as those on the host, but they will not have the 3854 * associated ACPI methods. This implicitly checks that we are at 3855 * the right bridge. 3856 */ 3857 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3858 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3859 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3860 return; 3861 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3862 3863 /* magic sequence */ 3864 acpi_execute_simple_method(SXIO, NULL, 1); 3865 acpi_execute_simple_method(SXFP, NULL, 0); 3866 msleep(300); 3867 acpi_execute_simple_method(SXLV, NULL, 0); 3868 acpi_execute_simple_method(SXIO, NULL, 0); 3869 acpi_execute_simple_method(SXLV, NULL, 0); 3870 } 3871 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3872 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3873 quirk_apple_poweroff_thunderbolt); 3874 #endif 3875 3876 /* 3877 * Following are device-specific reset methods which can be used to 3878 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3879 * not available. 3880 */ 3881 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3882 { 3883 /* 3884 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3885 * 3886 * The 82599 supports FLR on VFs, but FLR support is reported only 3887 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3888 * Thus we must call pcie_flr() directly without first checking if it is 3889 * supported. 3890 */ 3891 if (!probe) 3892 pcie_flr(dev); 3893 return 0; 3894 } 3895 3896 #define SOUTH_CHICKEN2 0xc2004 3897 #define PCH_PP_STATUS 0xc7200 3898 #define PCH_PP_CONTROL 0xc7204 3899 #define MSG_CTL 0x45010 3900 #define NSDE_PWR_STATE 0xd0100 3901 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3902 3903 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3904 { 3905 void __iomem *mmio_base; 3906 unsigned long timeout; 3907 u32 val; 3908 3909 if (probe) 3910 return 0; 3911 3912 mmio_base = pci_iomap(dev, 0, 0); 3913 if (!mmio_base) 3914 return -ENOMEM; 3915 3916 iowrite32(0x00000002, mmio_base + MSG_CTL); 3917 3918 /* 3919 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3920 * driver loaded sets the right bits. However, this's a reset and 3921 * the bits have been set by i915 previously, so we clobber 3922 * SOUTH_CHICKEN2 register directly here. 3923 */ 3924 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3925 3926 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3927 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3928 3929 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3930 do { 3931 val = ioread32(mmio_base + PCH_PP_STATUS); 3932 if ((val & 0xb0000000) == 0) 3933 goto reset_complete; 3934 msleep(10); 3935 } while (time_before(jiffies, timeout)); 3936 pci_warn(dev, "timeout during reset\n"); 3937 3938 reset_complete: 3939 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3940 3941 pci_iounmap(dev, mmio_base); 3942 return 0; 3943 } 3944 3945 /* Device-specific reset method for Chelsio T4-based adapters */ 3946 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3947 { 3948 u16 old_command; 3949 u16 msix_flags; 3950 3951 /* 3952 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3953 * that we have no device-specific reset method. 3954 */ 3955 if ((dev->device & 0xf000) != 0x4000) 3956 return -ENOTTY; 3957 3958 /* 3959 * If this is the "probe" phase, return 0 indicating that we can 3960 * reset this device. 3961 */ 3962 if (probe) 3963 return 0; 3964 3965 /* 3966 * T4 can wedge if there are DMAs in flight within the chip and Bus 3967 * Master has been disabled. We need to have it on till the Function 3968 * Level Reset completes. (BUS_MASTER is disabled in 3969 * pci_reset_function()). 3970 */ 3971 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3972 pci_write_config_word(dev, PCI_COMMAND, 3973 old_command | PCI_COMMAND_MASTER); 3974 3975 /* 3976 * Perform the actual device function reset, saving and restoring 3977 * configuration information around the reset. 3978 */ 3979 pci_save_state(dev); 3980 3981 /* 3982 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3983 * are disabled when an MSI-X interrupt message needs to be delivered. 3984 * So we briefly re-enable MSI-X interrupts for the duration of the 3985 * FLR. The pci_restore_state() below will restore the original 3986 * MSI-X state. 3987 */ 3988 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3989 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3990 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3991 msix_flags | 3992 PCI_MSIX_FLAGS_ENABLE | 3993 PCI_MSIX_FLAGS_MASKALL); 3994 3995 pcie_flr(dev); 3996 3997 /* 3998 * Restore the configuration information (BAR values, etc.) including 3999 * the original PCI Configuration Space Command word, and return 4000 * success. 4001 */ 4002 pci_restore_state(dev); 4003 pci_write_config_word(dev, PCI_COMMAND, old_command); 4004 return 0; 4005 } 4006 4007 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4008 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4009 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4010 4011 /* 4012 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4013 * FLR where config space reads from the device return -1. We seem to be 4014 * able to avoid this condition if we disable the NVMe controller prior to 4015 * FLR. This quirk is generic for any NVMe class device requiring similar 4016 * assistance to quiesce the device prior to FLR. 4017 * 4018 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4019 * Revision 1.0e: 4020 * Chapter 2: Required and optional PCI config registers 4021 * Chapter 3: NVMe control registers 4022 * Chapter 7.3: Reset behavior 4023 */ 4024 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4025 { 4026 void __iomem *bar; 4027 u16 cmd; 4028 u32 cfg; 4029 4030 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4031 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4032 return -ENOTTY; 4033 4034 if (probe) 4035 return 0; 4036 4037 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4038 if (!bar) 4039 return -ENOTTY; 4040 4041 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4042 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4043 4044 cfg = readl(bar + NVME_REG_CC); 4045 4046 /* Disable controller if enabled */ 4047 if (cfg & NVME_CC_ENABLE) { 4048 u32 cap = readl(bar + NVME_REG_CAP); 4049 unsigned long timeout; 4050 4051 /* 4052 * Per nvme_disable_ctrl() skip shutdown notification as it 4053 * could complete commands to the admin queue. We only intend 4054 * to quiesce the device before reset. 4055 */ 4056 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4057 4058 writel(cfg, bar + NVME_REG_CC); 4059 4060 /* 4061 * Some controllers require an additional delay here, see 4062 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4063 * supported by this quirk. 4064 */ 4065 4066 /* Cap register provides max timeout in 500ms increments */ 4067 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4068 4069 for (;;) { 4070 u32 status = readl(bar + NVME_REG_CSTS); 4071 4072 /* Ready status becomes zero on disable complete */ 4073 if (!(status & NVME_CSTS_RDY)) 4074 break; 4075 4076 msleep(100); 4077 4078 if (time_after(jiffies, timeout)) { 4079 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4080 break; 4081 } 4082 } 4083 } 4084 4085 pci_iounmap(dev, bar); 4086 4087 pcie_flr(dev); 4088 4089 return 0; 4090 } 4091 4092 /* 4093 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4094 * timeout waiting for ready status to change after NVMe enable if the driver 4095 * starts interacting with the device too soon after FLR. A 250ms delay after 4096 * FLR has heuristically proven to produce reliably working results for device 4097 * assignment cases. 4098 */ 4099 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4100 { 4101 if (probe) 4102 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4103 4104 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4105 4106 msleep(250); 4107 4108 return 0; 4109 } 4110 4111 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4112 #define HINIC_VF_FLR_TYPE 0x1000 4113 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4114 #define HINIC_VF_OP 0xE80 4115 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4116 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4117 4118 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4119 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4120 { 4121 unsigned long timeout; 4122 void __iomem *bar; 4123 u32 val; 4124 4125 if (probe) 4126 return 0; 4127 4128 bar = pci_iomap(pdev, 0, 0); 4129 if (!bar) 4130 return -ENOTTY; 4131 4132 /* Get and check firmware capabilities */ 4133 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4134 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4135 pci_iounmap(pdev, bar); 4136 return -ENOTTY; 4137 } 4138 4139 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4140 val = ioread32be(bar + HINIC_VF_OP); 4141 val = val | HINIC_VF_FLR_PROC_BIT; 4142 iowrite32be(val, bar + HINIC_VF_OP); 4143 4144 pcie_flr(pdev); 4145 4146 /* 4147 * The device must recapture its Bus and Device Numbers after FLR 4148 * in order generate Completions. Issue a config write to let the 4149 * device capture this information. 4150 */ 4151 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4152 4153 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4154 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4155 do { 4156 val = ioread32be(bar + HINIC_VF_OP); 4157 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4158 goto reset_complete; 4159 msleep(20); 4160 } while (time_before(jiffies, timeout)); 4161 4162 val = ioread32be(bar + HINIC_VF_OP); 4163 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4164 goto reset_complete; 4165 4166 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4167 4168 reset_complete: 4169 pci_iounmap(pdev, bar); 4170 4171 return 0; 4172 } 4173 4174 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4175 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4176 reset_intel_82599_sfp_virtfn }, 4177 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4178 reset_ivb_igd }, 4179 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4180 reset_ivb_igd }, 4181 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4182 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4183 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4184 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4185 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4186 reset_chelsio_generic_dev }, 4187 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4188 reset_hinic_vf_dev }, 4189 { 0 } 4190 }; 4191 4192 /* 4193 * These device-specific reset methods are here rather than in a driver 4194 * because when a host assigns a device to a guest VM, the host may need 4195 * to reset the device but probably doesn't have a driver for it. 4196 */ 4197 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4198 { 4199 const struct pci_dev_reset_methods *i; 4200 4201 for (i = pci_dev_reset_methods; i->reset; i++) { 4202 if ((i->vendor == dev->vendor || 4203 i->vendor == (u16)PCI_ANY_ID) && 4204 (i->device == dev->device || 4205 i->device == (u16)PCI_ANY_ID)) 4206 return i->reset(dev, probe); 4207 } 4208 4209 return -ENOTTY; 4210 } 4211 4212 static void quirk_dma_func0_alias(struct pci_dev *dev) 4213 { 4214 if (PCI_FUNC(dev->devfn) != 0) 4215 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4216 } 4217 4218 /* 4219 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4220 * 4221 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4222 */ 4223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4225 4226 static void quirk_dma_func1_alias(struct pci_dev *dev) 4227 { 4228 if (PCI_FUNC(dev->devfn) != 1) 4229 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4230 } 4231 4232 /* 4233 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4234 * SKUs function 1 is present and is a legacy IDE controller, in other 4235 * SKUs this function is not present, making this a ghost requester. 4236 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4237 */ 4238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4239 quirk_dma_func1_alias); 4240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4241 quirk_dma_func1_alias); 4242 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4244 quirk_dma_func1_alias); 4245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4246 quirk_dma_func1_alias); 4247 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4249 quirk_dma_func1_alias); 4250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4251 quirk_dma_func1_alias); 4252 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4254 quirk_dma_func1_alias); 4255 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4257 quirk_dma_func1_alias); 4258 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4260 quirk_dma_func1_alias); 4261 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4263 quirk_dma_func1_alias); 4264 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4266 quirk_dma_func1_alias); 4267 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4269 quirk_dma_func1_alias); 4270 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4272 quirk_dma_func1_alias); 4273 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4275 quirk_dma_func1_alias); 4276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4277 quirk_dma_func1_alias); 4278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4279 quirk_dma_func1_alias); 4280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4281 quirk_dma_func1_alias); 4282 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4284 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4285 quirk_dma_func1_alias); 4286 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4287 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4288 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4289 quirk_dma_func1_alias); 4290 4291 /* 4292 * Some devices DMA with the wrong devfn, not just the wrong function. 4293 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4294 * the alias is "fixed" and independent of the device devfn. 4295 * 4296 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4297 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4298 * single device on the secondary bus. In reality, the single exposed 4299 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4300 * that provides a bridge to the internal bus of the I/O processor. The 4301 * controller supports private devices, which can be hidden from PCI config 4302 * space. In the case of the Adaptec 3405, a private device at 01.0 4303 * appears to be the DMA engine, which therefore needs to become a DMA 4304 * alias for the device. 4305 */ 4306 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4307 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4308 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4309 .driver_data = PCI_DEVFN(1, 0) }, 4310 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4311 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4312 .driver_data = PCI_DEVFN(1, 0) }, 4313 { 0 } 4314 }; 4315 4316 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4317 { 4318 const struct pci_device_id *id; 4319 4320 id = pci_match_id(fixed_dma_alias_tbl, dev); 4321 if (id) 4322 pci_add_dma_alias(dev, id->driver_data, 1); 4323 } 4324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4325 4326 /* 4327 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4328 * using the wrong DMA alias for the device. Some of these devices can be 4329 * used as either forward or reverse bridges, so we need to test whether the 4330 * device is operating in the correct mode. We could probably apply this 4331 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4332 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4333 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4334 */ 4335 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4336 { 4337 if (!pci_is_root_bus(pdev->bus) && 4338 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4339 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4340 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4341 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4342 } 4343 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4345 quirk_use_pcie_bridge_dma_alias); 4346 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4347 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4348 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4349 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4350 /* ITE 8893 has the same problem as the 8892 */ 4351 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4352 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4353 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4354 4355 /* 4356 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4357 * be added as aliases to the DMA device in order to allow buffer access 4358 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4359 * programmed in the EEPROM. 4360 */ 4361 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4362 { 4363 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4364 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4365 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4366 } 4367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4369 4370 /* 4371 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4372 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4373 * 4374 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4375 * when IOMMU is enabled. These aliases allow computational unit access to 4376 * host memory. These aliases mark the whole VCA device as one IOMMU 4377 * group. 4378 * 4379 * All possible slot numbers (0x20) are used, since we are unable to tell 4380 * what slot is used on other side. This quirk is intended for both host 4381 * and computational unit sides. The VCA devices have up to five functions 4382 * (four for DMA channels and one additional). 4383 */ 4384 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4385 { 4386 const unsigned int num_pci_slots = 0x20; 4387 unsigned int slot; 4388 4389 for (slot = 0; slot < num_pci_slots; slot++) 4390 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4391 } 4392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4393 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4394 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4395 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4398 4399 /* 4400 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4401 * associated not at the root bus, but at a bridge below. This quirk avoids 4402 * generating invalid DMA aliases. 4403 */ 4404 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4405 { 4406 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4407 } 4408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4409 quirk_bridge_cavm_thrx2_pcie_root); 4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4411 quirk_bridge_cavm_thrx2_pcie_root); 4412 4413 /* 4414 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4415 * class code. Fix it. 4416 */ 4417 static void quirk_tw686x_class(struct pci_dev *pdev) 4418 { 4419 u32 class = pdev->class; 4420 4421 /* Use "Multimedia controller" class */ 4422 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4423 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4424 class, pdev->class); 4425 } 4426 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4427 quirk_tw686x_class); 4428 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4429 quirk_tw686x_class); 4430 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4431 quirk_tw686x_class); 4432 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4433 quirk_tw686x_class); 4434 4435 /* 4436 * Some devices have problems with Transaction Layer Packets with the Relaxed 4437 * Ordering Attribute set. Such devices should mark themselves and other 4438 * device drivers should check before sending TLPs with RO set. 4439 */ 4440 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4441 { 4442 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4443 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4444 } 4445 4446 /* 4447 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4448 * Complex have a Flow Control Credit issue which can cause performance 4449 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4450 */ 4451 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4452 quirk_relaxedordering_disable); 4453 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4454 quirk_relaxedordering_disable); 4455 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4456 quirk_relaxedordering_disable); 4457 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4458 quirk_relaxedordering_disable); 4459 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4460 quirk_relaxedordering_disable); 4461 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4462 quirk_relaxedordering_disable); 4463 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4464 quirk_relaxedordering_disable); 4465 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4466 quirk_relaxedordering_disable); 4467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4468 quirk_relaxedordering_disable); 4469 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4470 quirk_relaxedordering_disable); 4471 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4472 quirk_relaxedordering_disable); 4473 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4474 quirk_relaxedordering_disable); 4475 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4476 quirk_relaxedordering_disable); 4477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4478 quirk_relaxedordering_disable); 4479 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4480 quirk_relaxedordering_disable); 4481 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4482 quirk_relaxedordering_disable); 4483 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4484 quirk_relaxedordering_disable); 4485 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4486 quirk_relaxedordering_disable); 4487 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4488 quirk_relaxedordering_disable); 4489 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4490 quirk_relaxedordering_disable); 4491 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4492 quirk_relaxedordering_disable); 4493 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4494 quirk_relaxedordering_disable); 4495 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4496 quirk_relaxedordering_disable); 4497 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4498 quirk_relaxedordering_disable); 4499 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4500 quirk_relaxedordering_disable); 4501 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4502 quirk_relaxedordering_disable); 4503 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4504 quirk_relaxedordering_disable); 4505 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4506 quirk_relaxedordering_disable); 4507 4508 /* 4509 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4510 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4511 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4512 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4513 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4514 * November 10, 2010). As a result, on this platform we can't use Relaxed 4515 * Ordering for Upstream TLPs. 4516 */ 4517 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4518 quirk_relaxedordering_disable); 4519 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4520 quirk_relaxedordering_disable); 4521 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4522 quirk_relaxedordering_disable); 4523 4524 /* 4525 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4526 * values for the Attribute as were supplied in the header of the 4527 * corresponding Request, except as explicitly allowed when IDO is used." 4528 * 4529 * If a non-compliant device generates a completion with a different 4530 * attribute than the request, the receiver may accept it (which itself 4531 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4532 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4533 * device access timeout. 4534 * 4535 * If the non-compliant device generates completions with zero attributes 4536 * (instead of copying the attributes from the request), we can work around 4537 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4538 * upstream devices so they always generate requests with zero attributes. 4539 * 4540 * This affects other devices under the same Root Port, but since these 4541 * attributes are performance hints, there should be no functional problem. 4542 * 4543 * Note that Configuration Space accesses are never supposed to have TLP 4544 * Attributes, so we're safe waiting till after any Configuration Space 4545 * accesses to do the Root Port fixup. 4546 */ 4547 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4548 { 4549 struct pci_dev *root_port = pcie_find_root_port(pdev); 4550 4551 if (!root_port) { 4552 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4553 return; 4554 } 4555 4556 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4557 dev_name(&pdev->dev)); 4558 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4559 PCI_EXP_DEVCTL_RELAX_EN | 4560 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4561 } 4562 4563 /* 4564 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4565 * Completion it generates. 4566 */ 4567 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4568 { 4569 /* 4570 * This mask/compare operation selects for Physical Function 4 on a 4571 * T5. We only need to fix up the Root Port once for any of the 4572 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4573 * 0x54xx so we use that one. 4574 */ 4575 if ((pdev->device & 0xff00) == 0x5400) 4576 quirk_disable_root_port_attributes(pdev); 4577 } 4578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4579 quirk_chelsio_T5_disable_root_port_attributes); 4580 4581 /* 4582 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4583 * by a device 4584 * @acs_ctrl_req: Bitmask of desired ACS controls 4585 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4586 * the hardware design 4587 * 4588 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4589 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4590 * caller desires. Return 0 otherwise. 4591 */ 4592 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4593 { 4594 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4595 return 1; 4596 return 0; 4597 } 4598 4599 /* 4600 * AMD has indicated that the devices below do not support peer-to-peer 4601 * in any system where they are found in the southbridge with an AMD 4602 * IOMMU in the system. Multifunction devices that do not support 4603 * peer-to-peer between functions can claim to support a subset of ACS. 4604 * Such devices effectively enable request redirect (RR) and completion 4605 * redirect (CR) since all transactions are redirected to the upstream 4606 * root complex. 4607 * 4608 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4609 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4610 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4611 * 4612 * 1002:4385 SBx00 SMBus Controller 4613 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4614 * 1002:4383 SBx00 Azalia (Intel HDA) 4615 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4616 * 1002:4384 SBx00 PCI to PCI Bridge 4617 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4618 * 4619 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4620 * 4621 * 1022:780f [AMD] FCH PCI Bridge 4622 * 1022:7809 [AMD] FCH USB OHCI Controller 4623 */ 4624 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4625 { 4626 #ifdef CONFIG_ACPI 4627 struct acpi_table_header *header = NULL; 4628 acpi_status status; 4629 4630 /* Targeting multifunction devices on the SB (appears on root bus) */ 4631 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4632 return -ENODEV; 4633 4634 /* The IVRS table describes the AMD IOMMU */ 4635 status = acpi_get_table("IVRS", 0, &header); 4636 if (ACPI_FAILURE(status)) 4637 return -ENODEV; 4638 4639 acpi_put_table(header); 4640 4641 /* Filter out flags not applicable to multifunction */ 4642 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4643 4644 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4645 #else 4646 return -ENODEV; 4647 #endif 4648 } 4649 4650 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4651 { 4652 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4653 return false; 4654 4655 switch (dev->device) { 4656 /* 4657 * Effectively selects all downstream ports for whole ThunderX1 4658 * (which represents 8 SoCs). 4659 */ 4660 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4661 case 0xaf84: /* ThunderX2 */ 4662 case 0xb884: /* ThunderX3 */ 4663 return true; 4664 default: 4665 return false; 4666 } 4667 } 4668 4669 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4670 { 4671 if (!pci_quirk_cavium_acs_match(dev)) 4672 return -ENOTTY; 4673 4674 /* 4675 * Cavium Root Ports don't advertise an ACS capability. However, 4676 * the RTL internally implements similar protection as if ACS had 4677 * Source Validation, Request Redirection, Completion Redirection, 4678 * and Upstream Forwarding features enabled. Assert that the 4679 * hardware implements and enables equivalent ACS functionality for 4680 * these flags. 4681 */ 4682 return pci_acs_ctrl_enabled(acs_flags, 4683 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4684 } 4685 4686 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4687 { 4688 /* 4689 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4690 * transactions with others, allowing masking out these bits as if they 4691 * were unimplemented in the ACS capability. 4692 */ 4693 return pci_acs_ctrl_enabled(acs_flags, 4694 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4695 } 4696 4697 /* 4698 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4699 * But the implementation could block peer-to-peer transactions between them 4700 * and provide ACS-like functionality. 4701 */ 4702 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4703 { 4704 if (!pci_is_pcie(dev) || 4705 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4706 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4707 return -ENOTTY; 4708 4709 switch (dev->device) { 4710 case 0x0710 ... 0x071e: 4711 case 0x0721: 4712 case 0x0723 ... 0x0732: 4713 return pci_acs_ctrl_enabled(acs_flags, 4714 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4715 } 4716 4717 return false; 4718 } 4719 4720 /* 4721 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4722 * transactions and validate bus numbers in requests, but do not provide an 4723 * actual PCIe ACS capability. This is the list of device IDs known to fall 4724 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4725 */ 4726 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4727 /* Ibexpeak PCH */ 4728 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4729 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4730 /* Cougarpoint PCH */ 4731 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4732 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4733 /* Pantherpoint PCH */ 4734 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4735 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4736 /* Lynxpoint-H PCH */ 4737 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4738 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4739 /* Lynxpoint-LP PCH */ 4740 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4741 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4742 /* Wildcat PCH */ 4743 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4744 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4745 /* Patsburg (X79) PCH */ 4746 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4747 /* Wellsburg (X99) PCH */ 4748 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4749 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4750 /* Lynx Point (9 series) PCH */ 4751 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4752 }; 4753 4754 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4755 { 4756 int i; 4757 4758 /* Filter out a few obvious non-matches first */ 4759 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4760 return false; 4761 4762 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4763 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4764 return true; 4765 4766 return false; 4767 } 4768 4769 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4770 { 4771 if (!pci_quirk_intel_pch_acs_match(dev)) 4772 return -ENOTTY; 4773 4774 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4775 return pci_acs_ctrl_enabled(acs_flags, 4776 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4777 4778 return pci_acs_ctrl_enabled(acs_flags, 0); 4779 } 4780 4781 /* 4782 * These QCOM Root Ports do provide ACS-like features to disable peer 4783 * transactions and validate bus numbers in requests, but do not provide an 4784 * actual PCIe ACS capability. Hardware supports source validation but it 4785 * will report the issue as Completer Abort instead of ACS Violation. 4786 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4787 * Complex with unique segment numbers. It is not possible for one Root 4788 * Port to pass traffic to another Root Port. All PCIe transactions are 4789 * terminated inside the Root Port. 4790 */ 4791 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4792 { 4793 return pci_acs_ctrl_enabled(acs_flags, 4794 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4795 } 4796 4797 /* 4798 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4799 * number and does provide isolation features to disable peer transactions 4800 * and validate bus numbers in requests, but does not provide an ACS 4801 * capability. 4802 */ 4803 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4804 { 4805 return pci_acs_ctrl_enabled(acs_flags, 4806 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4807 } 4808 4809 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4810 { 4811 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4812 return -ENOTTY; 4813 4814 /* 4815 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4816 * but do include ACS-like functionality. The hardware doesn't support 4817 * peer-to-peer transactions via the root port and each has a unique 4818 * segment number. 4819 * 4820 * Additionally, the root ports cannot send traffic to each other. 4821 */ 4822 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4823 4824 return acs_flags ? 0 : 1; 4825 } 4826 4827 /* 4828 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4829 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4830 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4831 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4832 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4833 * control register is at offset 8 instead of 6 and we should probably use 4834 * dword accesses to them. This applies to the following PCI Device IDs, as 4835 * found in volume 1 of the datasheet[2]: 4836 * 4837 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4838 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4839 * 4840 * N.B. This doesn't fix what lspci shows. 4841 * 4842 * The 100 series chipset specification update includes this as errata #23[3]. 4843 * 4844 * The 200 series chipset (Union Point) has the same bug according to the 4845 * specification update (Intel 200 Series Chipset Family Platform Controller 4846 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4847 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4848 * chipset include: 4849 * 4850 * 0xa290-0xa29f PCI Express Root port #{0-16} 4851 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4852 * 4853 * Mobile chipsets are also affected, 7th & 8th Generation 4854 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4855 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4856 * Processor Family I/O for U Quad Core Platforms Specification Update, 4857 * August 2017, Revision 002, Document#: 334660-002)[6] 4858 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4859 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4860 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4861 * 4862 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4863 * 4864 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4865 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4866 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4867 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4868 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4869 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4870 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4871 */ 4872 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4873 { 4874 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4875 return false; 4876 4877 switch (dev->device) { 4878 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4879 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4880 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4881 return true; 4882 } 4883 4884 return false; 4885 } 4886 4887 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4888 4889 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4890 { 4891 int pos; 4892 u32 cap, ctrl; 4893 4894 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4895 return -ENOTTY; 4896 4897 pos = dev->acs_cap; 4898 if (!pos) 4899 return -ENOTTY; 4900 4901 /* see pci_acs_flags_enabled() */ 4902 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4903 acs_flags &= (cap | PCI_ACS_EC); 4904 4905 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4906 4907 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4908 } 4909 4910 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4911 { 4912 /* 4913 * SV, TB, and UF are not relevant to multifunction endpoints. 4914 * 4915 * Multifunction devices are only required to implement RR, CR, and DT 4916 * in their ACS capability if they support peer-to-peer transactions. 4917 * Devices matching this quirk have been verified by the vendor to not 4918 * perform peer-to-peer with other functions, allowing us to mask out 4919 * these bits as if they were unimplemented in the ACS capability. 4920 */ 4921 return pci_acs_ctrl_enabled(acs_flags, 4922 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4923 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4924 } 4925 4926 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4927 { 4928 /* 4929 * Intel RCiEP's are required to allow p2p only on translated 4930 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4931 * "Root-Complex Peer to Peer Considerations". 4932 */ 4933 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4934 return -ENOTTY; 4935 4936 return pci_acs_ctrl_enabled(acs_flags, 4937 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4938 } 4939 4940 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4941 { 4942 /* 4943 * iProc PAXB Root Ports don't advertise an ACS capability, but 4944 * they do not allow peer-to-peer transactions between Root Ports. 4945 * Allow each Root Port to be in a separate IOMMU group by masking 4946 * SV/RR/CR/UF bits. 4947 */ 4948 return pci_acs_ctrl_enabled(acs_flags, 4949 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4950 } 4951 4952 /* 4953 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function 4954 * devices, peer-to-peer transactions are not be used between the functions. 4955 * So add an ACS quirk for below devices to isolate functions. 4956 * SFxxx 1G NICs(em). 4957 * RP1000/RP2000 10G NICs(sp). 4958 */ 4959 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 4960 { 4961 switch (dev->device) { 4962 case 0x0100 ... 0x010F: 4963 case 0x1001: 4964 case 0x2001: 4965 return pci_acs_ctrl_enabled(acs_flags, 4966 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4967 } 4968 4969 return false; 4970 } 4971 4972 static const struct pci_dev_acs_enabled { 4973 u16 vendor; 4974 u16 device; 4975 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4976 } pci_dev_acs_enabled[] = { 4977 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4978 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4979 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4980 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4981 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4982 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4983 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4984 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4985 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4986 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4987 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4988 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4989 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4990 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4991 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4992 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4993 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4994 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4995 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4996 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4997 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4998 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4999 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5000 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5001 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5002 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5003 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5004 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5005 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5006 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5007 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5008 /* 82580 */ 5009 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5010 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5011 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5012 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5013 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5014 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5015 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5016 /* 82576 */ 5017 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5018 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5019 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5020 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5021 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5022 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5023 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5024 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5025 /* 82575 */ 5026 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5027 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5028 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5029 /* I350 */ 5030 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5031 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5032 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5033 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5034 /* 82571 (Quads omitted due to non-ACS switch) */ 5035 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5036 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5037 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5038 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5039 /* I219 */ 5040 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5041 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5042 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5043 /* QCOM QDF2xxx root ports */ 5044 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5045 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5046 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5047 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5048 /* Intel PCH root ports */ 5049 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5050 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5051 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5052 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5053 /* Cavium ThunderX */ 5054 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5055 /* Cavium multi-function devices */ 5056 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5057 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5058 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5059 /* APM X-Gene */ 5060 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5061 /* Ampere Computing */ 5062 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5063 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5064 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5065 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5066 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5067 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5068 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5069 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5070 /* Broadcom multi-function device */ 5071 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5072 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5073 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5074 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5075 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5076 /* Amazon Annapurna Labs */ 5077 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5078 /* Zhaoxin multi-function devices */ 5079 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5080 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5081 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5082 /* NXP root ports, xx=16, 12, or 08 cores */ 5083 /* LX2xx0A : without security features + CAN-FD */ 5084 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5085 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5086 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5087 /* LX2xx0C : security features + CAN-FD */ 5088 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5089 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5090 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5091 /* LX2xx0E : security features + CAN */ 5092 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5093 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5094 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5095 /* LX2xx0N : without security features + CAN */ 5096 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5097 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5098 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5099 /* LX2xx2A : without security features + CAN-FD */ 5100 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5101 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5102 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5103 /* LX2xx2C : security features + CAN-FD */ 5104 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5105 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5106 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5107 /* LX2xx2E : security features + CAN */ 5108 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5109 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5110 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5111 /* LX2xx2N : without security features + CAN */ 5112 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5113 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5114 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5115 /* Zhaoxin Root/Downstream Ports */ 5116 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5117 /* Wangxun nics */ 5118 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5119 { 0 } 5120 }; 5121 5122 /* 5123 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5124 * @dev: PCI device 5125 * @acs_flags: Bitmask of desired ACS controls 5126 * 5127 * Returns: 5128 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5129 * device provides the desired controls 5130 * 0: Device does not provide all the desired controls 5131 * >0: Device provides all the controls in @acs_flags 5132 */ 5133 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5134 { 5135 const struct pci_dev_acs_enabled *i; 5136 int ret; 5137 5138 /* 5139 * Allow devices that do not expose standard PCIe ACS capabilities 5140 * or control to indicate their support here. Multi-function express 5141 * devices which do not allow internal peer-to-peer between functions, 5142 * but do not implement PCIe ACS may wish to return true here. 5143 */ 5144 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5145 if ((i->vendor == dev->vendor || 5146 i->vendor == (u16)PCI_ANY_ID) && 5147 (i->device == dev->device || 5148 i->device == (u16)PCI_ANY_ID)) { 5149 ret = i->acs_enabled(dev, acs_flags); 5150 if (ret >= 0) 5151 return ret; 5152 } 5153 } 5154 5155 return -ENOTTY; 5156 } 5157 5158 /* Config space offset of Root Complex Base Address register */ 5159 #define INTEL_LPC_RCBA_REG 0xf0 5160 /* 31:14 RCBA address */ 5161 #define INTEL_LPC_RCBA_MASK 0xffffc000 5162 /* RCBA Enable */ 5163 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5164 5165 /* Backbone Scratch Pad Register */ 5166 #define INTEL_BSPR_REG 0x1104 5167 /* Backbone Peer Non-Posted Disable */ 5168 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5169 /* Backbone Peer Posted Disable */ 5170 #define INTEL_BSPR_REG_BPPD (1 << 9) 5171 5172 /* Upstream Peer Decode Configuration Register */ 5173 #define INTEL_UPDCR_REG 0x1014 5174 /* 5:0 Peer Decode Enable bits */ 5175 #define INTEL_UPDCR_REG_MASK 0x3f 5176 5177 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5178 { 5179 u32 rcba, bspr, updcr; 5180 void __iomem *rcba_mem; 5181 5182 /* 5183 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5184 * are D28:F* and therefore get probed before LPC, thus we can't 5185 * use pci_get_slot()/pci_read_config_dword() here. 5186 */ 5187 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5188 INTEL_LPC_RCBA_REG, &rcba); 5189 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5190 return -EINVAL; 5191 5192 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5193 PAGE_ALIGN(INTEL_UPDCR_REG)); 5194 if (!rcba_mem) 5195 return -ENOMEM; 5196 5197 /* 5198 * The BSPR can disallow peer cycles, but it's set by soft strap and 5199 * therefore read-only. If both posted and non-posted peer cycles are 5200 * disallowed, we're ok. If either are allowed, then we need to use 5201 * the UPDCR to disable peer decodes for each port. This provides the 5202 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5203 */ 5204 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5205 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5206 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5207 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5208 if (updcr & INTEL_UPDCR_REG_MASK) { 5209 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5210 updcr &= ~INTEL_UPDCR_REG_MASK; 5211 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5212 } 5213 } 5214 5215 iounmap(rcba_mem); 5216 return 0; 5217 } 5218 5219 /* Miscellaneous Port Configuration register */ 5220 #define INTEL_MPC_REG 0xd8 5221 /* MPC: Invalid Receive Bus Number Check Enable */ 5222 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5223 5224 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5225 { 5226 u32 mpc; 5227 5228 /* 5229 * When enabled, the IRBNCE bit of the MPC register enables the 5230 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5231 * ensures that requester IDs fall within the bus number range 5232 * of the bridge. Enable if not already. 5233 */ 5234 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5235 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5236 pci_info(dev, "Enabling MPC IRBNCE\n"); 5237 mpc |= INTEL_MPC_REG_IRBNCE; 5238 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5239 } 5240 } 5241 5242 /* 5243 * Currently this quirk does the equivalent of 5244 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5245 * 5246 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5247 * if dev->external_facing || dev->untrusted 5248 */ 5249 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5250 { 5251 if (!pci_quirk_intel_pch_acs_match(dev)) 5252 return -ENOTTY; 5253 5254 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5255 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5256 return 0; 5257 } 5258 5259 pci_quirk_enable_intel_rp_mpc_acs(dev); 5260 5261 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5262 5263 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5264 5265 return 0; 5266 } 5267 5268 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5269 { 5270 int pos; 5271 u32 cap, ctrl; 5272 5273 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5274 return -ENOTTY; 5275 5276 pos = dev->acs_cap; 5277 if (!pos) 5278 return -ENOTTY; 5279 5280 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5281 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5282 5283 ctrl |= (cap & PCI_ACS_SV); 5284 ctrl |= (cap & PCI_ACS_RR); 5285 ctrl |= (cap & PCI_ACS_CR); 5286 ctrl |= (cap & PCI_ACS_UF); 5287 5288 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5289 ctrl |= (cap & PCI_ACS_TB); 5290 5291 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5292 5293 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5294 5295 return 0; 5296 } 5297 5298 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5299 { 5300 int pos; 5301 u32 cap, ctrl; 5302 5303 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5304 return -ENOTTY; 5305 5306 pos = dev->acs_cap; 5307 if (!pos) 5308 return -ENOTTY; 5309 5310 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5311 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5312 5313 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5314 5315 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5316 5317 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5318 5319 return 0; 5320 } 5321 5322 static const struct pci_dev_acs_ops { 5323 u16 vendor; 5324 u16 device; 5325 int (*enable_acs)(struct pci_dev *dev); 5326 int (*disable_acs_redir)(struct pci_dev *dev); 5327 } pci_dev_acs_ops[] = { 5328 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5329 .enable_acs = pci_quirk_enable_intel_pch_acs, 5330 }, 5331 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5332 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5333 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5334 }, 5335 }; 5336 5337 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5338 { 5339 const struct pci_dev_acs_ops *p; 5340 int i, ret; 5341 5342 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5343 p = &pci_dev_acs_ops[i]; 5344 if ((p->vendor == dev->vendor || 5345 p->vendor == (u16)PCI_ANY_ID) && 5346 (p->device == dev->device || 5347 p->device == (u16)PCI_ANY_ID) && 5348 p->enable_acs) { 5349 ret = p->enable_acs(dev); 5350 if (ret >= 0) 5351 return ret; 5352 } 5353 } 5354 5355 return -ENOTTY; 5356 } 5357 5358 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5359 { 5360 const struct pci_dev_acs_ops *p; 5361 int i, ret; 5362 5363 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5364 p = &pci_dev_acs_ops[i]; 5365 if ((p->vendor == dev->vendor || 5366 p->vendor == (u16)PCI_ANY_ID) && 5367 (p->device == dev->device || 5368 p->device == (u16)PCI_ANY_ID) && 5369 p->disable_acs_redir) { 5370 ret = p->disable_acs_redir(dev); 5371 if (ret >= 0) 5372 return ret; 5373 } 5374 } 5375 5376 return -ENOTTY; 5377 } 5378 5379 /* 5380 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5381 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5382 * Next Capability pointer in the MSI Capability Structure should point to 5383 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5384 * the list. 5385 */ 5386 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5387 { 5388 int pos, i = 0, ret; 5389 u8 next_cap; 5390 u16 reg16, *cap; 5391 struct pci_cap_saved_state *state; 5392 5393 /* Bail if the hardware bug is fixed */ 5394 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5395 return; 5396 5397 /* Bail if MSI Capability Structure is not found for some reason */ 5398 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5399 if (!pos) 5400 return; 5401 5402 /* 5403 * Bail if Next Capability pointer in the MSI Capability Structure 5404 * is not the expected incorrect 0x00. 5405 */ 5406 pci_read_config_byte(pdev, pos + 1, &next_cap); 5407 if (next_cap) 5408 return; 5409 5410 /* 5411 * PCIe Capability Structure is expected to be at 0x50 and should 5412 * terminate the list (Next Capability pointer is 0x00). Verify 5413 * Capability Id and Next Capability pointer is as expected. 5414 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5415 * to correctly set kernel data structures which have already been 5416 * set incorrectly due to the hardware bug. 5417 */ 5418 pos = 0x50; 5419 pci_read_config_word(pdev, pos, ®16); 5420 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5421 u32 status; 5422 #ifndef PCI_EXP_SAVE_REGS 5423 #define PCI_EXP_SAVE_REGS 7 5424 #endif 5425 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5426 5427 pdev->pcie_cap = pos; 5428 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5429 pdev->pcie_flags_reg = reg16; 5430 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5431 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5432 5433 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5434 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5435 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5436 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5437 5438 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5439 return; 5440 5441 /* Save PCIe cap */ 5442 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5443 if (!state) 5444 return; 5445 5446 state->cap.cap_nr = PCI_CAP_ID_EXP; 5447 state->cap.cap_extended = 0; 5448 state->cap.size = size; 5449 cap = (u16 *)&state->cap.data[0]; 5450 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5451 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5452 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5453 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5454 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5455 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5456 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5457 hlist_add_head(&state->next, &pdev->saved_cap_space); 5458 } 5459 } 5460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5461 5462 /* 5463 * FLR may cause the following to devices to hang: 5464 * 5465 * AMD Starship/Matisse HD Audio Controller 0x1487 5466 * AMD Starship USB 3.0 Host Controller 0x148c 5467 * AMD Matisse USB 3.0 Host Controller 0x149c 5468 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5469 * Intel 82579V Gigabit Ethernet Controller 0x1503 5470 * 5471 */ 5472 static void quirk_no_flr(struct pci_dev *dev) 5473 { 5474 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5475 } 5476 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5477 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5478 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5479 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5480 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5481 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5482 5483 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5484 static void quirk_no_flr_snet(struct pci_dev *dev) 5485 { 5486 if (dev->revision == 0x1) 5487 quirk_no_flr(dev); 5488 } 5489 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5490 5491 static void quirk_no_ext_tags(struct pci_dev *pdev) 5492 { 5493 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5494 5495 if (!bridge) 5496 return; 5497 5498 bridge->no_ext_tags = 1; 5499 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5500 5501 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5502 } 5503 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5504 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5505 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5506 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5507 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5508 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5509 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5510 5511 #ifdef CONFIG_PCI_ATS 5512 static void quirk_no_ats(struct pci_dev *pdev) 5513 { 5514 pci_info(pdev, "disabling ATS\n"); 5515 pdev->ats_cap = 0; 5516 } 5517 5518 /* 5519 * Some devices require additional driver setup to enable ATS. Don't use 5520 * ATS for those devices as ATS will be enabled before the driver has had a 5521 * chance to load and configure the device. 5522 */ 5523 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5524 { 5525 if (pdev->device == 0x15d8) { 5526 if (pdev->revision == 0xcf && 5527 pdev->subsystem_vendor == 0xea50 && 5528 (pdev->subsystem_device == 0xce19 || 5529 pdev->subsystem_device == 0xcc10 || 5530 pdev->subsystem_device == 0xcc08)) 5531 quirk_no_ats(pdev); 5532 } else { 5533 quirk_no_ats(pdev); 5534 } 5535 } 5536 5537 /* AMD Stoney platform GPU */ 5538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5539 /* AMD Iceland dGPU */ 5540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5541 /* AMD Navi10 dGPU */ 5542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5550 /* AMD Navi14 dGPU */ 5551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5555 /* AMD Raven platform iGPU */ 5556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5557 5558 /* 5559 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5560 * in ATS Invalidate Request message body. Disable ATS for those devices. 5561 */ 5562 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5563 { 5564 if (pdev->revision < 0x20) 5565 quirk_no_ats(pdev); 5566 } 5567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5576 #endif /* CONFIG_PCI_ATS */ 5577 5578 /* Freescale PCIe doesn't support MSI in RC mode */ 5579 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5580 { 5581 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5582 pdev->no_msi = 1; 5583 } 5584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5585 5586 /* 5587 * Although not allowed by the spec, some multi-function devices have 5588 * dependencies of one function (consumer) on another (supplier). For the 5589 * consumer to work in D0, the supplier must also be in D0. Create a 5590 * device link from the consumer to the supplier to enforce this 5591 * dependency. Runtime PM is allowed by default on the consumer to prevent 5592 * it from permanently keeping the supplier awake. 5593 */ 5594 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5595 unsigned int supplier, unsigned int class, 5596 unsigned int class_shift) 5597 { 5598 struct pci_dev *supplier_pdev; 5599 5600 if (PCI_FUNC(pdev->devfn) != consumer) 5601 return; 5602 5603 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5604 pdev->bus->number, 5605 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5606 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5607 pci_dev_put(supplier_pdev); 5608 return; 5609 } 5610 5611 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5612 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5613 pci_info(pdev, "D0 power state depends on %s\n", 5614 pci_name(supplier_pdev)); 5615 else 5616 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5617 pci_name(supplier_pdev)); 5618 5619 pm_runtime_allow(&pdev->dev); 5620 pci_dev_put(supplier_pdev); 5621 } 5622 5623 /* 5624 * Create device link for GPUs with integrated HDA controller for streaming 5625 * audio to attached displays. 5626 */ 5627 static void quirk_gpu_hda(struct pci_dev *hda) 5628 { 5629 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5630 } 5631 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5632 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5633 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5634 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5635 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5636 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5637 5638 /* 5639 * Create device link for GPUs with integrated USB xHCI Host 5640 * controller to VGA. 5641 */ 5642 static void quirk_gpu_usb(struct pci_dev *usb) 5643 { 5644 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5645 } 5646 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5647 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5648 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5649 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5650 5651 /* 5652 * Create device link for GPUs with integrated Type-C UCSI controller 5653 * to VGA. Currently there is no class code defined for UCSI device over PCI 5654 * so using UNKNOWN class for now and it will be updated when UCSI 5655 * over PCI gets a class code. 5656 */ 5657 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5658 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5659 { 5660 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5661 } 5662 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5663 PCI_CLASS_SERIAL_UNKNOWN, 8, 5664 quirk_gpu_usb_typec_ucsi); 5665 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5666 PCI_CLASS_SERIAL_UNKNOWN, 8, 5667 quirk_gpu_usb_typec_ucsi); 5668 5669 /* 5670 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5671 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5672 */ 5673 static void quirk_nvidia_hda(struct pci_dev *gpu) 5674 { 5675 u8 hdr_type; 5676 u32 val; 5677 5678 /* There was no integrated HDA controller before MCP89 */ 5679 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5680 return; 5681 5682 /* Bit 25 at offset 0x488 enables the HDA controller */ 5683 pci_read_config_dword(gpu, 0x488, &val); 5684 if (val & BIT(25)) 5685 return; 5686 5687 pci_info(gpu, "Enabling HDA controller\n"); 5688 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5689 5690 /* The GPU becomes a multi-function device when the HDA is enabled */ 5691 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5692 gpu->multifunction = !!(hdr_type & 0x80); 5693 } 5694 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5695 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5696 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5697 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5698 5699 /* 5700 * Some IDT switches incorrectly flag an ACS Source Validation error on 5701 * completions for config read requests even though PCIe r4.0, sec 5702 * 6.12.1.1, says that completions are never affected by ACS Source 5703 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5704 * 5705 * Item #36 - Downstream port applies ACS Source Validation to Completions 5706 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5707 * completions are never affected by ACS Source Validation. However, 5708 * completions received by a downstream port of the PCIe switch from a 5709 * device that has not yet captured a PCIe bus number are incorrectly 5710 * dropped by ACS Source Validation by the switch downstream port. 5711 * 5712 * The workaround suggested by IDT is to issue a config write to the 5713 * downstream device before issuing the first config read. This allows the 5714 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5715 * sec 2.2.9), thus avoiding the ACS error on the completion. 5716 * 5717 * However, we don't know when the device is ready to accept the config 5718 * write, so we do config reads until we receive a non-Config Request Retry 5719 * Status, then do the config write. 5720 * 5721 * To avoid hitting the erratum when doing the config reads, we disable ACS 5722 * SV around this process. 5723 */ 5724 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5725 { 5726 int pos; 5727 u16 ctrl = 0; 5728 bool found; 5729 struct pci_dev *bridge = bus->self; 5730 5731 pos = bridge->acs_cap; 5732 5733 /* Disable ACS SV before initial config reads */ 5734 if (pos) { 5735 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5736 if (ctrl & PCI_ACS_SV) 5737 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5738 ctrl & ~PCI_ACS_SV); 5739 } 5740 5741 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5742 5743 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5744 if (found) 5745 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5746 5747 /* Re-enable ACS_SV if it was previously enabled */ 5748 if (ctrl & PCI_ACS_SV) 5749 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5750 5751 return found; 5752 } 5753 5754 /* 5755 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5756 * NT endpoints via the internal switch fabric. These IDs replace the 5757 * originating Requester ID TLPs which access host memory on peer NTB 5758 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5759 * to permit access when the IOMMU is turned on. 5760 */ 5761 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5762 { 5763 void __iomem *mmio; 5764 struct ntb_info_regs __iomem *mmio_ntb; 5765 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5766 u64 partition_map; 5767 u8 partition; 5768 int pp; 5769 5770 if (pci_enable_device(pdev)) { 5771 pci_err(pdev, "Cannot enable Switchtec device\n"); 5772 return; 5773 } 5774 5775 mmio = pci_iomap(pdev, 0, 0); 5776 if (mmio == NULL) { 5777 pci_disable_device(pdev); 5778 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5779 return; 5780 } 5781 5782 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5783 5784 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5785 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5786 5787 partition = ioread8(&mmio_ntb->partition_id); 5788 5789 partition_map = ioread32(&mmio_ntb->ep_map); 5790 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5791 partition_map &= ~(1ULL << partition); 5792 5793 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5794 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5795 u32 table_sz = 0; 5796 int te; 5797 5798 if (!(partition_map & (1ULL << pp))) 5799 continue; 5800 5801 pci_dbg(pdev, "Processing partition %d\n", pp); 5802 5803 mmio_peer_ctrl = &mmio_ctrl[pp]; 5804 5805 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5806 if (!table_sz) { 5807 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5808 continue; 5809 } 5810 5811 if (table_sz > 512) { 5812 pci_warn(pdev, 5813 "Invalid Switchtec partition %d table_sz %d\n", 5814 pp, table_sz); 5815 continue; 5816 } 5817 5818 for (te = 0; te < table_sz; te++) { 5819 u32 rid_entry; 5820 u8 devfn; 5821 5822 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5823 devfn = (rid_entry >> 1) & 0xFF; 5824 pci_dbg(pdev, 5825 "Aliasing Partition %d Proxy ID %02x.%d\n", 5826 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5827 pci_add_dma_alias(pdev, devfn, 1); 5828 } 5829 } 5830 5831 pci_iounmap(pdev, mmio); 5832 pci_disable_device(pdev); 5833 } 5834 #define SWITCHTEC_QUIRK(vid) \ 5835 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5836 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5837 5838 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5839 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5840 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5841 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5842 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5843 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5844 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5845 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5846 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5847 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5848 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5849 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5850 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5851 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5852 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5853 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5854 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5855 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5856 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5857 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5858 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5859 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5860 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5861 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5862 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5863 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5864 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5865 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5866 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5867 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5868 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5869 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5870 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5871 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5872 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5873 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5874 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5875 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5876 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5877 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5878 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5879 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5880 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5881 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5882 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5883 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5884 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5885 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5886 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 5887 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 5888 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 5889 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 5890 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 5891 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 5892 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 5893 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 5894 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 5895 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 5896 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 5897 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 5898 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 5899 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 5900 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 5901 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 5902 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 5903 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 5904 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 5905 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 5906 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 5907 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 5908 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 5909 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 5910 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 5911 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 5912 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 5913 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 5914 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 5915 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 5916 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 5917 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 5918 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 5919 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 5920 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 5921 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 5922 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 5923 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 5924 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 5925 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 5926 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 5927 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 5928 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 5929 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 5930 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 5931 5932 /* 5933 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5934 * These IDs are used to forward responses to the originator on the other 5935 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5936 * the IOMMU is turned on. 5937 */ 5938 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5939 { 5940 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5941 /* PLX NTB may use all 256 devfns */ 5942 pci_add_dma_alias(pdev, 0, 256); 5943 } 5944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 5945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 5946 5947 /* 5948 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 5949 * not always reset the secondary Nvidia GPU between reboots if the system 5950 * is configured to use Hybrid Graphics mode. This results in the GPU 5951 * being left in whatever state it was in during the *previous* boot, which 5952 * causes spurious interrupts from the GPU, which in turn causes us to 5953 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 5954 * this also completely breaks nouveau. 5955 * 5956 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 5957 * clean state and fixes all these issues. 5958 * 5959 * When the machine is configured in Dedicated display mode, the issue 5960 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 5961 * mode, so we can detect that and avoid resetting it. 5962 */ 5963 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 5964 { 5965 void __iomem *map; 5966 int ret; 5967 5968 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 5969 pdev->subsystem_device != 0x222e || 5970 !pci_reset_supported(pdev)) 5971 return; 5972 5973 if (pci_enable_device_mem(pdev)) 5974 return; 5975 5976 /* 5977 * Based on nvkm_device_ctor() in 5978 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 5979 */ 5980 map = pci_iomap(pdev, 0, 0x23000); 5981 if (!map) { 5982 pci_err(pdev, "Can't map MMIO space\n"); 5983 goto out_disable; 5984 } 5985 5986 /* 5987 * Make sure the GPU looks like it's been POSTed before resetting 5988 * it. 5989 */ 5990 if (ioread32(map + 0x2240c) & 0x2) { 5991 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 5992 ret = pci_reset_bus(pdev); 5993 if (ret < 0) 5994 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 5995 } 5996 5997 iounmap(map); 5998 out_disable: 5999 pci_disable_device(pdev); 6000 } 6001 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6002 PCI_CLASS_DISPLAY_VGA, 8, 6003 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6004 6005 /* 6006 * Device [1b21:2142] 6007 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6008 */ 6009 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6010 { 6011 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6012 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6013 } 6014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6015 6016 /* 6017 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6018 * 6019 * These devices advertise PME# support in all power states but don't 6020 * reliably assert it. 6021 * 6022 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6023 * says "The MSI Function is not implemented on this device" in chapters 6024 * 7.3.27, 7.3.29-7.3.31. 6025 */ 6026 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6027 { 6028 #ifdef CONFIG_PCI_MSI 6029 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6030 dev->no_msi = 1; 6031 #endif 6032 pci_info(dev, "PME# is unreliable, disabling it\n"); 6033 dev->pme_support = 0; 6034 } 6035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6037 6038 static void apex_pci_fixup_class(struct pci_dev *pdev) 6039 { 6040 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6041 } 6042 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6043 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6044 6045 /* 6046 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6047 * ACS P2P Request Redirect is not functional 6048 * 6049 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6050 * between upstream and downstream ports, packets are queued in an internal 6051 * buffer until CPLD packet. The workaround is to use the switch in store and 6052 * forward mode. 6053 */ 6054 #define PI7C9X2Gxxx_MODE_REG 0x74 6055 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6056 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6057 { 6058 struct pci_dev *upstream; 6059 u16 val; 6060 6061 /* Downstream ports only */ 6062 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6063 return; 6064 6065 /* Check for ACS P2P Request Redirect use */ 6066 if (!pdev->acs_cap) 6067 return; 6068 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6069 if (!(val & PCI_ACS_RR)) 6070 return; 6071 6072 upstream = pci_upstream_bridge(pdev); 6073 if (!upstream) 6074 return; 6075 6076 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6077 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6078 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6079 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6080 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6081 } 6082 } 6083 /* 6084 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6085 * ACS configuration changes or switch mode is reset 6086 */ 6087 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6088 pci_fixup_pericom_acs_store_forward); 6089 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6090 pci_fixup_pericom_acs_store_forward); 6091 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6092 pci_fixup_pericom_acs_store_forward); 6093 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6094 pci_fixup_pericom_acs_store_forward); 6095 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6096 pci_fixup_pericom_acs_store_forward); 6097 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6098 pci_fixup_pericom_acs_store_forward); 6099 6100 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6101 { 6102 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6103 } 6104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6105 6106 static void rom_bar_overlap_defect(struct pci_dev *dev) 6107 { 6108 pci_info(dev, "working around ROM BAR overlap defect\n"); 6109 dev->rom_bar_overlap = 1; 6110 } 6111 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6112 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6113 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6114 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6115 6116 #ifdef CONFIG_PCIEASPM 6117 /* 6118 * Several Intel DG2 graphics devices advertise that they can only tolerate 6119 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6120 * from being enabled. But in fact these devices can tolerate unlimited 6121 * latency. Override their Device Capabilities value to allow ASPM L1 to 6122 * be enabled. 6123 */ 6124 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6125 { 6126 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6127 6128 if (l1_lat < 7) { 6129 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6130 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6131 l1_lat); 6132 } 6133 } 6134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6149 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6160 #endif 6161 6162 #ifdef CONFIG_PCIE_DPC 6163 /* 6164 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6165 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6166 * Ports. 6167 */ 6168 static void dpc_log_size(struct pci_dev *dev) 6169 { 6170 u16 dpc, val; 6171 6172 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6173 if (!dpc) 6174 return; 6175 6176 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6177 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6178 return; 6179 6180 if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) { 6181 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); 6182 dev->dpc_rp_log_size = 4; 6183 } 6184 } 6185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6191 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6193 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6194 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6195 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6201 #endif 6202 6203 /* 6204 * For a PCI device with multiple downstream devices, its driver may use 6205 * a flattened device tree to describe the downstream devices. 6206 * To overlay the flattened device tree, the PCI device and all its ancestor 6207 * devices need to have device tree nodes on system base device tree. Thus, 6208 * before driver probing, it might need to add a device tree node as the final 6209 * fixup. 6210 */ 6211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6214 6215 /* 6216 * Devices known to require a longer delay before first config space access 6217 * after reset recovery or resume from D3cold: 6218 * 6219 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6220 */ 6221 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6222 { 6223 pdev->d3cold_delay = 1000; 6224 } 6225 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6226