1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include <linux/kallsyms.h> 25 #include "pci.h" 26 27 /* The Mellanox Tavor device gives false positive parity errors 28 * Mark this device with a broken_parity_status, to allow 29 * PCI scanning code to "skip" this now blacklisted device. 30 */ 31 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 32 { 33 dev->broken_parity_status = 1; /* This device gives false positives */ 34 } 35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 36 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 37 38 /* Deal with broken BIOS'es that neglect to enable passive release, 39 which can cause problems in combination with the 82441FX/PPro MTRRs */ 40 static void quirk_passive_release(struct pci_dev *dev) 41 { 42 struct pci_dev *d = NULL; 43 unsigned char dlc; 44 45 /* We have to make sure a particular bit is set in the PIIX3 46 ISA bridge, so we have to go out and find it. */ 47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 48 pci_read_config_byte(d, 0x82, &dlc); 49 if (!(dlc & 1<<1)) { 50 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n"); 51 dlc |= 1<<1; 52 pci_write_config_byte(d, 0x82, dlc); 53 } 54 } 55 } 56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 57 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 58 59 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 60 but VIA don't answer queries. If you happen to have good contacts at VIA 61 ask them for me please -- Alan 62 63 This appears to be BIOS not version dependent. So presumably there is a 64 chipset level fix */ 65 int isa_dma_bridge_buggy; 66 EXPORT_SYMBOL(isa_dma_bridge_buggy); 67 68 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 69 { 70 if (!isa_dma_bridge_buggy) { 71 isa_dma_bridge_buggy=1; 72 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 73 } 74 } 75 /* 76 * Its not totally clear which chipsets are the problematic ones 77 * We know 82C586 and 82C596 variants are affected. 78 */ 79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 85 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 86 87 int pci_pci_problems; 88 EXPORT_SYMBOL(pci_pci_problems); 89 90 /* 91 * Chipsets where PCI->PCI transfers vanish or hang 92 */ 93 static void __devinit quirk_nopcipci(struct pci_dev *dev) 94 { 95 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 96 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 97 pci_pci_problems |= PCIPCI_FAIL; 98 } 99 } 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 102 103 static void __devinit quirk_nopciamd(struct pci_dev *dev) 104 { 105 u8 rev; 106 pci_read_config_byte(dev, 0x08, &rev); 107 if (rev == 0x13) { 108 /* Erratum 24 */ 109 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 110 pci_pci_problems |= PCIAGP_FAIL; 111 } 112 } 113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 114 115 /* 116 * Triton requires workarounds to be used by the drivers 117 */ 118 static void __devinit quirk_triton(struct pci_dev *dev) 119 { 120 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 121 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 122 pci_pci_problems |= PCIPCI_TRITON; 123 } 124 } 125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 129 130 /* 131 * VIA Apollo KT133 needs PCI latency patch 132 * Made according to a windows driver based patch by George E. Breese 133 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 134 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 135 * the info on which Mr Breese based his work. 136 * 137 * Updated based on further information from the site and also on 138 * information provided by VIA 139 */ 140 static void quirk_vialatency(struct pci_dev *dev) 141 { 142 struct pci_dev *p; 143 u8 busarb; 144 /* Ok we have a potential problem chipset here. Now see if we have 145 a buggy southbridge */ 146 147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 148 if (p!=NULL) { 149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 150 /* Check for buggy part revisions */ 151 if (p->revision < 0x40 || p->revision > 0x42) 152 goto exit; 153 } else { 154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 155 if (p==NULL) /* No problem parts */ 156 goto exit; 157 /* Check for buggy part revisions */ 158 if (p->revision < 0x10 || p->revision > 0x12) 159 goto exit; 160 } 161 162 /* 163 * Ok we have the problem. Now set the PCI master grant to 164 * occur every master grant. The apparent bug is that under high 165 * PCI load (quite common in Linux of course) you can get data 166 * loss when the CPU is held off the bus for 3 bus master requests 167 * This happens to include the IDE controllers.... 168 * 169 * VIA only apply this fix when an SB Live! is present but under 170 * both Linux and Windows this isnt enough, and we have seen 171 * corruption without SB Live! but with things like 3 UDMA IDE 172 * controllers. So we ignore that bit of the VIA recommendation.. 173 */ 174 175 pci_read_config_byte(dev, 0x76, &busarb); 176 /* Set bit 4 and bi 5 of byte 76 to 0x01 177 "Master priority rotation on every PCI master grant */ 178 busarb &= ~(1<<5); 179 busarb |= (1<<4); 180 pci_write_config_byte(dev, 0x76, busarb); 181 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 182 exit: 183 pci_dev_put(p); 184 } 185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 188 /* Must restore this on a resume from RAM */ 189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 191 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 192 193 /* 194 * VIA Apollo VP3 needs ETBF on BT848/878 195 */ 196 static void __devinit quirk_viaetbf(struct pci_dev *dev) 197 { 198 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 199 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 200 pci_pci_problems |= PCIPCI_VIAETBF; 201 } 202 } 203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 204 205 static void __devinit quirk_vsfx(struct pci_dev *dev) 206 { 207 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 208 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 209 pci_pci_problems |= PCIPCI_VSFX; 210 } 211 } 212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 213 214 /* 215 * Ali Magik requires workarounds to be used by the drivers 216 * that DMA to AGP space. Latency must be set to 0xA and triton 217 * workaround applied too 218 * [Info kindly provided by ALi] 219 */ 220 static void __init quirk_alimagik(struct pci_dev *dev) 221 { 222 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 223 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 224 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 225 } 226 } 227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 229 230 /* 231 * Natoma has some interesting boundary conditions with Zoran stuff 232 * at least 233 */ 234 static void __devinit quirk_natoma(struct pci_dev *dev) 235 { 236 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 238 pci_pci_problems |= PCIPCI_NATOMA; 239 } 240 } 241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 247 248 /* 249 * This chip can cause PCI parity errors if config register 0xA0 is read 250 * while DMAs are occurring. 251 */ 252 static void __devinit quirk_citrine(struct pci_dev *dev) 253 { 254 dev->cfg_size = 0xA0; 255 } 256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 257 258 /* 259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 260 * If it's needed, re-allocate the region. 261 */ 262 static void __devinit quirk_s3_64M(struct pci_dev *dev) 263 { 264 struct resource *r = &dev->resource[0]; 265 266 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 267 r->start = 0; 268 r->end = 0x3ffffff; 269 } 270 } 271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 273 274 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 275 unsigned size, int nr, const char *name) 276 { 277 region &= ~(size-1); 278 if (region) { 279 struct pci_bus_region bus_region; 280 struct resource *res = dev->resource + nr; 281 282 res->name = pci_name(dev); 283 res->start = region; 284 res->end = region + size - 1; 285 res->flags = IORESOURCE_IO; 286 287 /* Convert from PCI bus to resource space. */ 288 bus_region.start = res->start; 289 bus_region.end = res->end; 290 pcibios_bus_to_resource(dev, res, &bus_region); 291 292 pci_claim_resource(dev, nr); 293 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 294 } 295 } 296 297 /* 298 * ATI Northbridge setups MCE the processor if you even 299 * read somewhere between 0x3b0->0x3bb or read 0x3d3 300 */ 301 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 302 { 303 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 305 request_region(0x3b0, 0x0C, "RadeonIGP"); 306 request_region(0x3d3, 0x01, "RadeonIGP"); 307 } 308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 309 310 /* 311 * Let's make the southbridge information explicit instead 312 * of having to worry about people probing the ACPI areas, 313 * for example.. (Yes, it happens, and if you read the wrong 314 * ACPI register it will put the machine to sleep with no 315 * way of waking it up again. Bummer). 316 * 317 * ALI M7101: Two IO regions pointed to by words at 318 * 0xE0 (64 bytes of ACPI registers) 319 * 0xE2 (32 bytes of SMB registers) 320 */ 321 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 322 { 323 u16 region; 324 325 pci_read_config_word(dev, 0xE0, ®ion); 326 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 327 pci_read_config_word(dev, 0xE2, ®ion); 328 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 329 } 330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 331 332 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 333 { 334 u32 devres; 335 u32 mask, size, base; 336 337 pci_read_config_dword(dev, port, &devres); 338 if ((devres & enable) != enable) 339 return; 340 mask = (devres >> 16) & 15; 341 base = devres & 0xffff; 342 size = 16; 343 for (;;) { 344 unsigned bit = size >> 1; 345 if ((bit & mask) == bit) 346 break; 347 size = bit; 348 } 349 /* 350 * For now we only print it out. Eventually we'll want to 351 * reserve it (at least if it's in the 0x1000+ range), but 352 * let's get enough confirmation reports first. 353 */ 354 base &= -size; 355 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 356 } 357 358 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 359 { 360 u32 devres; 361 u32 mask, size, base; 362 363 pci_read_config_dword(dev, port, &devres); 364 if ((devres & enable) != enable) 365 return; 366 base = devres & 0xffff0000; 367 mask = (devres & 0x3f) << 16; 368 size = 128 << 16; 369 for (;;) { 370 unsigned bit = size >> 1; 371 if ((bit & mask) == bit) 372 break; 373 size = bit; 374 } 375 /* 376 * For now we only print it out. Eventually we'll want to 377 * reserve it, but let's get enough confirmation reports first. 378 */ 379 base &= -size; 380 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 381 } 382 383 /* 384 * PIIX4 ACPI: Two IO regions pointed to by longwords at 385 * 0x40 (64 bytes of ACPI registers) 386 * 0x90 (16 bytes of SMB registers) 387 * and a few strange programmable PIIX4 device resources. 388 */ 389 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 390 { 391 u32 region, res_a; 392 393 pci_read_config_dword(dev, 0x40, ®ion); 394 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 395 pci_read_config_dword(dev, 0x90, ®ion); 396 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 397 398 /* Device resource A has enables for some of the other ones */ 399 pci_read_config_dword(dev, 0x5c, &res_a); 400 401 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 402 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 403 404 /* Device resource D is just bitfields for static resources */ 405 406 /* Device 12 enabled? */ 407 if (res_a & (1 << 29)) { 408 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 409 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 410 } 411 /* Device 13 enabled? */ 412 if (res_a & (1 << 30)) { 413 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 414 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 415 } 416 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 417 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 418 } 419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 421 422 /* 423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 424 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 425 * 0x58 (64 bytes of GPIO I/O space) 426 */ 427 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 428 { 429 u32 region; 430 431 pci_read_config_dword(dev, 0x40, ®ion); 432 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 433 434 pci_read_config_dword(dev, 0x58, ®ion); 435 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 436 } 437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 447 448 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 449 { 450 u32 region; 451 452 pci_read_config_dword(dev, 0x40, ®ion); 453 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 454 455 pci_read_config_dword(dev, 0x48, ®ion); 456 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 457 } 458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi); 459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi); 460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi); 461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi); 462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi); 463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi); 464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi); 465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi); 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi); 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi); 468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi); 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi); 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi); 471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi); 472 473 /* 474 * VIA ACPI: One IO region pointed to by longword at 475 * 0x48 or 0x20 (256 bytes of ACPI registers) 476 */ 477 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 478 { 479 u32 region; 480 481 if (dev->revision & 0x10) { 482 pci_read_config_dword(dev, 0x48, ®ion); 483 region &= PCI_BASE_ADDRESS_IO_MASK; 484 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 485 } 486 } 487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 488 489 /* 490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 491 * 0x48 (256 bytes of ACPI registers) 492 * 0x70 (128 bytes of hardware monitoring register) 493 * 0x90 (16 bytes of SMB registers) 494 */ 495 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 496 { 497 u16 hm; 498 u32 smb; 499 500 quirk_vt82c586_acpi(dev); 501 502 pci_read_config_word(dev, 0x70, &hm); 503 hm &= PCI_BASE_ADDRESS_IO_MASK; 504 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 505 506 pci_read_config_dword(dev, 0x90, &smb); 507 smb &= PCI_BASE_ADDRESS_IO_MASK; 508 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 509 } 510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 511 512 /* 513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 514 * 0x88 (128 bytes of power management registers) 515 * 0xd0 (16 bytes of SMB registers) 516 */ 517 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 518 { 519 u16 pm, smb; 520 521 pci_read_config_word(dev, 0x88, &pm); 522 pm &= PCI_BASE_ADDRESS_IO_MASK; 523 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 524 525 pci_read_config_word(dev, 0xd0, &smb); 526 smb &= PCI_BASE_ADDRESS_IO_MASK; 527 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 528 } 529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 530 531 532 #ifdef CONFIG_X86_IO_APIC 533 534 #include <asm/io_apic.h> 535 536 /* 537 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 538 * devices to the external APIC. 539 * 540 * TODO: When we have device-specific interrupt routers, 541 * this code will go away from quirks. 542 */ 543 static void quirk_via_ioapic(struct pci_dev *dev) 544 { 545 u8 tmp; 546 547 if (nr_ioapics < 1) 548 tmp = 0; /* nothing routed to external APIC */ 549 else 550 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 551 552 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 553 tmp == 0 ? "Disa" : "Ena"); 554 555 /* Offset 0x58: External APIC IRQ output control */ 556 pci_write_config_byte (dev, 0x58, tmp); 557 } 558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 560 561 /* 562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 563 * This leads to doubled level interrupt rates. 564 * Set this bit to get rid of cycle wastage. 565 * Otherwise uncritical. 566 */ 567 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 568 { 569 u8 misc_control2; 570 #define BYPASS_APIC_DEASSERT 8 571 572 pci_read_config_byte(dev, 0x5B, &misc_control2); 573 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 574 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 575 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 576 } 577 } 578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 579 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 580 581 /* 582 * The AMD io apic can hang the box when an apic irq is masked. 583 * We check all revs >= B0 (yet not in the pre production!) as the bug 584 * is currently marked NoFix 585 * 586 * We have multiple reports of hangs with this chipset that went away with 587 * noapic specified. For the moment we assume it's the erratum. We may be wrong 588 * of course. However the advice is demonstrably good even if so.. 589 */ 590 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 591 { 592 if (dev->revision >= 0x02) { 593 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 594 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 595 } 596 } 597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 598 599 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 600 { 601 if (dev->devfn == 0 && dev->bus->number == 0) 602 sis_apic_bug = 1; 603 } 604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 605 606 #define AMD8131_revA0 0x01 607 #define AMD8131_revB0 0x11 608 #define AMD8131_MISC 0x40 609 #define AMD8131_NIOAMODE_BIT 0 610 static void quirk_amd_8131_ioapic(struct pci_dev *dev) 611 { 612 unsigned char tmp; 613 614 if (nr_ioapics == 0) 615 return; 616 617 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) { 618 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n"); 619 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 620 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 621 pci_write_config_byte( dev, AMD8131_MISC, tmp); 622 } 623 } 624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 625 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 626 #endif /* CONFIG_X86_IO_APIC */ 627 628 /* 629 * Some settings of MMRBC can lead to data corruption so block changes. 630 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 631 */ 632 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 633 { 634 if (dev->subordinate && dev->revision <= 0x12) { 635 dev_info(&dev->dev, "AMD8131 rev %x detected; " 636 "disabling PCI-X MMRBC\n", dev->revision); 637 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 638 } 639 } 640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 641 642 /* 643 * FIXME: it is questionable that quirk_via_acpi 644 * is needed. It shows up as an ISA bridge, and does not 645 * support the PCI_INTERRUPT_LINE register at all. Therefore 646 * it seems like setting the pci_dev's 'irq' to the 647 * value of the ACPI SCI interrupt is only done for convenience. 648 * -jgarzik 649 */ 650 static void __devinit quirk_via_acpi(struct pci_dev *d) 651 { 652 /* 653 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 654 */ 655 u8 irq; 656 pci_read_config_byte(d, 0x42, &irq); 657 irq &= 0xf; 658 if (irq && (irq != 2)) 659 d->irq = irq; 660 } 661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 662 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 663 664 665 /* 666 * VIA bridges which have VLink 667 */ 668 669 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 670 671 static void quirk_via_bridge(struct pci_dev *dev) 672 { 673 /* See what bridge we have and find the device ranges */ 674 switch (dev->device) { 675 case PCI_DEVICE_ID_VIA_82C686: 676 /* The VT82C686 is special, it attaches to PCI and can have 677 any device number. All its subdevices are functions of 678 that single device. */ 679 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 680 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 681 break; 682 case PCI_DEVICE_ID_VIA_8237: 683 case PCI_DEVICE_ID_VIA_8237A: 684 via_vlink_dev_lo = 15; 685 break; 686 case PCI_DEVICE_ID_VIA_8235: 687 via_vlink_dev_lo = 16; 688 break; 689 case PCI_DEVICE_ID_VIA_8231: 690 case PCI_DEVICE_ID_VIA_8233_0: 691 case PCI_DEVICE_ID_VIA_8233A: 692 case PCI_DEVICE_ID_VIA_8233C_0: 693 via_vlink_dev_lo = 17; 694 break; 695 } 696 } 697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 705 706 /** 707 * quirk_via_vlink - VIA VLink IRQ number update 708 * @dev: PCI device 709 * 710 * If the device we are dealing with is on a PIC IRQ we need to 711 * ensure that the IRQ line register which usually is not relevant 712 * for PCI cards, is actually written so that interrupts get sent 713 * to the right place. 714 * We only do this on systems where a VIA south bridge was detected, 715 * and only for VIA devices on the motherboard (see quirk_via_bridge 716 * above). 717 */ 718 719 static void quirk_via_vlink(struct pci_dev *dev) 720 { 721 u8 irq, new_irq; 722 723 /* Check if we have VLink at all */ 724 if (via_vlink_dev_lo == -1) 725 return; 726 727 new_irq = dev->irq; 728 729 /* Don't quirk interrupts outside the legacy IRQ range */ 730 if (!new_irq || new_irq > 15) 731 return; 732 733 /* Internal device ? */ 734 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 735 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 736 return; 737 738 /* This is an internal VLink device on a PIC interrupt. The BIOS 739 ought to have set this but may not have, so we redo it */ 740 741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 742 if (new_irq != irq) { 743 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 744 irq, new_irq); 745 udelay(15); /* unknown if delay really needed */ 746 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 747 } 748 } 749 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 750 751 /* 752 * VIA VT82C598 has its device ID settable and many BIOSes 753 * set it to the ID of VT82C597 for backward compatibility. 754 * We need to switch it off to be able to recognize the real 755 * type of the chip. 756 */ 757 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 758 { 759 pci_write_config_byte(dev, 0xfc, 0); 760 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 761 } 762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 763 764 /* 765 * CardBus controllers have a legacy base address that enables them 766 * to respond as i82365 pcmcia controllers. We don't want them to 767 * do this even if the Linux CardBus driver is not loaded, because 768 * the Linux i82365 driver does not (and should not) handle CardBus. 769 */ 770 static void quirk_cardbus_legacy(struct pci_dev *dev) 771 { 772 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 773 return; 774 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 775 } 776 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 777 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 778 779 /* 780 * Following the PCI ordering rules is optional on the AMD762. I'm not 781 * sure what the designers were smoking but let's not inhale... 782 * 783 * To be fair to AMD, it follows the spec by default, its BIOS people 784 * who turn it off! 785 */ 786 static void quirk_amd_ordering(struct pci_dev *dev) 787 { 788 u32 pcic; 789 pci_read_config_dword(dev, 0x4C, &pcic); 790 if ((pcic&6)!=6) { 791 pcic |= 6; 792 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 793 pci_write_config_dword(dev, 0x4C, pcic); 794 pci_read_config_dword(dev, 0x84, &pcic); 795 pcic |= (1<<23); /* Required in this mode */ 796 pci_write_config_dword(dev, 0x84, pcic); 797 } 798 } 799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 800 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 801 802 /* 803 * DreamWorks provided workaround for Dunord I-3000 problem 804 * 805 * This card decodes and responds to addresses not apparently 806 * assigned to it. We force a larger allocation to ensure that 807 * nothing gets put too close to it. 808 */ 809 static void __devinit quirk_dunord ( struct pci_dev * dev ) 810 { 811 struct resource *r = &dev->resource [1]; 812 r->start = 0; 813 r->end = 0xffffff; 814 } 815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 816 817 /* 818 * i82380FB mobile docking controller: its PCI-to-PCI bridge 819 * is subtractive decoding (transparent), and does indicate this 820 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 821 * instead of 0x01. 822 */ 823 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 824 { 825 dev->transparent = 1; 826 } 827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 829 830 /* 831 * Common misconfiguration of the MediaGX/Geode PCI master that will 832 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 833 * datasheets found at http://www.national.com/ds/GX for info on what 834 * these bits do. <christer@weinigel.se> 835 */ 836 static void quirk_mediagx_master(struct pci_dev *dev) 837 { 838 u8 reg; 839 pci_read_config_byte(dev, 0x41, ®); 840 if (reg & 2) { 841 reg &= ~2; 842 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 843 pci_write_config_byte(dev, 0x41, reg); 844 } 845 } 846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 847 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 848 849 /* 850 * Ensure C0 rev restreaming is off. This is normally done by 851 * the BIOS but in the odd case it is not the results are corruption 852 * hence the presence of a Linux check 853 */ 854 static void quirk_disable_pxb(struct pci_dev *pdev) 855 { 856 u16 config; 857 858 if (pdev->revision != 0x04) /* Only C0 requires this */ 859 return; 860 pci_read_config_word(pdev, 0x40, &config); 861 if (config & (1<<6)) { 862 config &= ~(1<<6); 863 pci_write_config_word(pdev, 0x40, config); 864 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 865 } 866 } 867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 868 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 869 870 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 871 { 872 /* set sb600/sb700/sb800 sata to ahci mode */ 873 u8 tmp; 874 875 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 876 if (tmp == 0x01) { 877 pci_read_config_byte(pdev, 0x40, &tmp); 878 pci_write_config_byte(pdev, 0x40, tmp|1); 879 pci_write_config_byte(pdev, 0x9, 1); 880 pci_write_config_byte(pdev, 0xa, 6); 881 pci_write_config_byte(pdev, 0x40, tmp); 882 883 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 884 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 885 } 886 } 887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 888 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 890 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 891 892 /* 893 * Serverworks CSB5 IDE does not fully support native mode 894 */ 895 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 896 { 897 u8 prog; 898 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 899 if (prog & 5) { 900 prog &= ~5; 901 pdev->class &= ~5; 902 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 903 /* PCI layer will sort out resources */ 904 } 905 } 906 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 907 908 /* 909 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 910 */ 911 static void __init quirk_ide_samemode(struct pci_dev *pdev) 912 { 913 u8 prog; 914 915 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 916 917 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 918 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 919 prog &= ~5; 920 pdev->class &= ~5; 921 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 922 } 923 } 924 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 925 926 /* This was originally an Alpha specific thing, but it really fits here. 927 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 928 */ 929 static void __init quirk_eisa_bridge(struct pci_dev *dev) 930 { 931 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 932 } 933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 934 935 936 /* 937 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 938 * is not activated. The myth is that Asus said that they do not want the 939 * users to be irritated by just another PCI Device in the Win98 device 940 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 941 * package 2.7.0 for details) 942 * 943 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 944 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 945 * becomes necessary to do this tweak in two steps -- the chosen trigger 946 * is either the Host bridge (preferred) or on-board VGA controller. 947 * 948 * Note that we used to unhide the SMBus that way on Toshiba laptops 949 * (Satellite A40 and Tecra M2) but then found that the thermal management 950 * was done by SMM code, which could cause unsynchronized concurrent 951 * accesses to the SMBus registers, with potentially bad effects. Thus you 952 * should be very careful when adding new entries: if SMM is accessing the 953 * Intel SMBus, this is a very good reason to leave it hidden. 954 * 955 * Likewise, many recent laptops use ACPI for thermal management. If the 956 * ACPI DSDT code accesses the SMBus, then Linux should not access it 957 * natively, and keeping the SMBus hidden is the right thing to do. If you 958 * are about to add an entry in the table below, please first disassemble 959 * the DSDT and double-check that there is no code accessing the SMBus. 960 */ 961 static int asus_hides_smbus; 962 963 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 964 { 965 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 966 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 967 switch(dev->subsystem_device) { 968 case 0x8025: /* P4B-LX */ 969 case 0x8070: /* P4B */ 970 case 0x8088: /* P4B533 */ 971 case 0x1626: /* L3C notebook */ 972 asus_hides_smbus = 1; 973 } 974 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 975 switch(dev->subsystem_device) { 976 case 0x80b1: /* P4GE-V */ 977 case 0x80b2: /* P4PE */ 978 case 0x8093: /* P4B533-V */ 979 asus_hides_smbus = 1; 980 } 981 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 982 switch(dev->subsystem_device) { 983 case 0x8030: /* P4T533 */ 984 asus_hides_smbus = 1; 985 } 986 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 987 switch (dev->subsystem_device) { 988 case 0x8070: /* P4G8X Deluxe */ 989 asus_hides_smbus = 1; 990 } 991 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 992 switch (dev->subsystem_device) { 993 case 0x80c9: /* PU-DLS */ 994 asus_hides_smbus = 1; 995 } 996 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 997 switch (dev->subsystem_device) { 998 case 0x1751: /* M2N notebook */ 999 case 0x1821: /* M5N notebook */ 1000 asus_hides_smbus = 1; 1001 } 1002 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1003 switch (dev->subsystem_device) { 1004 case 0x184b: /* W1N notebook */ 1005 case 0x186a: /* M6Ne notebook */ 1006 asus_hides_smbus = 1; 1007 } 1008 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1009 switch (dev->subsystem_device) { 1010 case 0x80f2: /* P4P800-X */ 1011 asus_hides_smbus = 1; 1012 } 1013 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1014 switch (dev->subsystem_device) { 1015 case 0x1882: /* M6V notebook */ 1016 case 0x1977: /* A6VA notebook */ 1017 asus_hides_smbus = 1; 1018 } 1019 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1020 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1021 switch(dev->subsystem_device) { 1022 case 0x088C: /* HP Compaq nc8000 */ 1023 case 0x0890: /* HP Compaq nc6000 */ 1024 asus_hides_smbus = 1; 1025 } 1026 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1027 switch (dev->subsystem_device) { 1028 case 0x12bc: /* HP D330L */ 1029 case 0x12bd: /* HP D530 */ 1030 asus_hides_smbus = 1; 1031 } 1032 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1033 switch (dev->subsystem_device) { 1034 case 0x12bf: /* HP xw4100 */ 1035 asus_hides_smbus = 1; 1036 } 1037 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1038 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1039 switch(dev->subsystem_device) { 1040 case 0xC00C: /* Samsung P35 notebook */ 1041 asus_hides_smbus = 1; 1042 } 1043 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1044 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1045 switch(dev->subsystem_device) { 1046 case 0x0058: /* Compaq Evo N620c */ 1047 asus_hides_smbus = 1; 1048 } 1049 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1050 switch(dev->subsystem_device) { 1051 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1052 /* Motherboard doesn't have Host bridge 1053 * subvendor/subdevice IDs, therefore checking 1054 * its on-board VGA controller */ 1055 asus_hides_smbus = 1; 1056 } 1057 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG) 1058 switch(dev->subsystem_device) { 1059 case 0x00b8: /* Compaq Evo D510 CMT */ 1060 case 0x00b9: /* Compaq Evo D510 SFF */ 1061 asus_hides_smbus = 1; 1062 } 1063 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1064 switch (dev->subsystem_device) { 1065 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1066 /* Motherboard doesn't have host bridge 1067 * subvendor/subdevice IDs, therefore checking 1068 * its on-board VGA controller */ 1069 asus_hides_smbus = 1; 1070 } 1071 } 1072 } 1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1083 1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge); 1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1087 1088 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1089 { 1090 u16 val; 1091 1092 if (likely(!asus_hides_smbus)) 1093 return; 1094 1095 pci_read_config_word(dev, 0xF2, &val); 1096 if (val & 0x8) { 1097 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1098 pci_read_config_word(dev, 0xF2, &val); 1099 if (val & 0x8) 1100 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1101 else 1102 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1103 } 1104 } 1105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1112 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1113 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1117 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1119 1120 /* It appears we just have one such device. If not, we have a warning */ 1121 static void __iomem *asus_rcba_base; 1122 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1123 { 1124 u32 rcba; 1125 1126 if (likely(!asus_hides_smbus)) 1127 return; 1128 WARN_ON(asus_rcba_base); 1129 1130 pci_read_config_dword(dev, 0xF0, &rcba); 1131 /* use bits 31:14, 16 kB aligned */ 1132 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1133 if (asus_rcba_base == NULL) 1134 return; 1135 } 1136 1137 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1138 { 1139 u32 val; 1140 1141 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1142 return; 1143 /* read the Function Disable register, dword mode only */ 1144 val = readl(asus_rcba_base + 0x3418); 1145 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1146 } 1147 1148 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1149 { 1150 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1151 return; 1152 iounmap(asus_rcba_base); 1153 asus_rcba_base = NULL; 1154 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1155 } 1156 1157 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1158 { 1159 asus_hides_smbus_lpc_ich6_suspend(dev); 1160 asus_hides_smbus_lpc_ich6_resume_early(dev); 1161 asus_hides_smbus_lpc_ich6_resume(dev); 1162 } 1163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1164 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1165 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1166 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1167 1168 /* 1169 * SiS 96x south bridge: BIOS typically hides SMBus device... 1170 */ 1171 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1172 { 1173 u8 val = 0; 1174 pci_read_config_byte(dev, 0x77, &val); 1175 if (val & 0x10) { 1176 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1177 pci_write_config_byte(dev, 0x77, val & ~0x10); 1178 } 1179 } 1180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1184 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1185 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1186 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1187 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1188 1189 /* 1190 * ... This is further complicated by the fact that some SiS96x south 1191 * bridges pretend to be 85C503/5513 instead. In that case see if we 1192 * spotted a compatible north bridge to make sure. 1193 * (pci_find_device doesn't work yet) 1194 * 1195 * We can also enable the sis96x bit in the discovery register.. 1196 */ 1197 #define SIS_DETECT_REGISTER 0x40 1198 1199 static void quirk_sis_503(struct pci_dev *dev) 1200 { 1201 u8 reg; 1202 u16 devid; 1203 1204 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1205 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1206 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1207 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1208 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1209 return; 1210 } 1211 1212 /* 1213 * Ok, it now shows up as a 96x.. run the 96x quirk by 1214 * hand in case it has already been processed. 1215 * (depends on link order, which is apparently not guaranteed) 1216 */ 1217 dev->device = devid; 1218 quirk_sis_96x_smbus(dev); 1219 } 1220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1221 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1222 1223 1224 /* 1225 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1226 * and MC97 modem controller are disabled when a second PCI soundcard is 1227 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1228 * -- bjd 1229 */ 1230 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1231 { 1232 u8 val; 1233 int asus_hides_ac97 = 0; 1234 1235 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1236 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1237 asus_hides_ac97 = 1; 1238 } 1239 1240 if (!asus_hides_ac97) 1241 return; 1242 1243 pci_read_config_byte(dev, 0x50, &val); 1244 if (val & 0xc0) { 1245 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1246 pci_read_config_byte(dev, 0x50, &val); 1247 if (val & 0xc0) 1248 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1249 else 1250 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1251 } 1252 } 1253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1254 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1255 1256 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1257 1258 /* 1259 * If we are using libata we can drive this chip properly but must 1260 * do this early on to make the additional device appear during 1261 * the PCI scanning. 1262 */ 1263 static void quirk_jmicron_ata(struct pci_dev *pdev) 1264 { 1265 u32 conf1, conf5, class; 1266 u8 hdr; 1267 1268 /* Only poke fn 0 */ 1269 if (PCI_FUNC(pdev->devfn)) 1270 return; 1271 1272 pci_read_config_dword(pdev, 0x40, &conf1); 1273 pci_read_config_dword(pdev, 0x80, &conf5); 1274 1275 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1276 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1277 1278 switch (pdev->device) { 1279 case PCI_DEVICE_ID_JMICRON_JMB360: 1280 /* The controller should be in single function ahci mode */ 1281 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1282 break; 1283 1284 case PCI_DEVICE_ID_JMICRON_JMB365: 1285 case PCI_DEVICE_ID_JMICRON_JMB366: 1286 /* Redirect IDE second PATA port to the right spot */ 1287 conf5 |= (1 << 24); 1288 /* Fall through */ 1289 case PCI_DEVICE_ID_JMICRON_JMB361: 1290 case PCI_DEVICE_ID_JMICRON_JMB363: 1291 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1292 /* Set the class codes correctly and then direct IDE 0 */ 1293 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1294 break; 1295 1296 case PCI_DEVICE_ID_JMICRON_JMB368: 1297 /* The controller should be in single function IDE mode */ 1298 conf1 |= 0x00C00000; /* Set 22, 23 */ 1299 break; 1300 } 1301 1302 pci_write_config_dword(pdev, 0x40, conf1); 1303 pci_write_config_dword(pdev, 0x80, conf5); 1304 1305 /* Update pdev accordingly */ 1306 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1307 pdev->hdr_type = hdr & 0x7f; 1308 pdev->multifunction = !!(hdr & 0x80); 1309 1310 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1311 pdev->class = class >> 8; 1312 } 1313 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1314 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1315 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1316 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1317 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1318 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1319 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1320 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1321 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1322 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1323 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1324 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1325 1326 #endif 1327 1328 #ifdef CONFIG_X86_IO_APIC 1329 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1330 { 1331 int i; 1332 1333 if ((pdev->class >> 8) != 0xff00) 1334 return; 1335 1336 /* the first BAR is the location of the IO APIC...we must 1337 * not touch this (and it's already covered by the fixmap), so 1338 * forcibly insert it into the resource tree */ 1339 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1340 insert_resource(&iomem_resource, &pdev->resource[0]); 1341 1342 /* The next five BARs all seem to be rubbish, so just clean 1343 * them out */ 1344 for (i=1; i < 6; i++) { 1345 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1346 } 1347 1348 } 1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1350 #endif 1351 1352 int pcie_mch_quirk; 1353 EXPORT_SYMBOL(pcie_mch_quirk); 1354 1355 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1356 { 1357 pcie_mch_quirk = 1; 1358 } 1359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1362 1363 1364 /* 1365 * It's possible for the MSI to get corrupted if shpc and acpi 1366 * are used together on certain PXH-based systems. 1367 */ 1368 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1369 { 1370 pci_msi_off(dev); 1371 dev->no_msi = 1; 1372 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1373 } 1374 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1375 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1376 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1377 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1378 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1379 1380 /* 1381 * Some Intel PCI Express chipsets have trouble with downstream 1382 * device power management. 1383 */ 1384 static void quirk_intel_pcie_pm(struct pci_dev * dev) 1385 { 1386 pci_pm_d3_delay = 120; 1387 dev->no_d1d2 = 1; 1388 } 1389 1390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1411 1412 /* 1413 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1414 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1415 * Re-allocate the region if needed... 1416 */ 1417 static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1418 { 1419 struct resource *r = &dev->resource[0]; 1420 1421 if (r->start & 0x8) { 1422 r->start = 0; 1423 r->end = 0xf; 1424 } 1425 } 1426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1427 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1428 quirk_tc86c001_ide); 1429 1430 static void __devinit quirk_netmos(struct pci_dev *dev) 1431 { 1432 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1433 unsigned int num_serial = dev->subsystem_device & 0xf; 1434 1435 /* 1436 * These Netmos parts are multiport serial devices with optional 1437 * parallel ports. Even when parallel ports are present, they 1438 * are identified as class SERIAL, which means the serial driver 1439 * will claim them. To prevent this, mark them as class OTHER. 1440 * These combo devices should be claimed by parport_serial. 1441 * 1442 * The subdevice ID is of the form 0x00PS, where <P> is the number 1443 * of parallel ports and <S> is the number of serial ports. 1444 */ 1445 switch (dev->device) { 1446 case PCI_DEVICE_ID_NETMOS_9735: 1447 case PCI_DEVICE_ID_NETMOS_9745: 1448 case PCI_DEVICE_ID_NETMOS_9835: 1449 case PCI_DEVICE_ID_NETMOS_9845: 1450 case PCI_DEVICE_ID_NETMOS_9855: 1451 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1452 num_parallel) { 1453 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1454 "%u serial); changing class SERIAL to OTHER " 1455 "(use parport_serial)\n", 1456 dev->device, num_parallel, num_serial); 1457 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1458 (dev->class & 0xff); 1459 } 1460 } 1461 } 1462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1463 1464 static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1465 { 1466 u16 command, pmcsr; 1467 u8 __iomem *csr; 1468 u8 cmd_hi; 1469 int pm; 1470 1471 switch (dev->device) { 1472 /* PCI IDs taken from drivers/net/e100.c */ 1473 case 0x1029: 1474 case 0x1030 ... 0x1034: 1475 case 0x1038 ... 0x103E: 1476 case 0x1050 ... 0x1057: 1477 case 0x1059: 1478 case 0x1064 ... 0x106B: 1479 case 0x1091 ... 0x1095: 1480 case 0x1209: 1481 case 0x1229: 1482 case 0x2449: 1483 case 0x2459: 1484 case 0x245D: 1485 case 0x27DC: 1486 break; 1487 default: 1488 return; 1489 } 1490 1491 /* 1492 * Some firmware hands off the e100 with interrupts enabled, 1493 * which can cause a flood of interrupts if packets are 1494 * received before the driver attaches to the device. So 1495 * disable all e100 interrupts here. The driver will 1496 * re-enable them when it's ready. 1497 */ 1498 pci_read_config_word(dev, PCI_COMMAND, &command); 1499 1500 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1501 return; 1502 1503 /* 1504 * Check that the device is in the D0 power state. If it's not, 1505 * there is no point to look any further. 1506 */ 1507 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1508 if (pm) { 1509 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 1510 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1511 return; 1512 } 1513 1514 /* Convert from PCI bus to resource space. */ 1515 csr = ioremap(pci_resource_start(dev, 0), 8); 1516 if (!csr) { 1517 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1518 return; 1519 } 1520 1521 cmd_hi = readb(csr + 3); 1522 if (cmd_hi == 0) { 1523 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1524 "disabling\n"); 1525 writeb(1, csr + 3); 1526 } 1527 1528 iounmap(csr); 1529 } 1530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1531 1532 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1533 { 1534 /* rev 1 ncr53c810 chips don't set the class at all which means 1535 * they don't get their resources remapped. Fix that here. 1536 */ 1537 1538 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1539 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1540 dev->class = PCI_CLASS_STORAGE_SCSI; 1541 } 1542 } 1543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1544 1545 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1546 { 1547 while (f < end) { 1548 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1549 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1550 #ifdef DEBUG 1551 dev_dbg(&dev->dev, "calling "); 1552 print_fn_descriptor_symbol("%s\n", f->hook); 1553 #endif 1554 f->hook(dev); 1555 } 1556 f++; 1557 } 1558 } 1559 1560 extern struct pci_fixup __start_pci_fixups_early[]; 1561 extern struct pci_fixup __end_pci_fixups_early[]; 1562 extern struct pci_fixup __start_pci_fixups_header[]; 1563 extern struct pci_fixup __end_pci_fixups_header[]; 1564 extern struct pci_fixup __start_pci_fixups_final[]; 1565 extern struct pci_fixup __end_pci_fixups_final[]; 1566 extern struct pci_fixup __start_pci_fixups_enable[]; 1567 extern struct pci_fixup __end_pci_fixups_enable[]; 1568 extern struct pci_fixup __start_pci_fixups_resume[]; 1569 extern struct pci_fixup __end_pci_fixups_resume[]; 1570 extern struct pci_fixup __start_pci_fixups_resume_early[]; 1571 extern struct pci_fixup __end_pci_fixups_resume_early[]; 1572 extern struct pci_fixup __start_pci_fixups_suspend[]; 1573 extern struct pci_fixup __end_pci_fixups_suspend[]; 1574 1575 1576 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1577 { 1578 struct pci_fixup *start, *end; 1579 1580 switch(pass) { 1581 case pci_fixup_early: 1582 start = __start_pci_fixups_early; 1583 end = __end_pci_fixups_early; 1584 break; 1585 1586 case pci_fixup_header: 1587 start = __start_pci_fixups_header; 1588 end = __end_pci_fixups_header; 1589 break; 1590 1591 case pci_fixup_final: 1592 start = __start_pci_fixups_final; 1593 end = __end_pci_fixups_final; 1594 break; 1595 1596 case pci_fixup_enable: 1597 start = __start_pci_fixups_enable; 1598 end = __end_pci_fixups_enable; 1599 break; 1600 1601 case pci_fixup_resume: 1602 start = __start_pci_fixups_resume; 1603 end = __end_pci_fixups_resume; 1604 break; 1605 1606 case pci_fixup_resume_early: 1607 start = __start_pci_fixups_resume_early; 1608 end = __end_pci_fixups_resume_early; 1609 break; 1610 1611 case pci_fixup_suspend: 1612 start = __start_pci_fixups_suspend; 1613 end = __end_pci_fixups_suspend; 1614 break; 1615 1616 default: 1617 /* stupid compiler warning, you would think with an enum... */ 1618 return; 1619 } 1620 pci_do_fixups(dev, start, end); 1621 } 1622 EXPORT_SYMBOL(pci_fixup_device); 1623 1624 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1625 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1626 { 1627 u16 en1k; 1628 u8 io_base_lo, io_limit_lo; 1629 unsigned long base, limit; 1630 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1631 1632 pci_read_config_word(dev, 0x40, &en1k); 1633 1634 if (en1k & 0x200) { 1635 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1636 1637 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1638 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1639 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1640 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1641 1642 if (base <= limit) { 1643 res->start = base; 1644 res->end = limit + 0x3ff; 1645 } 1646 } 1647 } 1648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1649 1650 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 1651 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 1652 * in drivers/pci/setup-bus.c 1653 */ 1654 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 1655 { 1656 u16 en1k, iobl_adr, iobl_adr_1k; 1657 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1658 1659 pci_read_config_word(dev, 0x40, &en1k); 1660 1661 if (en1k & 0x200) { 1662 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 1663 1664 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1665 1666 if (iobl_adr != iobl_adr_1k) { 1667 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", 1668 iobl_adr,iobl_adr_1k); 1669 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1670 } 1671 } 1672 } 1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 1674 1675 /* Under some circumstances, AER is not linked with extended capabilities. 1676 * Force it to be linked by setting the corresponding control bit in the 1677 * config space. 1678 */ 1679 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1680 { 1681 uint8_t b; 1682 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1683 if (!(b & 0x20)) { 1684 pci_write_config_byte(dev, 0xf41, b | 0x20); 1685 dev_info(&dev->dev, 1686 "Linking AER extended capability\n"); 1687 } 1688 } 1689 } 1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1691 quirk_nvidia_ck804_pcie_aer_ext_cap); 1692 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1693 quirk_nvidia_ck804_pcie_aer_ext_cap); 1694 1695 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 1696 { 1697 /* 1698 * Disable PCI Bus Parking and PCI Master read caching on CX700 1699 * which causes unspecified timing errors with a VT6212L on the PCI 1700 * bus leading to USB2.0 packet loss. The defaults are that these 1701 * features are turned off but some BIOSes turn them on. 1702 */ 1703 1704 uint8_t b; 1705 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 1706 if (b & 0x40) { 1707 /* Turn off PCI Bus Parking */ 1708 pci_write_config_byte(dev, 0x76, b ^ 0x40); 1709 1710 dev_info(&dev->dev, 1711 "Disabling VIA CX700 PCI parking\n"); 1712 } 1713 } 1714 1715 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 1716 if (b != 0) { 1717 /* Turn off PCI Master read caching */ 1718 pci_write_config_byte(dev, 0x72, 0x0); 1719 1720 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 1721 pci_write_config_byte(dev, 0x75, 0x1); 1722 1723 /* Disable "Read FIFO Timer" */ 1724 pci_write_config_byte(dev, 0x77, 0x0); 1725 1726 dev_info(&dev->dev, 1727 "Disabling VIA CX700 PCI caching\n"); 1728 } 1729 } 1730 } 1731 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 1732 1733 /* 1734 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 1735 * VPD end tag will hang the device. This problem was initially 1736 * observed when a vpd entry was created in sysfs 1737 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 1738 * will dump 32k of data. Reading a full 32k will cause an access 1739 * beyond the VPD end tag causing the device to hang. Once the device 1740 * is hung, the bnx2 driver will not be able to reset the device. 1741 * We believe that it is legal to read beyond the end tag and 1742 * therefore the solution is to limit the read/write length. 1743 */ 1744 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 1745 { 1746 /* Only disable the VPD capability for 5706, 5708, and 5709 rev. A */ 1747 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 1748 (dev->device == PCI_DEVICE_ID_NX2_5708) || 1749 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 1750 (dev->revision & 0xf0) == 0x0)) { 1751 if (dev->vpd) 1752 dev->vpd->len = 0x80; 1753 } 1754 } 1755 1756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 1757 PCI_DEVICE_ID_NX2_5706, 1758 quirk_brcm_570x_limit_vpd); 1759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 1760 PCI_DEVICE_ID_NX2_5706S, 1761 quirk_brcm_570x_limit_vpd); 1762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 1763 PCI_DEVICE_ID_NX2_5708, 1764 quirk_brcm_570x_limit_vpd); 1765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 1766 PCI_DEVICE_ID_NX2_5708S, 1767 quirk_brcm_570x_limit_vpd); 1768 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 1769 PCI_DEVICE_ID_NX2_5709, 1770 quirk_brcm_570x_limit_vpd); 1771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 1772 PCI_DEVICE_ID_NX2_5709S, 1773 quirk_brcm_570x_limit_vpd); 1774 1775 #ifdef CONFIG_PCI_MSI 1776 /* Some chipsets do not support MSI. We cannot easily rely on setting 1777 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 1778 * some other busses controlled by the chipset even if Linux is not 1779 * aware of it. Instead of setting the flag on all busses in the 1780 * machine, simply disable MSI globally. 1781 */ 1782 static void __init quirk_disable_all_msi(struct pci_dev *dev) 1783 { 1784 pci_no_msi(); 1785 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 1786 } 1787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 1788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 1789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 1791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 1792 1793 /* Disable MSI on chipsets that are known to not support it */ 1794 static void __devinit quirk_disable_msi(struct pci_dev *dev) 1795 { 1796 if (dev->subordinate) { 1797 dev_warn(&dev->dev, "MSI quirk detected; " 1798 "subordinate MSI disabled\n"); 1799 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1800 } 1801 } 1802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 1803 1804 /* Go through the list of Hypertransport capabilities and 1805 * return 1 if a HT MSI capability is found and enabled */ 1806 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 1807 { 1808 int pos, ttl = 48; 1809 1810 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 1811 while (pos && ttl--) { 1812 u8 flags; 1813 1814 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 1815 &flags) == 0) 1816 { 1817 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 1818 flags & HT_MSI_FLAGS_ENABLE ? 1819 "enabled" : "disabled"); 1820 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 1821 } 1822 1823 pos = pci_find_next_ht_capability(dev, pos, 1824 HT_CAPTYPE_MSI_MAPPING); 1825 } 1826 return 0; 1827 } 1828 1829 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 1830 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 1831 { 1832 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 1833 dev_warn(&dev->dev, "MSI quirk detected; " 1834 "subordinate MSI disabled\n"); 1835 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1836 } 1837 } 1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 1839 quirk_msi_ht_cap); 1840 1841 1842 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 1843 * MSI are supported if the MSI capability set in any of these mappings. 1844 */ 1845 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 1846 { 1847 struct pci_dev *pdev; 1848 1849 if (!dev->subordinate) 1850 return; 1851 1852 /* check HT MSI cap on this chipset and the root one. 1853 * a single one having MSI is enough to be sure that MSI are supported. 1854 */ 1855 pdev = pci_get_slot(dev->bus, 0); 1856 if (!pdev) 1857 return; 1858 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 1859 dev_warn(&dev->dev, "MSI quirk detected; " 1860 "subordinate MSI disabled\n"); 1861 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1862 } 1863 pci_dev_put(pdev); 1864 } 1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1866 quirk_nvidia_ck804_msi_ht_cap); 1867 1868 /* Force enable MSI mapping capability on HT bridges */ 1869 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 1870 { 1871 int pos, ttl = 48; 1872 1873 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 1874 while (pos && ttl--) { 1875 u8 flags; 1876 1877 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 1878 &flags) == 0) { 1879 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 1880 1881 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 1882 flags | HT_MSI_FLAGS_ENABLE); 1883 } 1884 pos = pci_find_next_ht_capability(dev, pos, 1885 HT_CAPTYPE_MSI_MAPPING); 1886 } 1887 } 1888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 1889 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 1890 ht_enable_msi_mapping); 1891 1892 static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev) 1893 { 1894 struct pci_dev *host_bridge; 1895 int pos, ttl = 48; 1896 1897 /* 1898 * HT MSI mapping should be disabled on devices that are below 1899 * a non-Hypertransport host bridge. Locate the host bridge... 1900 */ 1901 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 1902 if (host_bridge == NULL) { 1903 dev_warn(&dev->dev, 1904 "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 1905 return; 1906 } 1907 1908 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 1909 if (pos != 0) { 1910 /* Host bridge is to HT */ 1911 ht_enable_msi_mapping(dev); 1912 return; 1913 } 1914 1915 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 1916 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 1917 while (pos && ttl--) { 1918 u8 flags; 1919 1920 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 1921 &flags) == 0) { 1922 dev_info(&dev->dev, "Disabling HT MSI mapping"); 1923 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 1924 flags & ~HT_MSI_FLAGS_ENABLE); 1925 } 1926 pos = pci_find_next_ht_capability(dev, pos, 1927 HT_CAPTYPE_MSI_MAPPING); 1928 } 1929 } 1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk); 1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk); 1932 1933 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) 1934 { 1935 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 1936 } 1937 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 1938 { 1939 struct pci_dev *p; 1940 1941 /* SB700 MSI issue will be fixed at HW level from revision A21, 1942 * we need check PCI REVISION ID of SMBus controller to get SB700 1943 * revision. 1944 */ 1945 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1946 NULL); 1947 if (!p) 1948 return; 1949 1950 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 1951 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 1952 pci_dev_put(p); 1953 } 1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1955 PCI_DEVICE_ID_TIGON3_5780, 1956 quirk_msi_intx_disable_bug); 1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1958 PCI_DEVICE_ID_TIGON3_5780S, 1959 quirk_msi_intx_disable_bug); 1960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1961 PCI_DEVICE_ID_TIGON3_5714, 1962 quirk_msi_intx_disable_bug); 1963 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1964 PCI_DEVICE_ID_TIGON3_5714S, 1965 quirk_msi_intx_disable_bug); 1966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1967 PCI_DEVICE_ID_TIGON3_5715, 1968 quirk_msi_intx_disable_bug); 1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1970 PCI_DEVICE_ID_TIGON3_5715S, 1971 quirk_msi_intx_disable_bug); 1972 1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 1974 quirk_msi_intx_disable_ati_bug); 1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 1976 quirk_msi_intx_disable_ati_bug); 1977 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 1978 quirk_msi_intx_disable_ati_bug); 1979 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 1980 quirk_msi_intx_disable_ati_bug); 1981 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 1982 quirk_msi_intx_disable_ati_bug); 1983 1984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 1985 quirk_msi_intx_disable_bug); 1986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 1987 quirk_msi_intx_disable_bug); 1988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 1989 quirk_msi_intx_disable_bug); 1990 1991 #endif /* CONFIG_PCI_MSI */ 1992