1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/acpi.h> 21 #include <linux/kallsyms.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 29 #include "pci.h" 30 31 /* 32 * Decoding should be disabled for a PCI device during BAR sizing to avoid 33 * conflict. But doing so may cause problems on host bridge and perhaps other 34 * key system devices. For devices that need to have mmio decoding always-on, 35 * we need to set the dev->mmio_always_on bit. 36 */ 37 static void quirk_mmio_always_on(struct pci_dev *dev) 38 { 39 dev->mmio_always_on = 1; 40 } 41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 43 44 /* The Mellanox Tavor device gives false positive parity errors 45 * Mark this device with a broken_parity_status, to allow 46 * PCI scanning code to "skip" this now blacklisted device. 47 */ 48 static void quirk_mellanox_tavor(struct pci_dev *dev) 49 { 50 dev->broken_parity_status = 1; /* This device gives false positives */ 51 } 52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 54 55 /* Deal with broken BIOSes that neglect to enable passive release, 56 which can cause problems in combination with the 82441FX/PPro MTRRs */ 57 static void quirk_passive_release(struct pci_dev *dev) 58 { 59 struct pci_dev *d = NULL; 60 unsigned char dlc; 61 62 /* We have to make sure a particular bit is set in the PIIX3 63 ISA bridge, so we have to go out and find it. */ 64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 65 pci_read_config_byte(d, 0x82, &dlc); 66 if (!(dlc & 1<<1)) { 67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 68 dlc |= 1<<1; 69 pci_write_config_byte(d, 0x82, dlc); 70 } 71 } 72 } 73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 75 76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 77 but VIA don't answer queries. If you happen to have good contacts at VIA 78 ask them for me please -- Alan 79 80 This appears to be BIOS not version dependent. So presumably there is a 81 chipset level fix */ 82 83 static void quirk_isa_dma_hangs(struct pci_dev *dev) 84 { 85 if (!isa_dma_bridge_buggy) { 86 isa_dma_bridge_buggy = 1; 87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 88 } 89 } 90 /* 91 * Its not totally clear which chipsets are the problematic ones 92 * We know 82C586 and 82C596 variants are affected. 93 */ 94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 101 102 /* 103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 104 * for some HT machines to use C4 w/o hanging. 105 */ 106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 107 { 108 u32 pmbase; 109 u16 pm1a; 110 111 pci_read_config_dword(dev, 0x40, &pmbase); 112 pmbase = pmbase & 0xff80; 113 pm1a = inw(pmbase); 114 115 if (pm1a & 0x10) { 116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 117 outw(0x10, pmbase); 118 } 119 } 120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 121 122 /* 123 * Chipsets where PCI->PCI transfers vanish or hang 124 */ 125 static void quirk_nopcipci(struct pci_dev *dev) 126 { 127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 129 pci_pci_problems |= PCIPCI_FAIL; 130 } 131 } 132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 134 135 static void quirk_nopciamd(struct pci_dev *dev) 136 { 137 u8 rev; 138 pci_read_config_byte(dev, 0x08, &rev); 139 if (rev == 0x13) { 140 /* Erratum 24 */ 141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 142 pci_pci_problems |= PCIAGP_FAIL; 143 } 144 } 145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 146 147 /* 148 * Triton requires workarounds to be used by the drivers 149 */ 150 static void quirk_triton(struct pci_dev *dev) 151 { 152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 154 pci_pci_problems |= PCIPCI_TRITON; 155 } 156 } 157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 161 162 /* 163 * VIA Apollo KT133 needs PCI latency patch 164 * Made according to a windows driver based patch by George E. Breese 165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 166 * and http://www.georgebreese.com/net/software/#PCI 167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 168 * the info on which Mr Breese based his work. 169 * 170 * Updated based on further information from the site and also on 171 * information provided by VIA 172 */ 173 static void quirk_vialatency(struct pci_dev *dev) 174 { 175 struct pci_dev *p; 176 u8 busarb; 177 /* Ok we have a potential problem chipset here. Now see if we have 178 a buggy southbridge */ 179 180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 181 if (p != NULL) { 182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 183 /* Check for buggy part revisions */ 184 if (p->revision < 0x40 || p->revision > 0x42) 185 goto exit; 186 } else { 187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 188 if (p == NULL) /* No problem parts */ 189 goto exit; 190 /* Check for buggy part revisions */ 191 if (p->revision < 0x10 || p->revision > 0x12) 192 goto exit; 193 } 194 195 /* 196 * Ok we have the problem. Now set the PCI master grant to 197 * occur every master grant. The apparent bug is that under high 198 * PCI load (quite common in Linux of course) you can get data 199 * loss when the CPU is held off the bus for 3 bus master requests 200 * This happens to include the IDE controllers.... 201 * 202 * VIA only apply this fix when an SB Live! is present but under 203 * both Linux and Windows this isn't enough, and we have seen 204 * corruption without SB Live! but with things like 3 UDMA IDE 205 * controllers. So we ignore that bit of the VIA recommendation.. 206 */ 207 208 pci_read_config_byte(dev, 0x76, &busarb); 209 /* Set bit 4 and bi 5 of byte 76 to 0x01 210 "Master priority rotation on every PCI master grant */ 211 busarb &= ~(1<<5); 212 busarb |= (1<<4); 213 pci_write_config_byte(dev, 0x76, busarb); 214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 215 exit: 216 pci_dev_put(p); 217 } 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 221 /* Must restore this on a resume from RAM */ 222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 225 226 /* 227 * VIA Apollo VP3 needs ETBF on BT848/878 228 */ 229 static void quirk_viaetbf(struct pci_dev *dev) 230 { 231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 233 pci_pci_problems |= PCIPCI_VIAETBF; 234 } 235 } 236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 237 238 static void quirk_vsfx(struct pci_dev *dev) 239 { 240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 242 pci_pci_problems |= PCIPCI_VSFX; 243 } 244 } 245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 246 247 /* 248 * Ali Magik requires workarounds to be used by the drivers 249 * that DMA to AGP space. Latency must be set to 0xA and triton 250 * workaround applied too 251 * [Info kindly provided by ALi] 252 */ 253 static void quirk_alimagik(struct pci_dev *dev) 254 { 255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 258 } 259 } 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 262 263 /* 264 * Natoma has some interesting boundary conditions with Zoran stuff 265 * at least 266 */ 267 static void quirk_natoma(struct pci_dev *dev) 268 { 269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 271 pci_pci_problems |= PCIPCI_NATOMA; 272 } 273 } 274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 280 281 /* 282 * This chip can cause PCI parity errors if config register 0xA0 is read 283 * while DMAs are occurring. 284 */ 285 static void quirk_citrine(struct pci_dev *dev) 286 { 287 dev->cfg_size = 0xA0; 288 } 289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 290 291 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 292 static void quirk_extend_bar_to_page(struct pci_dev *dev) 293 { 294 int i; 295 296 for (i = 0; i < PCI_STD_RESOURCE_END; i++) { 297 struct resource *r = &dev->resource[i]; 298 299 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 300 r->end = PAGE_SIZE - 1; 301 r->start = 0; 302 r->flags |= IORESOURCE_UNSET; 303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 304 i, r); 305 } 306 } 307 } 308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 309 310 /* 311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 312 * If it's needed, re-allocate the region. 313 */ 314 static void quirk_s3_64M(struct pci_dev *dev) 315 { 316 struct resource *r = &dev->resource[0]; 317 318 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 319 r->flags |= IORESOURCE_UNSET; 320 r->start = 0; 321 r->end = 0x3ffffff; 322 } 323 } 324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 326 327 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 328 const char *name) 329 { 330 u32 region; 331 struct pci_bus_region bus_region; 332 struct resource *res = dev->resource + pos; 333 334 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 335 336 if (!region) 337 return; 338 339 res->name = pci_name(dev); 340 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 341 res->flags |= 342 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 343 region &= ~(size - 1); 344 345 /* Convert from PCI bus to resource space */ 346 bus_region.start = region; 347 bus_region.end = region + size - 1; 348 pcibios_bus_to_resource(dev->bus, res, &bus_region); 349 350 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 351 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 352 } 353 354 /* 355 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 356 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 357 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 358 * (which conflicts w/ BAR1's memory range). 359 * 360 * CS553x's ISA PCI BARs may also be read-only (ref: 361 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 362 */ 363 static void quirk_cs5536_vsa(struct pci_dev *dev) 364 { 365 static char *name = "CS5536 ISA bridge"; 366 367 if (pci_resource_len(dev, 0) != 8) { 368 quirk_io(dev, 0, 8, name); /* SMB */ 369 quirk_io(dev, 1, 256, name); /* GPIO */ 370 quirk_io(dev, 2, 64, name); /* MFGPT */ 371 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 372 name); 373 } 374 } 375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 376 377 static void quirk_io_region(struct pci_dev *dev, int port, 378 unsigned size, int nr, const char *name) 379 { 380 u16 region; 381 struct pci_bus_region bus_region; 382 struct resource *res = dev->resource + nr; 383 384 pci_read_config_word(dev, port, ®ion); 385 region &= ~(size - 1); 386 387 if (!region) 388 return; 389 390 res->name = pci_name(dev); 391 res->flags = IORESOURCE_IO; 392 393 /* Convert from PCI bus to resource space */ 394 bus_region.start = region; 395 bus_region.end = region + size - 1; 396 pcibios_bus_to_resource(dev->bus, res, &bus_region); 397 398 if (!pci_claim_resource(dev, nr)) 399 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 400 } 401 402 /* 403 * ATI Northbridge setups MCE the processor if you even 404 * read somewhere between 0x3b0->0x3bb or read 0x3d3 405 */ 406 static void quirk_ati_exploding_mce(struct pci_dev *dev) 407 { 408 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 409 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 410 request_region(0x3b0, 0x0C, "RadeonIGP"); 411 request_region(0x3d3, 0x01, "RadeonIGP"); 412 } 413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 414 415 /* 416 * In the AMD NL platform, this device ([1022:7912]) has a class code of 417 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 418 * claim it. 419 * But the dwc3 driver is a more specific driver for this device, and we'd 420 * prefer to use it instead of xhci. To prevent xhci from claiming the 421 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 422 * defines as "USB device (not host controller)". The dwc3 driver can then 423 * claim it based on its Vendor and Device ID. 424 */ 425 static void quirk_amd_nl_class(struct pci_dev *pdev) 426 { 427 /* 428 * Use 'USB Device' (0x0c03fe) instead of PCI header provided 429 */ 430 pdev->class = 0x0c03fe; 431 } 432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 433 quirk_amd_nl_class); 434 435 /* 436 * Let's make the southbridge information explicit instead 437 * of having to worry about people probing the ACPI areas, 438 * for example.. (Yes, it happens, and if you read the wrong 439 * ACPI register it will put the machine to sleep with no 440 * way of waking it up again. Bummer). 441 * 442 * ALI M7101: Two IO regions pointed to by words at 443 * 0xE0 (64 bytes of ACPI registers) 444 * 0xE2 (32 bytes of SMB registers) 445 */ 446 static void quirk_ali7101_acpi(struct pci_dev *dev) 447 { 448 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 449 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 450 } 451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 452 453 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 454 { 455 u32 devres; 456 u32 mask, size, base; 457 458 pci_read_config_dword(dev, port, &devres); 459 if ((devres & enable) != enable) 460 return; 461 mask = (devres >> 16) & 15; 462 base = devres & 0xffff; 463 size = 16; 464 for (;;) { 465 unsigned bit = size >> 1; 466 if ((bit & mask) == bit) 467 break; 468 size = bit; 469 } 470 /* 471 * For now we only print it out. Eventually we'll want to 472 * reserve it (at least if it's in the 0x1000+ range), but 473 * let's get enough confirmation reports first. 474 */ 475 base &= -size; 476 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 477 base + size - 1); 478 } 479 480 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 481 { 482 u32 devres; 483 u32 mask, size, base; 484 485 pci_read_config_dword(dev, port, &devres); 486 if ((devres & enable) != enable) 487 return; 488 base = devres & 0xffff0000; 489 mask = (devres & 0x3f) << 16; 490 size = 128 << 16; 491 for (;;) { 492 unsigned bit = size >> 1; 493 if ((bit & mask) == bit) 494 break; 495 size = bit; 496 } 497 /* 498 * For now we only print it out. Eventually we'll want to 499 * reserve it, but let's get enough confirmation reports first. 500 */ 501 base &= -size; 502 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 503 base + size - 1); 504 } 505 506 /* 507 * PIIX4 ACPI: Two IO regions pointed to by longwords at 508 * 0x40 (64 bytes of ACPI registers) 509 * 0x90 (16 bytes of SMB registers) 510 * and a few strange programmable PIIX4 device resources. 511 */ 512 static void quirk_piix4_acpi(struct pci_dev *dev) 513 { 514 u32 res_a; 515 516 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 517 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 518 519 /* Device resource A has enables for some of the other ones */ 520 pci_read_config_dword(dev, 0x5c, &res_a); 521 522 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 523 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 524 525 /* Device resource D is just bitfields for static resources */ 526 527 /* Device 12 enabled? */ 528 if (res_a & (1 << 29)) { 529 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 530 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 531 } 532 /* Device 13 enabled? */ 533 if (res_a & (1 << 30)) { 534 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 535 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 536 } 537 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 538 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 539 } 540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 542 543 #define ICH_PMBASE 0x40 544 #define ICH_ACPI_CNTL 0x44 545 #define ICH4_ACPI_EN 0x10 546 #define ICH6_ACPI_EN 0x80 547 #define ICH4_GPIOBASE 0x58 548 #define ICH4_GPIO_CNTL 0x5c 549 #define ICH4_GPIO_EN 0x10 550 #define ICH6_GPIOBASE 0x48 551 #define ICH6_GPIO_CNTL 0x4c 552 #define ICH6_GPIO_EN 0x10 553 554 /* 555 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 556 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 557 * 0x58 (64 bytes of GPIO I/O space) 558 */ 559 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 560 { 561 u8 enable; 562 563 /* 564 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 565 * with low legacy (and fixed) ports. We don't know the decoding 566 * priority and can't tell whether the legacy device or the one created 567 * here is really at that address. This happens on boards with broken 568 * BIOSes. 569 */ 570 571 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 572 if (enable & ICH4_ACPI_EN) 573 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 574 "ICH4 ACPI/GPIO/TCO"); 575 576 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 577 if (enable & ICH4_GPIO_EN) 578 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 579 "ICH4 GPIO"); 580 } 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 591 592 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 593 { 594 u8 enable; 595 596 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 597 if (enable & ICH6_ACPI_EN) 598 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 599 "ICH6 ACPI/GPIO/TCO"); 600 601 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 602 if (enable & ICH6_GPIO_EN) 603 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 604 "ICH6 GPIO"); 605 } 606 607 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 608 { 609 u32 val; 610 u32 size, base; 611 612 pci_read_config_dword(dev, reg, &val); 613 614 /* Enabled? */ 615 if (!(val & 1)) 616 return; 617 base = val & 0xfffc; 618 if (dynsize) { 619 /* 620 * This is not correct. It is 16, 32 or 64 bytes depending on 621 * register D31:F0:ADh bits 5:4. 622 * 623 * But this gets us at least _part_ of it. 624 */ 625 size = 16; 626 } else { 627 size = 128; 628 } 629 base &= ~(size-1); 630 631 /* Just print it out for now. We should reserve it after more debugging */ 632 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 633 } 634 635 static void quirk_ich6_lpc(struct pci_dev *dev) 636 { 637 /* Shared ACPI/GPIO decode with all ICH6+ */ 638 ich6_lpc_acpi_gpio(dev); 639 640 /* ICH6-specific generic IO decode */ 641 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 642 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 643 } 644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 646 647 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 648 { 649 u32 val; 650 u32 mask, base; 651 652 pci_read_config_dword(dev, reg, &val); 653 654 /* Enabled? */ 655 if (!(val & 1)) 656 return; 657 658 /* 659 * IO base in bits 15:2, mask in bits 23:18, both 660 * are dword-based 661 */ 662 base = val & 0xfffc; 663 mask = (val >> 16) & 0xfc; 664 mask |= 3; 665 666 /* Just print it out for now. We should reserve it after more debugging */ 667 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 668 } 669 670 /* ICH7-10 has the same common LPC generic IO decode registers */ 671 static void quirk_ich7_lpc(struct pci_dev *dev) 672 { 673 /* We share the common ACPI/GPIO decode with ICH6 */ 674 ich6_lpc_acpi_gpio(dev); 675 676 /* And have 4 ICH7+ generic decodes */ 677 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 678 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 679 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 680 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 681 } 682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 685 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 695 696 /* 697 * VIA ACPI: One IO region pointed to by longword at 698 * 0x48 or 0x20 (256 bytes of ACPI registers) 699 */ 700 static void quirk_vt82c586_acpi(struct pci_dev *dev) 701 { 702 if (dev->revision & 0x10) 703 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 704 "vt82c586 ACPI"); 705 } 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 707 708 /* 709 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 710 * 0x48 (256 bytes of ACPI registers) 711 * 0x70 (128 bytes of hardware monitoring register) 712 * 0x90 (16 bytes of SMB registers) 713 */ 714 static void quirk_vt82c686_acpi(struct pci_dev *dev) 715 { 716 quirk_vt82c586_acpi(dev); 717 718 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 719 "vt82c686 HW-mon"); 720 721 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 722 } 723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 724 725 /* 726 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 727 * 0x88 (128 bytes of power management registers) 728 * 0xd0 (16 bytes of SMB registers) 729 */ 730 static void quirk_vt8235_acpi(struct pci_dev *dev) 731 { 732 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 733 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 734 } 735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 736 737 /* 738 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 739 * Disable fast back-to-back on the secondary bus segment 740 */ 741 static void quirk_xio2000a(struct pci_dev *dev) 742 { 743 struct pci_dev *pdev; 744 u16 command; 745 746 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 747 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 748 pci_read_config_word(pdev, PCI_COMMAND, &command); 749 if (command & PCI_COMMAND_FAST_BACK) 750 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 751 } 752 } 753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 754 quirk_xio2000a); 755 756 #ifdef CONFIG_X86_IO_APIC 757 758 #include <asm/io_apic.h> 759 760 /* 761 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 762 * devices to the external APIC. 763 * 764 * TODO: When we have device-specific interrupt routers, 765 * this code will go away from quirks. 766 */ 767 static void quirk_via_ioapic(struct pci_dev *dev) 768 { 769 u8 tmp; 770 771 if (nr_ioapics < 1) 772 tmp = 0; /* nothing routed to external APIC */ 773 else 774 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 775 776 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 777 tmp == 0 ? "Disa" : "Ena"); 778 779 /* Offset 0x58: External APIC IRQ output control */ 780 pci_write_config_byte(dev, 0x58, tmp); 781 } 782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 783 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 784 785 /* 786 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 787 * This leads to doubled level interrupt rates. 788 * Set this bit to get rid of cycle wastage. 789 * Otherwise uncritical. 790 */ 791 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 792 { 793 u8 misc_control2; 794 #define BYPASS_APIC_DEASSERT 8 795 796 pci_read_config_byte(dev, 0x5B, &misc_control2); 797 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 798 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 799 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 800 } 801 } 802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 803 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 804 805 /* 806 * The AMD io apic can hang the box when an apic irq is masked. 807 * We check all revs >= B0 (yet not in the pre production!) as the bug 808 * is currently marked NoFix 809 * 810 * We have multiple reports of hangs with this chipset that went away with 811 * noapic specified. For the moment we assume it's the erratum. We may be wrong 812 * of course. However the advice is demonstrably good even if so.. 813 */ 814 static void quirk_amd_ioapic(struct pci_dev *dev) 815 { 816 if (dev->revision >= 0x02) { 817 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 818 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 819 } 820 } 821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 822 #endif /* CONFIG_X86_IO_APIC */ 823 824 /* 825 * Some settings of MMRBC can lead to data corruption so block changes. 826 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 827 */ 828 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 829 { 830 if (dev->subordinate && dev->revision <= 0x12) { 831 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 832 dev->revision); 833 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 834 } 835 } 836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 837 838 /* 839 * FIXME: it is questionable that quirk_via_acpi 840 * is needed. It shows up as an ISA bridge, and does not 841 * support the PCI_INTERRUPT_LINE register at all. Therefore 842 * it seems like setting the pci_dev's 'irq' to the 843 * value of the ACPI SCI interrupt is only done for convenience. 844 * -jgarzik 845 */ 846 static void quirk_via_acpi(struct pci_dev *d) 847 { 848 /* 849 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 850 */ 851 u8 irq; 852 pci_read_config_byte(d, 0x42, &irq); 853 irq &= 0xf; 854 if (irq && (irq != 2)) 855 d->irq = irq; 856 } 857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 859 860 861 /* 862 * VIA bridges which have VLink 863 */ 864 865 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 866 867 static void quirk_via_bridge(struct pci_dev *dev) 868 { 869 /* See what bridge we have and find the device ranges */ 870 switch (dev->device) { 871 case PCI_DEVICE_ID_VIA_82C686: 872 /* The VT82C686 is special, it attaches to PCI and can have 873 any device number. All its subdevices are functions of 874 that single device. */ 875 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 876 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 877 break; 878 case PCI_DEVICE_ID_VIA_8237: 879 case PCI_DEVICE_ID_VIA_8237A: 880 via_vlink_dev_lo = 15; 881 break; 882 case PCI_DEVICE_ID_VIA_8235: 883 via_vlink_dev_lo = 16; 884 break; 885 case PCI_DEVICE_ID_VIA_8231: 886 case PCI_DEVICE_ID_VIA_8233_0: 887 case PCI_DEVICE_ID_VIA_8233A: 888 case PCI_DEVICE_ID_VIA_8233C_0: 889 via_vlink_dev_lo = 17; 890 break; 891 } 892 } 893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 901 902 /** 903 * quirk_via_vlink - VIA VLink IRQ number update 904 * @dev: PCI device 905 * 906 * If the device we are dealing with is on a PIC IRQ we need to 907 * ensure that the IRQ line register which usually is not relevant 908 * for PCI cards, is actually written so that interrupts get sent 909 * to the right place. 910 * We only do this on systems where a VIA south bridge was detected, 911 * and only for VIA devices on the motherboard (see quirk_via_bridge 912 * above). 913 */ 914 915 static void quirk_via_vlink(struct pci_dev *dev) 916 { 917 u8 irq, new_irq; 918 919 /* Check if we have VLink at all */ 920 if (via_vlink_dev_lo == -1) 921 return; 922 923 new_irq = dev->irq; 924 925 /* Don't quirk interrupts outside the legacy IRQ range */ 926 if (!new_irq || new_irq > 15) 927 return; 928 929 /* Internal device ? */ 930 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 931 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 932 return; 933 934 /* This is an internal VLink device on a PIC interrupt. The BIOS 935 ought to have set this but may not have, so we redo it */ 936 937 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 938 if (new_irq != irq) { 939 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 940 irq, new_irq); 941 udelay(15); /* unknown if delay really needed */ 942 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 943 } 944 } 945 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 946 947 /* 948 * VIA VT82C598 has its device ID settable and many BIOSes 949 * set it to the ID of VT82C597 for backward compatibility. 950 * We need to switch it off to be able to recognize the real 951 * type of the chip. 952 */ 953 static void quirk_vt82c598_id(struct pci_dev *dev) 954 { 955 pci_write_config_byte(dev, 0xfc, 0); 956 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 957 } 958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 959 960 /* 961 * CardBus controllers have a legacy base address that enables them 962 * to respond as i82365 pcmcia controllers. We don't want them to 963 * do this even if the Linux CardBus driver is not loaded, because 964 * the Linux i82365 driver does not (and should not) handle CardBus. 965 */ 966 static void quirk_cardbus_legacy(struct pci_dev *dev) 967 { 968 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 969 } 970 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 971 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 972 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 973 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 974 975 /* 976 * Following the PCI ordering rules is optional on the AMD762. I'm not 977 * sure what the designers were smoking but let's not inhale... 978 * 979 * To be fair to AMD, it follows the spec by default, its BIOS people 980 * who turn it off! 981 */ 982 static void quirk_amd_ordering(struct pci_dev *dev) 983 { 984 u32 pcic; 985 pci_read_config_dword(dev, 0x4C, &pcic); 986 if ((pcic & 6) != 6) { 987 pcic |= 6; 988 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 989 pci_write_config_dword(dev, 0x4C, pcic); 990 pci_read_config_dword(dev, 0x84, &pcic); 991 pcic |= (1 << 23); /* Required in this mode */ 992 pci_write_config_dword(dev, 0x84, pcic); 993 } 994 } 995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 996 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 997 998 /* 999 * DreamWorks provided workaround for Dunord I-3000 problem 1000 * 1001 * This card decodes and responds to addresses not apparently 1002 * assigned to it. We force a larger allocation to ensure that 1003 * nothing gets put too close to it. 1004 */ 1005 static void quirk_dunord(struct pci_dev *dev) 1006 { 1007 struct resource *r = &dev->resource[1]; 1008 1009 r->flags |= IORESOURCE_UNSET; 1010 r->start = 0; 1011 r->end = 0xffffff; 1012 } 1013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1014 1015 /* 1016 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1017 * is subtractive decoding (transparent), and does indicate this 1018 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1019 * instead of 0x01. 1020 */ 1021 static void quirk_transparent_bridge(struct pci_dev *dev) 1022 { 1023 dev->transparent = 1; 1024 } 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1027 1028 /* 1029 * Common misconfiguration of the MediaGX/Geode PCI master that will 1030 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1031 * datasheets found at http://www.national.com/analog for info on what 1032 * these bits do. <christer@weinigel.se> 1033 */ 1034 static void quirk_mediagx_master(struct pci_dev *dev) 1035 { 1036 u8 reg; 1037 1038 pci_read_config_byte(dev, 0x41, ®); 1039 if (reg & 2) { 1040 reg &= ~2; 1041 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1042 reg); 1043 pci_write_config_byte(dev, 0x41, reg); 1044 } 1045 } 1046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1047 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1048 1049 /* 1050 * Ensure C0 rev restreaming is off. This is normally done by 1051 * the BIOS but in the odd case it is not the results are corruption 1052 * hence the presence of a Linux check 1053 */ 1054 static void quirk_disable_pxb(struct pci_dev *pdev) 1055 { 1056 u16 config; 1057 1058 if (pdev->revision != 0x04) /* Only C0 requires this */ 1059 return; 1060 pci_read_config_word(pdev, 0x40, &config); 1061 if (config & (1<<6)) { 1062 config &= ~(1<<6); 1063 pci_write_config_word(pdev, 0x40, config); 1064 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1065 } 1066 } 1067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1068 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1069 1070 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1071 { 1072 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1073 u8 tmp; 1074 1075 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1076 if (tmp == 0x01) { 1077 pci_read_config_byte(pdev, 0x40, &tmp); 1078 pci_write_config_byte(pdev, 0x40, tmp|1); 1079 pci_write_config_byte(pdev, 0x9, 1); 1080 pci_write_config_byte(pdev, 0xa, 6); 1081 pci_write_config_byte(pdev, 0x40, tmp); 1082 1083 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1084 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1085 } 1086 } 1087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1088 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1090 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1094 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1095 1096 /* 1097 * Serverworks CSB5 IDE does not fully support native mode 1098 */ 1099 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1100 { 1101 u8 prog; 1102 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1103 if (prog & 5) { 1104 prog &= ~5; 1105 pdev->class &= ~5; 1106 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1107 /* PCI layer will sort out resources */ 1108 } 1109 } 1110 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1111 1112 /* 1113 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1114 */ 1115 static void quirk_ide_samemode(struct pci_dev *pdev) 1116 { 1117 u8 prog; 1118 1119 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1120 1121 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1122 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1123 prog &= ~5; 1124 pdev->class &= ~5; 1125 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1126 } 1127 } 1128 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1129 1130 /* 1131 * Some ATA devices break if put into D3 1132 */ 1133 1134 static void quirk_no_ata_d3(struct pci_dev *pdev) 1135 { 1136 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1137 } 1138 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1139 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1140 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1141 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1142 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1143 /* ALi loses some register settings that we cannot then restore */ 1144 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1145 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1146 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1147 occur when mode detecting */ 1148 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1149 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1150 1151 /* This was originally an Alpha specific thing, but it really fits here. 1152 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1153 */ 1154 static void quirk_eisa_bridge(struct pci_dev *dev) 1155 { 1156 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1157 } 1158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1159 1160 1161 /* 1162 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1163 * is not activated. The myth is that Asus said that they do not want the 1164 * users to be irritated by just another PCI Device in the Win98 device 1165 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1166 * package 2.7.0 for details) 1167 * 1168 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1169 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1170 * becomes necessary to do this tweak in two steps -- the chosen trigger 1171 * is either the Host bridge (preferred) or on-board VGA controller. 1172 * 1173 * Note that we used to unhide the SMBus that way on Toshiba laptops 1174 * (Satellite A40 and Tecra M2) but then found that the thermal management 1175 * was done by SMM code, which could cause unsynchronized concurrent 1176 * accesses to the SMBus registers, with potentially bad effects. Thus you 1177 * should be very careful when adding new entries: if SMM is accessing the 1178 * Intel SMBus, this is a very good reason to leave it hidden. 1179 * 1180 * Likewise, many recent laptops use ACPI for thermal management. If the 1181 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1182 * natively, and keeping the SMBus hidden is the right thing to do. If you 1183 * are about to add an entry in the table below, please first disassemble 1184 * the DSDT and double-check that there is no code accessing the SMBus. 1185 */ 1186 static int asus_hides_smbus; 1187 1188 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1189 { 1190 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1191 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1192 switch (dev->subsystem_device) { 1193 case 0x8025: /* P4B-LX */ 1194 case 0x8070: /* P4B */ 1195 case 0x8088: /* P4B533 */ 1196 case 0x1626: /* L3C notebook */ 1197 asus_hides_smbus = 1; 1198 } 1199 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1200 switch (dev->subsystem_device) { 1201 case 0x80b1: /* P4GE-V */ 1202 case 0x80b2: /* P4PE */ 1203 case 0x8093: /* P4B533-V */ 1204 asus_hides_smbus = 1; 1205 } 1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1207 switch (dev->subsystem_device) { 1208 case 0x8030: /* P4T533 */ 1209 asus_hides_smbus = 1; 1210 } 1211 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1212 switch (dev->subsystem_device) { 1213 case 0x8070: /* P4G8X Deluxe */ 1214 asus_hides_smbus = 1; 1215 } 1216 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1217 switch (dev->subsystem_device) { 1218 case 0x80c9: /* PU-DLS */ 1219 asus_hides_smbus = 1; 1220 } 1221 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1222 switch (dev->subsystem_device) { 1223 case 0x1751: /* M2N notebook */ 1224 case 0x1821: /* M5N notebook */ 1225 case 0x1897: /* A6L notebook */ 1226 asus_hides_smbus = 1; 1227 } 1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1229 switch (dev->subsystem_device) { 1230 case 0x184b: /* W1N notebook */ 1231 case 0x186a: /* M6Ne notebook */ 1232 asus_hides_smbus = 1; 1233 } 1234 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1235 switch (dev->subsystem_device) { 1236 case 0x80f2: /* P4P800-X */ 1237 asus_hides_smbus = 1; 1238 } 1239 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1240 switch (dev->subsystem_device) { 1241 case 0x1882: /* M6V notebook */ 1242 case 0x1977: /* A6VA notebook */ 1243 asus_hides_smbus = 1; 1244 } 1245 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1246 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1247 switch (dev->subsystem_device) { 1248 case 0x088C: /* HP Compaq nc8000 */ 1249 case 0x0890: /* HP Compaq nc6000 */ 1250 asus_hides_smbus = 1; 1251 } 1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1253 switch (dev->subsystem_device) { 1254 case 0x12bc: /* HP D330L */ 1255 case 0x12bd: /* HP D530 */ 1256 case 0x006a: /* HP Compaq nx9500 */ 1257 asus_hides_smbus = 1; 1258 } 1259 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1260 switch (dev->subsystem_device) { 1261 case 0x12bf: /* HP xw4100 */ 1262 asus_hides_smbus = 1; 1263 } 1264 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1265 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1266 switch (dev->subsystem_device) { 1267 case 0xC00C: /* Samsung P35 notebook */ 1268 asus_hides_smbus = 1; 1269 } 1270 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1271 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1272 switch (dev->subsystem_device) { 1273 case 0x0058: /* Compaq Evo N620c */ 1274 asus_hides_smbus = 1; 1275 } 1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1277 switch (dev->subsystem_device) { 1278 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1279 /* Motherboard doesn't have Host bridge 1280 * subvendor/subdevice IDs, therefore checking 1281 * its on-board VGA controller */ 1282 asus_hides_smbus = 1; 1283 } 1284 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1285 switch (dev->subsystem_device) { 1286 case 0x00b8: /* Compaq Evo D510 CMT */ 1287 case 0x00b9: /* Compaq Evo D510 SFF */ 1288 case 0x00ba: /* Compaq Evo D510 USDT */ 1289 /* Motherboard doesn't have Host bridge 1290 * subvendor/subdevice IDs and on-board VGA 1291 * controller is disabled if an AGP card is 1292 * inserted, therefore checking USB UHCI 1293 * Controller #1 */ 1294 asus_hides_smbus = 1; 1295 } 1296 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1297 switch (dev->subsystem_device) { 1298 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1299 /* Motherboard doesn't have host bridge 1300 * subvendor/subdevice IDs, therefore checking 1301 * its on-board VGA controller */ 1302 asus_hides_smbus = 1; 1303 } 1304 } 1305 } 1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1316 1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1320 1321 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1322 { 1323 u16 val; 1324 1325 if (likely(!asus_hides_smbus)) 1326 return; 1327 1328 pci_read_config_word(dev, 0xF2, &val); 1329 if (val & 0x8) { 1330 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1331 pci_read_config_word(dev, 0xF2, &val); 1332 if (val & 0x8) 1333 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1334 val); 1335 else 1336 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1337 } 1338 } 1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1346 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1348 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1349 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1350 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1351 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1352 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1353 1354 /* It appears we just have one such device. If not, we have a warning */ 1355 static void __iomem *asus_rcba_base; 1356 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1357 { 1358 u32 rcba; 1359 1360 if (likely(!asus_hides_smbus)) 1361 return; 1362 WARN_ON(asus_rcba_base); 1363 1364 pci_read_config_dword(dev, 0xF0, &rcba); 1365 /* use bits 31:14, 16 kB aligned */ 1366 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1367 if (asus_rcba_base == NULL) 1368 return; 1369 } 1370 1371 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1372 { 1373 u32 val; 1374 1375 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1376 return; 1377 /* read the Function Disable register, dword mode only */ 1378 val = readl(asus_rcba_base + 0x3418); 1379 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1380 } 1381 1382 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1383 { 1384 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1385 return; 1386 iounmap(asus_rcba_base); 1387 asus_rcba_base = NULL; 1388 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1389 } 1390 1391 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1392 { 1393 asus_hides_smbus_lpc_ich6_suspend(dev); 1394 asus_hides_smbus_lpc_ich6_resume_early(dev); 1395 asus_hides_smbus_lpc_ich6_resume(dev); 1396 } 1397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1398 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1399 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1400 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1401 1402 /* 1403 * SiS 96x south bridge: BIOS typically hides SMBus device... 1404 */ 1405 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1406 { 1407 u8 val = 0; 1408 pci_read_config_byte(dev, 0x77, &val); 1409 if (val & 0x10) { 1410 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1411 pci_write_config_byte(dev, 0x77, val & ~0x10); 1412 } 1413 } 1414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1418 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1419 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1420 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1421 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1422 1423 /* 1424 * ... This is further complicated by the fact that some SiS96x south 1425 * bridges pretend to be 85C503/5513 instead. In that case see if we 1426 * spotted a compatible north bridge to make sure. 1427 * (pci_find_device doesn't work yet) 1428 * 1429 * We can also enable the sis96x bit in the discovery register.. 1430 */ 1431 #define SIS_DETECT_REGISTER 0x40 1432 1433 static void quirk_sis_503(struct pci_dev *dev) 1434 { 1435 u8 reg; 1436 u16 devid; 1437 1438 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1439 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1440 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1441 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1442 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1443 return; 1444 } 1445 1446 /* 1447 * Ok, it now shows up as a 96x.. run the 96x quirk by 1448 * hand in case it has already been processed. 1449 * (depends on link order, which is apparently not guaranteed) 1450 */ 1451 dev->device = devid; 1452 quirk_sis_96x_smbus(dev); 1453 } 1454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1455 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1456 1457 1458 /* 1459 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1460 * and MC97 modem controller are disabled when a second PCI soundcard is 1461 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1462 * -- bjd 1463 */ 1464 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1465 { 1466 u8 val; 1467 int asus_hides_ac97 = 0; 1468 1469 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1470 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1471 asus_hides_ac97 = 1; 1472 } 1473 1474 if (!asus_hides_ac97) 1475 return; 1476 1477 pci_read_config_byte(dev, 0x50, &val); 1478 if (val & 0xc0) { 1479 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1480 pci_read_config_byte(dev, 0x50, &val); 1481 if (val & 0xc0) 1482 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1483 val); 1484 else 1485 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1486 } 1487 } 1488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1489 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1490 1491 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1492 1493 /* 1494 * If we are using libata we can drive this chip properly but must 1495 * do this early on to make the additional device appear during 1496 * the PCI scanning. 1497 */ 1498 static void quirk_jmicron_ata(struct pci_dev *pdev) 1499 { 1500 u32 conf1, conf5, class; 1501 u8 hdr; 1502 1503 /* Only poke fn 0 */ 1504 if (PCI_FUNC(pdev->devfn)) 1505 return; 1506 1507 pci_read_config_dword(pdev, 0x40, &conf1); 1508 pci_read_config_dword(pdev, 0x80, &conf5); 1509 1510 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1511 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1512 1513 switch (pdev->device) { 1514 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1515 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1516 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1517 /* The controller should be in single function ahci mode */ 1518 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1519 break; 1520 1521 case PCI_DEVICE_ID_JMICRON_JMB365: 1522 case PCI_DEVICE_ID_JMICRON_JMB366: 1523 /* Redirect IDE second PATA port to the right spot */ 1524 conf5 |= (1 << 24); 1525 /* Fall through */ 1526 case PCI_DEVICE_ID_JMICRON_JMB361: 1527 case PCI_DEVICE_ID_JMICRON_JMB363: 1528 case PCI_DEVICE_ID_JMICRON_JMB369: 1529 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1530 /* Set the class codes correctly and then direct IDE 0 */ 1531 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1532 break; 1533 1534 case PCI_DEVICE_ID_JMICRON_JMB368: 1535 /* The controller should be in single function IDE mode */ 1536 conf1 |= 0x00C00000; /* Set 22, 23 */ 1537 break; 1538 } 1539 1540 pci_write_config_dword(pdev, 0x40, conf1); 1541 pci_write_config_dword(pdev, 0x80, conf5); 1542 1543 /* Update pdev accordingly */ 1544 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1545 pdev->hdr_type = hdr & 0x7f; 1546 pdev->multifunction = !!(hdr & 0x80); 1547 1548 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1549 pdev->class = class >> 8; 1550 } 1551 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1552 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1553 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1554 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1555 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1556 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1562 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1563 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1564 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1565 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1566 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1567 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1568 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1569 1570 #endif 1571 1572 #ifdef CONFIG_X86_IO_APIC 1573 static void quirk_alder_ioapic(struct pci_dev *pdev) 1574 { 1575 int i; 1576 1577 if ((pdev->class >> 8) != 0xff00) 1578 return; 1579 1580 /* the first BAR is the location of the IO APIC...we must 1581 * not touch this (and it's already covered by the fixmap), so 1582 * forcibly insert it into the resource tree */ 1583 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1584 insert_resource(&iomem_resource, &pdev->resource[0]); 1585 1586 /* The next five BARs all seem to be rubbish, so just clean 1587 * them out */ 1588 for (i = 1; i < 6; i++) 1589 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1590 } 1591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1592 #endif 1593 1594 static void quirk_pcie_mch(struct pci_dev *pdev) 1595 { 1596 pdev->no_msi = 1; 1597 } 1598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1601 1602 1603 /* 1604 * It's possible for the MSI to get corrupted if shpc and acpi 1605 * are used together on certain PXH-based systems. 1606 */ 1607 static void quirk_pcie_pxh(struct pci_dev *dev) 1608 { 1609 dev->no_msi = 1; 1610 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1611 } 1612 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1613 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1614 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1615 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1616 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1617 1618 /* 1619 * Some Intel PCI Express chipsets have trouble with downstream 1620 * device power management. 1621 */ 1622 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1623 { 1624 pci_pm_d3_delay = 120; 1625 dev->no_d1d2 = 1; 1626 } 1627 1628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1649 1650 #ifdef CONFIG_X86_IO_APIC 1651 /* 1652 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1653 * remap the original interrupt in the linux kernel to the boot interrupt, so 1654 * that a PCI device's interrupt handler is installed on the boot interrupt 1655 * line instead. 1656 */ 1657 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1658 { 1659 if (noioapicquirk || noioapicreroute) 1660 return; 1661 1662 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1663 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1664 dev->vendor, dev->device); 1665 } 1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1674 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1675 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1676 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1677 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1678 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1679 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1680 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1681 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1682 1683 /* 1684 * On some chipsets we can disable the generation of legacy INTx boot 1685 * interrupts. 1686 */ 1687 1688 /* 1689 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1690 * 300641-004US, section 5.7.3. 1691 */ 1692 #define INTEL_6300_IOAPIC_ABAR 0x40 1693 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1694 1695 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1696 { 1697 u16 pci_config_word; 1698 1699 if (noioapicquirk) 1700 return; 1701 1702 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1703 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1704 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1705 1706 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1707 dev->vendor, dev->device); 1708 } 1709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1710 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1711 1712 /* 1713 * disable boot interrupts on HT-1000 1714 */ 1715 #define BC_HT1000_FEATURE_REG 0x64 1716 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1717 #define BC_HT1000_MAP_IDX 0xC00 1718 #define BC_HT1000_MAP_DATA 0xC01 1719 1720 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1721 { 1722 u32 pci_config_dword; 1723 u8 irq; 1724 1725 if (noioapicquirk) 1726 return; 1727 1728 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1729 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1730 BC_HT1000_PIC_REGS_ENABLE); 1731 1732 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1733 outb(irq, BC_HT1000_MAP_IDX); 1734 outb(0x00, BC_HT1000_MAP_DATA); 1735 } 1736 1737 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1738 1739 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1740 dev->vendor, dev->device); 1741 } 1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1743 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1744 1745 /* 1746 * disable boot interrupts on AMD and ATI chipsets 1747 */ 1748 /* 1749 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1750 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1751 * (due to an erratum). 1752 */ 1753 #define AMD_813X_MISC 0x40 1754 #define AMD_813X_NOIOAMODE (1<<0) 1755 #define AMD_813X_REV_B1 0x12 1756 #define AMD_813X_REV_B2 0x13 1757 1758 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1759 { 1760 u32 pci_config_dword; 1761 1762 if (noioapicquirk) 1763 return; 1764 if ((dev->revision == AMD_813X_REV_B1) || 1765 (dev->revision == AMD_813X_REV_B2)) 1766 return; 1767 1768 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1769 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1770 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1771 1772 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1773 dev->vendor, dev->device); 1774 } 1775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1776 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1778 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1779 1780 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1781 1782 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1783 { 1784 u16 pci_config_word; 1785 1786 if (noioapicquirk) 1787 return; 1788 1789 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1790 if (!pci_config_word) { 1791 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1792 dev->vendor, dev->device); 1793 return; 1794 } 1795 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1796 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1797 dev->vendor, dev->device); 1798 } 1799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1800 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1801 #endif /* CONFIG_X86_IO_APIC */ 1802 1803 /* 1804 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1805 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1806 * Re-allocate the region if needed... 1807 */ 1808 static void quirk_tc86c001_ide(struct pci_dev *dev) 1809 { 1810 struct resource *r = &dev->resource[0]; 1811 1812 if (r->start & 0x8) { 1813 r->flags |= IORESOURCE_UNSET; 1814 r->start = 0; 1815 r->end = 0xf; 1816 } 1817 } 1818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1819 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1820 quirk_tc86c001_ide); 1821 1822 /* 1823 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1824 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1825 * being read correctly if bit 7 of the base address is set. 1826 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1827 * Re-allocate the regions to a 256-byte boundary if necessary. 1828 */ 1829 static void quirk_plx_pci9050(struct pci_dev *dev) 1830 { 1831 unsigned int bar; 1832 1833 /* Fixed in revision 2 (PCI 9052). */ 1834 if (dev->revision >= 2) 1835 return; 1836 for (bar = 0; bar <= 1; bar++) 1837 if (pci_resource_len(dev, bar) == 0x80 && 1838 (pci_resource_start(dev, bar) & 0x80)) { 1839 struct resource *r = &dev->resource[bar]; 1840 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1841 bar); 1842 r->flags |= IORESOURCE_UNSET; 1843 r->start = 0; 1844 r->end = 0xff; 1845 } 1846 } 1847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1848 quirk_plx_pci9050); 1849 /* 1850 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1851 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1852 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1853 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1854 * 1855 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1856 * driver. 1857 */ 1858 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1859 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1860 1861 static void quirk_netmos(struct pci_dev *dev) 1862 { 1863 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1864 unsigned int num_serial = dev->subsystem_device & 0xf; 1865 1866 /* 1867 * These Netmos parts are multiport serial devices with optional 1868 * parallel ports. Even when parallel ports are present, they 1869 * are identified as class SERIAL, which means the serial driver 1870 * will claim them. To prevent this, mark them as class OTHER. 1871 * These combo devices should be claimed by parport_serial. 1872 * 1873 * The subdevice ID is of the form 0x00PS, where <P> is the number 1874 * of parallel ports and <S> is the number of serial ports. 1875 */ 1876 switch (dev->device) { 1877 case PCI_DEVICE_ID_NETMOS_9835: 1878 /* Well, this rule doesn't hold for the following 9835 device */ 1879 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1880 dev->subsystem_device == 0x0299) 1881 return; 1882 case PCI_DEVICE_ID_NETMOS_9735: 1883 case PCI_DEVICE_ID_NETMOS_9745: 1884 case PCI_DEVICE_ID_NETMOS_9845: 1885 case PCI_DEVICE_ID_NETMOS_9855: 1886 if (num_parallel) { 1887 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1888 dev->device, num_parallel, num_serial); 1889 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1890 (dev->class & 0xff); 1891 } 1892 } 1893 } 1894 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1895 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1896 1897 static void quirk_e100_interrupt(struct pci_dev *dev) 1898 { 1899 u16 command, pmcsr; 1900 u8 __iomem *csr; 1901 u8 cmd_hi; 1902 1903 switch (dev->device) { 1904 /* PCI IDs taken from drivers/net/e100.c */ 1905 case 0x1029: 1906 case 0x1030 ... 0x1034: 1907 case 0x1038 ... 0x103E: 1908 case 0x1050 ... 0x1057: 1909 case 0x1059: 1910 case 0x1064 ... 0x106B: 1911 case 0x1091 ... 0x1095: 1912 case 0x1209: 1913 case 0x1229: 1914 case 0x2449: 1915 case 0x2459: 1916 case 0x245D: 1917 case 0x27DC: 1918 break; 1919 default: 1920 return; 1921 } 1922 1923 /* 1924 * Some firmware hands off the e100 with interrupts enabled, 1925 * which can cause a flood of interrupts if packets are 1926 * received before the driver attaches to the device. So 1927 * disable all e100 interrupts here. The driver will 1928 * re-enable them when it's ready. 1929 */ 1930 pci_read_config_word(dev, PCI_COMMAND, &command); 1931 1932 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1933 return; 1934 1935 /* 1936 * Check that the device is in the D0 power state. If it's not, 1937 * there is no point to look any further. 1938 */ 1939 if (dev->pm_cap) { 1940 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1941 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1942 return; 1943 } 1944 1945 /* Convert from PCI bus to resource space. */ 1946 csr = ioremap(pci_resource_start(dev, 0), 8); 1947 if (!csr) { 1948 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1949 return; 1950 } 1951 1952 cmd_hi = readb(csr + 3); 1953 if (cmd_hi == 0) { 1954 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 1955 writeb(1, csr + 3); 1956 } 1957 1958 iounmap(csr); 1959 } 1960 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1961 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 1962 1963 /* 1964 * The 82575 and 82598 may experience data corruption issues when transitioning 1965 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1966 */ 1967 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 1968 { 1969 dev_info(&dev->dev, "Disabling L0s\n"); 1970 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1971 } 1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1977 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1979 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1980 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1981 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1982 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1983 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1986 1987 static void fixup_rev1_53c810(struct pci_dev *dev) 1988 { 1989 /* rev 1 ncr53c810 chips don't set the class at all which means 1990 * they don't get their resources remapped. Fix that here. 1991 */ 1992 1993 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1994 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1995 dev->class = PCI_CLASS_STORAGE_SCSI; 1996 } 1997 } 1998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1999 2000 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2001 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2002 { 2003 u16 en1k; 2004 2005 pci_read_config_word(dev, 0x40, &en1k); 2006 2007 if (en1k & 0x200) { 2008 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2009 dev->io_window_1k = 1; 2010 } 2011 } 2012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2013 2014 /* Under some circumstances, AER is not linked with extended capabilities. 2015 * Force it to be linked by setting the corresponding control bit in the 2016 * config space. 2017 */ 2018 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2019 { 2020 uint8_t b; 2021 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2022 if (!(b & 0x20)) { 2023 pci_write_config_byte(dev, 0xf41, b | 0x20); 2024 dev_info(&dev->dev, "Linking AER extended capability\n"); 2025 } 2026 } 2027 } 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2029 quirk_nvidia_ck804_pcie_aer_ext_cap); 2030 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2031 quirk_nvidia_ck804_pcie_aer_ext_cap); 2032 2033 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2034 { 2035 /* 2036 * Disable PCI Bus Parking and PCI Master read caching on CX700 2037 * which causes unspecified timing errors with a VT6212L on the PCI 2038 * bus leading to USB2.0 packet loss. 2039 * 2040 * This quirk is only enabled if a second (on the external PCI bus) 2041 * VT6212L is found -- the CX700 core itself also contains a USB 2042 * host controller with the same PCI ID as the VT6212L. 2043 */ 2044 2045 /* Count VT6212L instances */ 2046 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2047 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2048 uint8_t b; 2049 2050 /* p should contain the first (internal) VT6212L -- see if we have 2051 an external one by searching again */ 2052 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2053 if (!p) 2054 return; 2055 pci_dev_put(p); 2056 2057 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2058 if (b & 0x40) { 2059 /* Turn off PCI Bus Parking */ 2060 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2061 2062 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2063 } 2064 } 2065 2066 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2067 if (b != 0) { 2068 /* Turn off PCI Master read caching */ 2069 pci_write_config_byte(dev, 0x72, 0x0); 2070 2071 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2072 pci_write_config_byte(dev, 0x75, 0x1); 2073 2074 /* Disable "Read FIFO Timer" */ 2075 pci_write_config_byte(dev, 0x77, 0x0); 2076 2077 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2078 } 2079 } 2080 } 2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2082 2083 /* 2084 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2085 * VPD end tag will hang the device. This problem was initially 2086 * observed when a vpd entry was created in sysfs 2087 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2088 * will dump 32k of data. Reading a full 32k will cause an access 2089 * beyond the VPD end tag causing the device to hang. Once the device 2090 * is hung, the bnx2 driver will not be able to reset the device. 2091 * We believe that it is legal to read beyond the end tag and 2092 * therefore the solution is to limit the read/write length. 2093 */ 2094 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2095 { 2096 /* 2097 * Only disable the VPD capability for 5706, 5706S, 5708, 2098 * 5708S and 5709 rev. A 2099 */ 2100 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2101 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2102 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2103 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2104 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2105 (dev->revision & 0xf0) == 0x0)) { 2106 if (dev->vpd) 2107 dev->vpd->len = 0x80; 2108 } 2109 } 2110 2111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2112 PCI_DEVICE_ID_NX2_5706, 2113 quirk_brcm_570x_limit_vpd); 2114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2115 PCI_DEVICE_ID_NX2_5706S, 2116 quirk_brcm_570x_limit_vpd); 2117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2118 PCI_DEVICE_ID_NX2_5708, 2119 quirk_brcm_570x_limit_vpd); 2120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2121 PCI_DEVICE_ID_NX2_5708S, 2122 quirk_brcm_570x_limit_vpd); 2123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2124 PCI_DEVICE_ID_NX2_5709, 2125 quirk_brcm_570x_limit_vpd); 2126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2127 PCI_DEVICE_ID_NX2_5709S, 2128 quirk_brcm_570x_limit_vpd); 2129 2130 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2131 { 2132 u32 rev; 2133 2134 pci_read_config_dword(dev, 0xf4, &rev); 2135 2136 /* Only CAP the MRRS if the device is a 5719 A0 */ 2137 if (rev == 0x05719000) { 2138 int readrq = pcie_get_readrq(dev); 2139 if (readrq > 2048) 2140 pcie_set_readrq(dev, 2048); 2141 } 2142 } 2143 2144 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2145 PCI_DEVICE_ID_TIGON3_5719, 2146 quirk_brcm_5719_limit_mrrs); 2147 2148 /* Originally in EDAC sources for i82875P: 2149 * Intel tells BIOS developers to hide device 6 which 2150 * configures the overflow device access containing 2151 * the DRBs - this is where we expose device 6. 2152 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2153 */ 2154 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2155 { 2156 u8 reg; 2157 2158 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2159 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2160 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2161 } 2162 } 2163 2164 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2165 quirk_unhide_mch_dev6); 2166 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2167 quirk_unhide_mch_dev6); 2168 2169 #ifdef CONFIG_TILEPRO 2170 /* 2171 * The Tilera TILEmpower tilepro platform needs to set the link speed 2172 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2173 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2174 * capability register of the PEX8624 PCIe switch. The switch 2175 * supports link speed auto negotiation, but falsely sets 2176 * the link speed to 5GT/s. 2177 */ 2178 static void quirk_tile_plx_gen1(struct pci_dev *dev) 2179 { 2180 if (tile_plx_gen1) { 2181 pci_write_config_dword(dev, 0x98, 0x1); 2182 mdelay(50); 2183 } 2184 } 2185 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2186 #endif /* CONFIG_TILEPRO */ 2187 2188 #ifdef CONFIG_PCI_MSI 2189 /* Some chipsets do not support MSI. We cannot easily rely on setting 2190 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2191 * some other buses controlled by the chipset even if Linux is not 2192 * aware of it. Instead of setting the flag on all buses in the 2193 * machine, simply disable MSI globally. 2194 */ 2195 static void quirk_disable_all_msi(struct pci_dev *dev) 2196 { 2197 pci_no_msi(); 2198 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2199 } 2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2207 2208 /* Disable MSI on chipsets that are known to not support it */ 2209 static void quirk_disable_msi(struct pci_dev *dev) 2210 { 2211 if (dev->subordinate) { 2212 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2213 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2214 } 2215 } 2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2219 2220 /* 2221 * The APC bridge device in AMD 780 family northbridges has some random 2222 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2223 * we use the possible vendor/device IDs of the host bridge for the 2224 * declared quirk, and search for the APC bridge by slot number. 2225 */ 2226 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2227 { 2228 struct pci_dev *apc_bridge; 2229 2230 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2231 if (apc_bridge) { 2232 if (apc_bridge->device == 0x9602) 2233 quirk_disable_msi(apc_bridge); 2234 pci_dev_put(apc_bridge); 2235 } 2236 } 2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2239 2240 /* Go through the list of Hypertransport capabilities and 2241 * return 1 if a HT MSI capability is found and enabled */ 2242 static int msi_ht_cap_enabled(struct pci_dev *dev) 2243 { 2244 int pos, ttl = 48; 2245 2246 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2247 while (pos && ttl--) { 2248 u8 flags; 2249 2250 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2251 &flags) == 0) { 2252 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2253 flags & HT_MSI_FLAGS_ENABLE ? 2254 "enabled" : "disabled"); 2255 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2256 } 2257 2258 pos = pci_find_next_ht_capability(dev, pos, 2259 HT_CAPTYPE_MSI_MAPPING); 2260 } 2261 return 0; 2262 } 2263 2264 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2265 static void quirk_msi_ht_cap(struct pci_dev *dev) 2266 { 2267 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2268 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2269 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2270 } 2271 } 2272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2273 quirk_msi_ht_cap); 2274 2275 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2276 * MSI are supported if the MSI capability set in any of these mappings. 2277 */ 2278 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2279 { 2280 struct pci_dev *pdev; 2281 2282 if (!dev->subordinate) 2283 return; 2284 2285 /* check HT MSI cap on this chipset and the root one. 2286 * a single one having MSI is enough to be sure that MSI are supported. 2287 */ 2288 pdev = pci_get_slot(dev->bus, 0); 2289 if (!pdev) 2290 return; 2291 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2292 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2293 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2294 } 2295 pci_dev_put(pdev); 2296 } 2297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2298 quirk_nvidia_ck804_msi_ht_cap); 2299 2300 /* Force enable MSI mapping capability on HT bridges */ 2301 static void ht_enable_msi_mapping(struct pci_dev *dev) 2302 { 2303 int pos, ttl = 48; 2304 2305 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2306 while (pos && ttl--) { 2307 u8 flags; 2308 2309 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2310 &flags) == 0) { 2311 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2312 2313 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2314 flags | HT_MSI_FLAGS_ENABLE); 2315 } 2316 pos = pci_find_next_ht_capability(dev, pos, 2317 HT_CAPTYPE_MSI_MAPPING); 2318 } 2319 } 2320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2321 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2322 ht_enable_msi_mapping); 2323 2324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2325 ht_enable_msi_mapping); 2326 2327 /* The P5N32-SLI motherboards from Asus have a problem with msi 2328 * for the MCP55 NIC. It is not yet determined whether the msi problem 2329 * also affects other devices. As for now, turn off msi for this device. 2330 */ 2331 static void nvenet_msi_disable(struct pci_dev *dev) 2332 { 2333 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2334 2335 if (board_name && 2336 (strstr(board_name, "P5N32-SLI PREMIUM") || 2337 strstr(board_name, "P5N32-E SLI"))) { 2338 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2339 dev->no_msi = 1; 2340 } 2341 } 2342 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2343 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2344 nvenet_msi_disable); 2345 2346 /* 2347 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2348 * config register. This register controls the routing of legacy 2349 * interrupts from devices that route through the MCP55. If this register 2350 * is misprogrammed, interrupts are only sent to the BSP, unlike 2351 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2352 * having this register set properly prevents kdump from booting up 2353 * properly, so let's make sure that we have it set correctly. 2354 * Note that this is an undocumented register. 2355 */ 2356 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2357 { 2358 u32 cfg; 2359 2360 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2361 return; 2362 2363 pci_read_config_dword(dev, 0x74, &cfg); 2364 2365 if (cfg & ((1 << 2) | (1 << 15))) { 2366 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2367 cfg &= ~((1 << 2) | (1 << 15)); 2368 pci_write_config_dword(dev, 0x74, cfg); 2369 } 2370 } 2371 2372 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2373 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2374 nvbridge_check_legacy_irq_routing); 2375 2376 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2377 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2378 nvbridge_check_legacy_irq_routing); 2379 2380 static int ht_check_msi_mapping(struct pci_dev *dev) 2381 { 2382 int pos, ttl = 48; 2383 int found = 0; 2384 2385 /* check if there is HT MSI cap or enabled on this device */ 2386 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2387 while (pos && ttl--) { 2388 u8 flags; 2389 2390 if (found < 1) 2391 found = 1; 2392 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2393 &flags) == 0) { 2394 if (flags & HT_MSI_FLAGS_ENABLE) { 2395 if (found < 2) { 2396 found = 2; 2397 break; 2398 } 2399 } 2400 } 2401 pos = pci_find_next_ht_capability(dev, pos, 2402 HT_CAPTYPE_MSI_MAPPING); 2403 } 2404 2405 return found; 2406 } 2407 2408 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2409 { 2410 struct pci_dev *dev; 2411 int pos; 2412 int i, dev_no; 2413 int found = 0; 2414 2415 dev_no = host_bridge->devfn >> 3; 2416 for (i = dev_no + 1; i < 0x20; i++) { 2417 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2418 if (!dev) 2419 continue; 2420 2421 /* found next host bridge ?*/ 2422 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2423 if (pos != 0) { 2424 pci_dev_put(dev); 2425 break; 2426 } 2427 2428 if (ht_check_msi_mapping(dev)) { 2429 found = 1; 2430 pci_dev_put(dev); 2431 break; 2432 } 2433 pci_dev_put(dev); 2434 } 2435 2436 return found; 2437 } 2438 2439 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2440 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2441 2442 static int is_end_of_ht_chain(struct pci_dev *dev) 2443 { 2444 int pos, ctrl_off; 2445 int end = 0; 2446 u16 flags, ctrl; 2447 2448 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2449 2450 if (!pos) 2451 goto out; 2452 2453 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2454 2455 ctrl_off = ((flags >> 10) & 1) ? 2456 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2457 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2458 2459 if (ctrl & (1 << 6)) 2460 end = 1; 2461 2462 out: 2463 return end; 2464 } 2465 2466 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2467 { 2468 struct pci_dev *host_bridge; 2469 int pos; 2470 int i, dev_no; 2471 int found = 0; 2472 2473 dev_no = dev->devfn >> 3; 2474 for (i = dev_no; i >= 0; i--) { 2475 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2476 if (!host_bridge) 2477 continue; 2478 2479 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2480 if (pos != 0) { 2481 found = 1; 2482 break; 2483 } 2484 pci_dev_put(host_bridge); 2485 } 2486 2487 if (!found) 2488 return; 2489 2490 /* don't enable end_device/host_bridge with leaf directly here */ 2491 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2492 host_bridge_with_leaf(host_bridge)) 2493 goto out; 2494 2495 /* root did that ! */ 2496 if (msi_ht_cap_enabled(host_bridge)) 2497 goto out; 2498 2499 ht_enable_msi_mapping(dev); 2500 2501 out: 2502 pci_dev_put(host_bridge); 2503 } 2504 2505 static void ht_disable_msi_mapping(struct pci_dev *dev) 2506 { 2507 int pos, ttl = 48; 2508 2509 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2510 while (pos && ttl--) { 2511 u8 flags; 2512 2513 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2514 &flags) == 0) { 2515 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2516 2517 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2518 flags & ~HT_MSI_FLAGS_ENABLE); 2519 } 2520 pos = pci_find_next_ht_capability(dev, pos, 2521 HT_CAPTYPE_MSI_MAPPING); 2522 } 2523 } 2524 2525 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2526 { 2527 struct pci_dev *host_bridge; 2528 int pos; 2529 int found; 2530 2531 if (!pci_msi_enabled()) 2532 return; 2533 2534 /* check if there is HT MSI cap or enabled on this device */ 2535 found = ht_check_msi_mapping(dev); 2536 2537 /* no HT MSI CAP */ 2538 if (found == 0) 2539 return; 2540 2541 /* 2542 * HT MSI mapping should be disabled on devices that are below 2543 * a non-Hypertransport host bridge. Locate the host bridge... 2544 */ 2545 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2546 if (host_bridge == NULL) { 2547 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2548 return; 2549 } 2550 2551 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2552 if (pos != 0) { 2553 /* Host bridge is to HT */ 2554 if (found == 1) { 2555 /* it is not enabled, try to enable it */ 2556 if (all) 2557 ht_enable_msi_mapping(dev); 2558 else 2559 nv_ht_enable_msi_mapping(dev); 2560 } 2561 goto out; 2562 } 2563 2564 /* HT MSI is not enabled */ 2565 if (found == 1) 2566 goto out; 2567 2568 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2569 ht_disable_msi_mapping(dev); 2570 2571 out: 2572 pci_dev_put(host_bridge); 2573 } 2574 2575 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2576 { 2577 return __nv_msi_ht_cap_quirk(dev, 1); 2578 } 2579 2580 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2581 { 2582 return __nv_msi_ht_cap_quirk(dev, 0); 2583 } 2584 2585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2587 2588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2590 2591 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2592 { 2593 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2594 } 2595 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2596 { 2597 struct pci_dev *p; 2598 2599 /* SB700 MSI issue will be fixed at HW level from revision A21, 2600 * we need check PCI REVISION ID of SMBus controller to get SB700 2601 * revision. 2602 */ 2603 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2604 NULL); 2605 if (!p) 2606 return; 2607 2608 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2609 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2610 pci_dev_put(p); 2611 } 2612 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2613 { 2614 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2615 if (dev->revision < 0x18) { 2616 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2617 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2618 } 2619 } 2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2621 PCI_DEVICE_ID_TIGON3_5780, 2622 quirk_msi_intx_disable_bug); 2623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2624 PCI_DEVICE_ID_TIGON3_5780S, 2625 quirk_msi_intx_disable_bug); 2626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2627 PCI_DEVICE_ID_TIGON3_5714, 2628 quirk_msi_intx_disable_bug); 2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2630 PCI_DEVICE_ID_TIGON3_5714S, 2631 quirk_msi_intx_disable_bug); 2632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2633 PCI_DEVICE_ID_TIGON3_5715, 2634 quirk_msi_intx_disable_bug); 2635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2636 PCI_DEVICE_ID_TIGON3_5715S, 2637 quirk_msi_intx_disable_bug); 2638 2639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2640 quirk_msi_intx_disable_ati_bug); 2641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2642 quirk_msi_intx_disable_ati_bug); 2643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2644 quirk_msi_intx_disable_ati_bug); 2645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2646 quirk_msi_intx_disable_ati_bug); 2647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2648 quirk_msi_intx_disable_ati_bug); 2649 2650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2651 quirk_msi_intx_disable_bug); 2652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2653 quirk_msi_intx_disable_bug); 2654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2655 quirk_msi_intx_disable_bug); 2656 2657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2658 quirk_msi_intx_disable_bug); 2659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2660 quirk_msi_intx_disable_bug); 2661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2662 quirk_msi_intx_disable_bug); 2663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2664 quirk_msi_intx_disable_bug); 2665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2666 quirk_msi_intx_disable_bug); 2667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2668 quirk_msi_intx_disable_bug); 2669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2670 quirk_msi_intx_disable_qca_bug); 2671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2672 quirk_msi_intx_disable_qca_bug); 2673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2674 quirk_msi_intx_disable_qca_bug); 2675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2676 quirk_msi_intx_disable_qca_bug); 2677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2678 quirk_msi_intx_disable_qca_bug); 2679 #endif /* CONFIG_PCI_MSI */ 2680 2681 /* Allow manual resource allocation for PCI hotplug bridges 2682 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2683 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2684 * kernel fails to allocate resources when hotplug device is 2685 * inserted and PCI bus is rescanned. 2686 */ 2687 static void quirk_hotplug_bridge(struct pci_dev *dev) 2688 { 2689 dev->is_hotplug_bridge = 1; 2690 } 2691 2692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2693 2694 /* 2695 * This is a quirk for the Ricoh MMC controller found as a part of 2696 * some mulifunction chips. 2697 2698 * This is very similar and based on the ricoh_mmc driver written by 2699 * Philip Langdale. Thank you for these magic sequences. 2700 * 2701 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2702 * and one or both of cardbus or firewire. 2703 * 2704 * It happens that they implement SD and MMC 2705 * support as separate controllers (and PCI functions). The linux SDHCI 2706 * driver supports MMC cards but the chip detects MMC cards in hardware 2707 * and directs them to the MMC controller - so the SDHCI driver never sees 2708 * them. 2709 * 2710 * To get around this, we must disable the useless MMC controller. 2711 * At that point, the SDHCI controller will start seeing them 2712 * It seems to be the case that the relevant PCI registers to deactivate the 2713 * MMC controller live on PCI function 0, which might be the cardbus controller 2714 * or the firewire controller, depending on the particular chip in question 2715 * 2716 * This has to be done early, because as soon as we disable the MMC controller 2717 * other pci functions shift up one level, e.g. function #2 becomes function 2718 * #1, and this will confuse the pci core. 2719 */ 2720 2721 #ifdef CONFIG_MMC_RICOH_MMC 2722 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2723 { 2724 /* disable via cardbus interface */ 2725 u8 write_enable; 2726 u8 write_target; 2727 u8 disable; 2728 2729 /* disable must be done via function #0 */ 2730 if (PCI_FUNC(dev->devfn)) 2731 return; 2732 2733 pci_read_config_byte(dev, 0xB7, &disable); 2734 if (disable & 0x02) 2735 return; 2736 2737 pci_read_config_byte(dev, 0x8E, &write_enable); 2738 pci_write_config_byte(dev, 0x8E, 0xAA); 2739 pci_read_config_byte(dev, 0x8D, &write_target); 2740 pci_write_config_byte(dev, 0x8D, 0xB7); 2741 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2742 pci_write_config_byte(dev, 0x8E, write_enable); 2743 pci_write_config_byte(dev, 0x8D, write_target); 2744 2745 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2746 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2747 } 2748 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2750 2751 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2752 { 2753 /* disable via firewire interface */ 2754 u8 write_enable; 2755 u8 disable; 2756 2757 /* disable must be done via function #0 */ 2758 if (PCI_FUNC(dev->devfn)) 2759 return; 2760 /* 2761 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2762 * certain types of SD/MMC cards. Lowering the SD base 2763 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2764 * 2765 * 0x150 - SD2.0 mode enable for changing base clock 2766 * frequency to 50Mhz 2767 * 0xe1 - Base clock frequency 2768 * 0x32 - 50Mhz new clock frequency 2769 * 0xf9 - Key register for 0x150 2770 * 0xfc - key register for 0xe1 2771 */ 2772 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2773 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2774 pci_write_config_byte(dev, 0xf9, 0xfc); 2775 pci_write_config_byte(dev, 0x150, 0x10); 2776 pci_write_config_byte(dev, 0xf9, 0x00); 2777 pci_write_config_byte(dev, 0xfc, 0x01); 2778 pci_write_config_byte(dev, 0xe1, 0x32); 2779 pci_write_config_byte(dev, 0xfc, 0x00); 2780 2781 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2782 } 2783 2784 pci_read_config_byte(dev, 0xCB, &disable); 2785 2786 if (disable & 0x02) 2787 return; 2788 2789 pci_read_config_byte(dev, 0xCA, &write_enable); 2790 pci_write_config_byte(dev, 0xCA, 0x57); 2791 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2792 pci_write_config_byte(dev, 0xCA, write_enable); 2793 2794 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2795 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2796 2797 } 2798 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2799 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2800 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2801 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2802 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2803 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2804 #endif /*CONFIG_MMC_RICOH_MMC*/ 2805 2806 #ifdef CONFIG_DMAR_TABLE 2807 #define VTUNCERRMSK_REG 0x1ac 2808 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2809 /* 2810 * This is a quirk for masking vt-d spec defined errors to platform error 2811 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2812 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2813 * on the RAS config settings of the platform) when a vt-d fault happens. 2814 * The resulting SMI caused the system to hang. 2815 * 2816 * VT-d spec related errors are already handled by the VT-d OS code, so no 2817 * need to report the same error through other channels. 2818 */ 2819 static void vtd_mask_spec_errors(struct pci_dev *dev) 2820 { 2821 u32 word; 2822 2823 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2824 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2825 } 2826 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2827 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2828 #endif 2829 2830 static void fixup_ti816x_class(struct pci_dev *dev) 2831 { 2832 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2833 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); 2834 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; 2835 } 2836 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2837 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); 2838 2839 /* Some PCIe devices do not work reliably with the claimed maximum 2840 * payload size supported. 2841 */ 2842 static void fixup_mpss_256(struct pci_dev *dev) 2843 { 2844 dev->pcie_mpss = 1; /* 256 bytes */ 2845 } 2846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2847 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2849 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2851 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2852 2853 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2854 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2855 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2856 * until all of the devices are discovered and buses walked, read completion 2857 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2858 * it is possible to hotplug a device with MPS of 256B. 2859 */ 2860 static void quirk_intel_mc_errata(struct pci_dev *dev) 2861 { 2862 int err; 2863 u16 rcc; 2864 2865 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 2866 return; 2867 2868 /* Intel errata specifies bits to change but does not say what they are. 2869 * Keeping them magical until such time as the registers and values can 2870 * be explained. 2871 */ 2872 err = pci_read_config_word(dev, 0x48, &rcc); 2873 if (err) { 2874 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 2875 return; 2876 } 2877 2878 if (!(rcc & (1 << 10))) 2879 return; 2880 2881 rcc &= ~(1 << 10); 2882 2883 err = pci_write_config_word(dev, 0x48, rcc); 2884 if (err) { 2885 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 2886 return; 2887 } 2888 2889 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 2890 } 2891 /* Intel 5000 series memory controllers and ports 2-7 */ 2892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2906 /* Intel 5100 series memory controllers and ports 2-7 */ 2907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2918 2919 2920 /* 2921 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 2922 * work around this, query the size it should be configured to by the device and 2923 * modify the resource end to correspond to this new size. 2924 */ 2925 static void quirk_intel_ntb(struct pci_dev *dev) 2926 { 2927 int rc; 2928 u8 val; 2929 2930 rc = pci_read_config_byte(dev, 0x00D0, &val); 2931 if (rc) 2932 return; 2933 2934 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 2935 2936 rc = pci_read_config_byte(dev, 0x00D1, &val); 2937 if (rc) 2938 return; 2939 2940 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 2941 } 2942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 2943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 2944 2945 static ktime_t fixup_debug_start(struct pci_dev *dev, 2946 void (*fn)(struct pci_dev *dev)) 2947 { 2948 ktime_t calltime = ktime_set(0, 0); 2949 2950 dev_dbg(&dev->dev, "calling %pF\n", fn); 2951 if (initcall_debug) { 2952 pr_debug("calling %pF @ %i for %s\n", 2953 fn, task_pid_nr(current), dev_name(&dev->dev)); 2954 calltime = ktime_get(); 2955 } 2956 2957 return calltime; 2958 } 2959 2960 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 2961 void (*fn)(struct pci_dev *dev)) 2962 { 2963 ktime_t delta, rettime; 2964 unsigned long long duration; 2965 2966 if (initcall_debug) { 2967 rettime = ktime_get(); 2968 delta = ktime_sub(rettime, calltime); 2969 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 2970 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 2971 fn, duration, dev_name(&dev->dev)); 2972 } 2973 } 2974 2975 /* 2976 * Some BIOS implementations leave the Intel GPU interrupts enabled, 2977 * even though no one is handling them (f.e. i915 driver is never loaded). 2978 * Additionally the interrupt destination is not set up properly 2979 * and the interrupt ends up -somewhere-. 2980 * 2981 * These spurious interrupts are "sticky" and the kernel disables 2982 * the (shared) interrupt line after 100.000+ generated interrupts. 2983 * 2984 * Fix it by disabling the still enabled interrupts. 2985 * This resolves crashes often seen on monitor unplug. 2986 */ 2987 #define I915_DEIER_REG 0x4400c 2988 static void disable_igfx_irq(struct pci_dev *dev) 2989 { 2990 void __iomem *regs = pci_iomap(dev, 0, 0); 2991 if (regs == NULL) { 2992 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 2993 return; 2994 } 2995 2996 /* Check if any interrupt line is still enabled */ 2997 if (readl(regs + I915_DEIER_REG) != 0) { 2998 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 2999 3000 writel(0, regs + I915_DEIER_REG); 3001 } 3002 3003 pci_iounmap(dev, regs); 3004 } 3005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3008 3009 /* 3010 * PCI devices which are on Intel chips can skip the 10ms delay 3011 * before entering D3 mode. 3012 */ 3013 static void quirk_remove_d3_delay(struct pci_dev *dev) 3014 { 3015 dev->d3_delay = 0; 3016 } 3017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3031 3032 /* 3033 * Some devices may pass our check in pci_intx_mask_supported if 3034 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3035 * support this feature. 3036 */ 3037 static void quirk_broken_intx_masking(struct pci_dev *dev) 3038 { 3039 dev->broken_intx_masking = 1; 3040 } 3041 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, 3042 quirk_broken_intx_masking); 3043 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3044 quirk_broken_intx_masking); 3045 /* 3046 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3047 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3048 * 3049 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3050 */ 3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169, 3052 quirk_broken_intx_masking); 3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3054 quirk_broken_intx_masking); 3055 3056 static void quirk_no_bus_reset(struct pci_dev *dev) 3057 { 3058 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3059 } 3060 3061 /* 3062 * Atheros AR93xx chips do not behave after a bus reset. The device will 3063 * throw a Link Down error on AER-capable systems and regardless of AER, 3064 * config space of the device is never accessible again and typically 3065 * causes the system to hang or reset when access is attempted. 3066 * http://www.spinics.net/lists/linux-pci/msg34797.html 3067 */ 3068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3069 3070 static void quirk_no_pm_reset(struct pci_dev *dev) 3071 { 3072 /* 3073 * We can't do a bus reset on root bus devices, but an ineffective 3074 * PM reset may be better than nothing. 3075 */ 3076 if (!pci_is_root_bus(dev->bus)) 3077 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3078 } 3079 3080 /* 3081 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3082 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3083 * to have no effect on the device: it retains the framebuffer contents and 3084 * monitor sync. Advertising this support makes other layers, like VFIO, 3085 * assume pci_reset_function() is viable for this device. Mark it as 3086 * unavailable to skip it when testing reset methods. 3087 */ 3088 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3089 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3090 3091 #ifdef CONFIG_ACPI 3092 /* 3093 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3094 * 3095 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3096 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3097 * be present after resume if a device was plugged in before suspend. 3098 * 3099 * The thunderbolt controller consists of a pcie switch with downstream 3100 * bridges leading to the NHI and to the tunnel pci bridges. 3101 * 3102 * This quirk cuts power to the whole chip. Therefore we have to apply it 3103 * during suspend_noirq of the upstream bridge. 3104 * 3105 * Power is automagically restored before resume. No action is needed. 3106 */ 3107 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3108 { 3109 acpi_handle bridge, SXIO, SXFP, SXLV; 3110 3111 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3112 return; 3113 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3114 return; 3115 bridge = ACPI_HANDLE(&dev->dev); 3116 if (!bridge) 3117 return; 3118 /* 3119 * SXIO and SXLV are present only on machines requiring this quirk. 3120 * TB bridges in external devices might have the same device id as those 3121 * on the host, but they will not have the associated ACPI methods. This 3122 * implicitly checks that we are at the right bridge. 3123 */ 3124 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3125 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3126 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3127 return; 3128 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3129 3130 /* magic sequence */ 3131 acpi_execute_simple_method(SXIO, NULL, 1); 3132 acpi_execute_simple_method(SXFP, NULL, 0); 3133 msleep(300); 3134 acpi_execute_simple_method(SXLV, NULL, 0); 3135 acpi_execute_simple_method(SXIO, NULL, 0); 3136 acpi_execute_simple_method(SXLV, NULL, 0); 3137 } 3138 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547, 3139 quirk_apple_poweroff_thunderbolt); 3140 3141 /* 3142 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3143 * 3144 * During suspend the thunderbolt controller is reset and all pci 3145 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3146 * during resume. We have to manually wait for the NHI since there is 3147 * no parent child relationship between the NHI and the tunneled 3148 * bridges. 3149 */ 3150 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3151 { 3152 struct pci_dev *sibling = NULL; 3153 struct pci_dev *nhi = NULL; 3154 3155 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3156 return; 3157 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3158 return; 3159 /* 3160 * Find the NHI and confirm that we are a bridge on the tb host 3161 * controller and not on a tb endpoint. 3162 */ 3163 sibling = pci_get_slot(dev->bus, 0x0); 3164 if (sibling == dev) 3165 goto out; /* we are the downstream bridge to the NHI */ 3166 if (!sibling || !sibling->subordinate) 3167 goto out; 3168 nhi = pci_get_slot(sibling->subordinate, 0x0); 3169 if (!nhi) 3170 goto out; 3171 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3172 || (nhi->device != 0x1547 && nhi->device != 0x156c) 3173 || nhi->subsystem_vendor != 0x2222 3174 || nhi->subsystem_device != 0x1111) 3175 goto out; 3176 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3177 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3178 out: 3179 pci_dev_put(nhi); 3180 pci_dev_put(sibling); 3181 } 3182 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547, 3183 quirk_apple_wait_for_thunderbolt); 3184 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d, 3185 quirk_apple_wait_for_thunderbolt); 3186 #endif 3187 3188 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3189 struct pci_fixup *end) 3190 { 3191 ktime_t calltime; 3192 3193 for (; f < end; f++) 3194 if ((f->class == (u32) (dev->class >> f->class_shift) || 3195 f->class == (u32) PCI_ANY_ID) && 3196 (f->vendor == dev->vendor || 3197 f->vendor == (u16) PCI_ANY_ID) && 3198 (f->device == dev->device || 3199 f->device == (u16) PCI_ANY_ID)) { 3200 calltime = fixup_debug_start(dev, f->hook); 3201 f->hook(dev); 3202 fixup_debug_report(dev, calltime, f->hook); 3203 } 3204 } 3205 3206 extern struct pci_fixup __start_pci_fixups_early[]; 3207 extern struct pci_fixup __end_pci_fixups_early[]; 3208 extern struct pci_fixup __start_pci_fixups_header[]; 3209 extern struct pci_fixup __end_pci_fixups_header[]; 3210 extern struct pci_fixup __start_pci_fixups_final[]; 3211 extern struct pci_fixup __end_pci_fixups_final[]; 3212 extern struct pci_fixup __start_pci_fixups_enable[]; 3213 extern struct pci_fixup __end_pci_fixups_enable[]; 3214 extern struct pci_fixup __start_pci_fixups_resume[]; 3215 extern struct pci_fixup __end_pci_fixups_resume[]; 3216 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3217 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3218 extern struct pci_fixup __start_pci_fixups_suspend[]; 3219 extern struct pci_fixup __end_pci_fixups_suspend[]; 3220 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3221 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3222 3223 static bool pci_apply_fixup_final_quirks; 3224 3225 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3226 { 3227 struct pci_fixup *start, *end; 3228 3229 switch (pass) { 3230 case pci_fixup_early: 3231 start = __start_pci_fixups_early; 3232 end = __end_pci_fixups_early; 3233 break; 3234 3235 case pci_fixup_header: 3236 start = __start_pci_fixups_header; 3237 end = __end_pci_fixups_header; 3238 break; 3239 3240 case pci_fixup_final: 3241 if (!pci_apply_fixup_final_quirks) 3242 return; 3243 start = __start_pci_fixups_final; 3244 end = __end_pci_fixups_final; 3245 break; 3246 3247 case pci_fixup_enable: 3248 start = __start_pci_fixups_enable; 3249 end = __end_pci_fixups_enable; 3250 break; 3251 3252 case pci_fixup_resume: 3253 start = __start_pci_fixups_resume; 3254 end = __end_pci_fixups_resume; 3255 break; 3256 3257 case pci_fixup_resume_early: 3258 start = __start_pci_fixups_resume_early; 3259 end = __end_pci_fixups_resume_early; 3260 break; 3261 3262 case pci_fixup_suspend: 3263 start = __start_pci_fixups_suspend; 3264 end = __end_pci_fixups_suspend; 3265 break; 3266 3267 case pci_fixup_suspend_late: 3268 start = __start_pci_fixups_suspend_late; 3269 end = __end_pci_fixups_suspend_late; 3270 break; 3271 3272 default: 3273 /* stupid compiler warning, you would think with an enum... */ 3274 return; 3275 } 3276 pci_do_fixups(dev, start, end); 3277 } 3278 EXPORT_SYMBOL(pci_fixup_device); 3279 3280 3281 static int __init pci_apply_final_quirks(void) 3282 { 3283 struct pci_dev *dev = NULL; 3284 u8 cls = 0; 3285 u8 tmp; 3286 3287 if (pci_cache_line_size) 3288 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3289 pci_cache_line_size << 2); 3290 3291 pci_apply_fixup_final_quirks = true; 3292 for_each_pci_dev(dev) { 3293 pci_fixup_device(pci_fixup_final, dev); 3294 /* 3295 * If arch hasn't set it explicitly yet, use the CLS 3296 * value shared by all PCI devices. If there's a 3297 * mismatch, fall back to the default value. 3298 */ 3299 if (!pci_cache_line_size) { 3300 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3301 if (!cls) 3302 cls = tmp; 3303 if (!tmp || cls == tmp) 3304 continue; 3305 3306 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3307 cls << 2, tmp << 2, 3308 pci_dfl_cache_line_size << 2); 3309 pci_cache_line_size = pci_dfl_cache_line_size; 3310 } 3311 } 3312 3313 if (!pci_cache_line_size) { 3314 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3315 cls << 2, pci_dfl_cache_line_size << 2); 3316 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3317 } 3318 3319 return 0; 3320 } 3321 3322 fs_initcall_sync(pci_apply_final_quirks); 3323 3324 /* 3325 * Followings are device-specific reset methods which can be used to 3326 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3327 * not available. 3328 */ 3329 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 3330 { 3331 int pos; 3332 3333 /* only implement PCI_CLASS_SERIAL_USB at present */ 3334 if (dev->class == PCI_CLASS_SERIAL_USB) { 3335 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 3336 if (!pos) 3337 return -ENOTTY; 3338 3339 if (probe) 3340 return 0; 3341 3342 pci_write_config_byte(dev, pos + 0x4, 1); 3343 msleep(100); 3344 3345 return 0; 3346 } else { 3347 return -ENOTTY; 3348 } 3349 } 3350 3351 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3352 { 3353 /* 3354 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3355 * 3356 * The 82599 supports FLR on VFs, but FLR support is reported only 3357 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3358 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP. 3359 */ 3360 3361 if (probe) 3362 return 0; 3363 3364 if (!pci_wait_for_pending_transaction(dev)) 3365 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3366 3367 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3368 3369 msleep(100); 3370 3371 return 0; 3372 } 3373 3374 #include "../gpu/drm/i915/i915_reg.h" 3375 #define MSG_CTL 0x45010 3376 #define NSDE_PWR_STATE 0xd0100 3377 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3378 3379 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3380 { 3381 void __iomem *mmio_base; 3382 unsigned long timeout; 3383 u32 val; 3384 3385 if (probe) 3386 return 0; 3387 3388 mmio_base = pci_iomap(dev, 0, 0); 3389 if (!mmio_base) 3390 return -ENOMEM; 3391 3392 iowrite32(0x00000002, mmio_base + MSG_CTL); 3393 3394 /* 3395 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3396 * driver loaded sets the right bits. However, this's a reset and 3397 * the bits have been set by i915 previously, so we clobber 3398 * SOUTH_CHICKEN2 register directly here. 3399 */ 3400 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3401 3402 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3403 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3404 3405 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3406 do { 3407 val = ioread32(mmio_base + PCH_PP_STATUS); 3408 if ((val & 0xb0000000) == 0) 3409 goto reset_complete; 3410 msleep(10); 3411 } while (time_before(jiffies, timeout)); 3412 dev_warn(&dev->dev, "timeout during reset\n"); 3413 3414 reset_complete: 3415 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3416 3417 pci_iounmap(dev, mmio_base); 3418 return 0; 3419 } 3420 3421 /* 3422 * Device-specific reset method for Chelsio T4-based adapters. 3423 */ 3424 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3425 { 3426 u16 old_command; 3427 u16 msix_flags; 3428 3429 /* 3430 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3431 * that we have no device-specific reset method. 3432 */ 3433 if ((dev->device & 0xf000) != 0x4000) 3434 return -ENOTTY; 3435 3436 /* 3437 * If this is the "probe" phase, return 0 indicating that we can 3438 * reset this device. 3439 */ 3440 if (probe) 3441 return 0; 3442 3443 /* 3444 * T4 can wedge if there are DMAs in flight within the chip and Bus 3445 * Master has been disabled. We need to have it on till the Function 3446 * Level Reset completes. (BUS_MASTER is disabled in 3447 * pci_reset_function()). 3448 */ 3449 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3450 pci_write_config_word(dev, PCI_COMMAND, 3451 old_command | PCI_COMMAND_MASTER); 3452 3453 /* 3454 * Perform the actual device function reset, saving and restoring 3455 * configuration information around the reset. 3456 */ 3457 pci_save_state(dev); 3458 3459 /* 3460 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3461 * are disabled when an MSI-X interrupt message needs to be delivered. 3462 * So we briefly re-enable MSI-X interrupts for the duration of the 3463 * FLR. The pci_restore_state() below will restore the original 3464 * MSI-X state. 3465 */ 3466 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3467 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3468 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3469 msix_flags | 3470 PCI_MSIX_FLAGS_ENABLE | 3471 PCI_MSIX_FLAGS_MASKALL); 3472 3473 /* 3474 * Start of pcie_flr() code sequence. This reset code is a copy of 3475 * the guts of pcie_flr() because that's not an exported function. 3476 */ 3477 3478 if (!pci_wait_for_pending_transaction(dev)) 3479 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3480 3481 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3482 msleep(100); 3483 3484 /* 3485 * End of pcie_flr() code sequence. 3486 */ 3487 3488 /* 3489 * Restore the configuration information (BAR values, etc.) including 3490 * the original PCI Configuration Space Command word, and return 3491 * success. 3492 */ 3493 pci_restore_state(dev); 3494 pci_write_config_word(dev, PCI_COMMAND, old_command); 3495 return 0; 3496 } 3497 3498 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3499 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3500 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3501 3502 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3503 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3504 reset_intel_82599_sfp_virtfn }, 3505 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3506 reset_ivb_igd }, 3507 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3508 reset_ivb_igd }, 3509 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3510 reset_intel_generic_dev }, 3511 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3512 reset_chelsio_generic_dev }, 3513 { 0 } 3514 }; 3515 3516 /* 3517 * These device-specific reset methods are here rather than in a driver 3518 * because when a host assigns a device to a guest VM, the host may need 3519 * to reset the device but probably doesn't have a driver for it. 3520 */ 3521 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3522 { 3523 const struct pci_dev_reset_methods *i; 3524 3525 for (i = pci_dev_reset_methods; i->reset; i++) { 3526 if ((i->vendor == dev->vendor || 3527 i->vendor == (u16)PCI_ANY_ID) && 3528 (i->device == dev->device || 3529 i->device == (u16)PCI_ANY_ID)) 3530 return i->reset(dev, probe); 3531 } 3532 3533 return -ENOTTY; 3534 } 3535 3536 static void quirk_dma_func0_alias(struct pci_dev *dev) 3537 { 3538 if (PCI_FUNC(dev->devfn) != 0) { 3539 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); 3540 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3541 } 3542 } 3543 3544 /* 3545 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3546 * 3547 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3548 */ 3549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3551 3552 static void quirk_dma_func1_alias(struct pci_dev *dev) 3553 { 3554 if (PCI_FUNC(dev->devfn) != 1) { 3555 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); 3556 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3557 } 3558 } 3559 3560 /* 3561 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3562 * SKUs function 1 is present and is a legacy IDE controller, in other 3563 * SKUs this function is not present, making this a ghost requester. 3564 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3565 */ 3566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3567 quirk_dma_func1_alias); 3568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3569 quirk_dma_func1_alias); 3570 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3572 quirk_dma_func1_alias); 3573 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3574 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3575 quirk_dma_func1_alias); 3576 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3577 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3578 quirk_dma_func1_alias); 3579 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3581 quirk_dma_func1_alias); 3582 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3584 quirk_dma_func1_alias); 3585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3586 quirk_dma_func1_alias); 3587 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3589 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3590 quirk_dma_func1_alias); 3591 3592 /* 3593 * Some devices DMA with the wrong devfn, not just the wrong function. 3594 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3595 * the alias is "fixed" and independent of the device devfn. 3596 * 3597 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3598 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3599 * single device on the secondary bus. In reality, the single exposed 3600 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3601 * that provides a bridge to the internal bus of the I/O processor. The 3602 * controller supports private devices, which can be hidden from PCI config 3603 * space. In the case of the Adaptec 3405, a private device at 01.0 3604 * appears to be the DMA engine, which therefore needs to become a DMA 3605 * alias for the device. 3606 */ 3607 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3608 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3609 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3610 .driver_data = PCI_DEVFN(1, 0) }, 3611 { 0 } 3612 }; 3613 3614 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3615 { 3616 const struct pci_device_id *id; 3617 3618 id = pci_match_id(fixed_dma_alias_tbl, dev); 3619 if (id) { 3620 dev->dma_alias_devfn = id->driver_data; 3621 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3622 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", 3623 PCI_SLOT(dev->dma_alias_devfn), 3624 PCI_FUNC(dev->dma_alias_devfn)); 3625 } 3626 } 3627 3628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3629 3630 /* 3631 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3632 * using the wrong DMA alias for the device. Some of these devices can be 3633 * used as either forward or reverse bridges, so we need to test whether the 3634 * device is operating in the correct mode. We could probably apply this 3635 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3636 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3637 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3638 */ 3639 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3640 { 3641 if (!pci_is_root_bus(pdev->bus) && 3642 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3643 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3644 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3645 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3646 } 3647 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3649 quirk_use_pcie_bridge_dma_alias); 3650 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3651 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3652 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3653 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3654 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3655 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3656 3657 /* 3658 * AMD has indicated that the devices below do not support peer-to-peer 3659 * in any system where they are found in the southbridge with an AMD 3660 * IOMMU in the system. Multifunction devices that do not support 3661 * peer-to-peer between functions can claim to support a subset of ACS. 3662 * Such devices effectively enable request redirect (RR) and completion 3663 * redirect (CR) since all transactions are redirected to the upstream 3664 * root complex. 3665 * 3666 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 3667 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 3668 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 3669 * 3670 * 1002:4385 SBx00 SMBus Controller 3671 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 3672 * 1002:4383 SBx00 Azalia (Intel HDA) 3673 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 3674 * 1002:4384 SBx00 PCI to PCI Bridge 3675 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 3676 * 3677 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 3678 * 3679 * 1022:780f [AMD] FCH PCI Bridge 3680 * 1022:7809 [AMD] FCH USB OHCI Controller 3681 */ 3682 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 3683 { 3684 #ifdef CONFIG_ACPI 3685 struct acpi_table_header *header = NULL; 3686 acpi_status status; 3687 3688 /* Targeting multifunction devices on the SB (appears on root bus) */ 3689 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 3690 return -ENODEV; 3691 3692 /* The IVRS table describes the AMD IOMMU */ 3693 status = acpi_get_table("IVRS", 0, &header); 3694 if (ACPI_FAILURE(status)) 3695 return -ENODEV; 3696 3697 /* Filter out flags not applicable to multifunction */ 3698 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 3699 3700 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 3701 #else 3702 return -ENODEV; 3703 #endif 3704 } 3705 3706 /* 3707 * Many Intel PCH root ports do provide ACS-like features to disable peer 3708 * transactions and validate bus numbers in requests, but do not provide an 3709 * actual PCIe ACS capability. This is the list of device IDs known to fall 3710 * into that category as provided by Intel in Red Hat bugzilla 1037684. 3711 */ 3712 static const u16 pci_quirk_intel_pch_acs_ids[] = { 3713 /* Ibexpeak PCH */ 3714 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 3715 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 3716 /* Cougarpoint PCH */ 3717 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 3718 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 3719 /* Pantherpoint PCH */ 3720 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 3721 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 3722 /* Lynxpoint-H PCH */ 3723 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 3724 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 3725 /* Lynxpoint-LP PCH */ 3726 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 3727 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 3728 /* Wildcat PCH */ 3729 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 3730 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 3731 /* Patsburg (X79) PCH */ 3732 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 3733 /* Wellsburg (X99) PCH */ 3734 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 3735 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 3736 /* Lynx Point (9 series) PCH */ 3737 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 3738 }; 3739 3740 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 3741 { 3742 int i; 3743 3744 /* Filter out a few obvious non-matches first */ 3745 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 3746 return false; 3747 3748 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 3749 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 3750 return true; 3751 3752 return false; 3753 } 3754 3755 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 3756 3757 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 3758 { 3759 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 3760 INTEL_PCH_ACS_FLAGS : 0; 3761 3762 if (!pci_quirk_intel_pch_acs_match(dev)) 3763 return -ENOTTY; 3764 3765 return acs_flags & ~flags ? 0 : 1; 3766 } 3767 3768 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 3769 { 3770 /* 3771 * SV, TB, and UF are not relevant to multifunction endpoints. 3772 * 3773 * Multifunction devices are only required to implement RR, CR, and DT 3774 * in their ACS capability if they support peer-to-peer transactions. 3775 * Devices matching this quirk have been verified by the vendor to not 3776 * perform peer-to-peer with other functions, allowing us to mask out 3777 * these bits as if they were unimplemented in the ACS capability. 3778 */ 3779 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 3780 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 3781 3782 return acs_flags ? 0 : 1; 3783 } 3784 3785 static const struct pci_dev_acs_enabled { 3786 u16 vendor; 3787 u16 device; 3788 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 3789 } pci_dev_acs_enabled[] = { 3790 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 3791 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 3792 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 3793 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 3794 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 3795 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 3796 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 3797 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 3798 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 3799 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 3800 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 3801 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 3802 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 3803 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 3804 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 3805 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 3806 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 3807 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 3808 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 3809 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 3810 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 3811 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 3812 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 3813 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 3814 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 3815 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 3816 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 3817 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 3818 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 3819 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 3820 /* 82580 */ 3821 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 3822 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 3823 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 3824 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 3825 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 3826 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 3827 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 3828 /* 82576 */ 3829 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 3830 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 3831 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 3832 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 3833 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 3834 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 3835 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 3836 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 3837 /* 82575 */ 3838 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 3839 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 3840 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 3841 /* I350 */ 3842 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 3843 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 3844 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 3845 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 3846 /* 82571 (Quads omitted due to non-ACS switch) */ 3847 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 3848 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 3849 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 3850 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 3851 /* Intel PCH root ports */ 3852 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 3853 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 3854 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 3855 { 0 } 3856 }; 3857 3858 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 3859 { 3860 const struct pci_dev_acs_enabled *i; 3861 int ret; 3862 3863 /* 3864 * Allow devices that do not expose standard PCIe ACS capabilities 3865 * or control to indicate their support here. Multi-function express 3866 * devices which do not allow internal peer-to-peer between functions, 3867 * but do not implement PCIe ACS may wish to return true here. 3868 */ 3869 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 3870 if ((i->vendor == dev->vendor || 3871 i->vendor == (u16)PCI_ANY_ID) && 3872 (i->device == dev->device || 3873 i->device == (u16)PCI_ANY_ID)) { 3874 ret = i->acs_enabled(dev, acs_flags); 3875 if (ret >= 0) 3876 return ret; 3877 } 3878 } 3879 3880 return -ENOTTY; 3881 } 3882 3883 /* Config space offset of Root Complex Base Address register */ 3884 #define INTEL_LPC_RCBA_REG 0xf0 3885 /* 31:14 RCBA address */ 3886 #define INTEL_LPC_RCBA_MASK 0xffffc000 3887 /* RCBA Enable */ 3888 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 3889 3890 /* Backbone Scratch Pad Register */ 3891 #define INTEL_BSPR_REG 0x1104 3892 /* Backbone Peer Non-Posted Disable */ 3893 #define INTEL_BSPR_REG_BPNPD (1 << 8) 3894 /* Backbone Peer Posted Disable */ 3895 #define INTEL_BSPR_REG_BPPD (1 << 9) 3896 3897 /* Upstream Peer Decode Configuration Register */ 3898 #define INTEL_UPDCR_REG 0x1114 3899 /* 5:0 Peer Decode Enable bits */ 3900 #define INTEL_UPDCR_REG_MASK 0x3f 3901 3902 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 3903 { 3904 u32 rcba, bspr, updcr; 3905 void __iomem *rcba_mem; 3906 3907 /* 3908 * Read the RCBA register from the LPC (D31:F0). PCH root ports 3909 * are D28:F* and therefore get probed before LPC, thus we can't 3910 * use pci_get_slot/pci_read_config_dword here. 3911 */ 3912 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 3913 INTEL_LPC_RCBA_REG, &rcba); 3914 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 3915 return -EINVAL; 3916 3917 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 3918 PAGE_ALIGN(INTEL_UPDCR_REG)); 3919 if (!rcba_mem) 3920 return -ENOMEM; 3921 3922 /* 3923 * The BSPR can disallow peer cycles, but it's set by soft strap and 3924 * therefore read-only. If both posted and non-posted peer cycles are 3925 * disallowed, we're ok. If either are allowed, then we need to use 3926 * the UPDCR to disable peer decodes for each port. This provides the 3927 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 3928 */ 3929 bspr = readl(rcba_mem + INTEL_BSPR_REG); 3930 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 3931 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 3932 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 3933 if (updcr & INTEL_UPDCR_REG_MASK) { 3934 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 3935 updcr &= ~INTEL_UPDCR_REG_MASK; 3936 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 3937 } 3938 } 3939 3940 iounmap(rcba_mem); 3941 return 0; 3942 } 3943 3944 /* Miscellaneous Port Configuration register */ 3945 #define INTEL_MPC_REG 0xd8 3946 /* MPC: Invalid Receive Bus Number Check Enable */ 3947 #define INTEL_MPC_REG_IRBNCE (1 << 26) 3948 3949 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 3950 { 3951 u32 mpc; 3952 3953 /* 3954 * When enabled, the IRBNCE bit of the MPC register enables the 3955 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 3956 * ensures that requester IDs fall within the bus number range 3957 * of the bridge. Enable if not already. 3958 */ 3959 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 3960 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 3961 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 3962 mpc |= INTEL_MPC_REG_IRBNCE; 3963 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 3964 } 3965 } 3966 3967 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 3968 { 3969 if (!pci_quirk_intel_pch_acs_match(dev)) 3970 return -ENOTTY; 3971 3972 if (pci_quirk_enable_intel_lpc_acs(dev)) { 3973 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 3974 return 0; 3975 } 3976 3977 pci_quirk_enable_intel_rp_mpc_acs(dev); 3978 3979 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 3980 3981 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 3982 3983 return 0; 3984 } 3985 3986 static const struct pci_dev_enable_acs { 3987 u16 vendor; 3988 u16 device; 3989 int (*enable_acs)(struct pci_dev *dev); 3990 } pci_dev_enable_acs[] = { 3991 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 3992 { 0 } 3993 }; 3994 3995 void pci_dev_specific_enable_acs(struct pci_dev *dev) 3996 { 3997 const struct pci_dev_enable_acs *i; 3998 int ret; 3999 4000 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4001 if ((i->vendor == dev->vendor || 4002 i->vendor == (u16)PCI_ANY_ID) && 4003 (i->device == dev->device || 4004 i->device == (u16)PCI_ANY_ID)) { 4005 ret = i->enable_acs(dev); 4006 if (ret >= 0) 4007 return; 4008 } 4009 } 4010 } 4011