1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <linux/ioport.h> 24 #include <linux/sched.h> 25 #include <linux/ktime.h> 26 #include <linux/mm.h> 27 #include <linux/nvme.h> 28 #include <linux/platform_data/x86/apple.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/switchtec.h> 31 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 32 #include "pci.h" 33 34 static ktime_t fixup_debug_start(struct pci_dev *dev, 35 void (*fn)(struct pci_dev *dev)) 36 { 37 if (initcall_debug) 38 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 39 40 return ktime_get(); 41 } 42 43 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 44 void (*fn)(struct pci_dev *dev)) 45 { 46 ktime_t delta, rettime; 47 unsigned long long duration; 48 49 rettime = ktime_get(); 50 delta = ktime_sub(rettime, calltime); 51 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 52 if (initcall_debug || duration > 10000) 53 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 54 } 55 56 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 57 struct pci_fixup *end) 58 { 59 ktime_t calltime; 60 61 for (; f < end; f++) 62 if ((f->class == (u32) (dev->class >> f->class_shift) || 63 f->class == (u32) PCI_ANY_ID) && 64 (f->vendor == dev->vendor || 65 f->vendor == (u16) PCI_ANY_ID) && 66 (f->device == dev->device || 67 f->device == (u16) PCI_ANY_ID)) { 68 void (*hook)(struct pci_dev *dev); 69 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 70 hook = offset_to_ptr(&f->hook_offset); 71 #else 72 hook = f->hook; 73 #endif 74 calltime = fixup_debug_start(dev, hook); 75 hook(dev); 76 fixup_debug_report(dev, calltime, hook); 77 } 78 } 79 80 extern struct pci_fixup __start_pci_fixups_early[]; 81 extern struct pci_fixup __end_pci_fixups_early[]; 82 extern struct pci_fixup __start_pci_fixups_header[]; 83 extern struct pci_fixup __end_pci_fixups_header[]; 84 extern struct pci_fixup __start_pci_fixups_final[]; 85 extern struct pci_fixup __end_pci_fixups_final[]; 86 extern struct pci_fixup __start_pci_fixups_enable[]; 87 extern struct pci_fixup __end_pci_fixups_enable[]; 88 extern struct pci_fixup __start_pci_fixups_resume[]; 89 extern struct pci_fixup __end_pci_fixups_resume[]; 90 extern struct pci_fixup __start_pci_fixups_resume_early[]; 91 extern struct pci_fixup __end_pci_fixups_resume_early[]; 92 extern struct pci_fixup __start_pci_fixups_suspend[]; 93 extern struct pci_fixup __end_pci_fixups_suspend[]; 94 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 95 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 96 97 static bool pci_apply_fixup_final_quirks; 98 99 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 100 { 101 struct pci_fixup *start, *end; 102 103 switch (pass) { 104 case pci_fixup_early: 105 start = __start_pci_fixups_early; 106 end = __end_pci_fixups_early; 107 break; 108 109 case pci_fixup_header: 110 start = __start_pci_fixups_header; 111 end = __end_pci_fixups_header; 112 break; 113 114 case pci_fixup_final: 115 if (!pci_apply_fixup_final_quirks) 116 return; 117 start = __start_pci_fixups_final; 118 end = __end_pci_fixups_final; 119 break; 120 121 case pci_fixup_enable: 122 start = __start_pci_fixups_enable; 123 end = __end_pci_fixups_enable; 124 break; 125 126 case pci_fixup_resume: 127 start = __start_pci_fixups_resume; 128 end = __end_pci_fixups_resume; 129 break; 130 131 case pci_fixup_resume_early: 132 start = __start_pci_fixups_resume_early; 133 end = __end_pci_fixups_resume_early; 134 break; 135 136 case pci_fixup_suspend: 137 start = __start_pci_fixups_suspend; 138 end = __end_pci_fixups_suspend; 139 break; 140 141 case pci_fixup_suspend_late: 142 start = __start_pci_fixups_suspend_late; 143 end = __end_pci_fixups_suspend_late; 144 break; 145 146 default: 147 /* stupid compiler warning, you would think with an enum... */ 148 return; 149 } 150 pci_do_fixups(dev, start, end); 151 } 152 EXPORT_SYMBOL(pci_fixup_device); 153 154 static int __init pci_apply_final_quirks(void) 155 { 156 struct pci_dev *dev = NULL; 157 u8 cls = 0; 158 u8 tmp; 159 160 if (pci_cache_line_size) 161 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 162 163 pci_apply_fixup_final_quirks = true; 164 for_each_pci_dev(dev) { 165 pci_fixup_device(pci_fixup_final, dev); 166 /* 167 * If arch hasn't set it explicitly yet, use the CLS 168 * value shared by all PCI devices. If there's a 169 * mismatch, fall back to the default value. 170 */ 171 if (!pci_cache_line_size) { 172 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 173 if (!cls) 174 cls = tmp; 175 if (!tmp || cls == tmp) 176 continue; 177 178 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 179 cls << 2, tmp << 2, 180 pci_dfl_cache_line_size << 2); 181 pci_cache_line_size = pci_dfl_cache_line_size; 182 } 183 } 184 185 if (!pci_cache_line_size) { 186 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 187 pci_dfl_cache_line_size << 2); 188 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 189 } 190 191 return 0; 192 } 193 fs_initcall_sync(pci_apply_final_quirks); 194 195 /* 196 * Decoding should be disabled for a PCI device during BAR sizing to avoid 197 * conflict. But doing so may cause problems on host bridge and perhaps other 198 * key system devices. For devices that need to have mmio decoding always-on, 199 * we need to set the dev->mmio_always_on bit. 200 */ 201 static void quirk_mmio_always_on(struct pci_dev *dev) 202 { 203 dev->mmio_always_on = 1; 204 } 205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 206 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 207 208 /* 209 * The Mellanox Tavor device gives false positive parity errors. Mark this 210 * device with a broken_parity_status to allow PCI scanning code to "skip" 211 * this now blacklisted device. 212 */ 213 static void quirk_mellanox_tavor(struct pci_dev *dev) 214 { 215 dev->broken_parity_status = 1; /* This device gives false positives */ 216 } 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 219 220 /* 221 * Deal with broken BIOSes that neglect to enable passive release, 222 * which can cause problems in combination with the 82441FX/PPro MTRRs 223 */ 224 static void quirk_passive_release(struct pci_dev *dev) 225 { 226 struct pci_dev *d = NULL; 227 unsigned char dlc; 228 229 /* 230 * We have to make sure a particular bit is set in the PIIX3 231 * ISA bridge, so we have to go out and find it. 232 */ 233 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 234 pci_read_config_byte(d, 0x82, &dlc); 235 if (!(dlc & 1<<1)) { 236 pci_info(d, "PIIX3: Enabling Passive Release\n"); 237 dlc |= 1<<1; 238 pci_write_config_byte(d, 0x82, dlc); 239 } 240 } 241 } 242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 243 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 244 245 /* 246 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 247 * workaround but VIA don't answer queries. If you happen to have good 248 * contacts at VIA ask them for me please -- Alan 249 * 250 * This appears to be BIOS not version dependent. So presumably there is a 251 * chipset level fix. 252 */ 253 static void quirk_isa_dma_hangs(struct pci_dev *dev) 254 { 255 if (!isa_dma_bridge_buggy) { 256 isa_dma_bridge_buggy = 1; 257 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 258 } 259 } 260 /* 261 * It's not totally clear which chipsets are the problematic ones. We know 262 * 82C586 and 82C596 variants are affected. 263 */ 264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 271 272 /* 273 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 274 * for some HT machines to use C4 w/o hanging. 275 */ 276 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 277 { 278 u32 pmbase; 279 u16 pm1a; 280 281 pci_read_config_dword(dev, 0x40, &pmbase); 282 pmbase = pmbase & 0xff80; 283 pm1a = inw(pmbase); 284 285 if (pm1a & 0x10) { 286 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 287 outw(0x10, pmbase); 288 } 289 } 290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 291 292 /* Chipsets where PCI->PCI transfers vanish or hang */ 293 static void quirk_nopcipci(struct pci_dev *dev) 294 { 295 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 296 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 297 pci_pci_problems |= PCIPCI_FAIL; 298 } 299 } 300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 302 303 static void quirk_nopciamd(struct pci_dev *dev) 304 { 305 u8 rev; 306 pci_read_config_byte(dev, 0x08, &rev); 307 if (rev == 0x13) { 308 /* Erratum 24 */ 309 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 310 pci_pci_problems |= PCIAGP_FAIL; 311 } 312 } 313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 314 315 /* Triton requires workarounds to be used by the drivers */ 316 static void quirk_triton(struct pci_dev *dev) 317 { 318 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 319 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 320 pci_pci_problems |= PCIPCI_TRITON; 321 } 322 } 323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 327 328 /* 329 * VIA Apollo KT133 needs PCI latency patch 330 * Made according to a Windows driver-based patch by George E. Breese; 331 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 332 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 333 * which Mr Breese based his work. 334 * 335 * Updated based on further information from the site and also on 336 * information provided by VIA 337 */ 338 static void quirk_vialatency(struct pci_dev *dev) 339 { 340 struct pci_dev *p; 341 u8 busarb; 342 343 /* 344 * Ok, we have a potential problem chipset here. Now see if we have 345 * a buggy southbridge. 346 */ 347 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 348 if (p != NULL) { 349 350 /* 351 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 352 * thanks Dan Hollis. 353 * Check for buggy part revisions 354 */ 355 if (p->revision < 0x40 || p->revision > 0x42) 356 goto exit; 357 } else { 358 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 359 if (p == NULL) /* No problem parts */ 360 goto exit; 361 362 /* Check for buggy part revisions */ 363 if (p->revision < 0x10 || p->revision > 0x12) 364 goto exit; 365 } 366 367 /* 368 * Ok we have the problem. Now set the PCI master grant to occur 369 * every master grant. The apparent bug is that under high PCI load 370 * (quite common in Linux of course) you can get data loss when the 371 * CPU is held off the bus for 3 bus master requests. This happens 372 * to include the IDE controllers.... 373 * 374 * VIA only apply this fix when an SB Live! is present but under 375 * both Linux and Windows this isn't enough, and we have seen 376 * corruption without SB Live! but with things like 3 UDMA IDE 377 * controllers. So we ignore that bit of the VIA recommendation.. 378 */ 379 pci_read_config_byte(dev, 0x76, &busarb); 380 381 /* 382 * Set bit 4 and bit 5 of byte 76 to 0x01 383 * "Master priority rotation on every PCI master grant" 384 */ 385 busarb &= ~(1<<5); 386 busarb |= (1<<4); 387 pci_write_config_byte(dev, 0x76, busarb); 388 pci_info(dev, "Applying VIA southbridge workaround\n"); 389 exit: 390 pci_dev_put(p); 391 } 392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 395 /* Must restore this on a resume from RAM */ 396 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 397 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 399 400 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 401 static void quirk_viaetbf(struct pci_dev *dev) 402 { 403 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 404 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 405 pci_pci_problems |= PCIPCI_VIAETBF; 406 } 407 } 408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 409 410 static void quirk_vsfx(struct pci_dev *dev) 411 { 412 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 413 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 414 pci_pci_problems |= PCIPCI_VSFX; 415 } 416 } 417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 418 419 /* 420 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 421 * space. Latency must be set to 0xA and Triton workaround applied too. 422 * [Info kindly provided by ALi] 423 */ 424 static void quirk_alimagik(struct pci_dev *dev) 425 { 426 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 427 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 428 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 429 } 430 } 431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 433 434 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 435 static void quirk_natoma(struct pci_dev *dev) 436 { 437 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 438 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 439 pci_pci_problems |= PCIPCI_NATOMA; 440 } 441 } 442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 448 449 /* 450 * This chip can cause PCI parity errors if config register 0xA0 is read 451 * while DMAs are occurring. 452 */ 453 static void quirk_citrine(struct pci_dev *dev) 454 { 455 dev->cfg_size = 0xA0; 456 } 457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 458 459 /* 460 * This chip can cause bus lockups if config addresses above 0x600 461 * are read or written. 462 */ 463 static void quirk_nfp6000(struct pci_dev *dev) 464 { 465 dev->cfg_size = 0x600; 466 } 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 471 472 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 473 static void quirk_extend_bar_to_page(struct pci_dev *dev) 474 { 475 int i; 476 477 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 478 struct resource *r = &dev->resource[i]; 479 480 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 481 r->end = PAGE_SIZE - 1; 482 r->start = 0; 483 r->flags |= IORESOURCE_UNSET; 484 pci_info(dev, "expanded BAR %d to page size: %pR\n", 485 i, r); 486 } 487 } 488 } 489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 490 491 /* 492 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 493 * If it's needed, re-allocate the region. 494 */ 495 static void quirk_s3_64M(struct pci_dev *dev) 496 { 497 struct resource *r = &dev->resource[0]; 498 499 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 500 r->flags |= IORESOURCE_UNSET; 501 r->start = 0; 502 r->end = 0x3ffffff; 503 } 504 } 505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 507 508 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 509 const char *name) 510 { 511 u32 region; 512 struct pci_bus_region bus_region; 513 struct resource *res = dev->resource + pos; 514 515 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 516 517 if (!region) 518 return; 519 520 res->name = pci_name(dev); 521 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 522 res->flags |= 523 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 524 region &= ~(size - 1); 525 526 /* Convert from PCI bus to resource space */ 527 bus_region.start = region; 528 bus_region.end = region + size - 1; 529 pcibios_bus_to_resource(dev->bus, res, &bus_region); 530 531 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 532 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 533 } 534 535 /* 536 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 537 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 538 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 539 * (which conflicts w/ BAR1's memory range). 540 * 541 * CS553x's ISA PCI BARs may also be read-only (ref: 542 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 543 */ 544 static void quirk_cs5536_vsa(struct pci_dev *dev) 545 { 546 static char *name = "CS5536 ISA bridge"; 547 548 if (pci_resource_len(dev, 0) != 8) { 549 quirk_io(dev, 0, 8, name); /* SMB */ 550 quirk_io(dev, 1, 256, name); /* GPIO */ 551 quirk_io(dev, 2, 64, name); /* MFGPT */ 552 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 553 name); 554 } 555 } 556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 557 558 static void quirk_io_region(struct pci_dev *dev, int port, 559 unsigned size, int nr, const char *name) 560 { 561 u16 region; 562 struct pci_bus_region bus_region; 563 struct resource *res = dev->resource + nr; 564 565 pci_read_config_word(dev, port, ®ion); 566 region &= ~(size - 1); 567 568 if (!region) 569 return; 570 571 res->name = pci_name(dev); 572 res->flags = IORESOURCE_IO; 573 574 /* Convert from PCI bus to resource space */ 575 bus_region.start = region; 576 bus_region.end = region + size - 1; 577 pcibios_bus_to_resource(dev->bus, res, &bus_region); 578 579 if (!pci_claim_resource(dev, nr)) 580 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 581 } 582 583 /* 584 * ATI Northbridge setups MCE the processor if you even read somewhere 585 * between 0x3b0->0x3bb or read 0x3d3 586 */ 587 static void quirk_ati_exploding_mce(struct pci_dev *dev) 588 { 589 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 590 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 591 request_region(0x3b0, 0x0C, "RadeonIGP"); 592 request_region(0x3d3, 0x01, "RadeonIGP"); 593 } 594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 595 596 /* 597 * In the AMD NL platform, this device ([1022:7912]) has a class code of 598 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 599 * claim it. 600 * 601 * But the dwc3 driver is a more specific driver for this device, and we'd 602 * prefer to use it instead of xhci. To prevent xhci from claiming the 603 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 604 * defines as "USB device (not host controller)". The dwc3 driver can then 605 * claim it based on its Vendor and Device ID. 606 */ 607 static void quirk_amd_nl_class(struct pci_dev *pdev) 608 { 609 u32 class = pdev->class; 610 611 /* Use "USB Device (not host controller)" class */ 612 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 613 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 614 class, pdev->class); 615 } 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 617 quirk_amd_nl_class); 618 619 /* 620 * Synopsys USB 3.x host HAPS platform has a class code of 621 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 622 * devices should use dwc3-haps driver. Change these devices' class code to 623 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 624 * them. 625 */ 626 static void quirk_synopsys_haps(struct pci_dev *pdev) 627 { 628 u32 class = pdev->class; 629 630 switch (pdev->device) { 631 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 632 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 633 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 634 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 635 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 636 class, pdev->class); 637 break; 638 } 639 } 640 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 641 PCI_CLASS_SERIAL_USB_XHCI, 0, 642 quirk_synopsys_haps); 643 644 /* 645 * Let's make the southbridge information explicit instead of having to 646 * worry about people probing the ACPI areas, for example.. (Yes, it 647 * happens, and if you read the wrong ACPI register it will put the machine 648 * to sleep with no way of waking it up again. Bummer). 649 * 650 * ALI M7101: Two IO regions pointed to by words at 651 * 0xE0 (64 bytes of ACPI registers) 652 * 0xE2 (32 bytes of SMB registers) 653 */ 654 static void quirk_ali7101_acpi(struct pci_dev *dev) 655 { 656 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 657 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 658 } 659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 660 661 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 662 { 663 u32 devres; 664 u32 mask, size, base; 665 666 pci_read_config_dword(dev, port, &devres); 667 if ((devres & enable) != enable) 668 return; 669 mask = (devres >> 16) & 15; 670 base = devres & 0xffff; 671 size = 16; 672 for (;;) { 673 unsigned bit = size >> 1; 674 if ((bit & mask) == bit) 675 break; 676 size = bit; 677 } 678 /* 679 * For now we only print it out. Eventually we'll want to 680 * reserve it (at least if it's in the 0x1000+ range), but 681 * let's get enough confirmation reports first. 682 */ 683 base &= -size; 684 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 685 } 686 687 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 688 { 689 u32 devres; 690 u32 mask, size, base; 691 692 pci_read_config_dword(dev, port, &devres); 693 if ((devres & enable) != enable) 694 return; 695 base = devres & 0xffff0000; 696 mask = (devres & 0x3f) << 16; 697 size = 128 << 16; 698 for (;;) { 699 unsigned bit = size >> 1; 700 if ((bit & mask) == bit) 701 break; 702 size = bit; 703 } 704 705 /* 706 * For now we only print it out. Eventually we'll want to 707 * reserve it, but let's get enough confirmation reports first. 708 */ 709 base &= -size; 710 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 711 } 712 713 /* 714 * PIIX4 ACPI: Two IO regions pointed to by longwords at 715 * 0x40 (64 bytes of ACPI registers) 716 * 0x90 (16 bytes of SMB registers) 717 * and a few strange programmable PIIX4 device resources. 718 */ 719 static void quirk_piix4_acpi(struct pci_dev *dev) 720 { 721 u32 res_a; 722 723 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 724 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 725 726 /* Device resource A has enables for some of the other ones */ 727 pci_read_config_dword(dev, 0x5c, &res_a); 728 729 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 730 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 731 732 /* Device resource D is just bitfields for static resources */ 733 734 /* Device 12 enabled? */ 735 if (res_a & (1 << 29)) { 736 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 737 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 738 } 739 /* Device 13 enabled? */ 740 if (res_a & (1 << 30)) { 741 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 742 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 743 } 744 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 745 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 746 } 747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 749 750 #define ICH_PMBASE 0x40 751 #define ICH_ACPI_CNTL 0x44 752 #define ICH4_ACPI_EN 0x10 753 #define ICH6_ACPI_EN 0x80 754 #define ICH4_GPIOBASE 0x58 755 #define ICH4_GPIO_CNTL 0x5c 756 #define ICH4_GPIO_EN 0x10 757 #define ICH6_GPIOBASE 0x48 758 #define ICH6_GPIO_CNTL 0x4c 759 #define ICH6_GPIO_EN 0x10 760 761 /* 762 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 763 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 764 * 0x58 (64 bytes of GPIO I/O space) 765 */ 766 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 767 { 768 u8 enable; 769 770 /* 771 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 772 * with low legacy (and fixed) ports. We don't know the decoding 773 * priority and can't tell whether the legacy device or the one created 774 * here is really at that address. This happens on boards with broken 775 * BIOSes. 776 */ 777 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 778 if (enable & ICH4_ACPI_EN) 779 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 780 "ICH4 ACPI/GPIO/TCO"); 781 782 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 783 if (enable & ICH4_GPIO_EN) 784 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 785 "ICH4 GPIO"); 786 } 787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 797 798 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 799 { 800 u8 enable; 801 802 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 803 if (enable & ICH6_ACPI_EN) 804 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 805 "ICH6 ACPI/GPIO/TCO"); 806 807 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 808 if (enable & ICH6_GPIO_EN) 809 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 810 "ICH6 GPIO"); 811 } 812 813 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 814 const char *name, int dynsize) 815 { 816 u32 val; 817 u32 size, base; 818 819 pci_read_config_dword(dev, reg, &val); 820 821 /* Enabled? */ 822 if (!(val & 1)) 823 return; 824 base = val & 0xfffc; 825 if (dynsize) { 826 /* 827 * This is not correct. It is 16, 32 or 64 bytes depending on 828 * register D31:F0:ADh bits 5:4. 829 * 830 * But this gets us at least _part_ of it. 831 */ 832 size = 16; 833 } else { 834 size = 128; 835 } 836 base &= ~(size-1); 837 838 /* 839 * Just print it out for now. We should reserve it after more 840 * debugging. 841 */ 842 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 843 } 844 845 static void quirk_ich6_lpc(struct pci_dev *dev) 846 { 847 /* Shared ACPI/GPIO decode with all ICH6+ */ 848 ich6_lpc_acpi_gpio(dev); 849 850 /* ICH6-specific generic IO decode */ 851 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 852 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 853 } 854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 856 857 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 858 const char *name) 859 { 860 u32 val; 861 u32 mask, base; 862 863 pci_read_config_dword(dev, reg, &val); 864 865 /* Enabled? */ 866 if (!(val & 1)) 867 return; 868 869 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 870 base = val & 0xfffc; 871 mask = (val >> 16) & 0xfc; 872 mask |= 3; 873 874 /* 875 * Just print it out for now. We should reserve it after more 876 * debugging. 877 */ 878 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 879 } 880 881 /* ICH7-10 has the same common LPC generic IO decode registers */ 882 static void quirk_ich7_lpc(struct pci_dev *dev) 883 { 884 /* We share the common ACPI/GPIO decode with ICH6 */ 885 ich6_lpc_acpi_gpio(dev); 886 887 /* And have 4 ICH7+ generic decodes */ 888 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 889 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 890 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 891 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 892 } 893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 906 907 /* 908 * VIA ACPI: One IO region pointed to by longword at 909 * 0x48 or 0x20 (256 bytes of ACPI registers) 910 */ 911 static void quirk_vt82c586_acpi(struct pci_dev *dev) 912 { 913 if (dev->revision & 0x10) 914 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 915 "vt82c586 ACPI"); 916 } 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 918 919 /* 920 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 921 * 0x48 (256 bytes of ACPI registers) 922 * 0x70 (128 bytes of hardware monitoring register) 923 * 0x90 (16 bytes of SMB registers) 924 */ 925 static void quirk_vt82c686_acpi(struct pci_dev *dev) 926 { 927 quirk_vt82c586_acpi(dev); 928 929 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 930 "vt82c686 HW-mon"); 931 932 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 933 } 934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 935 936 /* 937 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 938 * 0x88 (128 bytes of power management registers) 939 * 0xd0 (16 bytes of SMB registers) 940 */ 941 static void quirk_vt8235_acpi(struct pci_dev *dev) 942 { 943 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 944 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 945 } 946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 947 948 /* 949 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 950 * back-to-back: Disable fast back-to-back on the secondary bus segment 951 */ 952 static void quirk_xio2000a(struct pci_dev *dev) 953 { 954 struct pci_dev *pdev; 955 u16 command; 956 957 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 958 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 959 pci_read_config_word(pdev, PCI_COMMAND, &command); 960 if (command & PCI_COMMAND_FAST_BACK) 961 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 962 } 963 } 964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 965 quirk_xio2000a); 966 967 #ifdef CONFIG_X86_IO_APIC 968 969 #include <asm/io_apic.h> 970 971 /* 972 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 973 * devices to the external APIC. 974 * 975 * TODO: When we have device-specific interrupt routers, this code will go 976 * away from quirks. 977 */ 978 static void quirk_via_ioapic(struct pci_dev *dev) 979 { 980 u8 tmp; 981 982 if (nr_ioapics < 1) 983 tmp = 0; /* nothing routed to external APIC */ 984 else 985 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 986 987 pci_info(dev, "%sbling VIA external APIC routing\n", 988 tmp == 0 ? "Disa" : "Ena"); 989 990 /* Offset 0x58: External APIC IRQ output control */ 991 pci_write_config_byte(dev, 0x58, tmp); 992 } 993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 994 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 995 996 /* 997 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 998 * This leads to doubled level interrupt rates. 999 * Set this bit to get rid of cycle wastage. 1000 * Otherwise uncritical. 1001 */ 1002 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1003 { 1004 u8 misc_control2; 1005 #define BYPASS_APIC_DEASSERT 8 1006 1007 pci_read_config_byte(dev, 0x5B, &misc_control2); 1008 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1009 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1010 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1011 } 1012 } 1013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1014 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1015 1016 /* 1017 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1018 * We check all revs >= B0 (yet not in the pre production!) as the bug 1019 * is currently marked NoFix 1020 * 1021 * We have multiple reports of hangs with this chipset that went away with 1022 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1023 * of course. However the advice is demonstrably good even if so. 1024 */ 1025 static void quirk_amd_ioapic(struct pci_dev *dev) 1026 { 1027 if (dev->revision >= 0x02) { 1028 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1029 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1030 } 1031 } 1032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1033 #endif /* CONFIG_X86_IO_APIC */ 1034 1035 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1036 1037 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1038 { 1039 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1040 if (dev->subsystem_device == 0xa118) 1041 dev->sriov->link = dev->devfn; 1042 } 1043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1044 #endif 1045 1046 /* 1047 * Some settings of MMRBC can lead to data corruption so block changes. 1048 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1049 */ 1050 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1051 { 1052 if (dev->subordinate && dev->revision <= 0x12) { 1053 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1054 dev->revision); 1055 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1056 } 1057 } 1058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1059 1060 /* 1061 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1062 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1063 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1064 * of the ACPI SCI interrupt is only done for convenience. 1065 * -jgarzik 1066 */ 1067 static void quirk_via_acpi(struct pci_dev *d) 1068 { 1069 u8 irq; 1070 1071 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1072 pci_read_config_byte(d, 0x42, &irq); 1073 irq &= 0xf; 1074 if (irq && (irq != 2)) 1075 d->irq = irq; 1076 } 1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1079 1080 /* VIA bridges which have VLink */ 1081 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1082 1083 static void quirk_via_bridge(struct pci_dev *dev) 1084 { 1085 /* See what bridge we have and find the device ranges */ 1086 switch (dev->device) { 1087 case PCI_DEVICE_ID_VIA_82C686: 1088 /* 1089 * The VT82C686 is special; it attaches to PCI and can have 1090 * any device number. All its subdevices are functions of 1091 * that single device. 1092 */ 1093 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1094 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1095 break; 1096 case PCI_DEVICE_ID_VIA_8237: 1097 case PCI_DEVICE_ID_VIA_8237A: 1098 via_vlink_dev_lo = 15; 1099 break; 1100 case PCI_DEVICE_ID_VIA_8235: 1101 via_vlink_dev_lo = 16; 1102 break; 1103 case PCI_DEVICE_ID_VIA_8231: 1104 case PCI_DEVICE_ID_VIA_8233_0: 1105 case PCI_DEVICE_ID_VIA_8233A: 1106 case PCI_DEVICE_ID_VIA_8233C_0: 1107 via_vlink_dev_lo = 17; 1108 break; 1109 } 1110 } 1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1119 1120 /* 1121 * quirk_via_vlink - VIA VLink IRQ number update 1122 * @dev: PCI device 1123 * 1124 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1125 * the IRQ line register which usually is not relevant for PCI cards, is 1126 * actually written so that interrupts get sent to the right place. 1127 * 1128 * We only do this on systems where a VIA south bridge was detected, and 1129 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1130 */ 1131 static void quirk_via_vlink(struct pci_dev *dev) 1132 { 1133 u8 irq, new_irq; 1134 1135 /* Check if we have VLink at all */ 1136 if (via_vlink_dev_lo == -1) 1137 return; 1138 1139 new_irq = dev->irq; 1140 1141 /* Don't quirk interrupts outside the legacy IRQ range */ 1142 if (!new_irq || new_irq > 15) 1143 return; 1144 1145 /* Internal device ? */ 1146 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1147 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1148 return; 1149 1150 /* 1151 * This is an internal VLink device on a PIC interrupt. The BIOS 1152 * ought to have set this but may not have, so we redo it. 1153 */ 1154 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1155 if (new_irq != irq) { 1156 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1157 irq, new_irq); 1158 udelay(15); /* unknown if delay really needed */ 1159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1160 } 1161 } 1162 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1163 1164 /* 1165 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1166 * of VT82C597 for backward compatibility. We need to switch it off to be 1167 * able to recognize the real type of the chip. 1168 */ 1169 static void quirk_vt82c598_id(struct pci_dev *dev) 1170 { 1171 pci_write_config_byte(dev, 0xfc, 0); 1172 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1173 } 1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1175 1176 /* 1177 * CardBus controllers have a legacy base address that enables them to 1178 * respond as i82365 pcmcia controllers. We don't want them to do this 1179 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1180 * driver does not (and should not) handle CardBus. 1181 */ 1182 static void quirk_cardbus_legacy(struct pci_dev *dev) 1183 { 1184 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1185 } 1186 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1187 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1188 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1189 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1190 1191 /* 1192 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1193 * what the designers were smoking but let's not inhale... 1194 * 1195 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1196 * turn it off! 1197 */ 1198 static void quirk_amd_ordering(struct pci_dev *dev) 1199 { 1200 u32 pcic; 1201 pci_read_config_dword(dev, 0x4C, &pcic); 1202 if ((pcic & 6) != 6) { 1203 pcic |= 6; 1204 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1205 pci_write_config_dword(dev, 0x4C, pcic); 1206 pci_read_config_dword(dev, 0x84, &pcic); 1207 pcic |= (1 << 23); /* Required in this mode */ 1208 pci_write_config_dword(dev, 0x84, pcic); 1209 } 1210 } 1211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1212 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1213 1214 /* 1215 * DreamWorks-provided workaround for Dunord I-3000 problem 1216 * 1217 * This card decodes and responds to addresses not apparently assigned to 1218 * it. We force a larger allocation to ensure that nothing gets put too 1219 * close to it. 1220 */ 1221 static void quirk_dunord(struct pci_dev *dev) 1222 { 1223 struct resource *r = &dev->resource[1]; 1224 1225 r->flags |= IORESOURCE_UNSET; 1226 r->start = 0; 1227 r->end = 0xffffff; 1228 } 1229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1230 1231 /* 1232 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1233 * decoding (transparent), and does indicate this in the ProgIf. 1234 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1235 */ 1236 static void quirk_transparent_bridge(struct pci_dev *dev) 1237 { 1238 dev->transparent = 1; 1239 } 1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1242 1243 /* 1244 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1245 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1246 * found at http://www.national.com/analog for info on what these bits do. 1247 * <christer@weinigel.se> 1248 */ 1249 static void quirk_mediagx_master(struct pci_dev *dev) 1250 { 1251 u8 reg; 1252 1253 pci_read_config_byte(dev, 0x41, ®); 1254 if (reg & 2) { 1255 reg &= ~2; 1256 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1257 reg); 1258 pci_write_config_byte(dev, 0x41, reg); 1259 } 1260 } 1261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1262 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1263 1264 /* 1265 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1266 * in the odd case it is not the results are corruption hence the presence 1267 * of a Linux check. 1268 */ 1269 static void quirk_disable_pxb(struct pci_dev *pdev) 1270 { 1271 u16 config; 1272 1273 if (pdev->revision != 0x04) /* Only C0 requires this */ 1274 return; 1275 pci_read_config_word(pdev, 0x40, &config); 1276 if (config & (1<<6)) { 1277 config &= ~(1<<6); 1278 pci_write_config_word(pdev, 0x40, config); 1279 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1280 } 1281 } 1282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1283 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1284 1285 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1286 { 1287 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1288 u8 tmp; 1289 1290 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1291 if (tmp == 0x01) { 1292 pci_read_config_byte(pdev, 0x40, &tmp); 1293 pci_write_config_byte(pdev, 0x40, tmp|1); 1294 pci_write_config_byte(pdev, 0x9, 1); 1295 pci_write_config_byte(pdev, 0xa, 6); 1296 pci_write_config_byte(pdev, 0x40, tmp); 1297 1298 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1299 pci_info(pdev, "set SATA to AHCI mode\n"); 1300 } 1301 } 1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1305 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1309 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1310 1311 /* Serverworks CSB5 IDE does not fully support native mode */ 1312 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1313 { 1314 u8 prog; 1315 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1316 if (prog & 5) { 1317 prog &= ~5; 1318 pdev->class &= ~5; 1319 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1320 /* PCI layer will sort out resources */ 1321 } 1322 } 1323 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1324 1325 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1326 static void quirk_ide_samemode(struct pci_dev *pdev) 1327 { 1328 u8 prog; 1329 1330 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1331 1332 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1333 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1334 prog &= ~5; 1335 pdev->class &= ~5; 1336 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1337 } 1338 } 1339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1340 1341 /* Some ATA devices break if put into D3 */ 1342 static void quirk_no_ata_d3(struct pci_dev *pdev) 1343 { 1344 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1345 } 1346 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1347 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1348 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1349 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1350 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1351 /* ALi loses some register settings that we cannot then restore */ 1352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1353 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1354 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1355 occur when mode detecting */ 1356 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1357 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1358 1359 /* 1360 * This was originally an Alpha-specific thing, but it really fits here. 1361 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1362 */ 1363 static void quirk_eisa_bridge(struct pci_dev *dev) 1364 { 1365 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1366 } 1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1368 1369 /* 1370 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1371 * is not activated. The myth is that Asus said that they do not want the 1372 * users to be irritated by just another PCI Device in the Win98 device 1373 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1374 * package 2.7.0 for details) 1375 * 1376 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1377 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1378 * becomes necessary to do this tweak in two steps -- the chosen trigger 1379 * is either the Host bridge (preferred) or on-board VGA controller. 1380 * 1381 * Note that we used to unhide the SMBus that way on Toshiba laptops 1382 * (Satellite A40 and Tecra M2) but then found that the thermal management 1383 * was done by SMM code, which could cause unsynchronized concurrent 1384 * accesses to the SMBus registers, with potentially bad effects. Thus you 1385 * should be very careful when adding new entries: if SMM is accessing the 1386 * Intel SMBus, this is a very good reason to leave it hidden. 1387 * 1388 * Likewise, many recent laptops use ACPI for thermal management. If the 1389 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1390 * natively, and keeping the SMBus hidden is the right thing to do. If you 1391 * are about to add an entry in the table below, please first disassemble 1392 * the DSDT and double-check that there is no code accessing the SMBus. 1393 */ 1394 static int asus_hides_smbus; 1395 1396 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1397 { 1398 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1399 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1400 switch (dev->subsystem_device) { 1401 case 0x8025: /* P4B-LX */ 1402 case 0x8070: /* P4B */ 1403 case 0x8088: /* P4B533 */ 1404 case 0x1626: /* L3C notebook */ 1405 asus_hides_smbus = 1; 1406 } 1407 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1408 switch (dev->subsystem_device) { 1409 case 0x80b1: /* P4GE-V */ 1410 case 0x80b2: /* P4PE */ 1411 case 0x8093: /* P4B533-V */ 1412 asus_hides_smbus = 1; 1413 } 1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1415 switch (dev->subsystem_device) { 1416 case 0x8030: /* P4T533 */ 1417 asus_hides_smbus = 1; 1418 } 1419 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1420 switch (dev->subsystem_device) { 1421 case 0x8070: /* P4G8X Deluxe */ 1422 asus_hides_smbus = 1; 1423 } 1424 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1425 switch (dev->subsystem_device) { 1426 case 0x80c9: /* PU-DLS */ 1427 asus_hides_smbus = 1; 1428 } 1429 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1430 switch (dev->subsystem_device) { 1431 case 0x1751: /* M2N notebook */ 1432 case 0x1821: /* M5N notebook */ 1433 case 0x1897: /* A6L notebook */ 1434 asus_hides_smbus = 1; 1435 } 1436 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1437 switch (dev->subsystem_device) { 1438 case 0x184b: /* W1N notebook */ 1439 case 0x186a: /* M6Ne notebook */ 1440 asus_hides_smbus = 1; 1441 } 1442 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1443 switch (dev->subsystem_device) { 1444 case 0x80f2: /* P4P800-X */ 1445 asus_hides_smbus = 1; 1446 } 1447 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1448 switch (dev->subsystem_device) { 1449 case 0x1882: /* M6V notebook */ 1450 case 0x1977: /* A6VA notebook */ 1451 asus_hides_smbus = 1; 1452 } 1453 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1454 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1455 switch (dev->subsystem_device) { 1456 case 0x088C: /* HP Compaq nc8000 */ 1457 case 0x0890: /* HP Compaq nc6000 */ 1458 asus_hides_smbus = 1; 1459 } 1460 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1461 switch (dev->subsystem_device) { 1462 case 0x12bc: /* HP D330L */ 1463 case 0x12bd: /* HP D530 */ 1464 case 0x006a: /* HP Compaq nx9500 */ 1465 asus_hides_smbus = 1; 1466 } 1467 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1468 switch (dev->subsystem_device) { 1469 case 0x12bf: /* HP xw4100 */ 1470 asus_hides_smbus = 1; 1471 } 1472 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1473 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1474 switch (dev->subsystem_device) { 1475 case 0xC00C: /* Samsung P35 notebook */ 1476 asus_hides_smbus = 1; 1477 } 1478 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1479 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1480 switch (dev->subsystem_device) { 1481 case 0x0058: /* Compaq Evo N620c */ 1482 asus_hides_smbus = 1; 1483 } 1484 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1485 switch (dev->subsystem_device) { 1486 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1487 /* Motherboard doesn't have Host bridge 1488 * subvendor/subdevice IDs, therefore checking 1489 * its on-board VGA controller */ 1490 asus_hides_smbus = 1; 1491 } 1492 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1493 switch (dev->subsystem_device) { 1494 case 0x00b8: /* Compaq Evo D510 CMT */ 1495 case 0x00b9: /* Compaq Evo D510 SFF */ 1496 case 0x00ba: /* Compaq Evo D510 USDT */ 1497 /* Motherboard doesn't have Host bridge 1498 * subvendor/subdevice IDs and on-board VGA 1499 * controller is disabled if an AGP card is 1500 * inserted, therefore checking USB UHCI 1501 * Controller #1 */ 1502 asus_hides_smbus = 1; 1503 } 1504 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1505 switch (dev->subsystem_device) { 1506 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1507 /* Motherboard doesn't have host bridge 1508 * subvendor/subdevice IDs, therefore checking 1509 * its on-board VGA controller */ 1510 asus_hides_smbus = 1; 1511 } 1512 } 1513 } 1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1524 1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1528 1529 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1530 { 1531 u16 val; 1532 1533 if (likely(!asus_hides_smbus)) 1534 return; 1535 1536 pci_read_config_word(dev, 0xF2, &val); 1537 if (val & 0x8) { 1538 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1539 pci_read_config_word(dev, 0xF2, &val); 1540 if (val & 0x8) 1541 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1542 val); 1543 else 1544 pci_info(dev, "Enabled i801 SMBus device\n"); 1545 } 1546 } 1547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1557 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1561 1562 /* It appears we just have one such device. If not, we have a warning */ 1563 static void __iomem *asus_rcba_base; 1564 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1565 { 1566 u32 rcba; 1567 1568 if (likely(!asus_hides_smbus)) 1569 return; 1570 WARN_ON(asus_rcba_base); 1571 1572 pci_read_config_dword(dev, 0xF0, &rcba); 1573 /* use bits 31:14, 16 kB aligned */ 1574 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1575 if (asus_rcba_base == NULL) 1576 return; 1577 } 1578 1579 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1580 { 1581 u32 val; 1582 1583 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1584 return; 1585 1586 /* read the Function Disable register, dword mode only */ 1587 val = readl(asus_rcba_base + 0x3418); 1588 1589 /* enable the SMBus device */ 1590 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1591 } 1592 1593 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1594 { 1595 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1596 return; 1597 1598 iounmap(asus_rcba_base); 1599 asus_rcba_base = NULL; 1600 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1601 } 1602 1603 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1604 { 1605 asus_hides_smbus_lpc_ich6_suspend(dev); 1606 asus_hides_smbus_lpc_ich6_resume_early(dev); 1607 asus_hides_smbus_lpc_ich6_resume(dev); 1608 } 1609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1610 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1612 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1613 1614 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1615 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1616 { 1617 u8 val = 0; 1618 pci_read_config_byte(dev, 0x77, &val); 1619 if (val & 0x10) { 1620 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1621 pci_write_config_byte(dev, 0x77, val & ~0x10); 1622 } 1623 } 1624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1628 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1629 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1630 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1631 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1632 1633 /* 1634 * ... This is further complicated by the fact that some SiS96x south 1635 * bridges pretend to be 85C503/5513 instead. In that case see if we 1636 * spotted a compatible north bridge to make sure. 1637 * (pci_find_device() doesn't work yet) 1638 * 1639 * We can also enable the sis96x bit in the discovery register.. 1640 */ 1641 #define SIS_DETECT_REGISTER 0x40 1642 1643 static void quirk_sis_503(struct pci_dev *dev) 1644 { 1645 u8 reg; 1646 u16 devid; 1647 1648 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1649 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1650 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1651 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1652 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1653 return; 1654 } 1655 1656 /* 1657 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1658 * it has already been processed. (Depends on link order, which is 1659 * apparently not guaranteed) 1660 */ 1661 dev->device = devid; 1662 quirk_sis_96x_smbus(dev); 1663 } 1664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1665 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1666 1667 /* 1668 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1669 * and MC97 modem controller are disabled when a second PCI soundcard is 1670 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1671 * -- bjd 1672 */ 1673 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1674 { 1675 u8 val; 1676 int asus_hides_ac97 = 0; 1677 1678 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1679 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1680 asus_hides_ac97 = 1; 1681 } 1682 1683 if (!asus_hides_ac97) 1684 return; 1685 1686 pci_read_config_byte(dev, 0x50, &val); 1687 if (val & 0xc0) { 1688 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1689 pci_read_config_byte(dev, 0x50, &val); 1690 if (val & 0xc0) 1691 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1692 val); 1693 else 1694 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1695 } 1696 } 1697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1698 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1699 1700 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1701 1702 /* 1703 * If we are using libata we can drive this chip properly but must do this 1704 * early on to make the additional device appear during the PCI scanning. 1705 */ 1706 static void quirk_jmicron_ata(struct pci_dev *pdev) 1707 { 1708 u32 conf1, conf5, class; 1709 u8 hdr; 1710 1711 /* Only poke fn 0 */ 1712 if (PCI_FUNC(pdev->devfn)) 1713 return; 1714 1715 pci_read_config_dword(pdev, 0x40, &conf1); 1716 pci_read_config_dword(pdev, 0x80, &conf5); 1717 1718 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1719 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1720 1721 switch (pdev->device) { 1722 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1723 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1724 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1725 /* The controller should be in single function ahci mode */ 1726 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1727 break; 1728 1729 case PCI_DEVICE_ID_JMICRON_JMB365: 1730 case PCI_DEVICE_ID_JMICRON_JMB366: 1731 /* Redirect IDE second PATA port to the right spot */ 1732 conf5 |= (1 << 24); 1733 fallthrough; 1734 case PCI_DEVICE_ID_JMICRON_JMB361: 1735 case PCI_DEVICE_ID_JMICRON_JMB363: 1736 case PCI_DEVICE_ID_JMICRON_JMB369: 1737 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1738 /* Set the class codes correctly and then direct IDE 0 */ 1739 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1740 break; 1741 1742 case PCI_DEVICE_ID_JMICRON_JMB368: 1743 /* The controller should be in single function IDE mode */ 1744 conf1 |= 0x00C00000; /* Set 22, 23 */ 1745 break; 1746 } 1747 1748 pci_write_config_dword(pdev, 0x40, conf1); 1749 pci_write_config_dword(pdev, 0x80, conf5); 1750 1751 /* Update pdev accordingly */ 1752 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1753 pdev->hdr_type = hdr & 0x7f; 1754 pdev->multifunction = !!(hdr & 0x80); 1755 1756 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1757 pdev->class = class >> 8; 1758 } 1759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1764 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1773 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1777 1778 #endif 1779 1780 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1781 { 1782 if (dev->multifunction) { 1783 device_disable_async_suspend(&dev->dev); 1784 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1785 } 1786 } 1787 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1788 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1791 1792 #ifdef CONFIG_X86_IO_APIC 1793 static void quirk_alder_ioapic(struct pci_dev *pdev) 1794 { 1795 int i; 1796 1797 if ((pdev->class >> 8) != 0xff00) 1798 return; 1799 1800 /* 1801 * The first BAR is the location of the IO-APIC... we must 1802 * not touch this (and it's already covered by the fixmap), so 1803 * forcibly insert it into the resource tree. 1804 */ 1805 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1806 insert_resource(&iomem_resource, &pdev->resource[0]); 1807 1808 /* 1809 * The next five BARs all seem to be rubbish, so just clean 1810 * them out. 1811 */ 1812 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1813 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1814 } 1815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1816 #endif 1817 1818 static void quirk_pcie_mch(struct pci_dev *pdev) 1819 { 1820 pdev->no_msi = 1; 1821 } 1822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1825 1826 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1827 1828 /* 1829 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1830 * together on certain PXH-based systems. 1831 */ 1832 static void quirk_pcie_pxh(struct pci_dev *dev) 1833 { 1834 dev->no_msi = 1; 1835 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1836 } 1837 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1838 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1839 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1840 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1841 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1842 1843 /* 1844 * Some Intel PCI Express chipsets have trouble with downstream device 1845 * power management. 1846 */ 1847 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1848 { 1849 pci_pm_d3hot_delay = 120; 1850 dev->no_d1d2 = 1; 1851 } 1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1873 1874 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 1875 { 1876 if (dev->d3hot_delay >= delay) 1877 return; 1878 1879 dev->d3hot_delay = delay; 1880 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 1881 dev->d3hot_delay); 1882 } 1883 1884 static void quirk_radeon_pm(struct pci_dev *dev) 1885 { 1886 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1887 dev->subsystem_device == 0x00e2) 1888 quirk_d3hot_delay(dev, 20); 1889 } 1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1891 1892 /* 1893 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 1894 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 1895 * 1896 * The kernel attempts to transition these devices to D3cold, but that seems 1897 * to be ineffective on the platforms in question; the PCI device appears to 1898 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 1899 * extended delay in order to succeed. 1900 */ 1901 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 1902 { 1903 quirk_d3hot_delay(dev, 20); 1904 } 1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 1907 1908 #ifdef CONFIG_X86_IO_APIC 1909 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1910 { 1911 noioapicreroute = 1; 1912 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1913 1914 return 0; 1915 } 1916 1917 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1918 /* 1919 * Systems to exclude from boot interrupt reroute quirks 1920 */ 1921 { 1922 .callback = dmi_disable_ioapicreroute, 1923 .ident = "ASUSTek Computer INC. M2N-LR", 1924 .matches = { 1925 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1926 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1927 }, 1928 }, 1929 {} 1930 }; 1931 1932 /* 1933 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1934 * remap the original interrupt in the Linux kernel to the boot interrupt, so 1935 * that a PCI device's interrupt handler is installed on the boot interrupt 1936 * line instead. 1937 */ 1938 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1939 { 1940 dmi_check_system(boot_interrupt_dmi_table); 1941 if (noioapicquirk || noioapicreroute) 1942 return; 1943 1944 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1945 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 1946 dev->vendor, dev->device); 1947 } 1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1956 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1957 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1958 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1959 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1960 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1961 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1962 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1963 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1964 1965 /* 1966 * On some chipsets we can disable the generation of legacy INTx boot 1967 * interrupts. 1968 */ 1969 1970 /* 1971 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 1972 * 300641-004US, section 5.7.3. 1973 * 1974 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 1975 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 1976 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 1977 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 1978 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 1979 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 1980 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 1981 * Core IO on Xeon D-1500, see Intel order no 332051-001. 1982 * Core IO on Xeon Scalable, see Intel order no 610950. 1983 */ 1984 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 1985 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1986 1987 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 1988 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 1989 1990 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1991 { 1992 u16 pci_config_word; 1993 u32 pci_config_dword; 1994 1995 if (noioapicquirk) 1996 return; 1997 1998 switch (dev->device) { 1999 case PCI_DEVICE_ID_INTEL_ESB_10: 2000 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2001 &pci_config_word); 2002 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2003 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2004 pci_config_word); 2005 break; 2006 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2007 case 0x0e28: /* Xeon E5/E7 V2 */ 2008 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2009 case 0x6f28: /* Xeon D-1500 */ 2010 case 0x2034: /* Xeon Scalable Family */ 2011 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2012 &pci_config_dword); 2013 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2014 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2015 pci_config_dword); 2016 break; 2017 default: 2018 return; 2019 } 2020 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2021 dev->vendor, dev->device); 2022 } 2023 /* 2024 * Device 29 Func 5 Device IDs of IO-APIC 2025 * containing ABAR—APIC1 Alternate Base Address Register 2026 */ 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2028 quirk_disable_intel_boot_interrupt); 2029 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2030 quirk_disable_intel_boot_interrupt); 2031 2032 /* 2033 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2034 * containing Coherent Interface Protocol Interrupt Control 2035 * 2036 * Device IDs obtained from volume 2 datasheets of commented 2037 * families above. 2038 */ 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2040 quirk_disable_intel_boot_interrupt); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2042 quirk_disable_intel_boot_interrupt); 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2044 quirk_disable_intel_boot_interrupt); 2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2046 quirk_disable_intel_boot_interrupt); 2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2048 quirk_disable_intel_boot_interrupt); 2049 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2050 quirk_disable_intel_boot_interrupt); 2051 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2052 quirk_disable_intel_boot_interrupt); 2053 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2054 quirk_disable_intel_boot_interrupt); 2055 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2056 quirk_disable_intel_boot_interrupt); 2057 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2058 quirk_disable_intel_boot_interrupt); 2059 2060 /* Disable boot interrupts on HT-1000 */ 2061 #define BC_HT1000_FEATURE_REG 0x64 2062 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2063 #define BC_HT1000_MAP_IDX 0xC00 2064 #define BC_HT1000_MAP_DATA 0xC01 2065 2066 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2067 { 2068 u32 pci_config_dword; 2069 u8 irq; 2070 2071 if (noioapicquirk) 2072 return; 2073 2074 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2075 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2076 BC_HT1000_PIC_REGS_ENABLE); 2077 2078 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2079 outb(irq, BC_HT1000_MAP_IDX); 2080 outb(0x00, BC_HT1000_MAP_DATA); 2081 } 2082 2083 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2084 2085 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2086 dev->vendor, dev->device); 2087 } 2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2089 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2090 2091 /* Disable boot interrupts on AMD and ATI chipsets */ 2092 2093 /* 2094 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2095 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2096 * (due to an erratum). 2097 */ 2098 #define AMD_813X_MISC 0x40 2099 #define AMD_813X_NOIOAMODE (1<<0) 2100 #define AMD_813X_REV_B1 0x12 2101 #define AMD_813X_REV_B2 0x13 2102 2103 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2104 { 2105 u32 pci_config_dword; 2106 2107 if (noioapicquirk) 2108 return; 2109 if ((dev->revision == AMD_813X_REV_B1) || 2110 (dev->revision == AMD_813X_REV_B2)) 2111 return; 2112 2113 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2114 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2115 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2116 2117 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2118 dev->vendor, dev->device); 2119 } 2120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2121 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2123 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2124 2125 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2126 2127 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2128 { 2129 u16 pci_config_word; 2130 2131 if (noioapicquirk) 2132 return; 2133 2134 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2135 if (!pci_config_word) { 2136 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2137 dev->vendor, dev->device); 2138 return; 2139 } 2140 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2141 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2142 dev->vendor, dev->device); 2143 } 2144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2145 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2146 #endif /* CONFIG_X86_IO_APIC */ 2147 2148 /* 2149 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2150 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2151 * Re-allocate the region if needed... 2152 */ 2153 static void quirk_tc86c001_ide(struct pci_dev *dev) 2154 { 2155 struct resource *r = &dev->resource[0]; 2156 2157 if (r->start & 0x8) { 2158 r->flags |= IORESOURCE_UNSET; 2159 r->start = 0; 2160 r->end = 0xf; 2161 } 2162 } 2163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2164 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2165 quirk_tc86c001_ide); 2166 2167 /* 2168 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2169 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2170 * being read correctly if bit 7 of the base address is set. 2171 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2172 * Re-allocate the regions to a 256-byte boundary if necessary. 2173 */ 2174 static void quirk_plx_pci9050(struct pci_dev *dev) 2175 { 2176 unsigned int bar; 2177 2178 /* Fixed in revision 2 (PCI 9052). */ 2179 if (dev->revision >= 2) 2180 return; 2181 for (bar = 0; bar <= 1; bar++) 2182 if (pci_resource_len(dev, bar) == 0x80 && 2183 (pci_resource_start(dev, bar) & 0x80)) { 2184 struct resource *r = &dev->resource[bar]; 2185 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2186 bar); 2187 r->flags |= IORESOURCE_UNSET; 2188 r->start = 0; 2189 r->end = 0xff; 2190 } 2191 } 2192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2193 quirk_plx_pci9050); 2194 /* 2195 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2196 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2197 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2198 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2199 * 2200 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2201 * driver. 2202 */ 2203 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2204 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2205 2206 static void quirk_netmos(struct pci_dev *dev) 2207 { 2208 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2209 unsigned int num_serial = dev->subsystem_device & 0xf; 2210 2211 /* 2212 * These Netmos parts are multiport serial devices with optional 2213 * parallel ports. Even when parallel ports are present, they 2214 * are identified as class SERIAL, which means the serial driver 2215 * will claim them. To prevent this, mark them as class OTHER. 2216 * These combo devices should be claimed by parport_serial. 2217 * 2218 * The subdevice ID is of the form 0x00PS, where <P> is the number 2219 * of parallel ports and <S> is the number of serial ports. 2220 */ 2221 switch (dev->device) { 2222 case PCI_DEVICE_ID_NETMOS_9835: 2223 /* Well, this rule doesn't hold for the following 9835 device */ 2224 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2225 dev->subsystem_device == 0x0299) 2226 return; 2227 fallthrough; 2228 case PCI_DEVICE_ID_NETMOS_9735: 2229 case PCI_DEVICE_ID_NETMOS_9745: 2230 case PCI_DEVICE_ID_NETMOS_9845: 2231 case PCI_DEVICE_ID_NETMOS_9855: 2232 if (num_parallel) { 2233 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2234 dev->device, num_parallel, num_serial); 2235 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2236 (dev->class & 0xff); 2237 } 2238 } 2239 } 2240 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2241 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2242 2243 static void quirk_e100_interrupt(struct pci_dev *dev) 2244 { 2245 u16 command, pmcsr; 2246 u8 __iomem *csr; 2247 u8 cmd_hi; 2248 2249 switch (dev->device) { 2250 /* PCI IDs taken from drivers/net/e100.c */ 2251 case 0x1029: 2252 case 0x1030 ... 0x1034: 2253 case 0x1038 ... 0x103E: 2254 case 0x1050 ... 0x1057: 2255 case 0x1059: 2256 case 0x1064 ... 0x106B: 2257 case 0x1091 ... 0x1095: 2258 case 0x1209: 2259 case 0x1229: 2260 case 0x2449: 2261 case 0x2459: 2262 case 0x245D: 2263 case 0x27DC: 2264 break; 2265 default: 2266 return; 2267 } 2268 2269 /* 2270 * Some firmware hands off the e100 with interrupts enabled, 2271 * which can cause a flood of interrupts if packets are 2272 * received before the driver attaches to the device. So 2273 * disable all e100 interrupts here. The driver will 2274 * re-enable them when it's ready. 2275 */ 2276 pci_read_config_word(dev, PCI_COMMAND, &command); 2277 2278 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2279 return; 2280 2281 /* 2282 * Check that the device is in the D0 power state. If it's not, 2283 * there is no point to look any further. 2284 */ 2285 if (dev->pm_cap) { 2286 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2287 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2288 return; 2289 } 2290 2291 /* Convert from PCI bus to resource space. */ 2292 csr = ioremap(pci_resource_start(dev, 0), 8); 2293 if (!csr) { 2294 pci_warn(dev, "Can't map e100 registers\n"); 2295 return; 2296 } 2297 2298 cmd_hi = readb(csr + 3); 2299 if (cmd_hi == 0) { 2300 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2301 writeb(1, csr + 3); 2302 } 2303 2304 iounmap(csr); 2305 } 2306 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2307 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2308 2309 /* 2310 * The 82575 and 82598 may experience data corruption issues when transitioning 2311 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2312 */ 2313 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2314 { 2315 pci_info(dev, "Disabling L0s\n"); 2316 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2317 } 2318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2332 2333 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2334 { 2335 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2336 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2337 } 2338 2339 /* 2340 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2341 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2342 * disable both L0s and L1 for now to be safe. 2343 */ 2344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2345 2346 /* 2347 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2348 * Link bit cleared after starting the link retrain process to allow this 2349 * process to finish. 2350 * 2351 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2352 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2353 */ 2354 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2355 { 2356 dev->clear_retrain_link = 1; 2357 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2358 } 2359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2362 2363 static void fixup_rev1_53c810(struct pci_dev *dev) 2364 { 2365 u32 class = dev->class; 2366 2367 /* 2368 * rev 1 ncr53c810 chips don't set the class at all which means 2369 * they don't get their resources remapped. Fix that here. 2370 */ 2371 if (class) 2372 return; 2373 2374 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2375 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2376 class, dev->class); 2377 } 2378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2379 2380 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2381 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2382 { 2383 u16 en1k; 2384 2385 pci_read_config_word(dev, 0x40, &en1k); 2386 2387 if (en1k & 0x200) { 2388 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2389 dev->io_window_1k = 1; 2390 } 2391 } 2392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2393 2394 /* 2395 * Under some circumstances, AER is not linked with extended capabilities. 2396 * Force it to be linked by setting the corresponding control bit in the 2397 * config space. 2398 */ 2399 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2400 { 2401 uint8_t b; 2402 2403 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2404 if (!(b & 0x20)) { 2405 pci_write_config_byte(dev, 0xf41, b | 0x20); 2406 pci_info(dev, "Linking AER extended capability\n"); 2407 } 2408 } 2409 } 2410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2411 quirk_nvidia_ck804_pcie_aer_ext_cap); 2412 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2413 quirk_nvidia_ck804_pcie_aer_ext_cap); 2414 2415 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2416 { 2417 /* 2418 * Disable PCI Bus Parking and PCI Master read caching on CX700 2419 * which causes unspecified timing errors with a VT6212L on the PCI 2420 * bus leading to USB2.0 packet loss. 2421 * 2422 * This quirk is only enabled if a second (on the external PCI bus) 2423 * VT6212L is found -- the CX700 core itself also contains a USB 2424 * host controller with the same PCI ID as the VT6212L. 2425 */ 2426 2427 /* Count VT6212L instances */ 2428 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2429 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2430 uint8_t b; 2431 2432 /* 2433 * p should contain the first (internal) VT6212L -- see if we have 2434 * an external one by searching again. 2435 */ 2436 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2437 if (!p) 2438 return; 2439 pci_dev_put(p); 2440 2441 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2442 if (b & 0x40) { 2443 /* Turn off PCI Bus Parking */ 2444 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2445 2446 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2447 } 2448 } 2449 2450 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2451 if (b != 0) { 2452 /* Turn off PCI Master read caching */ 2453 pci_write_config_byte(dev, 0x72, 0x0); 2454 2455 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2456 pci_write_config_byte(dev, 0x75, 0x1); 2457 2458 /* Disable "Read FIFO Timer" */ 2459 pci_write_config_byte(dev, 0x77, 0x0); 2460 2461 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2462 } 2463 } 2464 } 2465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2466 2467 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2468 { 2469 u32 rev; 2470 2471 pci_read_config_dword(dev, 0xf4, &rev); 2472 2473 /* Only CAP the MRRS if the device is a 5719 A0 */ 2474 if (rev == 0x05719000) { 2475 int readrq = pcie_get_readrq(dev); 2476 if (readrq > 2048) 2477 pcie_set_readrq(dev, 2048); 2478 } 2479 } 2480 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2481 PCI_DEVICE_ID_TIGON3_5719, 2482 quirk_brcm_5719_limit_mrrs); 2483 2484 /* 2485 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2486 * hide device 6 which configures the overflow device access containing the 2487 * DRBs - this is where we expose device 6. 2488 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2489 */ 2490 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2491 { 2492 u8 reg; 2493 2494 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2495 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2496 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2497 } 2498 } 2499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2500 quirk_unhide_mch_dev6); 2501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2502 quirk_unhide_mch_dev6); 2503 2504 #ifdef CONFIG_PCI_MSI 2505 /* 2506 * Some chipsets do not support MSI. We cannot easily rely on setting 2507 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2508 * other buses controlled by the chipset even if Linux is not aware of it. 2509 * Instead of setting the flag on all buses in the machine, simply disable 2510 * MSI globally. 2511 */ 2512 static void quirk_disable_all_msi(struct pci_dev *dev) 2513 { 2514 pci_no_msi(); 2515 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2516 } 2517 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2526 2527 /* Disable MSI on chipsets that are known to not support it */ 2528 static void quirk_disable_msi(struct pci_dev *dev) 2529 { 2530 if (dev->subordinate) { 2531 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2532 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2533 } 2534 } 2535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2538 2539 /* 2540 * The APC bridge device in AMD 780 family northbridges has some random 2541 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2542 * we use the possible vendor/device IDs of the host bridge for the 2543 * declared quirk, and search for the APC bridge by slot number. 2544 */ 2545 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2546 { 2547 struct pci_dev *apc_bridge; 2548 2549 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2550 if (apc_bridge) { 2551 if (apc_bridge->device == 0x9602) 2552 quirk_disable_msi(apc_bridge); 2553 pci_dev_put(apc_bridge); 2554 } 2555 } 2556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2558 2559 /* 2560 * Go through the list of HyperTransport capabilities and return 1 if a HT 2561 * MSI capability is found and enabled. 2562 */ 2563 static int msi_ht_cap_enabled(struct pci_dev *dev) 2564 { 2565 int pos, ttl = PCI_FIND_CAP_TTL; 2566 2567 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2568 while (pos && ttl--) { 2569 u8 flags; 2570 2571 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2572 &flags) == 0) { 2573 pci_info(dev, "Found %s HT MSI Mapping\n", 2574 flags & HT_MSI_FLAGS_ENABLE ? 2575 "enabled" : "disabled"); 2576 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2577 } 2578 2579 pos = pci_find_next_ht_capability(dev, pos, 2580 HT_CAPTYPE_MSI_MAPPING); 2581 } 2582 return 0; 2583 } 2584 2585 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2586 static void quirk_msi_ht_cap(struct pci_dev *dev) 2587 { 2588 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2589 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2590 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2591 } 2592 } 2593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2594 quirk_msi_ht_cap); 2595 2596 /* 2597 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2598 * if the MSI capability is set in any of these mappings. 2599 */ 2600 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2601 { 2602 struct pci_dev *pdev; 2603 2604 if (!dev->subordinate) 2605 return; 2606 2607 /* 2608 * Check HT MSI cap on this chipset and the root one. A single one 2609 * having MSI is enough to be sure that MSI is supported. 2610 */ 2611 pdev = pci_get_slot(dev->bus, 0); 2612 if (!pdev) 2613 return; 2614 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2615 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2616 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2617 } 2618 pci_dev_put(pdev); 2619 } 2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2621 quirk_nvidia_ck804_msi_ht_cap); 2622 2623 /* Force enable MSI mapping capability on HT bridges */ 2624 static void ht_enable_msi_mapping(struct pci_dev *dev) 2625 { 2626 int pos, ttl = PCI_FIND_CAP_TTL; 2627 2628 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2629 while (pos && ttl--) { 2630 u8 flags; 2631 2632 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2633 &flags) == 0) { 2634 pci_info(dev, "Enabling HT MSI Mapping\n"); 2635 2636 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2637 flags | HT_MSI_FLAGS_ENABLE); 2638 } 2639 pos = pci_find_next_ht_capability(dev, pos, 2640 HT_CAPTYPE_MSI_MAPPING); 2641 } 2642 } 2643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2644 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2645 ht_enable_msi_mapping); 2646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2647 ht_enable_msi_mapping); 2648 2649 /* 2650 * The P5N32-SLI motherboards from Asus have a problem with MSI 2651 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2652 * also affects other devices. As for now, turn off MSI for this device. 2653 */ 2654 static void nvenet_msi_disable(struct pci_dev *dev) 2655 { 2656 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2657 2658 if (board_name && 2659 (strstr(board_name, "P5N32-SLI PREMIUM") || 2660 strstr(board_name, "P5N32-E SLI"))) { 2661 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2662 dev->no_msi = 1; 2663 } 2664 } 2665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2666 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2667 nvenet_msi_disable); 2668 2669 /* 2670 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled, 2671 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't 2672 * generate MSI interrupts for PME and AER events instead only INTx interrupts 2673 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts 2674 * for other events, since PCIe specificiation doesn't support using a mix of 2675 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2676 * service drivers registering their respective ISRs for MSIs. 2677 */ 2678 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2679 { 2680 dev->no_msi = 1; 2681 } 2682 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2683 PCI_CLASS_BRIDGE_PCI, 8, 2684 pci_quirk_nvidia_tegra_disable_rp_msi); 2685 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2686 PCI_CLASS_BRIDGE_PCI, 8, 2687 pci_quirk_nvidia_tegra_disable_rp_msi); 2688 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2689 PCI_CLASS_BRIDGE_PCI, 8, 2690 pci_quirk_nvidia_tegra_disable_rp_msi); 2691 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2692 PCI_CLASS_BRIDGE_PCI, 8, 2693 pci_quirk_nvidia_tegra_disable_rp_msi); 2694 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2695 PCI_CLASS_BRIDGE_PCI, 8, 2696 pci_quirk_nvidia_tegra_disable_rp_msi); 2697 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2698 PCI_CLASS_BRIDGE_PCI, 8, 2699 pci_quirk_nvidia_tegra_disable_rp_msi); 2700 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2701 PCI_CLASS_BRIDGE_PCI, 8, 2702 pci_quirk_nvidia_tegra_disable_rp_msi); 2703 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2704 PCI_CLASS_BRIDGE_PCI, 8, 2705 pci_quirk_nvidia_tegra_disable_rp_msi); 2706 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2707 PCI_CLASS_BRIDGE_PCI, 8, 2708 pci_quirk_nvidia_tegra_disable_rp_msi); 2709 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2710 PCI_CLASS_BRIDGE_PCI, 8, 2711 pci_quirk_nvidia_tegra_disable_rp_msi); 2712 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2713 PCI_CLASS_BRIDGE_PCI, 8, 2714 pci_quirk_nvidia_tegra_disable_rp_msi); 2715 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2716 PCI_CLASS_BRIDGE_PCI, 8, 2717 pci_quirk_nvidia_tegra_disable_rp_msi); 2718 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2719 PCI_CLASS_BRIDGE_PCI, 8, 2720 pci_quirk_nvidia_tegra_disable_rp_msi); 2721 2722 /* 2723 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2724 * config register. This register controls the routing of legacy 2725 * interrupts from devices that route through the MCP55. If this register 2726 * is misprogrammed, interrupts are only sent to the BSP, unlike 2727 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2728 * having this register set properly prevents kdump from booting up 2729 * properly, so let's make sure that we have it set correctly. 2730 * Note that this is an undocumented register. 2731 */ 2732 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2733 { 2734 u32 cfg; 2735 2736 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2737 return; 2738 2739 pci_read_config_dword(dev, 0x74, &cfg); 2740 2741 if (cfg & ((1 << 2) | (1 << 15))) { 2742 pr_info("Rewriting IRQ routing register on MCP55\n"); 2743 cfg &= ~((1 << 2) | (1 << 15)); 2744 pci_write_config_dword(dev, 0x74, cfg); 2745 } 2746 } 2747 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2748 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2749 nvbridge_check_legacy_irq_routing); 2750 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2751 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2752 nvbridge_check_legacy_irq_routing); 2753 2754 static int ht_check_msi_mapping(struct pci_dev *dev) 2755 { 2756 int pos, ttl = PCI_FIND_CAP_TTL; 2757 int found = 0; 2758 2759 /* Check if there is HT MSI cap or enabled on this device */ 2760 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2761 while (pos && ttl--) { 2762 u8 flags; 2763 2764 if (found < 1) 2765 found = 1; 2766 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2767 &flags) == 0) { 2768 if (flags & HT_MSI_FLAGS_ENABLE) { 2769 if (found < 2) { 2770 found = 2; 2771 break; 2772 } 2773 } 2774 } 2775 pos = pci_find_next_ht_capability(dev, pos, 2776 HT_CAPTYPE_MSI_MAPPING); 2777 } 2778 2779 return found; 2780 } 2781 2782 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2783 { 2784 struct pci_dev *dev; 2785 int pos; 2786 int i, dev_no; 2787 int found = 0; 2788 2789 dev_no = host_bridge->devfn >> 3; 2790 for (i = dev_no + 1; i < 0x20; i++) { 2791 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2792 if (!dev) 2793 continue; 2794 2795 /* found next host bridge? */ 2796 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2797 if (pos != 0) { 2798 pci_dev_put(dev); 2799 break; 2800 } 2801 2802 if (ht_check_msi_mapping(dev)) { 2803 found = 1; 2804 pci_dev_put(dev); 2805 break; 2806 } 2807 pci_dev_put(dev); 2808 } 2809 2810 return found; 2811 } 2812 2813 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2814 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2815 2816 static int is_end_of_ht_chain(struct pci_dev *dev) 2817 { 2818 int pos, ctrl_off; 2819 int end = 0; 2820 u16 flags, ctrl; 2821 2822 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2823 2824 if (!pos) 2825 goto out; 2826 2827 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2828 2829 ctrl_off = ((flags >> 10) & 1) ? 2830 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2831 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2832 2833 if (ctrl & (1 << 6)) 2834 end = 1; 2835 2836 out: 2837 return end; 2838 } 2839 2840 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2841 { 2842 struct pci_dev *host_bridge; 2843 int pos; 2844 int i, dev_no; 2845 int found = 0; 2846 2847 dev_no = dev->devfn >> 3; 2848 for (i = dev_no; i >= 0; i--) { 2849 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2850 if (!host_bridge) 2851 continue; 2852 2853 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2854 if (pos != 0) { 2855 found = 1; 2856 break; 2857 } 2858 pci_dev_put(host_bridge); 2859 } 2860 2861 if (!found) 2862 return; 2863 2864 /* don't enable end_device/host_bridge with leaf directly here */ 2865 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2866 host_bridge_with_leaf(host_bridge)) 2867 goto out; 2868 2869 /* root did that ! */ 2870 if (msi_ht_cap_enabled(host_bridge)) 2871 goto out; 2872 2873 ht_enable_msi_mapping(dev); 2874 2875 out: 2876 pci_dev_put(host_bridge); 2877 } 2878 2879 static void ht_disable_msi_mapping(struct pci_dev *dev) 2880 { 2881 int pos, ttl = PCI_FIND_CAP_TTL; 2882 2883 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2884 while (pos && ttl--) { 2885 u8 flags; 2886 2887 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2888 &flags) == 0) { 2889 pci_info(dev, "Disabling HT MSI Mapping\n"); 2890 2891 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2892 flags & ~HT_MSI_FLAGS_ENABLE); 2893 } 2894 pos = pci_find_next_ht_capability(dev, pos, 2895 HT_CAPTYPE_MSI_MAPPING); 2896 } 2897 } 2898 2899 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2900 { 2901 struct pci_dev *host_bridge; 2902 int pos; 2903 int found; 2904 2905 if (!pci_msi_enabled()) 2906 return; 2907 2908 /* check if there is HT MSI cap or enabled on this device */ 2909 found = ht_check_msi_mapping(dev); 2910 2911 /* no HT MSI CAP */ 2912 if (found == 0) 2913 return; 2914 2915 /* 2916 * HT MSI mapping should be disabled on devices that are below 2917 * a non-Hypertransport host bridge. Locate the host bridge... 2918 */ 2919 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2920 PCI_DEVFN(0, 0)); 2921 if (host_bridge == NULL) { 2922 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2923 return; 2924 } 2925 2926 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2927 if (pos != 0) { 2928 /* Host bridge is to HT */ 2929 if (found == 1) { 2930 /* it is not enabled, try to enable it */ 2931 if (all) 2932 ht_enable_msi_mapping(dev); 2933 else 2934 nv_ht_enable_msi_mapping(dev); 2935 } 2936 goto out; 2937 } 2938 2939 /* HT MSI is not enabled */ 2940 if (found == 1) 2941 goto out; 2942 2943 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2944 ht_disable_msi_mapping(dev); 2945 2946 out: 2947 pci_dev_put(host_bridge); 2948 } 2949 2950 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2951 { 2952 return __nv_msi_ht_cap_quirk(dev, 1); 2953 } 2954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2955 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2956 2957 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2958 { 2959 return __nv_msi_ht_cap_quirk(dev, 0); 2960 } 2961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2962 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2963 2964 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2965 { 2966 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2967 } 2968 2969 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2970 { 2971 struct pci_dev *p; 2972 2973 /* 2974 * SB700 MSI issue will be fixed at HW level from revision A21; 2975 * we need check PCI REVISION ID of SMBus controller to get SB700 2976 * revision. 2977 */ 2978 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2979 NULL); 2980 if (!p) 2981 return; 2982 2983 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2984 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2985 pci_dev_put(p); 2986 } 2987 2988 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2989 { 2990 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2991 if (dev->revision < 0x18) { 2992 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2993 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2994 } 2995 } 2996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2997 PCI_DEVICE_ID_TIGON3_5780, 2998 quirk_msi_intx_disable_bug); 2999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3000 PCI_DEVICE_ID_TIGON3_5780S, 3001 quirk_msi_intx_disable_bug); 3002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3003 PCI_DEVICE_ID_TIGON3_5714, 3004 quirk_msi_intx_disable_bug); 3005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3006 PCI_DEVICE_ID_TIGON3_5714S, 3007 quirk_msi_intx_disable_bug); 3008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3009 PCI_DEVICE_ID_TIGON3_5715, 3010 quirk_msi_intx_disable_bug); 3011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3012 PCI_DEVICE_ID_TIGON3_5715S, 3013 quirk_msi_intx_disable_bug); 3014 3015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3016 quirk_msi_intx_disable_ati_bug); 3017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3018 quirk_msi_intx_disable_ati_bug); 3019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3020 quirk_msi_intx_disable_ati_bug); 3021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3022 quirk_msi_intx_disable_ati_bug); 3023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3024 quirk_msi_intx_disable_ati_bug); 3025 3026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3027 quirk_msi_intx_disable_bug); 3028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3029 quirk_msi_intx_disable_bug); 3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3031 quirk_msi_intx_disable_bug); 3032 3033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3034 quirk_msi_intx_disable_bug); 3035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3036 quirk_msi_intx_disable_bug); 3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3038 quirk_msi_intx_disable_bug); 3039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3040 quirk_msi_intx_disable_bug); 3041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3042 quirk_msi_intx_disable_bug); 3043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3044 quirk_msi_intx_disable_bug); 3045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3046 quirk_msi_intx_disable_qca_bug); 3047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3048 quirk_msi_intx_disable_qca_bug); 3049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3050 quirk_msi_intx_disable_qca_bug); 3051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3052 quirk_msi_intx_disable_qca_bug); 3053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3054 quirk_msi_intx_disable_qca_bug); 3055 3056 /* 3057 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3058 * should be disabled on platforms where the device (mistakenly) advertises it. 3059 * 3060 * Notice that this quirk also disables MSI (which may work, but hasn't been 3061 * tested), since currently there is no standard way to disable only MSI-X. 3062 * 3063 * The 0031 device id is reused for other non Root Port device types, 3064 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3065 */ 3066 static void quirk_al_msi_disable(struct pci_dev *dev) 3067 { 3068 dev->no_msi = 1; 3069 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3070 } 3071 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3072 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3073 #endif /* CONFIG_PCI_MSI */ 3074 3075 /* 3076 * Allow manual resource allocation for PCI hotplug bridges via 3077 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3078 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3079 * allocate resources when hotplug device is inserted and PCI bus is 3080 * rescanned. 3081 */ 3082 static void quirk_hotplug_bridge(struct pci_dev *dev) 3083 { 3084 dev->is_hotplug_bridge = 1; 3085 } 3086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3087 3088 /* 3089 * This is a quirk for the Ricoh MMC controller found as a part of some 3090 * multifunction chips. 3091 * 3092 * This is very similar and based on the ricoh_mmc driver written by 3093 * Philip Langdale. Thank you for these magic sequences. 3094 * 3095 * These chips implement the four main memory card controllers (SD, MMC, 3096 * MS, xD) and one or both of CardBus or FireWire. 3097 * 3098 * It happens that they implement SD and MMC support as separate 3099 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3100 * cards but the chip detects MMC cards in hardware and directs them to the 3101 * MMC controller - so the SDHCI driver never sees them. 3102 * 3103 * To get around this, we must disable the useless MMC controller. At that 3104 * point, the SDHCI controller will start seeing them. It seems to be the 3105 * case that the relevant PCI registers to deactivate the MMC controller 3106 * live on PCI function 0, which might be the CardBus controller or the 3107 * FireWire controller, depending on the particular chip in question 3108 * 3109 * This has to be done early, because as soon as we disable the MMC controller 3110 * other PCI functions shift up one level, e.g. function #2 becomes function 3111 * #1, and this will confuse the PCI core. 3112 */ 3113 #ifdef CONFIG_MMC_RICOH_MMC 3114 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3115 { 3116 u8 write_enable; 3117 u8 write_target; 3118 u8 disable; 3119 3120 /* 3121 * Disable via CardBus interface 3122 * 3123 * This must be done via function #0 3124 */ 3125 if (PCI_FUNC(dev->devfn)) 3126 return; 3127 3128 pci_read_config_byte(dev, 0xB7, &disable); 3129 if (disable & 0x02) 3130 return; 3131 3132 pci_read_config_byte(dev, 0x8E, &write_enable); 3133 pci_write_config_byte(dev, 0x8E, 0xAA); 3134 pci_read_config_byte(dev, 0x8D, &write_target); 3135 pci_write_config_byte(dev, 0x8D, 0xB7); 3136 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3137 pci_write_config_byte(dev, 0x8E, write_enable); 3138 pci_write_config_byte(dev, 0x8D, write_target); 3139 3140 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3141 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3142 } 3143 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3144 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3145 3146 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3147 { 3148 u8 write_enable; 3149 u8 disable; 3150 3151 /* 3152 * Disable via FireWire interface 3153 * 3154 * This must be done via function #0 3155 */ 3156 if (PCI_FUNC(dev->devfn)) 3157 return; 3158 /* 3159 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3160 * certain types of SD/MMC cards. Lowering the SD base clock 3161 * frequency from 200Mhz to 50Mhz fixes this issue. 3162 * 3163 * 0x150 - SD2.0 mode enable for changing base clock 3164 * frequency to 50Mhz 3165 * 0xe1 - Base clock frequency 3166 * 0x32 - 50Mhz new clock frequency 3167 * 0xf9 - Key register for 0x150 3168 * 0xfc - key register for 0xe1 3169 */ 3170 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3171 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3172 pci_write_config_byte(dev, 0xf9, 0xfc); 3173 pci_write_config_byte(dev, 0x150, 0x10); 3174 pci_write_config_byte(dev, 0xf9, 0x00); 3175 pci_write_config_byte(dev, 0xfc, 0x01); 3176 pci_write_config_byte(dev, 0xe1, 0x32); 3177 pci_write_config_byte(dev, 0xfc, 0x00); 3178 3179 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3180 } 3181 3182 pci_read_config_byte(dev, 0xCB, &disable); 3183 3184 if (disable & 0x02) 3185 return; 3186 3187 pci_read_config_byte(dev, 0xCA, &write_enable); 3188 pci_write_config_byte(dev, 0xCA, 0x57); 3189 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3190 pci_write_config_byte(dev, 0xCA, write_enable); 3191 3192 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3193 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3194 3195 } 3196 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3197 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3198 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3199 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3200 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3201 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3202 #endif /*CONFIG_MMC_RICOH_MMC*/ 3203 3204 #ifdef CONFIG_DMAR_TABLE 3205 #define VTUNCERRMSK_REG 0x1ac 3206 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3207 /* 3208 * This is a quirk for masking VT-d spec-defined errors to platform error 3209 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3210 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3211 * on the RAS config settings of the platform) when a VT-d fault happens. 3212 * The resulting SMI caused the system to hang. 3213 * 3214 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3215 * need to report the same error through other channels. 3216 */ 3217 static void vtd_mask_spec_errors(struct pci_dev *dev) 3218 { 3219 u32 word; 3220 3221 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3222 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3223 } 3224 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3225 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3226 #endif 3227 3228 static void fixup_ti816x_class(struct pci_dev *dev) 3229 { 3230 u32 class = dev->class; 3231 3232 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3233 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3234 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3235 class, dev->class); 3236 } 3237 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3238 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3239 3240 /* 3241 * Some PCIe devices do not work reliably with the claimed maximum 3242 * payload size supported. 3243 */ 3244 static void fixup_mpss_256(struct pci_dev *dev) 3245 { 3246 dev->pcie_mpss = 1; /* 256 bytes */ 3247 } 3248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3249 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3251 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3253 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3254 3255 /* 3256 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3257 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3258 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3259 * until all of the devices are discovered and buses walked, read completion 3260 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3261 * it is possible to hotplug a device with MPS of 256B. 3262 */ 3263 static void quirk_intel_mc_errata(struct pci_dev *dev) 3264 { 3265 int err; 3266 u16 rcc; 3267 3268 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3269 pcie_bus_config == PCIE_BUS_DEFAULT) 3270 return; 3271 3272 /* 3273 * Intel erratum specifies bits to change but does not say what 3274 * they are. Keeping them magical until such time as the registers 3275 * and values can be explained. 3276 */ 3277 err = pci_read_config_word(dev, 0x48, &rcc); 3278 if (err) { 3279 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3280 return; 3281 } 3282 3283 if (!(rcc & (1 << 10))) 3284 return; 3285 3286 rcc &= ~(1 << 10); 3287 3288 err = pci_write_config_word(dev, 0x48, rcc); 3289 if (err) { 3290 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3291 return; 3292 } 3293 3294 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3295 } 3296 /* Intel 5000 series memory controllers and ports 2-7 */ 3297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3311 /* Intel 5100 series memory controllers and ports 2-7 */ 3312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3323 3324 /* 3325 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3326 * To work around this, query the size it should be configured to by the 3327 * device and modify the resource end to correspond to this new size. 3328 */ 3329 static void quirk_intel_ntb(struct pci_dev *dev) 3330 { 3331 int rc; 3332 u8 val; 3333 3334 rc = pci_read_config_byte(dev, 0x00D0, &val); 3335 if (rc) 3336 return; 3337 3338 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3339 3340 rc = pci_read_config_byte(dev, 0x00D1, &val); 3341 if (rc) 3342 return; 3343 3344 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3345 } 3346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3348 3349 /* 3350 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3351 * though no one is handling them (e.g., if the i915 driver is never 3352 * loaded). Additionally the interrupt destination is not set up properly 3353 * and the interrupt ends up -somewhere-. 3354 * 3355 * These spurious interrupts are "sticky" and the kernel disables the 3356 * (shared) interrupt line after 100,000+ generated interrupts. 3357 * 3358 * Fix it by disabling the still enabled interrupts. This resolves crashes 3359 * often seen on monitor unplug. 3360 */ 3361 #define I915_DEIER_REG 0x4400c 3362 static void disable_igfx_irq(struct pci_dev *dev) 3363 { 3364 void __iomem *regs = pci_iomap(dev, 0, 0); 3365 if (regs == NULL) { 3366 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3367 return; 3368 } 3369 3370 /* Check if any interrupt line is still enabled */ 3371 if (readl(regs + I915_DEIER_REG) != 0) { 3372 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3373 3374 writel(0, regs + I915_DEIER_REG); 3375 } 3376 3377 pci_iounmap(dev, regs); 3378 } 3379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3386 3387 /* 3388 * PCI devices which are on Intel chips can skip the 10ms delay 3389 * before entering D3 mode. 3390 */ 3391 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3392 { 3393 dev->d3hot_delay = 0; 3394 } 3395 /* C600 Series devices do not need 10ms d3hot_delay */ 3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3399 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3411 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3421 3422 /* 3423 * Some devices may pass our check in pci_intx_mask_supported() if 3424 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3425 * support this feature. 3426 */ 3427 static void quirk_broken_intx_masking(struct pci_dev *dev) 3428 { 3429 dev->broken_intx_masking = 1; 3430 } 3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3432 quirk_broken_intx_masking); 3433 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3434 quirk_broken_intx_masking); 3435 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3436 quirk_broken_intx_masking); 3437 3438 /* 3439 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3440 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3441 * 3442 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3443 */ 3444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3445 quirk_broken_intx_masking); 3446 3447 /* 3448 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3449 * DisINTx can be set but the interrupt status bit is non-functional. 3450 */ 3451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3455 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3467 3468 static u16 mellanox_broken_intx_devs[] = { 3469 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3470 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3471 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3472 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3473 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3474 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3475 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3476 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3477 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3478 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3479 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3480 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3481 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3482 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3483 }; 3484 3485 #define CONNECTX_4_CURR_MAX_MINOR 99 3486 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3487 3488 /* 3489 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3490 * If so, don't mark it as broken. 3491 * FW minor > 99 means older FW version format and no INTx masking support. 3492 * FW minor < 14 means new FW version format and no INTx masking support. 3493 */ 3494 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3495 { 3496 __be32 __iomem *fw_ver; 3497 u16 fw_major; 3498 u16 fw_minor; 3499 u16 fw_subminor; 3500 u32 fw_maj_min; 3501 u32 fw_sub_min; 3502 int i; 3503 3504 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3505 if (pdev->device == mellanox_broken_intx_devs[i]) { 3506 pdev->broken_intx_masking = 1; 3507 return; 3508 } 3509 } 3510 3511 /* 3512 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3513 * support so shouldn't be checked further 3514 */ 3515 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3516 return; 3517 3518 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3519 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3520 return; 3521 3522 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3523 if (pci_enable_device_mem(pdev)) { 3524 pci_warn(pdev, "Can't enable device memory\n"); 3525 return; 3526 } 3527 3528 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3529 if (!fw_ver) { 3530 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3531 goto out; 3532 } 3533 3534 /* Reading from resource space should be 32b aligned */ 3535 fw_maj_min = ioread32be(fw_ver); 3536 fw_sub_min = ioread32be(fw_ver + 1); 3537 fw_major = fw_maj_min & 0xffff; 3538 fw_minor = fw_maj_min >> 16; 3539 fw_subminor = fw_sub_min & 0xffff; 3540 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3541 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3542 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3543 fw_major, fw_minor, fw_subminor, pdev->device == 3544 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3545 pdev->broken_intx_masking = 1; 3546 } 3547 3548 iounmap(fw_ver); 3549 3550 out: 3551 pci_disable_device(pdev); 3552 } 3553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3554 mellanox_check_broken_intx_masking); 3555 3556 static void quirk_no_bus_reset(struct pci_dev *dev) 3557 { 3558 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3559 } 3560 3561 /* 3562 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3563 * The device will throw a Link Down error on AER-capable systems and 3564 * regardless of AER, config space of the device is never accessible again 3565 * and typically causes the system to hang or reset when access is attempted. 3566 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3567 */ 3568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3573 3574 /* 3575 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3576 * reset when used with certain child devices. After the reset, config 3577 * accesses to the child may fail. 3578 */ 3579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3580 3581 static void quirk_no_pm_reset(struct pci_dev *dev) 3582 { 3583 /* 3584 * We can't do a bus reset on root bus devices, but an ineffective 3585 * PM reset may be better than nothing. 3586 */ 3587 if (!pci_is_root_bus(dev->bus)) 3588 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3589 } 3590 3591 /* 3592 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3593 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3594 * to have no effect on the device: it retains the framebuffer contents and 3595 * monitor sync. Advertising this support makes other layers, like VFIO, 3596 * assume pci_reset_function() is viable for this device. Mark it as 3597 * unavailable to skip it when testing reset methods. 3598 */ 3599 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3600 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3601 3602 /* 3603 * Thunderbolt controllers with broken MSI hotplug signaling: 3604 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3605 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3606 */ 3607 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3608 { 3609 if (pdev->is_hotplug_bridge && 3610 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3611 pdev->revision <= 1)) 3612 pdev->no_msi = 1; 3613 } 3614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3615 quirk_thunderbolt_hotplug_msi); 3616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3617 quirk_thunderbolt_hotplug_msi); 3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3619 quirk_thunderbolt_hotplug_msi); 3620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3621 quirk_thunderbolt_hotplug_msi); 3622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3623 quirk_thunderbolt_hotplug_msi); 3624 3625 #ifdef CONFIG_ACPI 3626 /* 3627 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3628 * 3629 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3630 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3631 * be present after resume if a device was plugged in before suspend. 3632 * 3633 * The Thunderbolt controller consists of a PCIe switch with downstream 3634 * bridges leading to the NHI and to the tunnel PCI bridges. 3635 * 3636 * This quirk cuts power to the whole chip. Therefore we have to apply it 3637 * during suspend_noirq of the upstream bridge. 3638 * 3639 * Power is automagically restored before resume. No action is needed. 3640 */ 3641 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3642 { 3643 acpi_handle bridge, SXIO, SXFP, SXLV; 3644 3645 if (!x86_apple_machine) 3646 return; 3647 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3648 return; 3649 bridge = ACPI_HANDLE(&dev->dev); 3650 if (!bridge) 3651 return; 3652 3653 /* 3654 * SXIO and SXLV are present only on machines requiring this quirk. 3655 * Thunderbolt bridges in external devices might have the same 3656 * device ID as those on the host, but they will not have the 3657 * associated ACPI methods. This implicitly checks that we are at 3658 * the right bridge. 3659 */ 3660 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3661 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3662 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3663 return; 3664 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3665 3666 /* magic sequence */ 3667 acpi_execute_simple_method(SXIO, NULL, 1); 3668 acpi_execute_simple_method(SXFP, NULL, 0); 3669 msleep(300); 3670 acpi_execute_simple_method(SXLV, NULL, 0); 3671 acpi_execute_simple_method(SXIO, NULL, 0); 3672 acpi_execute_simple_method(SXLV, NULL, 0); 3673 } 3674 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3675 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3676 quirk_apple_poweroff_thunderbolt); 3677 #endif 3678 3679 /* 3680 * Following are device-specific reset methods which can be used to 3681 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3682 * not available. 3683 */ 3684 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3685 { 3686 /* 3687 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3688 * 3689 * The 82599 supports FLR on VFs, but FLR support is reported only 3690 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3691 * Thus we must call pcie_flr() directly without first checking if it is 3692 * supported. 3693 */ 3694 if (!probe) 3695 pcie_flr(dev); 3696 return 0; 3697 } 3698 3699 #define SOUTH_CHICKEN2 0xc2004 3700 #define PCH_PP_STATUS 0xc7200 3701 #define PCH_PP_CONTROL 0xc7204 3702 #define MSG_CTL 0x45010 3703 #define NSDE_PWR_STATE 0xd0100 3704 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3705 3706 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3707 { 3708 void __iomem *mmio_base; 3709 unsigned long timeout; 3710 u32 val; 3711 3712 if (probe) 3713 return 0; 3714 3715 mmio_base = pci_iomap(dev, 0, 0); 3716 if (!mmio_base) 3717 return -ENOMEM; 3718 3719 iowrite32(0x00000002, mmio_base + MSG_CTL); 3720 3721 /* 3722 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3723 * driver loaded sets the right bits. However, this's a reset and 3724 * the bits have been set by i915 previously, so we clobber 3725 * SOUTH_CHICKEN2 register directly here. 3726 */ 3727 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3728 3729 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3730 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3731 3732 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3733 do { 3734 val = ioread32(mmio_base + PCH_PP_STATUS); 3735 if ((val & 0xb0000000) == 0) 3736 goto reset_complete; 3737 msleep(10); 3738 } while (time_before(jiffies, timeout)); 3739 pci_warn(dev, "timeout during reset\n"); 3740 3741 reset_complete: 3742 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3743 3744 pci_iounmap(dev, mmio_base); 3745 return 0; 3746 } 3747 3748 /* Device-specific reset method for Chelsio T4-based adapters */ 3749 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3750 { 3751 u16 old_command; 3752 u16 msix_flags; 3753 3754 /* 3755 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3756 * that we have no device-specific reset method. 3757 */ 3758 if ((dev->device & 0xf000) != 0x4000) 3759 return -ENOTTY; 3760 3761 /* 3762 * If this is the "probe" phase, return 0 indicating that we can 3763 * reset this device. 3764 */ 3765 if (probe) 3766 return 0; 3767 3768 /* 3769 * T4 can wedge if there are DMAs in flight within the chip and Bus 3770 * Master has been disabled. We need to have it on till the Function 3771 * Level Reset completes. (BUS_MASTER is disabled in 3772 * pci_reset_function()). 3773 */ 3774 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3775 pci_write_config_word(dev, PCI_COMMAND, 3776 old_command | PCI_COMMAND_MASTER); 3777 3778 /* 3779 * Perform the actual device function reset, saving and restoring 3780 * configuration information around the reset. 3781 */ 3782 pci_save_state(dev); 3783 3784 /* 3785 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3786 * are disabled when an MSI-X interrupt message needs to be delivered. 3787 * So we briefly re-enable MSI-X interrupts for the duration of the 3788 * FLR. The pci_restore_state() below will restore the original 3789 * MSI-X state. 3790 */ 3791 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3792 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3793 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3794 msix_flags | 3795 PCI_MSIX_FLAGS_ENABLE | 3796 PCI_MSIX_FLAGS_MASKALL); 3797 3798 pcie_flr(dev); 3799 3800 /* 3801 * Restore the configuration information (BAR values, etc.) including 3802 * the original PCI Configuration Space Command word, and return 3803 * success. 3804 */ 3805 pci_restore_state(dev); 3806 pci_write_config_word(dev, PCI_COMMAND, old_command); 3807 return 0; 3808 } 3809 3810 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3811 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3812 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3813 3814 /* 3815 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 3816 * FLR where config space reads from the device return -1. We seem to be 3817 * able to avoid this condition if we disable the NVMe controller prior to 3818 * FLR. This quirk is generic for any NVMe class device requiring similar 3819 * assistance to quiesce the device prior to FLR. 3820 * 3821 * NVMe specification: https://nvmexpress.org/resources/specifications/ 3822 * Revision 1.0e: 3823 * Chapter 2: Required and optional PCI config registers 3824 * Chapter 3: NVMe control registers 3825 * Chapter 7.3: Reset behavior 3826 */ 3827 static int nvme_disable_and_flr(struct pci_dev *dev, int probe) 3828 { 3829 void __iomem *bar; 3830 u16 cmd; 3831 u32 cfg; 3832 3833 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 3834 !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) 3835 return -ENOTTY; 3836 3837 if (probe) 3838 return 0; 3839 3840 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 3841 if (!bar) 3842 return -ENOTTY; 3843 3844 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3845 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 3846 3847 cfg = readl(bar + NVME_REG_CC); 3848 3849 /* Disable controller if enabled */ 3850 if (cfg & NVME_CC_ENABLE) { 3851 u32 cap = readl(bar + NVME_REG_CAP); 3852 unsigned long timeout; 3853 3854 /* 3855 * Per nvme_disable_ctrl() skip shutdown notification as it 3856 * could complete commands to the admin queue. We only intend 3857 * to quiesce the device before reset. 3858 */ 3859 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 3860 3861 writel(cfg, bar + NVME_REG_CC); 3862 3863 /* 3864 * Some controllers require an additional delay here, see 3865 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 3866 * supported by this quirk. 3867 */ 3868 3869 /* Cap register provides max timeout in 500ms increments */ 3870 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 3871 3872 for (;;) { 3873 u32 status = readl(bar + NVME_REG_CSTS); 3874 3875 /* Ready status becomes zero on disable complete */ 3876 if (!(status & NVME_CSTS_RDY)) 3877 break; 3878 3879 msleep(100); 3880 3881 if (time_after(jiffies, timeout)) { 3882 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 3883 break; 3884 } 3885 } 3886 } 3887 3888 pci_iounmap(dev, bar); 3889 3890 pcie_flr(dev); 3891 3892 return 0; 3893 } 3894 3895 /* 3896 * Intel DC P3700 NVMe controller will timeout waiting for ready status 3897 * to change after NVMe enable if the driver starts interacting with the 3898 * device too soon after FLR. A 250ms delay after FLR has heuristically 3899 * proven to produce reliably working results for device assignment cases. 3900 */ 3901 static int delay_250ms_after_flr(struct pci_dev *dev, int probe) 3902 { 3903 if (!pcie_has_flr(dev)) 3904 return -ENOTTY; 3905 3906 if (probe) 3907 return 0; 3908 3909 pcie_flr(dev); 3910 3911 msleep(250); 3912 3913 return 0; 3914 } 3915 3916 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3917 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3918 reset_intel_82599_sfp_virtfn }, 3919 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3920 reset_ivb_igd }, 3921 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3922 reset_ivb_igd }, 3923 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 3924 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 3925 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3926 reset_chelsio_generic_dev }, 3927 { 0 } 3928 }; 3929 3930 /* 3931 * These device-specific reset methods are here rather than in a driver 3932 * because when a host assigns a device to a guest VM, the host may need 3933 * to reset the device but probably doesn't have a driver for it. 3934 */ 3935 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3936 { 3937 const struct pci_dev_reset_methods *i; 3938 3939 for (i = pci_dev_reset_methods; i->reset; i++) { 3940 if ((i->vendor == dev->vendor || 3941 i->vendor == (u16)PCI_ANY_ID) && 3942 (i->device == dev->device || 3943 i->device == (u16)PCI_ANY_ID)) 3944 return i->reset(dev, probe); 3945 } 3946 3947 return -ENOTTY; 3948 } 3949 3950 static void quirk_dma_func0_alias(struct pci_dev *dev) 3951 { 3952 if (PCI_FUNC(dev->devfn) != 0) 3953 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 3954 } 3955 3956 /* 3957 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3958 * 3959 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3960 */ 3961 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3963 3964 static void quirk_dma_func1_alias(struct pci_dev *dev) 3965 { 3966 if (PCI_FUNC(dev->devfn) != 1) 3967 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 3968 } 3969 3970 /* 3971 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3972 * SKUs function 1 is present and is a legacy IDE controller, in other 3973 * SKUs this function is not present, making this a ghost requester. 3974 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3975 */ 3976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3977 quirk_dma_func1_alias); 3978 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3979 quirk_dma_func1_alias); 3980 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 3981 quirk_dma_func1_alias); 3982 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3983 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3984 quirk_dma_func1_alias); 3985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 3986 quirk_dma_func1_alias); 3987 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3989 quirk_dma_func1_alias); 3990 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3992 quirk_dma_func1_alias); 3993 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3995 quirk_dma_func1_alias); 3996 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 3997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 3998 quirk_dma_func1_alias); 3999 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4001 quirk_dma_func1_alias); 4002 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4004 quirk_dma_func1_alias); 4005 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4007 quirk_dma_func1_alias); 4008 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4010 quirk_dma_func1_alias); 4011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4012 quirk_dma_func1_alias); 4013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4014 quirk_dma_func1_alias); 4015 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4017 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4018 quirk_dma_func1_alias); 4019 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4020 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4021 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4022 quirk_dma_func1_alias); 4023 4024 /* 4025 * Some devices DMA with the wrong devfn, not just the wrong function. 4026 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4027 * the alias is "fixed" and independent of the device devfn. 4028 * 4029 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4030 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4031 * single device on the secondary bus. In reality, the single exposed 4032 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4033 * that provides a bridge to the internal bus of the I/O processor. The 4034 * controller supports private devices, which can be hidden from PCI config 4035 * space. In the case of the Adaptec 3405, a private device at 01.0 4036 * appears to be the DMA engine, which therefore needs to become a DMA 4037 * alias for the device. 4038 */ 4039 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4040 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4041 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4042 .driver_data = PCI_DEVFN(1, 0) }, 4043 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4044 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4045 .driver_data = PCI_DEVFN(1, 0) }, 4046 { 0 } 4047 }; 4048 4049 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4050 { 4051 const struct pci_device_id *id; 4052 4053 id = pci_match_id(fixed_dma_alias_tbl, dev); 4054 if (id) 4055 pci_add_dma_alias(dev, id->driver_data, 1); 4056 } 4057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4058 4059 /* 4060 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4061 * using the wrong DMA alias for the device. Some of these devices can be 4062 * used as either forward or reverse bridges, so we need to test whether the 4063 * device is operating in the correct mode. We could probably apply this 4064 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4065 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4066 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4067 */ 4068 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4069 { 4070 if (!pci_is_root_bus(pdev->bus) && 4071 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4072 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4073 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4074 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4075 } 4076 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4078 quirk_use_pcie_bridge_dma_alias); 4079 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4080 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4081 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4082 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4083 /* ITE 8893 has the same problem as the 8892 */ 4084 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4085 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4086 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4087 4088 /* 4089 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4090 * be added as aliases to the DMA device in order to allow buffer access 4091 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4092 * programmed in the EEPROM. 4093 */ 4094 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4095 { 4096 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4097 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4098 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4099 } 4100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4102 4103 /* 4104 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4105 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4106 * 4107 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4108 * when IOMMU is enabled. These aliases allow computational unit access to 4109 * host memory. These aliases mark the whole VCA device as one IOMMU 4110 * group. 4111 * 4112 * All possible slot numbers (0x20) are used, since we are unable to tell 4113 * what slot is used on other side. This quirk is intended for both host 4114 * and computational unit sides. The VCA devices have up to five functions 4115 * (four for DMA channels and one additional). 4116 */ 4117 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4118 { 4119 const unsigned int num_pci_slots = 0x20; 4120 unsigned int slot; 4121 4122 for (slot = 0; slot < num_pci_slots; slot++) 4123 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4124 } 4125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4131 4132 /* 4133 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4134 * associated not at the root bus, but at a bridge below. This quirk avoids 4135 * generating invalid DMA aliases. 4136 */ 4137 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4138 { 4139 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4140 } 4141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4142 quirk_bridge_cavm_thrx2_pcie_root); 4143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4144 quirk_bridge_cavm_thrx2_pcie_root); 4145 4146 /* 4147 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4148 * class code. Fix it. 4149 */ 4150 static void quirk_tw686x_class(struct pci_dev *pdev) 4151 { 4152 u32 class = pdev->class; 4153 4154 /* Use "Multimedia controller" class */ 4155 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4156 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4157 class, pdev->class); 4158 } 4159 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4160 quirk_tw686x_class); 4161 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4162 quirk_tw686x_class); 4163 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4164 quirk_tw686x_class); 4165 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4166 quirk_tw686x_class); 4167 4168 /* 4169 * Some devices have problems with Transaction Layer Packets with the Relaxed 4170 * Ordering Attribute set. Such devices should mark themselves and other 4171 * device drivers should check before sending TLPs with RO set. 4172 */ 4173 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4174 { 4175 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4176 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4177 } 4178 4179 /* 4180 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4181 * Complex have a Flow Control Credit issue which can cause performance 4182 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4183 */ 4184 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4185 quirk_relaxedordering_disable); 4186 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4187 quirk_relaxedordering_disable); 4188 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4189 quirk_relaxedordering_disable); 4190 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4191 quirk_relaxedordering_disable); 4192 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4193 quirk_relaxedordering_disable); 4194 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4195 quirk_relaxedordering_disable); 4196 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4197 quirk_relaxedordering_disable); 4198 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4199 quirk_relaxedordering_disable); 4200 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4201 quirk_relaxedordering_disable); 4202 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4203 quirk_relaxedordering_disable); 4204 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4205 quirk_relaxedordering_disable); 4206 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4207 quirk_relaxedordering_disable); 4208 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4209 quirk_relaxedordering_disable); 4210 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4211 quirk_relaxedordering_disable); 4212 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4213 quirk_relaxedordering_disable); 4214 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4215 quirk_relaxedordering_disable); 4216 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4217 quirk_relaxedordering_disable); 4218 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4219 quirk_relaxedordering_disable); 4220 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4221 quirk_relaxedordering_disable); 4222 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4223 quirk_relaxedordering_disable); 4224 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4225 quirk_relaxedordering_disable); 4226 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4227 quirk_relaxedordering_disable); 4228 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4229 quirk_relaxedordering_disable); 4230 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4231 quirk_relaxedordering_disable); 4232 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4233 quirk_relaxedordering_disable); 4234 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4235 quirk_relaxedordering_disable); 4236 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4237 quirk_relaxedordering_disable); 4238 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4239 quirk_relaxedordering_disable); 4240 4241 /* 4242 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4243 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4244 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4245 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4246 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4247 * November 10, 2010). As a result, on this platform we can't use Relaxed 4248 * Ordering for Upstream TLPs. 4249 */ 4250 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4251 quirk_relaxedordering_disable); 4252 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4253 quirk_relaxedordering_disable); 4254 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4255 quirk_relaxedordering_disable); 4256 4257 /* 4258 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4259 * values for the Attribute as were supplied in the header of the 4260 * corresponding Request, except as explicitly allowed when IDO is used." 4261 * 4262 * If a non-compliant device generates a completion with a different 4263 * attribute than the request, the receiver may accept it (which itself 4264 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4265 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4266 * device access timeout. 4267 * 4268 * If the non-compliant device generates completions with zero attributes 4269 * (instead of copying the attributes from the request), we can work around 4270 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4271 * upstream devices so they always generate requests with zero attributes. 4272 * 4273 * This affects other devices under the same Root Port, but since these 4274 * attributes are performance hints, there should be no functional problem. 4275 * 4276 * Note that Configuration Space accesses are never supposed to have TLP 4277 * Attributes, so we're safe waiting till after any Configuration Space 4278 * accesses to do the Root Port fixup. 4279 */ 4280 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4281 { 4282 struct pci_dev *root_port = pcie_find_root_port(pdev); 4283 4284 if (!root_port) { 4285 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4286 return; 4287 } 4288 4289 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4290 dev_name(&pdev->dev)); 4291 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4292 PCI_EXP_DEVCTL_RELAX_EN | 4293 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4294 } 4295 4296 /* 4297 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4298 * Completion it generates. 4299 */ 4300 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4301 { 4302 /* 4303 * This mask/compare operation selects for Physical Function 4 on a 4304 * T5. We only need to fix up the Root Port once for any of the 4305 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4306 * 0x54xx so we use that one. 4307 */ 4308 if ((pdev->device & 0xff00) == 0x5400) 4309 quirk_disable_root_port_attributes(pdev); 4310 } 4311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4312 quirk_chelsio_T5_disable_root_port_attributes); 4313 4314 /* 4315 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4316 * by a device 4317 * @acs_ctrl_req: Bitmask of desired ACS controls 4318 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4319 * the hardware design 4320 * 4321 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4322 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4323 * caller desires. Return 0 otherwise. 4324 */ 4325 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4326 { 4327 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4328 return 1; 4329 return 0; 4330 } 4331 4332 /* 4333 * AMD has indicated that the devices below do not support peer-to-peer 4334 * in any system where they are found in the southbridge with an AMD 4335 * IOMMU in the system. Multifunction devices that do not support 4336 * peer-to-peer between functions can claim to support a subset of ACS. 4337 * Such devices effectively enable request redirect (RR) and completion 4338 * redirect (CR) since all transactions are redirected to the upstream 4339 * root complex. 4340 * 4341 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4342 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4343 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4344 * 4345 * 1002:4385 SBx00 SMBus Controller 4346 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4347 * 1002:4383 SBx00 Azalia (Intel HDA) 4348 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4349 * 1002:4384 SBx00 PCI to PCI Bridge 4350 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4351 * 4352 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4353 * 4354 * 1022:780f [AMD] FCH PCI Bridge 4355 * 1022:7809 [AMD] FCH USB OHCI Controller 4356 */ 4357 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4358 { 4359 #ifdef CONFIG_ACPI 4360 struct acpi_table_header *header = NULL; 4361 acpi_status status; 4362 4363 /* Targeting multifunction devices on the SB (appears on root bus) */ 4364 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4365 return -ENODEV; 4366 4367 /* The IVRS table describes the AMD IOMMU */ 4368 status = acpi_get_table("IVRS", 0, &header); 4369 if (ACPI_FAILURE(status)) 4370 return -ENODEV; 4371 4372 acpi_put_table(header); 4373 4374 /* Filter out flags not applicable to multifunction */ 4375 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4376 4377 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4378 #else 4379 return -ENODEV; 4380 #endif 4381 } 4382 4383 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4384 { 4385 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4386 return false; 4387 4388 switch (dev->device) { 4389 /* 4390 * Effectively selects all downstream ports for whole ThunderX1 4391 * (which represents 8 SoCs). 4392 */ 4393 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4394 case 0xaf84: /* ThunderX2 */ 4395 case 0xb884: /* ThunderX3 */ 4396 return true; 4397 default: 4398 return false; 4399 } 4400 } 4401 4402 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4403 { 4404 if (!pci_quirk_cavium_acs_match(dev)) 4405 return -ENOTTY; 4406 4407 /* 4408 * Cavium Root Ports don't advertise an ACS capability. However, 4409 * the RTL internally implements similar protection as if ACS had 4410 * Source Validation, Request Redirection, Completion Redirection, 4411 * and Upstream Forwarding features enabled. Assert that the 4412 * hardware implements and enables equivalent ACS functionality for 4413 * these flags. 4414 */ 4415 return pci_acs_ctrl_enabled(acs_flags, 4416 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4417 } 4418 4419 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4420 { 4421 /* 4422 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4423 * transactions with others, allowing masking out these bits as if they 4424 * were unimplemented in the ACS capability. 4425 */ 4426 return pci_acs_ctrl_enabled(acs_flags, 4427 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4428 } 4429 4430 /* 4431 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4432 * But the implementation could block peer-to-peer transactions between them 4433 * and provide ACS-like functionality. 4434 */ 4435 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4436 { 4437 if (!pci_is_pcie(dev) || 4438 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4439 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4440 return -ENOTTY; 4441 4442 switch (dev->device) { 4443 case 0x0710 ... 0x071e: 4444 case 0x0721: 4445 case 0x0723 ... 0x0732: 4446 return pci_acs_ctrl_enabled(acs_flags, 4447 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4448 } 4449 4450 return false; 4451 } 4452 4453 /* 4454 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4455 * transactions and validate bus numbers in requests, but do not provide an 4456 * actual PCIe ACS capability. This is the list of device IDs known to fall 4457 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4458 */ 4459 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4460 /* Ibexpeak PCH */ 4461 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4462 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4463 /* Cougarpoint PCH */ 4464 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4465 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4466 /* Pantherpoint PCH */ 4467 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4468 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4469 /* Lynxpoint-H PCH */ 4470 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4471 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4472 /* Lynxpoint-LP PCH */ 4473 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4474 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4475 /* Wildcat PCH */ 4476 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4477 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4478 /* Patsburg (X79) PCH */ 4479 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4480 /* Wellsburg (X99) PCH */ 4481 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4482 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4483 /* Lynx Point (9 series) PCH */ 4484 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4485 }; 4486 4487 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4488 { 4489 int i; 4490 4491 /* Filter out a few obvious non-matches first */ 4492 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4493 return false; 4494 4495 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4496 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4497 return true; 4498 4499 return false; 4500 } 4501 4502 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4503 { 4504 if (!pci_quirk_intel_pch_acs_match(dev)) 4505 return -ENOTTY; 4506 4507 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4508 return pci_acs_ctrl_enabled(acs_flags, 4509 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4510 4511 return pci_acs_ctrl_enabled(acs_flags, 0); 4512 } 4513 4514 /* 4515 * These QCOM Root Ports do provide ACS-like features to disable peer 4516 * transactions and validate bus numbers in requests, but do not provide an 4517 * actual PCIe ACS capability. Hardware supports source validation but it 4518 * will report the issue as Completer Abort instead of ACS Violation. 4519 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4520 * Complex with unique segment numbers. It is not possible for one Root 4521 * Port to pass traffic to another Root Port. All PCIe transactions are 4522 * terminated inside the Root Port. 4523 */ 4524 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4525 { 4526 return pci_acs_ctrl_enabled(acs_flags, 4527 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4528 } 4529 4530 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4531 { 4532 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4533 return -ENOTTY; 4534 4535 /* 4536 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4537 * but do include ACS-like functionality. The hardware doesn't support 4538 * peer-to-peer transactions via the root port and each has a unique 4539 * segment number. 4540 * 4541 * Additionally, the root ports cannot send traffic to each other. 4542 */ 4543 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4544 4545 return acs_flags ? 0 : 1; 4546 } 4547 4548 /* 4549 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4550 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4551 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4552 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4553 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4554 * control register is at offset 8 instead of 6 and we should probably use 4555 * dword accesses to them. This applies to the following PCI Device IDs, as 4556 * found in volume 1 of the datasheet[2]: 4557 * 4558 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4559 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4560 * 4561 * N.B. This doesn't fix what lspci shows. 4562 * 4563 * The 100 series chipset specification update includes this as errata #23[3]. 4564 * 4565 * The 200 series chipset (Union Point) has the same bug according to the 4566 * specification update (Intel 200 Series Chipset Family Platform Controller 4567 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4568 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4569 * chipset include: 4570 * 4571 * 0xa290-0xa29f PCI Express Root port #{0-16} 4572 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4573 * 4574 * Mobile chipsets are also affected, 7th & 8th Generation 4575 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4576 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4577 * Processor Family I/O for U Quad Core Platforms Specification Update, 4578 * August 2017, Revision 002, Document#: 334660-002)[6] 4579 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4580 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4581 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4582 * 4583 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4584 * 4585 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4586 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4587 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4588 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4589 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4590 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4591 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4592 */ 4593 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4594 { 4595 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4596 return false; 4597 4598 switch (dev->device) { 4599 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4600 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4601 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4602 return true; 4603 } 4604 4605 return false; 4606 } 4607 4608 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4609 4610 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4611 { 4612 int pos; 4613 u32 cap, ctrl; 4614 4615 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4616 return -ENOTTY; 4617 4618 pos = dev->acs_cap; 4619 if (!pos) 4620 return -ENOTTY; 4621 4622 /* see pci_acs_flags_enabled() */ 4623 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4624 acs_flags &= (cap | PCI_ACS_EC); 4625 4626 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4627 4628 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4629 } 4630 4631 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4632 { 4633 /* 4634 * SV, TB, and UF are not relevant to multifunction endpoints. 4635 * 4636 * Multifunction devices are only required to implement RR, CR, and DT 4637 * in their ACS capability if they support peer-to-peer transactions. 4638 * Devices matching this quirk have been verified by the vendor to not 4639 * perform peer-to-peer with other functions, allowing us to mask out 4640 * these bits as if they were unimplemented in the ACS capability. 4641 */ 4642 return pci_acs_ctrl_enabled(acs_flags, 4643 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4644 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4645 } 4646 4647 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4648 { 4649 /* 4650 * Intel RCiEP's are required to allow p2p only on translated 4651 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4652 * "Root-Complex Peer to Peer Considerations". 4653 */ 4654 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4655 return -ENOTTY; 4656 4657 return pci_acs_ctrl_enabled(acs_flags, 4658 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4659 } 4660 4661 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4662 { 4663 /* 4664 * iProc PAXB Root Ports don't advertise an ACS capability, but 4665 * they do not allow peer-to-peer transactions between Root Ports. 4666 * Allow each Root Port to be in a separate IOMMU group by masking 4667 * SV/RR/CR/UF bits. 4668 */ 4669 return pci_acs_ctrl_enabled(acs_flags, 4670 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4671 } 4672 4673 static const struct pci_dev_acs_enabled { 4674 u16 vendor; 4675 u16 device; 4676 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4677 } pci_dev_acs_enabled[] = { 4678 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4679 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4680 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4681 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4682 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4683 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4684 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4685 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4686 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4687 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4688 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4689 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4690 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4691 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4692 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4693 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4694 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4695 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4696 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4697 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4698 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4699 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4700 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4701 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4702 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4703 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4704 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4705 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4706 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4707 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4708 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4709 /* 82580 */ 4710 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4711 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4712 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4713 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4714 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4715 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4716 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4717 /* 82576 */ 4718 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4719 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4720 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4721 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4722 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4723 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4724 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4725 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4726 /* 82575 */ 4727 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4728 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4729 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4730 /* I350 */ 4731 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4732 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4733 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4734 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4735 /* 82571 (Quads omitted due to non-ACS switch) */ 4736 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4737 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4738 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4739 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4740 /* I219 */ 4741 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4742 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4743 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 4744 /* QCOM QDF2xxx root ports */ 4745 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 4746 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 4747 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 4748 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 4749 /* Intel PCH root ports */ 4750 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4751 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4752 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4753 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4754 /* Cavium ThunderX */ 4755 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4756 /* APM X-Gene */ 4757 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4758 /* Ampere Computing */ 4759 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 4760 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 4761 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 4762 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 4763 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 4764 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4765 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4766 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4767 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 4768 /* Amazon Annapurna Labs */ 4769 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 4770 /* Zhaoxin multi-function devices */ 4771 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 4772 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 4773 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 4774 /* Zhaoxin Root/Downstream Ports */ 4775 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 4776 { 0 } 4777 }; 4778 4779 /* 4780 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 4781 * @dev: PCI device 4782 * @acs_flags: Bitmask of desired ACS controls 4783 * 4784 * Returns: 4785 * -ENOTTY: No quirk applies to this device; we can't tell whether the 4786 * device provides the desired controls 4787 * 0: Device does not provide all the desired controls 4788 * >0: Device provides all the controls in @acs_flags 4789 */ 4790 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4791 { 4792 const struct pci_dev_acs_enabled *i; 4793 int ret; 4794 4795 /* 4796 * Allow devices that do not expose standard PCIe ACS capabilities 4797 * or control to indicate their support here. Multi-function express 4798 * devices which do not allow internal peer-to-peer between functions, 4799 * but do not implement PCIe ACS may wish to return true here. 4800 */ 4801 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4802 if ((i->vendor == dev->vendor || 4803 i->vendor == (u16)PCI_ANY_ID) && 4804 (i->device == dev->device || 4805 i->device == (u16)PCI_ANY_ID)) { 4806 ret = i->acs_enabled(dev, acs_flags); 4807 if (ret >= 0) 4808 return ret; 4809 } 4810 } 4811 4812 return -ENOTTY; 4813 } 4814 4815 /* Config space offset of Root Complex Base Address register */ 4816 #define INTEL_LPC_RCBA_REG 0xf0 4817 /* 31:14 RCBA address */ 4818 #define INTEL_LPC_RCBA_MASK 0xffffc000 4819 /* RCBA Enable */ 4820 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4821 4822 /* Backbone Scratch Pad Register */ 4823 #define INTEL_BSPR_REG 0x1104 4824 /* Backbone Peer Non-Posted Disable */ 4825 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4826 /* Backbone Peer Posted Disable */ 4827 #define INTEL_BSPR_REG_BPPD (1 << 9) 4828 4829 /* Upstream Peer Decode Configuration Register */ 4830 #define INTEL_UPDCR_REG 0x1014 4831 /* 5:0 Peer Decode Enable bits */ 4832 #define INTEL_UPDCR_REG_MASK 0x3f 4833 4834 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4835 { 4836 u32 rcba, bspr, updcr; 4837 void __iomem *rcba_mem; 4838 4839 /* 4840 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4841 * are D28:F* and therefore get probed before LPC, thus we can't 4842 * use pci_get_slot()/pci_read_config_dword() here. 4843 */ 4844 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4845 INTEL_LPC_RCBA_REG, &rcba); 4846 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4847 return -EINVAL; 4848 4849 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 4850 PAGE_ALIGN(INTEL_UPDCR_REG)); 4851 if (!rcba_mem) 4852 return -ENOMEM; 4853 4854 /* 4855 * The BSPR can disallow peer cycles, but it's set by soft strap and 4856 * therefore read-only. If both posted and non-posted peer cycles are 4857 * disallowed, we're ok. If either are allowed, then we need to use 4858 * the UPDCR to disable peer decodes for each port. This provides the 4859 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4860 */ 4861 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4862 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4863 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4864 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4865 if (updcr & INTEL_UPDCR_REG_MASK) { 4866 pci_info(dev, "Disabling UPDCR peer decodes\n"); 4867 updcr &= ~INTEL_UPDCR_REG_MASK; 4868 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4869 } 4870 } 4871 4872 iounmap(rcba_mem); 4873 return 0; 4874 } 4875 4876 /* Miscellaneous Port Configuration register */ 4877 #define INTEL_MPC_REG 0xd8 4878 /* MPC: Invalid Receive Bus Number Check Enable */ 4879 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4880 4881 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4882 { 4883 u32 mpc; 4884 4885 /* 4886 * When enabled, the IRBNCE bit of the MPC register enables the 4887 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4888 * ensures that requester IDs fall within the bus number range 4889 * of the bridge. Enable if not already. 4890 */ 4891 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4892 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4893 pci_info(dev, "Enabling MPC IRBNCE\n"); 4894 mpc |= INTEL_MPC_REG_IRBNCE; 4895 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4896 } 4897 } 4898 4899 /* 4900 * Currently this quirk does the equivalent of 4901 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4902 * 4903 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 4904 * if dev->external_facing || dev->untrusted 4905 */ 4906 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4907 { 4908 if (!pci_quirk_intel_pch_acs_match(dev)) 4909 return -ENOTTY; 4910 4911 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4912 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 4913 return 0; 4914 } 4915 4916 pci_quirk_enable_intel_rp_mpc_acs(dev); 4917 4918 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4919 4920 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 4921 4922 return 0; 4923 } 4924 4925 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4926 { 4927 int pos; 4928 u32 cap, ctrl; 4929 4930 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4931 return -ENOTTY; 4932 4933 pos = dev->acs_cap; 4934 if (!pos) 4935 return -ENOTTY; 4936 4937 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4938 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4939 4940 ctrl |= (cap & PCI_ACS_SV); 4941 ctrl |= (cap & PCI_ACS_RR); 4942 ctrl |= (cap & PCI_ACS_CR); 4943 ctrl |= (cap & PCI_ACS_UF); 4944 4945 if (dev->external_facing || dev->untrusted) 4946 ctrl |= (cap & PCI_ACS_TB); 4947 4948 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4949 4950 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4951 4952 return 0; 4953 } 4954 4955 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 4956 { 4957 int pos; 4958 u32 cap, ctrl; 4959 4960 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4961 return -ENOTTY; 4962 4963 pos = dev->acs_cap; 4964 if (!pos) 4965 return -ENOTTY; 4966 4967 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4968 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4969 4970 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 4971 4972 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4973 4974 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 4975 4976 return 0; 4977 } 4978 4979 static const struct pci_dev_acs_ops { 4980 u16 vendor; 4981 u16 device; 4982 int (*enable_acs)(struct pci_dev *dev); 4983 int (*disable_acs_redir)(struct pci_dev *dev); 4984 } pci_dev_acs_ops[] = { 4985 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 4986 .enable_acs = pci_quirk_enable_intel_pch_acs, 4987 }, 4988 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 4989 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 4990 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 4991 }, 4992 }; 4993 4994 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4995 { 4996 const struct pci_dev_acs_ops *p; 4997 int i, ret; 4998 4999 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5000 p = &pci_dev_acs_ops[i]; 5001 if ((p->vendor == dev->vendor || 5002 p->vendor == (u16)PCI_ANY_ID) && 5003 (p->device == dev->device || 5004 p->device == (u16)PCI_ANY_ID) && 5005 p->enable_acs) { 5006 ret = p->enable_acs(dev); 5007 if (ret >= 0) 5008 return ret; 5009 } 5010 } 5011 5012 return -ENOTTY; 5013 } 5014 5015 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5016 { 5017 const struct pci_dev_acs_ops *p; 5018 int i, ret; 5019 5020 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5021 p = &pci_dev_acs_ops[i]; 5022 if ((p->vendor == dev->vendor || 5023 p->vendor == (u16)PCI_ANY_ID) && 5024 (p->device == dev->device || 5025 p->device == (u16)PCI_ANY_ID) && 5026 p->disable_acs_redir) { 5027 ret = p->disable_acs_redir(dev); 5028 if (ret >= 0) 5029 return ret; 5030 } 5031 } 5032 5033 return -ENOTTY; 5034 } 5035 5036 /* 5037 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5038 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5039 * Next Capability pointer in the MSI Capability Structure should point to 5040 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5041 * the list. 5042 */ 5043 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5044 { 5045 int pos, i = 0; 5046 u8 next_cap; 5047 u16 reg16, *cap; 5048 struct pci_cap_saved_state *state; 5049 5050 /* Bail if the hardware bug is fixed */ 5051 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5052 return; 5053 5054 /* Bail if MSI Capability Structure is not found for some reason */ 5055 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5056 if (!pos) 5057 return; 5058 5059 /* 5060 * Bail if Next Capability pointer in the MSI Capability Structure 5061 * is not the expected incorrect 0x00. 5062 */ 5063 pci_read_config_byte(pdev, pos + 1, &next_cap); 5064 if (next_cap) 5065 return; 5066 5067 /* 5068 * PCIe Capability Structure is expected to be at 0x50 and should 5069 * terminate the list (Next Capability pointer is 0x00). Verify 5070 * Capability Id and Next Capability pointer is as expected. 5071 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5072 * to correctly set kernel data structures which have already been 5073 * set incorrectly due to the hardware bug. 5074 */ 5075 pos = 0x50; 5076 pci_read_config_word(pdev, pos, ®16); 5077 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5078 u32 status; 5079 #ifndef PCI_EXP_SAVE_REGS 5080 #define PCI_EXP_SAVE_REGS 7 5081 #endif 5082 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5083 5084 pdev->pcie_cap = pos; 5085 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5086 pdev->pcie_flags_reg = reg16; 5087 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5088 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5089 5090 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5091 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 5092 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 5093 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5094 5095 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5096 return; 5097 5098 /* Save PCIe cap */ 5099 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5100 if (!state) 5101 return; 5102 5103 state->cap.cap_nr = PCI_CAP_ID_EXP; 5104 state->cap.cap_extended = 0; 5105 state->cap.size = size; 5106 cap = (u16 *)&state->cap.data[0]; 5107 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5108 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5109 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5110 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5111 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5112 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5113 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5114 hlist_add_head(&state->next, &pdev->saved_cap_space); 5115 } 5116 } 5117 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5118 5119 /* 5120 * FLR may cause the following to devices to hang: 5121 * 5122 * AMD Starship/Matisse HD Audio Controller 0x1487 5123 * AMD Starship USB 3.0 Host Controller 0x148c 5124 * AMD Matisse USB 3.0 Host Controller 0x149c 5125 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5126 * Intel 82579V Gigabit Ethernet Controller 0x1503 5127 * 5128 */ 5129 static void quirk_no_flr(struct pci_dev *dev) 5130 { 5131 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5132 } 5133 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5135 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5136 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5137 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5138 5139 static void quirk_no_ext_tags(struct pci_dev *pdev) 5140 { 5141 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5142 5143 if (!bridge) 5144 return; 5145 5146 bridge->no_ext_tags = 1; 5147 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5148 5149 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5150 } 5151 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5153 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5154 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5155 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5156 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5157 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5158 5159 #ifdef CONFIG_PCI_ATS 5160 /* 5161 * Some devices require additional driver setup to enable ATS. Don't use 5162 * ATS for those devices as ATS will be enabled before the driver has had a 5163 * chance to load and configure the device. 5164 */ 5165 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5166 { 5167 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || 5168 (pdev->device == 0x7340 && pdev->revision != 0xc5)) 5169 return; 5170 5171 if (pdev->device == 0x15d8) { 5172 if (pdev->revision == 0xcf && 5173 pdev->subsystem_vendor == 0xea50 && 5174 (pdev->subsystem_device == 0xce19 || 5175 pdev->subsystem_device == 0xcc10 || 5176 pdev->subsystem_device == 0xcc08)) 5177 goto no_ats; 5178 else 5179 return; 5180 } 5181 5182 no_ats: 5183 pci_info(pdev, "disabling ATS\n"); 5184 pdev->ats_cap = 0; 5185 } 5186 5187 /* AMD Stoney platform GPU */ 5188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5189 /* AMD Iceland dGPU */ 5190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5191 /* AMD Navi10 dGPU */ 5192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5193 /* AMD Navi14 dGPU */ 5194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5195 /* AMD Raven platform iGPU */ 5196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5197 #endif /* CONFIG_PCI_ATS */ 5198 5199 /* Freescale PCIe doesn't support MSI in RC mode */ 5200 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5201 { 5202 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5203 pdev->no_msi = 1; 5204 } 5205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5206 5207 /* 5208 * Although not allowed by the spec, some multi-function devices have 5209 * dependencies of one function (consumer) on another (supplier). For the 5210 * consumer to work in D0, the supplier must also be in D0. Create a 5211 * device link from the consumer to the supplier to enforce this 5212 * dependency. Runtime PM is allowed by default on the consumer to prevent 5213 * it from permanently keeping the supplier awake. 5214 */ 5215 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5216 unsigned int supplier, unsigned int class, 5217 unsigned int class_shift) 5218 { 5219 struct pci_dev *supplier_pdev; 5220 5221 if (PCI_FUNC(pdev->devfn) != consumer) 5222 return; 5223 5224 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5225 pdev->bus->number, 5226 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5227 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5228 pci_dev_put(supplier_pdev); 5229 return; 5230 } 5231 5232 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5233 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5234 pci_info(pdev, "D0 power state depends on %s\n", 5235 pci_name(supplier_pdev)); 5236 else 5237 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5238 pci_name(supplier_pdev)); 5239 5240 pm_runtime_allow(&pdev->dev); 5241 pci_dev_put(supplier_pdev); 5242 } 5243 5244 /* 5245 * Create device link for GPUs with integrated HDA controller for streaming 5246 * audio to attached displays. 5247 */ 5248 static void quirk_gpu_hda(struct pci_dev *hda) 5249 { 5250 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5251 } 5252 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5253 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5254 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5255 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5256 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5257 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5258 5259 /* 5260 * Create device link for NVIDIA GPU with integrated USB xHCI Host 5261 * controller to VGA. 5262 */ 5263 static void quirk_gpu_usb(struct pci_dev *usb) 5264 { 5265 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5266 } 5267 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5268 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5269 5270 /* 5271 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller 5272 * to VGA. Currently there is no class code defined for UCSI device over PCI 5273 * so using UNKNOWN class for now and it will be updated when UCSI 5274 * over PCI gets a class code. 5275 */ 5276 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5277 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5278 { 5279 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5280 } 5281 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5282 PCI_CLASS_SERIAL_UNKNOWN, 8, 5283 quirk_gpu_usb_typec_ucsi); 5284 5285 /* 5286 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5287 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5288 */ 5289 static void quirk_nvidia_hda(struct pci_dev *gpu) 5290 { 5291 u8 hdr_type; 5292 u32 val; 5293 5294 /* There was no integrated HDA controller before MCP89 */ 5295 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5296 return; 5297 5298 /* Bit 25 at offset 0x488 enables the HDA controller */ 5299 pci_read_config_dword(gpu, 0x488, &val); 5300 if (val & BIT(25)) 5301 return; 5302 5303 pci_info(gpu, "Enabling HDA controller\n"); 5304 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5305 5306 /* The GPU becomes a multi-function device when the HDA is enabled */ 5307 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5308 gpu->multifunction = !!(hdr_type & 0x80); 5309 } 5310 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5311 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5312 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5313 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5314 5315 /* 5316 * Some IDT switches incorrectly flag an ACS Source Validation error on 5317 * completions for config read requests even though PCIe r4.0, sec 5318 * 6.12.1.1, says that completions are never affected by ACS Source 5319 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5320 * 5321 * Item #36 - Downstream port applies ACS Source Validation to Completions 5322 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5323 * completions are never affected by ACS Source Validation. However, 5324 * completions received by a downstream port of the PCIe switch from a 5325 * device that has not yet captured a PCIe bus number are incorrectly 5326 * dropped by ACS Source Validation by the switch downstream port. 5327 * 5328 * The workaround suggested by IDT is to issue a config write to the 5329 * downstream device before issuing the first config read. This allows the 5330 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5331 * sec 2.2.9), thus avoiding the ACS error on the completion. 5332 * 5333 * However, we don't know when the device is ready to accept the config 5334 * write, so we do config reads until we receive a non-Config Request Retry 5335 * Status, then do the config write. 5336 * 5337 * To avoid hitting the erratum when doing the config reads, we disable ACS 5338 * SV around this process. 5339 */ 5340 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5341 { 5342 int pos; 5343 u16 ctrl = 0; 5344 bool found; 5345 struct pci_dev *bridge = bus->self; 5346 5347 pos = bridge->acs_cap; 5348 5349 /* Disable ACS SV before initial config reads */ 5350 if (pos) { 5351 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5352 if (ctrl & PCI_ACS_SV) 5353 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5354 ctrl & ~PCI_ACS_SV); 5355 } 5356 5357 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5358 5359 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5360 if (found) 5361 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5362 5363 /* Re-enable ACS_SV if it was previously enabled */ 5364 if (ctrl & PCI_ACS_SV) 5365 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5366 5367 return found; 5368 } 5369 5370 /* 5371 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5372 * NT endpoints via the internal switch fabric. These IDs replace the 5373 * originating requestor ID TLPs which access host memory on peer NTB 5374 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5375 * to permit access when the IOMMU is turned on. 5376 */ 5377 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5378 { 5379 void __iomem *mmio; 5380 struct ntb_info_regs __iomem *mmio_ntb; 5381 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5382 u64 partition_map; 5383 u8 partition; 5384 int pp; 5385 5386 if (pci_enable_device(pdev)) { 5387 pci_err(pdev, "Cannot enable Switchtec device\n"); 5388 return; 5389 } 5390 5391 mmio = pci_iomap(pdev, 0, 0); 5392 if (mmio == NULL) { 5393 pci_disable_device(pdev); 5394 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5395 return; 5396 } 5397 5398 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5399 5400 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5401 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5402 5403 partition = ioread8(&mmio_ntb->partition_id); 5404 5405 partition_map = ioread32(&mmio_ntb->ep_map); 5406 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5407 partition_map &= ~(1ULL << partition); 5408 5409 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5410 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5411 u32 table_sz = 0; 5412 int te; 5413 5414 if (!(partition_map & (1ULL << pp))) 5415 continue; 5416 5417 pci_dbg(pdev, "Processing partition %d\n", pp); 5418 5419 mmio_peer_ctrl = &mmio_ctrl[pp]; 5420 5421 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5422 if (!table_sz) { 5423 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5424 continue; 5425 } 5426 5427 if (table_sz > 512) { 5428 pci_warn(pdev, 5429 "Invalid Switchtec partition %d table_sz %d\n", 5430 pp, table_sz); 5431 continue; 5432 } 5433 5434 for (te = 0; te < table_sz; te++) { 5435 u32 rid_entry; 5436 u8 devfn; 5437 5438 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5439 devfn = (rid_entry >> 1) & 0xFF; 5440 pci_dbg(pdev, 5441 "Aliasing Partition %d Proxy ID %02x.%d\n", 5442 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5443 pci_add_dma_alias(pdev, devfn, 1); 5444 } 5445 } 5446 5447 pci_iounmap(pdev, mmio); 5448 pci_disable_device(pdev); 5449 } 5450 #define SWITCHTEC_QUIRK(vid) \ 5451 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5452 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5453 5454 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5455 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5456 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5457 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5458 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5459 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5460 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5461 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5462 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5463 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5464 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5465 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5466 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5467 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5468 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5469 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5470 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5471 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5472 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5473 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5474 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5475 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5476 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5477 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5478 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5479 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5480 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5481 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5482 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5483 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5484 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5485 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5486 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5487 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5488 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5489 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5490 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5491 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5492 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5493 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5494 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5495 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5496 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5497 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5498 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5499 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5500 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5501 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5502 5503 /* 5504 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5505 * These IDs are used to forward responses to the originator on the other 5506 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5507 * the IOMMU is turned on. 5508 */ 5509 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5510 { 5511 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5512 /* PLX NTB may use all 256 devfns */ 5513 pci_add_dma_alias(pdev, 0, 256); 5514 } 5515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 5516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 5517 5518 /* 5519 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 5520 * not always reset the secondary Nvidia GPU between reboots if the system 5521 * is configured to use Hybrid Graphics mode. This results in the GPU 5522 * being left in whatever state it was in during the *previous* boot, which 5523 * causes spurious interrupts from the GPU, which in turn causes us to 5524 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 5525 * this also completely breaks nouveau. 5526 * 5527 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 5528 * clean state and fixes all these issues. 5529 * 5530 * When the machine is configured in Dedicated display mode, the issue 5531 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 5532 * mode, so we can detect that and avoid resetting it. 5533 */ 5534 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 5535 { 5536 void __iomem *map; 5537 int ret; 5538 5539 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 5540 pdev->subsystem_device != 0x222e || 5541 !pdev->reset_fn) 5542 return; 5543 5544 if (pci_enable_device_mem(pdev)) 5545 return; 5546 5547 /* 5548 * Based on nvkm_device_ctor() in 5549 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 5550 */ 5551 map = pci_iomap(pdev, 0, 0x23000); 5552 if (!map) { 5553 pci_err(pdev, "Can't map MMIO space\n"); 5554 goto out_disable; 5555 } 5556 5557 /* 5558 * Make sure the GPU looks like it's been POSTed before resetting 5559 * it. 5560 */ 5561 if (ioread32(map + 0x2240c) & 0x2) { 5562 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 5563 ret = pci_reset_bus(pdev); 5564 if (ret < 0) 5565 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 5566 } 5567 5568 iounmap(map); 5569 out_disable: 5570 pci_disable_device(pdev); 5571 } 5572 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 5573 PCI_CLASS_DISPLAY_VGA, 8, 5574 quirk_reset_lenovo_thinkpad_p50_nvgpu); 5575 5576 /* 5577 * Device [1b21:2142] 5578 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 5579 */ 5580 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 5581 { 5582 pci_info(dev, "PME# does not work under D0, disabling it\n"); 5583 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 5584 } 5585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 5586 5587 /* 5588 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 5589 * 5590 * These devices advertise PME# support in all power states but don't 5591 * reliably assert it. 5592 * 5593 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 5594 * says "The MSI Function is not implemented on this device" in chapters 5595 * 7.3.27, 7.3.29-7.3.31. 5596 */ 5597 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 5598 { 5599 #ifdef CONFIG_PCI_MSI 5600 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 5601 dev->no_msi = 1; 5602 #endif 5603 pci_info(dev, "PME# is unreliable, disabling it\n"); 5604 dev->pme_support = 0; 5605 } 5606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 5607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 5608 5609 static void apex_pci_fixup_class(struct pci_dev *pdev) 5610 { 5611 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 5612 } 5613 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 5614 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 5615