1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include <linux/kallsyms.h> 25 #include <linux/dmi.h> 26 #include <linux/pci-aspm.h> 27 #include <linux/ioport.h> 28 #include "pci.h" 29 30 int isa_dma_bridge_buggy; 31 EXPORT_SYMBOL(isa_dma_bridge_buggy); 32 int pci_pci_problems; 33 EXPORT_SYMBOL(pci_pci_problems); 34 int pcie_mch_quirk; 35 EXPORT_SYMBOL(pcie_mch_quirk); 36 37 #ifdef CONFIG_PCI_QUIRKS 38 /* 39 * This quirk function disables the device and releases resources 40 * which is specified by kernel's boot parameter 'pci=resource_alignment='. 41 * It also rounds up size to specified alignment. 42 * Later on, the kernel will assign page-aligned memory resource back 43 * to that device. 44 */ 45 static void __devinit quirk_resource_alignment(struct pci_dev *dev) 46 { 47 int i; 48 struct resource *r; 49 resource_size_t align, size; 50 51 if (!pci_is_reassigndev(dev)) 52 return; 53 54 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 55 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 56 dev_warn(&dev->dev, 57 "Can't reassign resources to host bridge.\n"); 58 return; 59 } 60 61 dev_info(&dev->dev, "Disabling device and release resources.\n"); 62 pci_disable_device(dev); 63 64 align = pci_specified_resource_alignment(dev); 65 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { 66 r = &dev->resource[i]; 67 if (!(r->flags & IORESOURCE_MEM)) 68 continue; 69 size = resource_size(r); 70 if (size < align) { 71 size = align; 72 dev_info(&dev->dev, 73 "Rounding up size of resource #%d to %#llx.\n", 74 i, (unsigned long long)size); 75 } 76 r->end = size - 1; 77 r->start = 0; 78 } 79 /* Need to disable bridge's resource window, 80 * to enable the kernel to reassign new resource 81 * window later on. 82 */ 83 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 84 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 85 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 86 r = &dev->resource[i]; 87 if (!(r->flags & IORESOURCE_MEM)) 88 continue; 89 r->end = resource_size(r) - 1; 90 r->start = 0; 91 } 92 pci_disable_bridge_window(dev); 93 } 94 } 95 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); 96 97 /* The Mellanox Tavor device gives false positive parity errors 98 * Mark this device with a broken_parity_status, to allow 99 * PCI scanning code to "skip" this now blacklisted device. 100 */ 101 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 102 { 103 dev->broken_parity_status = 1; /* This device gives false positives */ 104 } 105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 107 108 /* Deal with broken BIOS'es that neglect to enable passive release, 109 which can cause problems in combination with the 82441FX/PPro MTRRs */ 110 static void quirk_passive_release(struct pci_dev *dev) 111 { 112 struct pci_dev *d = NULL; 113 unsigned char dlc; 114 115 /* We have to make sure a particular bit is set in the PIIX3 116 ISA bridge, so we have to go out and find it. */ 117 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 118 pci_read_config_byte(d, 0x82, &dlc); 119 if (!(dlc & 1<<1)) { 120 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 121 dlc |= 1<<1; 122 pci_write_config_byte(d, 0x82, dlc); 123 } 124 } 125 } 126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 127 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 128 129 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 130 but VIA don't answer queries. If you happen to have good contacts at VIA 131 ask them for me please -- Alan 132 133 This appears to be BIOS not version dependent. So presumably there is a 134 chipset level fix */ 135 136 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 137 { 138 if (!isa_dma_bridge_buggy) { 139 isa_dma_bridge_buggy=1; 140 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 141 } 142 } 143 /* 144 * Its not totally clear which chipsets are the problematic ones 145 * We know 82C586 and 82C596 variants are affected. 146 */ 147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 154 155 /* 156 * Chipsets where PCI->PCI transfers vanish or hang 157 */ 158 static void __devinit quirk_nopcipci(struct pci_dev *dev) 159 { 160 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 161 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 162 pci_pci_problems |= PCIPCI_FAIL; 163 } 164 } 165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 167 168 static void __devinit quirk_nopciamd(struct pci_dev *dev) 169 { 170 u8 rev; 171 pci_read_config_byte(dev, 0x08, &rev); 172 if (rev == 0x13) { 173 /* Erratum 24 */ 174 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 175 pci_pci_problems |= PCIAGP_FAIL; 176 } 177 } 178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 179 180 /* 181 * Triton requires workarounds to be used by the drivers 182 */ 183 static void __devinit quirk_triton(struct pci_dev *dev) 184 { 185 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 186 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 187 pci_pci_problems |= PCIPCI_TRITON; 188 } 189 } 190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 194 195 /* 196 * VIA Apollo KT133 needs PCI latency patch 197 * Made according to a windows driver based patch by George E. Breese 198 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 199 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 200 * the info on which Mr Breese based his work. 201 * 202 * Updated based on further information from the site and also on 203 * information provided by VIA 204 */ 205 static void quirk_vialatency(struct pci_dev *dev) 206 { 207 struct pci_dev *p; 208 u8 busarb; 209 /* Ok we have a potential problem chipset here. Now see if we have 210 a buggy southbridge */ 211 212 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 213 if (p!=NULL) { 214 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 215 /* Check for buggy part revisions */ 216 if (p->revision < 0x40 || p->revision > 0x42) 217 goto exit; 218 } else { 219 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 220 if (p==NULL) /* No problem parts */ 221 goto exit; 222 /* Check for buggy part revisions */ 223 if (p->revision < 0x10 || p->revision > 0x12) 224 goto exit; 225 } 226 227 /* 228 * Ok we have the problem. Now set the PCI master grant to 229 * occur every master grant. The apparent bug is that under high 230 * PCI load (quite common in Linux of course) you can get data 231 * loss when the CPU is held off the bus for 3 bus master requests 232 * This happens to include the IDE controllers.... 233 * 234 * VIA only apply this fix when an SB Live! is present but under 235 * both Linux and Windows this isnt enough, and we have seen 236 * corruption without SB Live! but with things like 3 UDMA IDE 237 * controllers. So we ignore that bit of the VIA recommendation.. 238 */ 239 240 pci_read_config_byte(dev, 0x76, &busarb); 241 /* Set bit 4 and bi 5 of byte 76 to 0x01 242 "Master priority rotation on every PCI master grant */ 243 busarb &= ~(1<<5); 244 busarb |= (1<<4); 245 pci_write_config_byte(dev, 0x76, busarb); 246 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 247 exit: 248 pci_dev_put(p); 249 } 250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 253 /* Must restore this on a resume from RAM */ 254 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 255 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 256 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 257 258 /* 259 * VIA Apollo VP3 needs ETBF on BT848/878 260 */ 261 static void __devinit quirk_viaetbf(struct pci_dev *dev) 262 { 263 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 264 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 265 pci_pci_problems |= PCIPCI_VIAETBF; 266 } 267 } 268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 269 270 static void __devinit quirk_vsfx(struct pci_dev *dev) 271 { 272 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 274 pci_pci_problems |= PCIPCI_VSFX; 275 } 276 } 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 278 279 /* 280 * Ali Magik requires workarounds to be used by the drivers 281 * that DMA to AGP space. Latency must be set to 0xA and triton 282 * workaround applied too 283 * [Info kindly provided by ALi] 284 */ 285 static void __init quirk_alimagik(struct pci_dev *dev) 286 { 287 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 288 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 289 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 290 } 291 } 292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 294 295 /* 296 * Natoma has some interesting boundary conditions with Zoran stuff 297 * at least 298 */ 299 static void __devinit quirk_natoma(struct pci_dev *dev) 300 { 301 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 302 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 303 pci_pci_problems |= PCIPCI_NATOMA; 304 } 305 } 306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 312 313 /* 314 * This chip can cause PCI parity errors if config register 0xA0 is read 315 * while DMAs are occurring. 316 */ 317 static void __devinit quirk_citrine(struct pci_dev *dev) 318 { 319 dev->cfg_size = 0xA0; 320 } 321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 322 323 /* 324 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 325 * If it's needed, re-allocate the region. 326 */ 327 static void __devinit quirk_s3_64M(struct pci_dev *dev) 328 { 329 struct resource *r = &dev->resource[0]; 330 331 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 332 r->start = 0; 333 r->end = 0x3ffffff; 334 } 335 } 336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 338 339 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 340 unsigned size, int nr, const char *name) 341 { 342 region &= ~(size-1); 343 if (region) { 344 struct pci_bus_region bus_region; 345 struct resource *res = dev->resource + nr; 346 347 res->name = pci_name(dev); 348 res->start = region; 349 res->end = region + size - 1; 350 res->flags = IORESOURCE_IO; 351 352 /* Convert from PCI bus to resource space. */ 353 bus_region.start = res->start; 354 bus_region.end = res->end; 355 pcibios_bus_to_resource(dev, res, &bus_region); 356 357 pci_claim_resource(dev, nr); 358 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 359 } 360 } 361 362 /* 363 * ATI Northbridge setups MCE the processor if you even 364 * read somewhere between 0x3b0->0x3bb or read 0x3d3 365 */ 366 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 367 { 368 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 369 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 370 request_region(0x3b0, 0x0C, "RadeonIGP"); 371 request_region(0x3d3, 0x01, "RadeonIGP"); 372 } 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 374 375 /* 376 * Let's make the southbridge information explicit instead 377 * of having to worry about people probing the ACPI areas, 378 * for example.. (Yes, it happens, and if you read the wrong 379 * ACPI register it will put the machine to sleep with no 380 * way of waking it up again. Bummer). 381 * 382 * ALI M7101: Two IO regions pointed to by words at 383 * 0xE0 (64 bytes of ACPI registers) 384 * 0xE2 (32 bytes of SMB registers) 385 */ 386 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 387 { 388 u16 region; 389 390 pci_read_config_word(dev, 0xE0, ®ion); 391 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 392 pci_read_config_word(dev, 0xE2, ®ion); 393 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 394 } 395 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 396 397 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 398 { 399 u32 devres; 400 u32 mask, size, base; 401 402 pci_read_config_dword(dev, port, &devres); 403 if ((devres & enable) != enable) 404 return; 405 mask = (devres >> 16) & 15; 406 base = devres & 0xffff; 407 size = 16; 408 for (;;) { 409 unsigned bit = size >> 1; 410 if ((bit & mask) == bit) 411 break; 412 size = bit; 413 } 414 /* 415 * For now we only print it out. Eventually we'll want to 416 * reserve it (at least if it's in the 0x1000+ range), but 417 * let's get enough confirmation reports first. 418 */ 419 base &= -size; 420 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 421 } 422 423 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 424 { 425 u32 devres; 426 u32 mask, size, base; 427 428 pci_read_config_dword(dev, port, &devres); 429 if ((devres & enable) != enable) 430 return; 431 base = devres & 0xffff0000; 432 mask = (devres & 0x3f) << 16; 433 size = 128 << 16; 434 for (;;) { 435 unsigned bit = size >> 1; 436 if ((bit & mask) == bit) 437 break; 438 size = bit; 439 } 440 /* 441 * For now we only print it out. Eventually we'll want to 442 * reserve it, but let's get enough confirmation reports first. 443 */ 444 base &= -size; 445 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 446 } 447 448 /* 449 * PIIX4 ACPI: Two IO regions pointed to by longwords at 450 * 0x40 (64 bytes of ACPI registers) 451 * 0x90 (16 bytes of SMB registers) 452 * and a few strange programmable PIIX4 device resources. 453 */ 454 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 455 { 456 u32 region, res_a; 457 458 pci_read_config_dword(dev, 0x40, ®ion); 459 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 460 pci_read_config_dword(dev, 0x90, ®ion); 461 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 462 463 /* Device resource A has enables for some of the other ones */ 464 pci_read_config_dword(dev, 0x5c, &res_a); 465 466 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 467 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 468 469 /* Device resource D is just bitfields for static resources */ 470 471 /* Device 12 enabled? */ 472 if (res_a & (1 << 29)) { 473 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 474 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 475 } 476 /* Device 13 enabled? */ 477 if (res_a & (1 << 30)) { 478 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 479 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 480 } 481 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 482 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 483 } 484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 486 487 /* 488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 490 * 0x58 (64 bytes of GPIO I/O space) 491 */ 492 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 493 { 494 u32 region; 495 496 pci_read_config_dword(dev, 0x40, ®ion); 497 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 498 499 pci_read_config_dword(dev, 0x58, ®ion); 500 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 501 } 502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 512 513 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) 514 { 515 u32 region; 516 517 pci_read_config_dword(dev, 0x40, ®ion); 518 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 519 520 pci_read_config_dword(dev, 0x48, ®ion); 521 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 522 } 523 524 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 525 { 526 u32 val; 527 u32 size, base; 528 529 pci_read_config_dword(dev, reg, &val); 530 531 /* Enabled? */ 532 if (!(val & 1)) 533 return; 534 base = val & 0xfffc; 535 if (dynsize) { 536 /* 537 * This is not correct. It is 16, 32 or 64 bytes depending on 538 * register D31:F0:ADh bits 5:4. 539 * 540 * But this gets us at least _part_ of it. 541 */ 542 size = 16; 543 } else { 544 size = 128; 545 } 546 base &= ~(size-1); 547 548 /* Just print it out for now. We should reserve it after more debugging */ 549 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 550 } 551 552 static void __devinit quirk_ich6_lpc(struct pci_dev *dev) 553 { 554 /* Shared ACPI/GPIO decode with all ICH6+ */ 555 ich6_lpc_acpi_gpio(dev); 556 557 /* ICH6-specific generic IO decode */ 558 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 559 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 560 } 561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 563 564 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 565 { 566 u32 val; 567 u32 mask, base; 568 569 pci_read_config_dword(dev, reg, &val); 570 571 /* Enabled? */ 572 if (!(val & 1)) 573 return; 574 575 /* 576 * IO base in bits 15:2, mask in bits 23:18, both 577 * are dword-based 578 */ 579 base = val & 0xfffc; 580 mask = (val >> 16) & 0xfc; 581 mask |= 3; 582 583 /* Just print it out for now. We should reserve it after more debugging */ 584 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 585 } 586 587 /* ICH7-10 has the same common LPC generic IO decode registers */ 588 static void __devinit quirk_ich7_lpc(struct pci_dev *dev) 589 { 590 /* We share the common ACPI/DPIO decode with ICH6 */ 591 ich6_lpc_acpi_gpio(dev); 592 593 /* And have 4 ICH7+ generic decodes */ 594 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 595 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 596 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 597 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 598 } 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 612 613 /* 614 * VIA ACPI: One IO region pointed to by longword at 615 * 0x48 or 0x20 (256 bytes of ACPI registers) 616 */ 617 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 618 { 619 u32 region; 620 621 if (dev->revision & 0x10) { 622 pci_read_config_dword(dev, 0x48, ®ion); 623 region &= PCI_BASE_ADDRESS_IO_MASK; 624 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 625 } 626 } 627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 628 629 /* 630 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 631 * 0x48 (256 bytes of ACPI registers) 632 * 0x70 (128 bytes of hardware monitoring register) 633 * 0x90 (16 bytes of SMB registers) 634 */ 635 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 636 { 637 u16 hm; 638 u32 smb; 639 640 quirk_vt82c586_acpi(dev); 641 642 pci_read_config_word(dev, 0x70, &hm); 643 hm &= PCI_BASE_ADDRESS_IO_MASK; 644 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 645 646 pci_read_config_dword(dev, 0x90, &smb); 647 smb &= PCI_BASE_ADDRESS_IO_MASK; 648 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 649 } 650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 651 652 /* 653 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 654 * 0x88 (128 bytes of power management registers) 655 * 0xd0 (16 bytes of SMB registers) 656 */ 657 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 658 { 659 u16 pm, smb; 660 661 pci_read_config_word(dev, 0x88, &pm); 662 pm &= PCI_BASE_ADDRESS_IO_MASK; 663 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 664 665 pci_read_config_word(dev, 0xd0, &smb); 666 smb &= PCI_BASE_ADDRESS_IO_MASK; 667 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 668 } 669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 670 671 672 #ifdef CONFIG_X86_IO_APIC 673 674 #include <asm/io_apic.h> 675 676 /* 677 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 678 * devices to the external APIC. 679 * 680 * TODO: When we have device-specific interrupt routers, 681 * this code will go away from quirks. 682 */ 683 static void quirk_via_ioapic(struct pci_dev *dev) 684 { 685 u8 tmp; 686 687 if (nr_ioapics < 1) 688 tmp = 0; /* nothing routed to external APIC */ 689 else 690 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 691 692 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 693 tmp == 0 ? "Disa" : "Ena"); 694 695 /* Offset 0x58: External APIC IRQ output control */ 696 pci_write_config_byte (dev, 0x58, tmp); 697 } 698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 699 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 700 701 /* 702 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 703 * This leads to doubled level interrupt rates. 704 * Set this bit to get rid of cycle wastage. 705 * Otherwise uncritical. 706 */ 707 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 708 { 709 u8 misc_control2; 710 #define BYPASS_APIC_DEASSERT 8 711 712 pci_read_config_byte(dev, 0x5B, &misc_control2); 713 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 714 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 715 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 716 } 717 } 718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 719 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 720 721 /* 722 * The AMD io apic can hang the box when an apic irq is masked. 723 * We check all revs >= B0 (yet not in the pre production!) as the bug 724 * is currently marked NoFix 725 * 726 * We have multiple reports of hangs with this chipset that went away with 727 * noapic specified. For the moment we assume it's the erratum. We may be wrong 728 * of course. However the advice is demonstrably good even if so.. 729 */ 730 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 731 { 732 if (dev->revision >= 0x02) { 733 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 734 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 735 } 736 } 737 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 738 739 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 740 { 741 if (dev->devfn == 0 && dev->bus->number == 0) 742 sis_apic_bug = 1; 743 } 744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 745 #endif /* CONFIG_X86_IO_APIC */ 746 747 /* 748 * Some settings of MMRBC can lead to data corruption so block changes. 749 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 750 */ 751 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 752 { 753 if (dev->subordinate && dev->revision <= 0x12) { 754 dev_info(&dev->dev, "AMD8131 rev %x detected; " 755 "disabling PCI-X MMRBC\n", dev->revision); 756 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 757 } 758 } 759 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 760 761 /* 762 * FIXME: it is questionable that quirk_via_acpi 763 * is needed. It shows up as an ISA bridge, and does not 764 * support the PCI_INTERRUPT_LINE register at all. Therefore 765 * it seems like setting the pci_dev's 'irq' to the 766 * value of the ACPI SCI interrupt is only done for convenience. 767 * -jgarzik 768 */ 769 static void __devinit quirk_via_acpi(struct pci_dev *d) 770 { 771 /* 772 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 773 */ 774 u8 irq; 775 pci_read_config_byte(d, 0x42, &irq); 776 irq &= 0xf; 777 if (irq && (irq != 2)) 778 d->irq = irq; 779 } 780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 782 783 784 /* 785 * VIA bridges which have VLink 786 */ 787 788 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 789 790 static void quirk_via_bridge(struct pci_dev *dev) 791 { 792 /* See what bridge we have and find the device ranges */ 793 switch (dev->device) { 794 case PCI_DEVICE_ID_VIA_82C686: 795 /* The VT82C686 is special, it attaches to PCI and can have 796 any device number. All its subdevices are functions of 797 that single device. */ 798 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 799 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 800 break; 801 case PCI_DEVICE_ID_VIA_8237: 802 case PCI_DEVICE_ID_VIA_8237A: 803 via_vlink_dev_lo = 15; 804 break; 805 case PCI_DEVICE_ID_VIA_8235: 806 via_vlink_dev_lo = 16; 807 break; 808 case PCI_DEVICE_ID_VIA_8231: 809 case PCI_DEVICE_ID_VIA_8233_0: 810 case PCI_DEVICE_ID_VIA_8233A: 811 case PCI_DEVICE_ID_VIA_8233C_0: 812 via_vlink_dev_lo = 17; 813 break; 814 } 815 } 816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 824 825 /** 826 * quirk_via_vlink - VIA VLink IRQ number update 827 * @dev: PCI device 828 * 829 * If the device we are dealing with is on a PIC IRQ we need to 830 * ensure that the IRQ line register which usually is not relevant 831 * for PCI cards, is actually written so that interrupts get sent 832 * to the right place. 833 * We only do this on systems where a VIA south bridge was detected, 834 * and only for VIA devices on the motherboard (see quirk_via_bridge 835 * above). 836 */ 837 838 static void quirk_via_vlink(struct pci_dev *dev) 839 { 840 u8 irq, new_irq; 841 842 /* Check if we have VLink at all */ 843 if (via_vlink_dev_lo == -1) 844 return; 845 846 new_irq = dev->irq; 847 848 /* Don't quirk interrupts outside the legacy IRQ range */ 849 if (!new_irq || new_irq > 15) 850 return; 851 852 /* Internal device ? */ 853 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 854 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 855 return; 856 857 /* This is an internal VLink device on a PIC interrupt. The BIOS 858 ought to have set this but may not have, so we redo it */ 859 860 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 861 if (new_irq != irq) { 862 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 863 irq, new_irq); 864 udelay(15); /* unknown if delay really needed */ 865 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 866 } 867 } 868 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 869 870 /* 871 * VIA VT82C598 has its device ID settable and many BIOSes 872 * set it to the ID of VT82C597 for backward compatibility. 873 * We need to switch it off to be able to recognize the real 874 * type of the chip. 875 */ 876 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 877 { 878 pci_write_config_byte(dev, 0xfc, 0); 879 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 880 } 881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 882 883 /* 884 * CardBus controllers have a legacy base address that enables them 885 * to respond as i82365 pcmcia controllers. We don't want them to 886 * do this even if the Linux CardBus driver is not loaded, because 887 * the Linux i82365 driver does not (and should not) handle CardBus. 888 */ 889 static void quirk_cardbus_legacy(struct pci_dev *dev) 890 { 891 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 892 return; 893 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 894 } 895 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 896 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 897 898 /* 899 * Following the PCI ordering rules is optional on the AMD762. I'm not 900 * sure what the designers were smoking but let's not inhale... 901 * 902 * To be fair to AMD, it follows the spec by default, its BIOS people 903 * who turn it off! 904 */ 905 static void quirk_amd_ordering(struct pci_dev *dev) 906 { 907 u32 pcic; 908 pci_read_config_dword(dev, 0x4C, &pcic); 909 if ((pcic&6)!=6) { 910 pcic |= 6; 911 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 912 pci_write_config_dword(dev, 0x4C, pcic); 913 pci_read_config_dword(dev, 0x84, &pcic); 914 pcic |= (1<<23); /* Required in this mode */ 915 pci_write_config_dword(dev, 0x84, pcic); 916 } 917 } 918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 919 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 920 921 /* 922 * DreamWorks provided workaround for Dunord I-3000 problem 923 * 924 * This card decodes and responds to addresses not apparently 925 * assigned to it. We force a larger allocation to ensure that 926 * nothing gets put too close to it. 927 */ 928 static void __devinit quirk_dunord ( struct pci_dev * dev ) 929 { 930 struct resource *r = &dev->resource [1]; 931 r->start = 0; 932 r->end = 0xffffff; 933 } 934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 935 936 /* 937 * i82380FB mobile docking controller: its PCI-to-PCI bridge 938 * is subtractive decoding (transparent), and does indicate this 939 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 940 * instead of 0x01. 941 */ 942 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 943 { 944 dev->transparent = 1; 945 } 946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 948 949 /* 950 * Common misconfiguration of the MediaGX/Geode PCI master that will 951 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 952 * datasheets found at http://www.national.com/ds/GX for info on what 953 * these bits do. <christer@weinigel.se> 954 */ 955 static void quirk_mediagx_master(struct pci_dev *dev) 956 { 957 u8 reg; 958 pci_read_config_byte(dev, 0x41, ®); 959 if (reg & 2) { 960 reg &= ~2; 961 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 962 pci_write_config_byte(dev, 0x41, reg); 963 } 964 } 965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 966 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 967 968 /* 969 * Ensure C0 rev restreaming is off. This is normally done by 970 * the BIOS but in the odd case it is not the results are corruption 971 * hence the presence of a Linux check 972 */ 973 static void quirk_disable_pxb(struct pci_dev *pdev) 974 { 975 u16 config; 976 977 if (pdev->revision != 0x04) /* Only C0 requires this */ 978 return; 979 pci_read_config_word(pdev, 0x40, &config); 980 if (config & (1<<6)) { 981 config &= ~(1<<6); 982 pci_write_config_word(pdev, 0x40, config); 983 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 984 } 985 } 986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 987 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 988 989 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 990 { 991 /* set sb600/sb700/sb800 sata to ahci mode */ 992 u8 tmp; 993 994 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 995 if (tmp == 0x01) { 996 pci_read_config_byte(pdev, 0x40, &tmp); 997 pci_write_config_byte(pdev, 0x40, tmp|1); 998 pci_write_config_byte(pdev, 0x9, 1); 999 pci_write_config_byte(pdev, 0xa, 6); 1000 pci_write_config_byte(pdev, 0x40, tmp); 1001 1002 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1003 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1004 } 1005 } 1006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1007 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1009 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1010 1011 /* 1012 * Serverworks CSB5 IDE does not fully support native mode 1013 */ 1014 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 1015 { 1016 u8 prog; 1017 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1018 if (prog & 5) { 1019 prog &= ~5; 1020 pdev->class &= ~5; 1021 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1022 /* PCI layer will sort out resources */ 1023 } 1024 } 1025 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1026 1027 /* 1028 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1029 */ 1030 static void __init quirk_ide_samemode(struct pci_dev *pdev) 1031 { 1032 u8 prog; 1033 1034 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1035 1036 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1037 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1038 prog &= ~5; 1039 pdev->class &= ~5; 1040 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1041 } 1042 } 1043 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1044 1045 /* 1046 * Some ATA devices break if put into D3 1047 */ 1048 1049 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) 1050 { 1051 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1052 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) 1053 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1054 } 1055 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); 1056 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); 1057 1058 /* This was originally an Alpha specific thing, but it really fits here. 1059 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1060 */ 1061 static void __init quirk_eisa_bridge(struct pci_dev *dev) 1062 { 1063 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1064 } 1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1066 1067 1068 /* 1069 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1070 * is not activated. The myth is that Asus said that they do not want the 1071 * users to be irritated by just another PCI Device in the Win98 device 1072 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1073 * package 2.7.0 for details) 1074 * 1075 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1076 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1077 * becomes necessary to do this tweak in two steps -- the chosen trigger 1078 * is either the Host bridge (preferred) or on-board VGA controller. 1079 * 1080 * Note that we used to unhide the SMBus that way on Toshiba laptops 1081 * (Satellite A40 and Tecra M2) but then found that the thermal management 1082 * was done by SMM code, which could cause unsynchronized concurrent 1083 * accesses to the SMBus registers, with potentially bad effects. Thus you 1084 * should be very careful when adding new entries: if SMM is accessing the 1085 * Intel SMBus, this is a very good reason to leave it hidden. 1086 * 1087 * Likewise, many recent laptops use ACPI for thermal management. If the 1088 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1089 * natively, and keeping the SMBus hidden is the right thing to do. If you 1090 * are about to add an entry in the table below, please first disassemble 1091 * the DSDT and double-check that there is no code accessing the SMBus. 1092 */ 1093 static int asus_hides_smbus; 1094 1095 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1096 { 1097 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1098 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1099 switch(dev->subsystem_device) { 1100 case 0x8025: /* P4B-LX */ 1101 case 0x8070: /* P4B */ 1102 case 0x8088: /* P4B533 */ 1103 case 0x1626: /* L3C notebook */ 1104 asus_hides_smbus = 1; 1105 } 1106 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1107 switch(dev->subsystem_device) { 1108 case 0x80b1: /* P4GE-V */ 1109 case 0x80b2: /* P4PE */ 1110 case 0x8093: /* P4B533-V */ 1111 asus_hides_smbus = 1; 1112 } 1113 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1114 switch(dev->subsystem_device) { 1115 case 0x8030: /* P4T533 */ 1116 asus_hides_smbus = 1; 1117 } 1118 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1119 switch (dev->subsystem_device) { 1120 case 0x8070: /* P4G8X Deluxe */ 1121 asus_hides_smbus = 1; 1122 } 1123 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1124 switch (dev->subsystem_device) { 1125 case 0x80c9: /* PU-DLS */ 1126 asus_hides_smbus = 1; 1127 } 1128 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1129 switch (dev->subsystem_device) { 1130 case 0x1751: /* M2N notebook */ 1131 case 0x1821: /* M5N notebook */ 1132 asus_hides_smbus = 1; 1133 } 1134 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1135 switch (dev->subsystem_device) { 1136 case 0x184b: /* W1N notebook */ 1137 case 0x186a: /* M6Ne notebook */ 1138 asus_hides_smbus = 1; 1139 } 1140 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1141 switch (dev->subsystem_device) { 1142 case 0x80f2: /* P4P800-X */ 1143 asus_hides_smbus = 1; 1144 } 1145 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1146 switch (dev->subsystem_device) { 1147 case 0x1882: /* M6V notebook */ 1148 case 0x1977: /* A6VA notebook */ 1149 asus_hides_smbus = 1; 1150 } 1151 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1152 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1153 switch(dev->subsystem_device) { 1154 case 0x088C: /* HP Compaq nc8000 */ 1155 case 0x0890: /* HP Compaq nc6000 */ 1156 asus_hides_smbus = 1; 1157 } 1158 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1159 switch (dev->subsystem_device) { 1160 case 0x12bc: /* HP D330L */ 1161 case 0x12bd: /* HP D530 */ 1162 asus_hides_smbus = 1; 1163 } 1164 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1165 switch (dev->subsystem_device) { 1166 case 0x12bf: /* HP xw4100 */ 1167 asus_hides_smbus = 1; 1168 } 1169 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1170 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1171 switch(dev->subsystem_device) { 1172 case 0xC00C: /* Samsung P35 notebook */ 1173 asus_hides_smbus = 1; 1174 } 1175 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1176 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1177 switch(dev->subsystem_device) { 1178 case 0x0058: /* Compaq Evo N620c */ 1179 asus_hides_smbus = 1; 1180 } 1181 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1182 switch(dev->subsystem_device) { 1183 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1184 /* Motherboard doesn't have Host bridge 1185 * subvendor/subdevice IDs, therefore checking 1186 * its on-board VGA controller */ 1187 asus_hides_smbus = 1; 1188 } 1189 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1190 switch(dev->subsystem_device) { 1191 case 0x00b8: /* Compaq Evo D510 CMT */ 1192 case 0x00b9: /* Compaq Evo D510 SFF */ 1193 /* Motherboard doesn't have Host bridge 1194 * subvendor/subdevice IDs and on-board VGA 1195 * controller is disabled if an AGP card is 1196 * inserted, therefore checking USB UHCI 1197 * Controller #1 */ 1198 asus_hides_smbus = 1; 1199 } 1200 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1201 switch (dev->subsystem_device) { 1202 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1203 /* Motherboard doesn't have host bridge 1204 * subvendor/subdevice IDs, therefore checking 1205 * its on-board VGA controller */ 1206 asus_hides_smbus = 1; 1207 } 1208 } 1209 } 1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1220 1221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1224 1225 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1226 { 1227 u16 val; 1228 1229 if (likely(!asus_hides_smbus)) 1230 return; 1231 1232 pci_read_config_word(dev, 0xF2, &val); 1233 if (val & 0x8) { 1234 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1235 pci_read_config_word(dev, 0xF2, &val); 1236 if (val & 0x8) 1237 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1238 else 1239 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1240 } 1241 } 1242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1249 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1250 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1251 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1252 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1253 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1254 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1255 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1256 1257 /* It appears we just have one such device. If not, we have a warning */ 1258 static void __iomem *asus_rcba_base; 1259 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1260 { 1261 u32 rcba; 1262 1263 if (likely(!asus_hides_smbus)) 1264 return; 1265 WARN_ON(asus_rcba_base); 1266 1267 pci_read_config_dword(dev, 0xF0, &rcba); 1268 /* use bits 31:14, 16 kB aligned */ 1269 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1270 if (asus_rcba_base == NULL) 1271 return; 1272 } 1273 1274 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1275 { 1276 u32 val; 1277 1278 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1279 return; 1280 /* read the Function Disable register, dword mode only */ 1281 val = readl(asus_rcba_base + 0x3418); 1282 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1283 } 1284 1285 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1286 { 1287 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1288 return; 1289 iounmap(asus_rcba_base); 1290 asus_rcba_base = NULL; 1291 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1292 } 1293 1294 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1295 { 1296 asus_hides_smbus_lpc_ich6_suspend(dev); 1297 asus_hides_smbus_lpc_ich6_resume_early(dev); 1298 asus_hides_smbus_lpc_ich6_resume(dev); 1299 } 1300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1301 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1302 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1304 1305 /* 1306 * SiS 96x south bridge: BIOS typically hides SMBus device... 1307 */ 1308 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1309 { 1310 u8 val = 0; 1311 pci_read_config_byte(dev, 0x77, &val); 1312 if (val & 0x10) { 1313 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1314 pci_write_config_byte(dev, 0x77, val & ~0x10); 1315 } 1316 } 1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1321 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1322 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1323 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1324 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1325 1326 /* 1327 * ... This is further complicated by the fact that some SiS96x south 1328 * bridges pretend to be 85C503/5513 instead. In that case see if we 1329 * spotted a compatible north bridge to make sure. 1330 * (pci_find_device doesn't work yet) 1331 * 1332 * We can also enable the sis96x bit in the discovery register.. 1333 */ 1334 #define SIS_DETECT_REGISTER 0x40 1335 1336 static void quirk_sis_503(struct pci_dev *dev) 1337 { 1338 u8 reg; 1339 u16 devid; 1340 1341 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1342 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1343 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1344 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1345 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1346 return; 1347 } 1348 1349 /* 1350 * Ok, it now shows up as a 96x.. run the 96x quirk by 1351 * hand in case it has already been processed. 1352 * (depends on link order, which is apparently not guaranteed) 1353 */ 1354 dev->device = devid; 1355 quirk_sis_96x_smbus(dev); 1356 } 1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1358 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1359 1360 1361 /* 1362 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1363 * and MC97 modem controller are disabled when a second PCI soundcard is 1364 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1365 * -- bjd 1366 */ 1367 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1368 { 1369 u8 val; 1370 int asus_hides_ac97 = 0; 1371 1372 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1373 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1374 asus_hides_ac97 = 1; 1375 } 1376 1377 if (!asus_hides_ac97) 1378 return; 1379 1380 pci_read_config_byte(dev, 0x50, &val); 1381 if (val & 0xc0) { 1382 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1383 pci_read_config_byte(dev, 0x50, &val); 1384 if (val & 0xc0) 1385 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1386 else 1387 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1388 } 1389 } 1390 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1392 1393 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1394 1395 /* 1396 * If we are using libata we can drive this chip properly but must 1397 * do this early on to make the additional device appear during 1398 * the PCI scanning. 1399 */ 1400 static void quirk_jmicron_ata(struct pci_dev *pdev) 1401 { 1402 u32 conf1, conf5, class; 1403 u8 hdr; 1404 1405 /* Only poke fn 0 */ 1406 if (PCI_FUNC(pdev->devfn)) 1407 return; 1408 1409 pci_read_config_dword(pdev, 0x40, &conf1); 1410 pci_read_config_dword(pdev, 0x80, &conf5); 1411 1412 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1413 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1414 1415 switch (pdev->device) { 1416 case PCI_DEVICE_ID_JMICRON_JMB360: 1417 /* The controller should be in single function ahci mode */ 1418 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1419 break; 1420 1421 case PCI_DEVICE_ID_JMICRON_JMB365: 1422 case PCI_DEVICE_ID_JMICRON_JMB366: 1423 /* Redirect IDE second PATA port to the right spot */ 1424 conf5 |= (1 << 24); 1425 /* Fall through */ 1426 case PCI_DEVICE_ID_JMICRON_JMB361: 1427 case PCI_DEVICE_ID_JMICRON_JMB363: 1428 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1429 /* Set the class codes correctly and then direct IDE 0 */ 1430 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1431 break; 1432 1433 case PCI_DEVICE_ID_JMICRON_JMB368: 1434 /* The controller should be in single function IDE mode */ 1435 conf1 |= 0x00C00000; /* Set 22, 23 */ 1436 break; 1437 } 1438 1439 pci_write_config_dword(pdev, 0x40, conf1); 1440 pci_write_config_dword(pdev, 0x80, conf5); 1441 1442 /* Update pdev accordingly */ 1443 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1444 pdev->hdr_type = hdr & 0x7f; 1445 pdev->multifunction = !!(hdr & 0x80); 1446 1447 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1448 pdev->class = class >> 8; 1449 } 1450 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1451 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1452 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1453 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1454 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1455 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1456 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1457 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1458 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1459 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1460 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1461 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1462 1463 #endif 1464 1465 #ifdef CONFIG_X86_IO_APIC 1466 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1467 { 1468 int i; 1469 1470 if ((pdev->class >> 8) != 0xff00) 1471 return; 1472 1473 /* the first BAR is the location of the IO APIC...we must 1474 * not touch this (and it's already covered by the fixmap), so 1475 * forcibly insert it into the resource tree */ 1476 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1477 insert_resource(&iomem_resource, &pdev->resource[0]); 1478 1479 /* The next five BARs all seem to be rubbish, so just clean 1480 * them out */ 1481 for (i=1; i < 6; i++) { 1482 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1483 } 1484 1485 } 1486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1487 #endif 1488 1489 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1490 { 1491 pcie_mch_quirk = 1; 1492 } 1493 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1496 1497 1498 /* 1499 * It's possible for the MSI to get corrupted if shpc and acpi 1500 * are used together on certain PXH-based systems. 1501 */ 1502 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1503 { 1504 pci_msi_off(dev); 1505 dev->no_msi = 1; 1506 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1507 } 1508 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1509 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1510 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1511 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1512 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1513 1514 /* 1515 * Some Intel PCI Express chipsets have trouble with downstream 1516 * device power management. 1517 */ 1518 static void quirk_intel_pcie_pm(struct pci_dev * dev) 1519 { 1520 pci_pm_d3_delay = 120; 1521 dev->no_d1d2 = 1; 1522 } 1523 1524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1527 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1545 1546 #ifdef CONFIG_X86_IO_APIC 1547 /* 1548 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1549 * remap the original interrupt in the linux kernel to the boot interrupt, so 1550 * that a PCI device's interrupt handler is installed on the boot interrupt 1551 * line instead. 1552 */ 1553 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1554 { 1555 if (noioapicquirk || noioapicreroute) 1556 return; 1557 1558 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1559 1560 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n", 1561 dev->vendor, dev->device); 1562 return; 1563 } 1564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1572 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1573 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1574 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1575 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1576 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1577 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1578 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1579 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1580 1581 /* 1582 * On some chipsets we can disable the generation of legacy INTx boot 1583 * interrupts. 1584 */ 1585 1586 /* 1587 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1588 * 300641-004US, section 5.7.3. 1589 */ 1590 #define INTEL_6300_IOAPIC_ABAR 0x40 1591 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1592 1593 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1594 { 1595 u16 pci_config_word; 1596 1597 if (noioapicquirk) 1598 return; 1599 1600 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1601 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1602 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1603 1604 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n", 1605 dev->vendor, dev->device); 1606 } 1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1608 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1609 1610 /* 1611 * disable boot interrupts on HT-1000 1612 */ 1613 #define BC_HT1000_FEATURE_REG 0x64 1614 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1615 #define BC_HT1000_MAP_IDX 0xC00 1616 #define BC_HT1000_MAP_DATA 0xC01 1617 1618 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1619 { 1620 u32 pci_config_dword; 1621 u8 irq; 1622 1623 if (noioapicquirk) 1624 return; 1625 1626 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1627 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1628 BC_HT1000_PIC_REGS_ENABLE); 1629 1630 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1631 outb(irq, BC_HT1000_MAP_IDX); 1632 outb(0x00, BC_HT1000_MAP_DATA); 1633 } 1634 1635 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1636 1637 printk(KERN_INFO "disabled boot interrupts on PCI device" 1638 "0x%04x:0x%04x\n", dev->vendor, dev->device); 1639 } 1640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1641 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1642 1643 /* 1644 * disable boot interrupts on AMD and ATI chipsets 1645 */ 1646 /* 1647 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1648 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1649 * (due to an erratum). 1650 */ 1651 #define AMD_813X_MISC 0x40 1652 #define AMD_813X_NOIOAMODE (1<<0) 1653 #define AMD_813X_REV_B2 0x13 1654 1655 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1656 { 1657 u32 pci_config_dword; 1658 1659 if (noioapicquirk) 1660 return; 1661 if (dev->revision == AMD_813X_REV_B2) 1662 return; 1663 1664 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1665 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1666 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1667 1668 printk(KERN_INFO "disabled boot interrupts on PCI device " 1669 "0x%04x:0x%04x\n", dev->vendor, dev->device); 1670 } 1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1672 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1673 1674 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1675 1676 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1677 { 1678 u16 pci_config_word; 1679 1680 if (noioapicquirk) 1681 return; 1682 1683 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1684 if (!pci_config_word) { 1685 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x " 1686 "already disabled\n", 1687 dev->vendor, dev->device); 1688 return; 1689 } 1690 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1691 printk(KERN_INFO "disabled boot interrupts on PCI device " 1692 "0x%04x:0x%04x\n", dev->vendor, dev->device); 1693 } 1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1695 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1696 #endif /* CONFIG_X86_IO_APIC */ 1697 1698 /* 1699 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1700 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1701 * Re-allocate the region if needed... 1702 */ 1703 static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1704 { 1705 struct resource *r = &dev->resource[0]; 1706 1707 if (r->start & 0x8) { 1708 r->start = 0; 1709 r->end = 0xf; 1710 } 1711 } 1712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1713 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1714 quirk_tc86c001_ide); 1715 1716 static void __devinit quirk_netmos(struct pci_dev *dev) 1717 { 1718 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1719 unsigned int num_serial = dev->subsystem_device & 0xf; 1720 1721 /* 1722 * These Netmos parts are multiport serial devices with optional 1723 * parallel ports. Even when parallel ports are present, they 1724 * are identified as class SERIAL, which means the serial driver 1725 * will claim them. To prevent this, mark them as class OTHER. 1726 * These combo devices should be claimed by parport_serial. 1727 * 1728 * The subdevice ID is of the form 0x00PS, where <P> is the number 1729 * of parallel ports and <S> is the number of serial ports. 1730 */ 1731 switch (dev->device) { 1732 case PCI_DEVICE_ID_NETMOS_9835: 1733 /* Well, this rule doesn't hold for the following 9835 device */ 1734 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1735 dev->subsystem_device == 0x0299) 1736 return; 1737 case PCI_DEVICE_ID_NETMOS_9735: 1738 case PCI_DEVICE_ID_NETMOS_9745: 1739 case PCI_DEVICE_ID_NETMOS_9845: 1740 case PCI_DEVICE_ID_NETMOS_9855: 1741 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1742 num_parallel) { 1743 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1744 "%u serial); changing class SERIAL to OTHER " 1745 "(use parport_serial)\n", 1746 dev->device, num_parallel, num_serial); 1747 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1748 (dev->class & 0xff); 1749 } 1750 } 1751 } 1752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1753 1754 static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1755 { 1756 u16 command, pmcsr; 1757 u8 __iomem *csr; 1758 u8 cmd_hi; 1759 int pm; 1760 1761 switch (dev->device) { 1762 /* PCI IDs taken from drivers/net/e100.c */ 1763 case 0x1029: 1764 case 0x1030 ... 0x1034: 1765 case 0x1038 ... 0x103E: 1766 case 0x1050 ... 0x1057: 1767 case 0x1059: 1768 case 0x1064 ... 0x106B: 1769 case 0x1091 ... 0x1095: 1770 case 0x1209: 1771 case 0x1229: 1772 case 0x2449: 1773 case 0x2459: 1774 case 0x245D: 1775 case 0x27DC: 1776 break; 1777 default: 1778 return; 1779 } 1780 1781 /* 1782 * Some firmware hands off the e100 with interrupts enabled, 1783 * which can cause a flood of interrupts if packets are 1784 * received before the driver attaches to the device. So 1785 * disable all e100 interrupts here. The driver will 1786 * re-enable them when it's ready. 1787 */ 1788 pci_read_config_word(dev, PCI_COMMAND, &command); 1789 1790 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1791 return; 1792 1793 /* 1794 * Check that the device is in the D0 power state. If it's not, 1795 * there is no point to look any further. 1796 */ 1797 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1798 if (pm) { 1799 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 1800 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1801 return; 1802 } 1803 1804 /* Convert from PCI bus to resource space. */ 1805 csr = ioremap(pci_resource_start(dev, 0), 8); 1806 if (!csr) { 1807 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1808 return; 1809 } 1810 1811 cmd_hi = readb(csr + 3); 1812 if (cmd_hi == 0) { 1813 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1814 "disabling\n"); 1815 writeb(1, csr + 3); 1816 } 1817 1818 iounmap(csr); 1819 } 1820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1821 1822 /* 1823 * The 82575 and 82598 may experience data corruption issues when transitioning 1824 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1825 */ 1826 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) 1827 { 1828 dev_info(&dev->dev, "Disabling L0s\n"); 1829 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1830 } 1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1845 1846 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1847 { 1848 /* rev 1 ncr53c810 chips don't set the class at all which means 1849 * they don't get their resources remapped. Fix that here. 1850 */ 1851 1852 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1853 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1854 dev->class = PCI_CLASS_STORAGE_SCSI; 1855 } 1856 } 1857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1858 1859 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1860 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1861 { 1862 u16 en1k; 1863 u8 io_base_lo, io_limit_lo; 1864 unsigned long base, limit; 1865 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1866 1867 pci_read_config_word(dev, 0x40, &en1k); 1868 1869 if (en1k & 0x200) { 1870 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1871 1872 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1873 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1874 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1875 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1876 1877 if (base <= limit) { 1878 res->start = base; 1879 res->end = limit + 0x3ff; 1880 } 1881 } 1882 } 1883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1884 1885 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 1886 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 1887 * in drivers/pci/setup-bus.c 1888 */ 1889 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 1890 { 1891 u16 en1k, iobl_adr, iobl_adr_1k; 1892 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1893 1894 pci_read_config_word(dev, 0x40, &en1k); 1895 1896 if (en1k & 0x200) { 1897 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 1898 1899 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1900 1901 if (iobl_adr != iobl_adr_1k) { 1902 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", 1903 iobl_adr,iobl_adr_1k); 1904 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1905 } 1906 } 1907 } 1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 1909 1910 /* Under some circumstances, AER is not linked with extended capabilities. 1911 * Force it to be linked by setting the corresponding control bit in the 1912 * config space. 1913 */ 1914 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1915 { 1916 uint8_t b; 1917 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1918 if (!(b & 0x20)) { 1919 pci_write_config_byte(dev, 0xf41, b | 0x20); 1920 dev_info(&dev->dev, 1921 "Linking AER extended capability\n"); 1922 } 1923 } 1924 } 1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1926 quirk_nvidia_ck804_pcie_aer_ext_cap); 1927 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1928 quirk_nvidia_ck804_pcie_aer_ext_cap); 1929 1930 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 1931 { 1932 /* 1933 * Disable PCI Bus Parking and PCI Master read caching on CX700 1934 * which causes unspecified timing errors with a VT6212L on the PCI 1935 * bus leading to USB2.0 packet loss. The defaults are that these 1936 * features are turned off but some BIOSes turn them on. 1937 */ 1938 1939 uint8_t b; 1940 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 1941 if (b & 0x40) { 1942 /* Turn off PCI Bus Parking */ 1943 pci_write_config_byte(dev, 0x76, b ^ 0x40); 1944 1945 dev_info(&dev->dev, 1946 "Disabling VIA CX700 PCI parking\n"); 1947 } 1948 } 1949 1950 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 1951 if (b != 0) { 1952 /* Turn off PCI Master read caching */ 1953 pci_write_config_byte(dev, 0x72, 0x0); 1954 1955 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 1956 pci_write_config_byte(dev, 0x75, 0x1); 1957 1958 /* Disable "Read FIFO Timer" */ 1959 pci_write_config_byte(dev, 0x77, 0x0); 1960 1961 dev_info(&dev->dev, 1962 "Disabling VIA CX700 PCI caching\n"); 1963 } 1964 } 1965 } 1966 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 1967 1968 /* 1969 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 1970 * VPD end tag will hang the device. This problem was initially 1971 * observed when a vpd entry was created in sysfs 1972 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 1973 * will dump 32k of data. Reading a full 32k will cause an access 1974 * beyond the VPD end tag causing the device to hang. Once the device 1975 * is hung, the bnx2 driver will not be able to reset the device. 1976 * We believe that it is legal to read beyond the end tag and 1977 * therefore the solution is to limit the read/write length. 1978 */ 1979 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 1980 { 1981 /* 1982 * Only disable the VPD capability for 5706, 5706S, 5708, 1983 * 5708S and 5709 rev. A 1984 */ 1985 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 1986 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 1987 (dev->device == PCI_DEVICE_ID_NX2_5708) || 1988 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 1989 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 1990 (dev->revision & 0xf0) == 0x0)) { 1991 if (dev->vpd) 1992 dev->vpd->len = 0x80; 1993 } 1994 } 1995 1996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1997 PCI_DEVICE_ID_NX2_5706, 1998 quirk_brcm_570x_limit_vpd); 1999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2000 PCI_DEVICE_ID_NX2_5706S, 2001 quirk_brcm_570x_limit_vpd); 2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2003 PCI_DEVICE_ID_NX2_5708, 2004 quirk_brcm_570x_limit_vpd); 2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2006 PCI_DEVICE_ID_NX2_5708S, 2007 quirk_brcm_570x_limit_vpd); 2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2009 PCI_DEVICE_ID_NX2_5709, 2010 quirk_brcm_570x_limit_vpd); 2011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2012 PCI_DEVICE_ID_NX2_5709S, 2013 quirk_brcm_570x_limit_vpd); 2014 2015 #ifdef CONFIG_PCI_MSI 2016 /* Some chipsets do not support MSI. We cannot easily rely on setting 2017 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2018 * some other busses controlled by the chipset even if Linux is not 2019 * aware of it. Instead of setting the flag on all busses in the 2020 * machine, simply disable MSI globally. 2021 */ 2022 static void __init quirk_disable_all_msi(struct pci_dev *dev) 2023 { 2024 pci_no_msi(); 2025 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2026 } 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2032 2033 /* Disable MSI on chipsets that are known to not support it */ 2034 static void __devinit quirk_disable_msi(struct pci_dev *dev) 2035 { 2036 if (dev->subordinate) { 2037 dev_warn(&dev->dev, "MSI quirk detected; " 2038 "subordinate MSI disabled\n"); 2039 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2040 } 2041 } 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2043 2044 /* Go through the list of Hypertransport capabilities and 2045 * return 1 if a HT MSI capability is found and enabled */ 2046 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 2047 { 2048 int pos, ttl = 48; 2049 2050 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2051 while (pos && ttl--) { 2052 u8 flags; 2053 2054 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2055 &flags) == 0) 2056 { 2057 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2058 flags & HT_MSI_FLAGS_ENABLE ? 2059 "enabled" : "disabled"); 2060 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2061 } 2062 2063 pos = pci_find_next_ht_capability(dev, pos, 2064 HT_CAPTYPE_MSI_MAPPING); 2065 } 2066 return 0; 2067 } 2068 2069 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2070 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 2071 { 2072 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2073 dev_warn(&dev->dev, "MSI quirk detected; " 2074 "subordinate MSI disabled\n"); 2075 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2076 } 2077 } 2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2079 quirk_msi_ht_cap); 2080 2081 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2082 * MSI are supported if the MSI capability set in any of these mappings. 2083 */ 2084 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2085 { 2086 struct pci_dev *pdev; 2087 2088 if (!dev->subordinate) 2089 return; 2090 2091 /* check HT MSI cap on this chipset and the root one. 2092 * a single one having MSI is enough to be sure that MSI are supported. 2093 */ 2094 pdev = pci_get_slot(dev->bus, 0); 2095 if (!pdev) 2096 return; 2097 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2098 dev_warn(&dev->dev, "MSI quirk detected; " 2099 "subordinate MSI disabled\n"); 2100 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2101 } 2102 pci_dev_put(pdev); 2103 } 2104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2105 quirk_nvidia_ck804_msi_ht_cap); 2106 2107 /* Force enable MSI mapping capability on HT bridges */ 2108 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 2109 { 2110 int pos, ttl = 48; 2111 2112 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2113 while (pos && ttl--) { 2114 u8 flags; 2115 2116 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2117 &flags) == 0) { 2118 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2119 2120 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2121 flags | HT_MSI_FLAGS_ENABLE); 2122 } 2123 pos = pci_find_next_ht_capability(dev, pos, 2124 HT_CAPTYPE_MSI_MAPPING); 2125 } 2126 } 2127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2128 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2129 ht_enable_msi_mapping); 2130 2131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2132 ht_enable_msi_mapping); 2133 2134 /* The P5N32-SLI Premium motherboard from Asus has a problem with msi 2135 * for the MCP55 NIC. It is not yet determined whether the msi problem 2136 * also affects other devices. As for now, turn off msi for this device. 2137 */ 2138 static void __devinit nvenet_msi_disable(struct pci_dev *dev) 2139 { 2140 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) { 2141 dev_info(&dev->dev, 2142 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n"); 2143 dev->no_msi = 1; 2144 } 2145 } 2146 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2147 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2148 nvenet_msi_disable); 2149 2150 static int __devinit ht_check_msi_mapping(struct pci_dev *dev) 2151 { 2152 int pos, ttl = 48; 2153 int found = 0; 2154 2155 /* check if there is HT MSI cap or enabled on this device */ 2156 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2157 while (pos && ttl--) { 2158 u8 flags; 2159 2160 if (found < 1) 2161 found = 1; 2162 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2163 &flags) == 0) { 2164 if (flags & HT_MSI_FLAGS_ENABLE) { 2165 if (found < 2) { 2166 found = 2; 2167 break; 2168 } 2169 } 2170 } 2171 pos = pci_find_next_ht_capability(dev, pos, 2172 HT_CAPTYPE_MSI_MAPPING); 2173 } 2174 2175 return found; 2176 } 2177 2178 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) 2179 { 2180 struct pci_dev *dev; 2181 int pos; 2182 int i, dev_no; 2183 int found = 0; 2184 2185 dev_no = host_bridge->devfn >> 3; 2186 for (i = dev_no + 1; i < 0x20; i++) { 2187 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2188 if (!dev) 2189 continue; 2190 2191 /* found next host bridge ?*/ 2192 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2193 if (pos != 0) { 2194 pci_dev_put(dev); 2195 break; 2196 } 2197 2198 if (ht_check_msi_mapping(dev)) { 2199 found = 1; 2200 pci_dev_put(dev); 2201 break; 2202 } 2203 pci_dev_put(dev); 2204 } 2205 2206 return found; 2207 } 2208 2209 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2210 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2211 2212 static int __devinit is_end_of_ht_chain(struct pci_dev *dev) 2213 { 2214 int pos, ctrl_off; 2215 int end = 0; 2216 u16 flags, ctrl; 2217 2218 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2219 2220 if (!pos) 2221 goto out; 2222 2223 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2224 2225 ctrl_off = ((flags >> 10) & 1) ? 2226 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2227 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2228 2229 if (ctrl & (1 << 6)) 2230 end = 1; 2231 2232 out: 2233 return end; 2234 } 2235 2236 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) 2237 { 2238 struct pci_dev *host_bridge; 2239 int pos; 2240 int i, dev_no; 2241 int found = 0; 2242 2243 dev_no = dev->devfn >> 3; 2244 for (i = dev_no; i >= 0; i--) { 2245 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2246 if (!host_bridge) 2247 continue; 2248 2249 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2250 if (pos != 0) { 2251 found = 1; 2252 break; 2253 } 2254 pci_dev_put(host_bridge); 2255 } 2256 2257 if (!found) 2258 return; 2259 2260 /* don't enable end_device/host_bridge with leaf directly here */ 2261 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2262 host_bridge_with_leaf(host_bridge)) 2263 goto out; 2264 2265 /* root did that ! */ 2266 if (msi_ht_cap_enabled(host_bridge)) 2267 goto out; 2268 2269 ht_enable_msi_mapping(dev); 2270 2271 out: 2272 pci_dev_put(host_bridge); 2273 } 2274 2275 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) 2276 { 2277 int pos, ttl = 48; 2278 2279 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2280 while (pos && ttl--) { 2281 u8 flags; 2282 2283 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2284 &flags) == 0) { 2285 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2286 2287 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2288 flags & ~HT_MSI_FLAGS_ENABLE); 2289 } 2290 pos = pci_find_next_ht_capability(dev, pos, 2291 HT_CAPTYPE_MSI_MAPPING); 2292 } 2293 } 2294 2295 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2296 { 2297 struct pci_dev *host_bridge; 2298 int pos; 2299 int found; 2300 2301 /* check if there is HT MSI cap or enabled on this device */ 2302 found = ht_check_msi_mapping(dev); 2303 2304 /* no HT MSI CAP */ 2305 if (found == 0) 2306 return; 2307 2308 /* 2309 * HT MSI mapping should be disabled on devices that are below 2310 * a non-Hypertransport host bridge. Locate the host bridge... 2311 */ 2312 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2313 if (host_bridge == NULL) { 2314 dev_warn(&dev->dev, 2315 "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2316 return; 2317 } 2318 2319 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2320 if (pos != 0) { 2321 /* Host bridge is to HT */ 2322 if (found == 1) { 2323 /* it is not enabled, try to enable it */ 2324 if (all) 2325 ht_enable_msi_mapping(dev); 2326 else 2327 nv_ht_enable_msi_mapping(dev); 2328 } 2329 return; 2330 } 2331 2332 /* HT MSI is not enabled */ 2333 if (found == 1) 2334 return; 2335 2336 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2337 ht_disable_msi_mapping(dev); 2338 } 2339 2340 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2341 { 2342 return __nv_msi_ht_cap_quirk(dev, 1); 2343 } 2344 2345 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2346 { 2347 return __nv_msi_ht_cap_quirk(dev, 0); 2348 } 2349 2350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2351 2352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2353 2354 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) 2355 { 2356 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2357 } 2358 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2359 { 2360 struct pci_dev *p; 2361 2362 /* SB700 MSI issue will be fixed at HW level from revision A21, 2363 * we need check PCI REVISION ID of SMBus controller to get SB700 2364 * revision. 2365 */ 2366 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2367 NULL); 2368 if (!p) 2369 return; 2370 2371 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2372 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2373 pci_dev_put(p); 2374 } 2375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2376 PCI_DEVICE_ID_TIGON3_5780, 2377 quirk_msi_intx_disable_bug); 2378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2379 PCI_DEVICE_ID_TIGON3_5780S, 2380 quirk_msi_intx_disable_bug); 2381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2382 PCI_DEVICE_ID_TIGON3_5714, 2383 quirk_msi_intx_disable_bug); 2384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2385 PCI_DEVICE_ID_TIGON3_5714S, 2386 quirk_msi_intx_disable_bug); 2387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2388 PCI_DEVICE_ID_TIGON3_5715, 2389 quirk_msi_intx_disable_bug); 2390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2391 PCI_DEVICE_ID_TIGON3_5715S, 2392 quirk_msi_intx_disable_bug); 2393 2394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2395 quirk_msi_intx_disable_ati_bug); 2396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2397 quirk_msi_intx_disable_ati_bug); 2398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2399 quirk_msi_intx_disable_ati_bug); 2400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2401 quirk_msi_intx_disable_ati_bug); 2402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2403 quirk_msi_intx_disable_ati_bug); 2404 2405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2406 quirk_msi_intx_disable_bug); 2407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2408 quirk_msi_intx_disable_bug); 2409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2410 quirk_msi_intx_disable_bug); 2411 2412 #endif /* CONFIG_PCI_MSI */ 2413 2414 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2415 struct pci_fixup *end) 2416 { 2417 while (f < end) { 2418 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 2419 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 2420 dev_dbg(&dev->dev, "calling %pF\n", f->hook); 2421 f->hook(dev); 2422 } 2423 f++; 2424 } 2425 } 2426 2427 extern struct pci_fixup __start_pci_fixups_early[]; 2428 extern struct pci_fixup __end_pci_fixups_early[]; 2429 extern struct pci_fixup __start_pci_fixups_header[]; 2430 extern struct pci_fixup __end_pci_fixups_header[]; 2431 extern struct pci_fixup __start_pci_fixups_final[]; 2432 extern struct pci_fixup __end_pci_fixups_final[]; 2433 extern struct pci_fixup __start_pci_fixups_enable[]; 2434 extern struct pci_fixup __end_pci_fixups_enable[]; 2435 extern struct pci_fixup __start_pci_fixups_resume[]; 2436 extern struct pci_fixup __end_pci_fixups_resume[]; 2437 extern struct pci_fixup __start_pci_fixups_resume_early[]; 2438 extern struct pci_fixup __end_pci_fixups_resume_early[]; 2439 extern struct pci_fixup __start_pci_fixups_suspend[]; 2440 extern struct pci_fixup __end_pci_fixups_suspend[]; 2441 2442 2443 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2444 { 2445 struct pci_fixup *start, *end; 2446 2447 switch(pass) { 2448 case pci_fixup_early: 2449 start = __start_pci_fixups_early; 2450 end = __end_pci_fixups_early; 2451 break; 2452 2453 case pci_fixup_header: 2454 start = __start_pci_fixups_header; 2455 end = __end_pci_fixups_header; 2456 break; 2457 2458 case pci_fixup_final: 2459 start = __start_pci_fixups_final; 2460 end = __end_pci_fixups_final; 2461 break; 2462 2463 case pci_fixup_enable: 2464 start = __start_pci_fixups_enable; 2465 end = __end_pci_fixups_enable; 2466 break; 2467 2468 case pci_fixup_resume: 2469 start = __start_pci_fixups_resume; 2470 end = __end_pci_fixups_resume; 2471 break; 2472 2473 case pci_fixup_resume_early: 2474 start = __start_pci_fixups_resume_early; 2475 end = __end_pci_fixups_resume_early; 2476 break; 2477 2478 case pci_fixup_suspend: 2479 start = __start_pci_fixups_suspend; 2480 end = __end_pci_fixups_suspend; 2481 break; 2482 2483 default: 2484 /* stupid compiler warning, you would think with an enum... */ 2485 return; 2486 } 2487 pci_do_fixups(dev, start, end); 2488 } 2489 #else 2490 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {} 2491 #endif 2492 EXPORT_SYMBOL(pci_fixup_device); 2493