xref: /openbmc/linux/drivers/pci/quirks.c (revision b6dcefde)
1 /*
2  *  This file contains work-arounds for many known PCI hardware
3  *  bugs.  Devices present only on certain architectures (host
4  *  bridges et cetera) should be handled in arch-specific code.
5  *
6  *  Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7  *
8  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9  *
10  *  Init/reset quirks for USB host controllers should be in the
11  *  USB quirks file, where their drivers can access reuse it.
12  *
13  *  The bridge optimization stuff has been removed. If you really
14  *  have a silly BIOS which is unable to set your host bridge right,
15  *  use the PowerTweak utility (see http://powertweak.sourceforge.net).
16  */
17 
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/ioport.h>
28 #include "pci.h"
29 
30 int isa_dma_bridge_buggy;
31 EXPORT_SYMBOL(isa_dma_bridge_buggy);
32 int pci_pci_problems;
33 EXPORT_SYMBOL(pci_pci_problems);
34 
35 #ifdef CONFIG_PCI_QUIRKS
36 /*
37  * This quirk function disables memory decoding and releases memory resources
38  * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
39  * It also rounds up size to specified alignment.
40  * Later on, the kernel will assign page-aligned memory resource back
41  * to the device.
42  */
43 static void __devinit quirk_resource_alignment(struct pci_dev *dev)
44 {
45 	int i;
46 	struct resource *r;
47 	resource_size_t align, size;
48 	u16 command;
49 
50 	if (!pci_is_reassigndev(dev))
51 		return;
52 
53 	if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
54 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
55 		dev_warn(&dev->dev,
56 			"Can't reassign resources to host bridge.\n");
57 		return;
58 	}
59 
60 	dev_info(&dev->dev,
61 		"Disabling memory decoding and releasing memory resources.\n");
62 	pci_read_config_word(dev, PCI_COMMAND, &command);
63 	command &= ~PCI_COMMAND_MEMORY;
64 	pci_write_config_word(dev, PCI_COMMAND, command);
65 
66 	align = pci_specified_resource_alignment(dev);
67 	for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
68 		r = &dev->resource[i];
69 		if (!(r->flags & IORESOURCE_MEM))
70 			continue;
71 		size = resource_size(r);
72 		if (size < align) {
73 			size = align;
74 			dev_info(&dev->dev,
75 				"Rounding up size of resource #%d to %#llx.\n",
76 				i, (unsigned long long)size);
77 		}
78 		r->end = size - 1;
79 		r->start = 0;
80 	}
81 	/* Need to disable bridge's resource window,
82 	 * to enable the kernel to reassign new resource
83 	 * window later on.
84 	 */
85 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
86 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
87 		for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
88 			r = &dev->resource[i];
89 			if (!(r->flags & IORESOURCE_MEM))
90 				continue;
91 			r->end = resource_size(r) - 1;
92 			r->start = 0;
93 		}
94 		pci_disable_bridge_window(dev);
95 	}
96 }
97 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
98 
99 /* The Mellanox Tavor device gives false positive parity errors
100  * Mark this device with a broken_parity_status, to allow
101  * PCI scanning code to "skip" this now blacklisted device.
102  */
103 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
104 {
105 	dev->broken_parity_status = 1;	/* This device gives false positives */
106 }
107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
109 
110 /* Deal with broken BIOS'es that neglect to enable passive release,
111    which can cause problems in combination with the 82441FX/PPro MTRRs */
112 static void quirk_passive_release(struct pci_dev *dev)
113 {
114 	struct pci_dev *d = NULL;
115 	unsigned char dlc;
116 
117 	/* We have to make sure a particular bit is set in the PIIX3
118 	   ISA bridge, so we have to go out and find it. */
119 	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
120 		pci_read_config_byte(d, 0x82, &dlc);
121 		if (!(dlc & 1<<1)) {
122 			dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
123 			dlc |= 1<<1;
124 			pci_write_config_byte(d, 0x82, dlc);
125 		}
126 	}
127 }
128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
129 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
130 
131 /*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
132     but VIA don't answer queries. If you happen to have good contacts at VIA
133     ask them for me please -- Alan
134 
135     This appears to be BIOS not version dependent. So presumably there is a
136     chipset level fix */
137 
138 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
139 {
140 	if (!isa_dma_bridge_buggy) {
141 		isa_dma_bridge_buggy=1;
142 		dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
143 	}
144 }
145 	/*
146 	 * Its not totally clear which chipsets are the problematic ones
147 	 * We know 82C586 and 82C596 variants are affected.
148 	 */
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_0,	quirk_isa_dma_hangs);
150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C596,	quirk_isa_dma_hangs);
151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1533, 	quirk_isa_dma_hangs);
153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_1,	quirk_isa_dma_hangs);
154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs);
155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs);
156 
157 /*
158  *	Chipsets where PCI->PCI transfers vanish or hang
159  */
160 static void __devinit quirk_nopcipci(struct pci_dev *dev)
161 {
162 	if ((pci_pci_problems & PCIPCI_FAIL)==0) {
163 		dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
164 		pci_pci_problems |= PCIPCI_FAIL;
165 	}
166 }
167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci);
168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci);
169 
170 static void __devinit quirk_nopciamd(struct pci_dev *dev)
171 {
172 	u8 rev;
173 	pci_read_config_byte(dev, 0x08, &rev);
174 	if (rev == 0x13) {
175 		/* Erratum 24 */
176 		dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
177 		pci_pci_problems |= PCIAGP_FAIL;
178 	}
179 }
180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopciamd);
181 
182 /*
183  *	Triton requires workarounds to be used by the drivers
184  */
185 static void __devinit quirk_triton(struct pci_dev *dev)
186 {
187 	if ((pci_pci_problems&PCIPCI_TRITON)==0) {
188 		dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
189 		pci_pci_problems |= PCIPCI_TRITON;
190 	}
191 }
192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82437, 	quirk_triton);
193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82437VX, 	quirk_triton);
194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82439, 	quirk_triton);
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82439TX, 	quirk_triton);
196 
197 /*
198  *	VIA Apollo KT133 needs PCI latency patch
199  *	Made according to a windows driver based patch by George E. Breese
200  *	see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
201  *      Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
202  *      the info on which Mr Breese based his work.
203  *
204  *	Updated based on further information from the site and also on
205  *	information provided by VIA
206  */
207 static void quirk_vialatency(struct pci_dev *dev)
208 {
209 	struct pci_dev *p;
210 	u8 busarb;
211 	/* Ok we have a potential problem chipset here. Now see if we have
212 	   a buggy southbridge */
213 
214 	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
215 	if (p!=NULL) {
216 		/* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
217 		/* Check for buggy part revisions */
218 		if (p->revision < 0x40 || p->revision > 0x42)
219 			goto exit;
220 	} else {
221 		p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
222 		if (p==NULL)	/* No problem parts */
223 			goto exit;
224 		/* Check for buggy part revisions */
225 		if (p->revision < 0x10 || p->revision > 0x12)
226 			goto exit;
227 	}
228 
229 	/*
230 	 *	Ok we have the problem. Now set the PCI master grant to
231 	 *	occur every master grant. The apparent bug is that under high
232 	 *	PCI load (quite common in Linux of course) you can get data
233 	 *	loss when the CPU is held off the bus for 3 bus master requests
234 	 *	This happens to include the IDE controllers....
235 	 *
236 	 *	VIA only apply this fix when an SB Live! is present but under
237 	 *	both Linux and Windows this isnt enough, and we have seen
238 	 *	corruption without SB Live! but with things like 3 UDMA IDE
239 	 *	controllers. So we ignore that bit of the VIA recommendation..
240 	 */
241 
242 	pci_read_config_byte(dev, 0x76, &busarb);
243 	/* Set bit 4 and bi 5 of byte 76 to 0x01
244 	   "Master priority rotation on every PCI master grant */
245 	busarb &= ~(1<<5);
246 	busarb |= (1<<4);
247 	pci_write_config_byte(dev, 0x76, busarb);
248 	dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
249 exit:
250 	pci_dev_put(p);
251 }
252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
255 /* Must restore this on a resume from RAM */
256 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
257 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
258 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
259 
260 /*
261  *	VIA Apollo VP3 needs ETBF on BT848/878
262  */
263 static void __devinit quirk_viaetbf(struct pci_dev *dev)
264 {
265 	if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
266 		dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
267 		pci_pci_problems |= PCIPCI_VIAETBF;
268 	}
269 }
270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_viaetbf);
271 
272 static void __devinit quirk_vsfx(struct pci_dev *dev)
273 {
274 	if ((pci_pci_problems&PCIPCI_VSFX)==0) {
275 		dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
276 		pci_pci_problems |= PCIPCI_VSFX;
277 	}
278 }
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx);
280 
281 /*
282  *	Ali Magik requires workarounds to be used by the drivers
283  *	that DMA to AGP space. Latency must be set to 0xA and triton
284  *	workaround applied too
285  *	[Info kindly provided by ALi]
286  */
287 static void __init quirk_alimagik(struct pci_dev *dev)
288 {
289 	if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
290 		dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
291 		pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
292 	}
293 }
294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 	PCI_DEVICE_ID_AL_M1647, 	quirk_alimagik);
295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 	PCI_DEVICE_ID_AL_M1651, 	quirk_alimagik);
296 
297 /*
298  *	Natoma has some interesting boundary conditions with Zoran stuff
299  *	at least
300  */
301 static void __devinit quirk_natoma(struct pci_dev *dev)
302 {
303 	if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
304 		dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
305 		pci_pci_problems |= PCIPCI_NATOMA;
306 	}
307 }
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82441, 	quirk_natoma);
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443LX_0, 	quirk_natoma);
310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443LX_1, 	quirk_natoma);
311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_0, 	quirk_natoma);
312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_1, 	quirk_natoma);
313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_2, 	quirk_natoma);
314 
315 /*
316  *  This chip can cause PCI parity errors if config register 0xA0 is read
317  *  while DMAs are occurring.
318  */
319 static void __devinit quirk_citrine(struct pci_dev *dev)
320 {
321 	dev->cfg_size = 0xA0;
322 }
323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine);
324 
325 /*
326  *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
327  *  If it's needed, re-allocate the region.
328  */
329 static void __devinit quirk_s3_64M(struct pci_dev *dev)
330 {
331 	struct resource *r = &dev->resource[0];
332 
333 	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
334 		r->start = 0;
335 		r->end = 0x3ffffff;
336 	}
337 }
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_868,		quirk_s3_64M);
339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_968,		quirk_s3_64M);
340 
341 /*
342  * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
343  * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
344  * BAR0 should be 8 bytes; instead, it may be set to something like 8k
345  * (which conflicts w/ BAR1's memory range).
346  */
347 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
348 {
349 	if (pci_resource_len(dev, 0) != 8) {
350 		struct resource *res = &dev->resource[0];
351 		res->end = res->start + 8 - 1;
352 		dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
353 				"(incorrect header); workaround applied.\n");
354 	}
355 }
356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
357 
358 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
359 	unsigned size, int nr, const char *name)
360 {
361 	region &= ~(size-1);
362 	if (region) {
363 		struct pci_bus_region bus_region;
364 		struct resource *res = dev->resource + nr;
365 
366 		res->name = pci_name(dev);
367 		res->start = region;
368 		res->end = region + size - 1;
369 		res->flags = IORESOURCE_IO;
370 
371 		/* Convert from PCI bus to resource space.  */
372 		bus_region.start = res->start;
373 		bus_region.end = res->end;
374 		pcibios_bus_to_resource(dev, res, &bus_region);
375 
376 		pci_claim_resource(dev, nr);
377 		dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
378 	}
379 }
380 
381 /*
382  *	ATI Northbridge setups MCE the processor if you even
383  *	read somewhere between 0x3b0->0x3bb or read 0x3d3
384  */
385 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
386 {
387 	dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
388 	/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
389 	request_region(0x3b0, 0x0C, "RadeonIGP");
390 	request_region(0x3d3, 0x01, "RadeonIGP");
391 }
392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
393 
394 /*
395  * Let's make the southbridge information explicit instead
396  * of having to worry about people probing the ACPI areas,
397  * for example.. (Yes, it happens, and if you read the wrong
398  * ACPI register it will put the machine to sleep with no
399  * way of waking it up again. Bummer).
400  *
401  * ALI M7101: Two IO regions pointed to by words at
402  *	0xE0 (64 bytes of ACPI registers)
403  *	0xE2 (32 bytes of SMB registers)
404  */
405 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
406 {
407 	u16 region;
408 
409 	pci_read_config_word(dev, 0xE0, &region);
410 	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
411 	pci_read_config_word(dev, 0xE2, &region);
412 	quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
413 }
414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi);
415 
416 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
417 {
418 	u32 devres;
419 	u32 mask, size, base;
420 
421 	pci_read_config_dword(dev, port, &devres);
422 	if ((devres & enable) != enable)
423 		return;
424 	mask = (devres >> 16) & 15;
425 	base = devres & 0xffff;
426 	size = 16;
427 	for (;;) {
428 		unsigned bit = size >> 1;
429 		if ((bit & mask) == bit)
430 			break;
431 		size = bit;
432 	}
433 	/*
434 	 * For now we only print it out. Eventually we'll want to
435 	 * reserve it (at least if it's in the 0x1000+ range), but
436 	 * let's get enough confirmation reports first.
437 	 */
438 	base &= -size;
439 	dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
440 }
441 
442 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
443 {
444 	u32 devres;
445 	u32 mask, size, base;
446 
447 	pci_read_config_dword(dev, port, &devres);
448 	if ((devres & enable) != enable)
449 		return;
450 	base = devres & 0xffff0000;
451 	mask = (devres & 0x3f) << 16;
452 	size = 128 << 16;
453 	for (;;) {
454 		unsigned bit = size >> 1;
455 		if ((bit & mask) == bit)
456 			break;
457 		size = bit;
458 	}
459 	/*
460 	 * For now we only print it out. Eventually we'll want to
461 	 * reserve it, but let's get enough confirmation reports first.
462 	 */
463 	base &= -size;
464 	dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
465 }
466 
467 /*
468  * PIIX4 ACPI: Two IO regions pointed to by longwords at
469  *	0x40 (64 bytes of ACPI registers)
470  *	0x90 (16 bytes of SMB registers)
471  * and a few strange programmable PIIX4 device resources.
472  */
473 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
474 {
475 	u32 region, res_a;
476 
477 	pci_read_config_dword(dev, 0x40, &region);
478 	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
479 	pci_read_config_dword(dev, 0x90, &region);
480 	quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
481 
482 	/* Device resource A has enables for some of the other ones */
483 	pci_read_config_dword(dev, 0x5c, &res_a);
484 
485 	piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
486 	piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
487 
488 	/* Device resource D is just bitfields for static resources */
489 
490 	/* Device 12 enabled? */
491 	if (res_a & (1 << 29)) {
492 		piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
493 		piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
494 	}
495 	/* Device 13 enabled? */
496 	if (res_a & (1 << 30)) {
497 		piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
498 		piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
499 	}
500 	piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
501 	piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
502 }
503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_3,	quirk_piix4_acpi);
504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443MX_3,	quirk_piix4_acpi);
505 
506 /*
507  * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
508  *	0x40 (128 bytes of ACPI, GPIO & TCO registers)
509  *	0x58 (64 bytes of GPIO I/O space)
510  */
511 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
512 {
513 	u32 region;
514 
515 	pci_read_config_dword(dev, 0x40, &region);
516 	quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
517 
518 	pci_read_config_dword(dev, 0x58, &region);
519 	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
520 }
521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,		quirk_ich4_lpc_acpi);
522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,		quirk_ich4_lpc_acpi);
523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,		quirk_ich4_lpc_acpi);
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,	quirk_ich4_lpc_acpi);
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,		quirk_ich4_lpc_acpi);
526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,	quirk_ich4_lpc_acpi);
527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,		quirk_ich4_lpc_acpi);
528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,	quirk_ich4_lpc_acpi);
529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi);
530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi);
531 
532 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
533 {
534 	u32 region;
535 
536 	pci_read_config_dword(dev, 0x40, &region);
537 	quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
538 
539 	pci_read_config_dword(dev, 0x48, &region);
540 	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
541 }
542 
543 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
544 {
545 	u32 val;
546 	u32 size, base;
547 
548 	pci_read_config_dword(dev, reg, &val);
549 
550 	/* Enabled? */
551 	if (!(val & 1))
552 		return;
553 	base = val & 0xfffc;
554 	if (dynsize) {
555 		/*
556 		 * This is not correct. It is 16, 32 or 64 bytes depending on
557 		 * register D31:F0:ADh bits 5:4.
558 		 *
559 		 * But this gets us at least _part_ of it.
560 		 */
561 		size = 16;
562 	} else {
563 		size = 128;
564 	}
565 	base &= ~(size-1);
566 
567 	/* Just print it out for now. We should reserve it after more debugging */
568 	dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
569 }
570 
571 static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
572 {
573 	/* Shared ACPI/GPIO decode with all ICH6+ */
574 	ich6_lpc_acpi_gpio(dev);
575 
576 	/* ICH6-specific generic IO decode */
577 	ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
578 	ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
579 }
580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
582 
583 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
584 {
585 	u32 val;
586 	u32 mask, base;
587 
588 	pci_read_config_dword(dev, reg, &val);
589 
590 	/* Enabled? */
591 	if (!(val & 1))
592 		return;
593 
594 	/*
595 	 * IO base in bits 15:2, mask in bits 23:18, both
596 	 * are dword-based
597 	 */
598 	base = val & 0xfffc;
599 	mask = (val >> 16) & 0xfc;
600 	mask |= 3;
601 
602 	/* Just print it out for now. We should reserve it after more debugging */
603 	dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
604 }
605 
606 /* ICH7-10 has the same common LPC generic IO decode registers */
607 static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
608 {
609 	/* We share the common ACPI/DPIO decode with ICH6 */
610 	ich6_lpc_acpi_gpio(dev);
611 
612 	/* And have 4 ICH7+ generic decodes */
613 	ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
614 	ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
615 	ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
616 	ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
617 }
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
631 
632 /*
633  * VIA ACPI: One IO region pointed to by longword at
634  *	0x48 or 0x20 (256 bytes of ACPI registers)
635  */
636 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
637 {
638 	u32 region;
639 
640 	if (dev->revision & 0x10) {
641 		pci_read_config_dword(dev, 0x48, &region);
642 		region &= PCI_BASE_ADDRESS_IO_MASK;
643 		quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
644 	}
645 }
646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_vt82c586_acpi);
647 
648 /*
649  * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
650  *	0x48 (256 bytes of ACPI registers)
651  *	0x70 (128 bytes of hardware monitoring register)
652  *	0x90 (16 bytes of SMB registers)
653  */
654 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
655 {
656 	u16 hm;
657 	u32 smb;
658 
659 	quirk_vt82c586_acpi(dev);
660 
661 	pci_read_config_word(dev, 0x70, &hm);
662 	hm &= PCI_BASE_ADDRESS_IO_MASK;
663 	quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
664 
665 	pci_read_config_dword(dev, 0x90, &smb);
666 	smb &= PCI_BASE_ADDRESS_IO_MASK;
667 	quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
668 }
669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi);
670 
671 /*
672  * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
673  *	0x88 (128 bytes of power management registers)
674  *	0xd0 (16 bytes of SMB registers)
675  */
676 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
677 {
678 	u16 pm, smb;
679 
680 	pci_read_config_word(dev, 0x88, &pm);
681 	pm &= PCI_BASE_ADDRESS_IO_MASK;
682 	quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
683 
684 	pci_read_config_word(dev, 0xd0, &smb);
685 	smb &= PCI_BASE_ADDRESS_IO_MASK;
686 	quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
687 }
688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);
689 
690 /*
691  * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
692  *	Disable fast back-to-back on the secondary bus segment
693  */
694 static void __devinit quirk_xio2000a(struct pci_dev *dev)
695 {
696 	struct pci_dev *pdev;
697 	u16 command;
698 
699 	dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
700 		"secondary bus fast back-to-back transfers disabled\n");
701 	list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
702 		pci_read_config_word(pdev, PCI_COMMAND, &command);
703 		if (command & PCI_COMMAND_FAST_BACK)
704 			pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
705 	}
706 }
707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
708 			quirk_xio2000a);
709 
710 #ifdef CONFIG_X86_IO_APIC
711 
712 #include <asm/io_apic.h>
713 
714 /*
715  * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
716  * devices to the external APIC.
717  *
718  * TODO: When we have device-specific interrupt routers,
719  * this code will go away from quirks.
720  */
721 static void quirk_via_ioapic(struct pci_dev *dev)
722 {
723 	u8 tmp;
724 
725 	if (nr_ioapics < 1)
726 		tmp = 0;    /* nothing routed to external APIC */
727 	else
728 		tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
729 
730 	dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
731 	       tmp == 0 ? "Disa" : "Ena");
732 
733 	/* Offset 0x58: External APIC IRQ output control */
734 	pci_write_config_byte (dev, 0x58, tmp);
735 }
736 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
737 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
738 
739 /*
740  * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
741  * This leads to doubled level interrupt rates.
742  * Set this bit to get rid of cycle wastage.
743  * Otherwise uncritical.
744  */
745 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
746 {
747 	u8 misc_control2;
748 #define BYPASS_APIC_DEASSERT 8
749 
750 	pci_read_config_byte(dev, 0x5B, &misc_control2);
751 	if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
752 		dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
753 		pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
754 	}
755 }
756 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
757 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
758 
759 /*
760  * The AMD io apic can hang the box when an apic irq is masked.
761  * We check all revs >= B0 (yet not in the pre production!) as the bug
762  * is currently marked NoFix
763  *
764  * We have multiple reports of hangs with this chipset that went away with
765  * noapic specified. For the moment we assume it's the erratum. We may be wrong
766  * of course. However the advice is demonstrably good even if so..
767  */
768 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
769 {
770 	if (dev->revision >= 0x02) {
771 		dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
772 		dev_warn(&dev->dev, "        : booting with the \"noapic\" option\n");
773 	}
774 }
775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);
776 
777 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
778 {
779 	if (dev->devfn == 0 && dev->bus->number == 0)
780 		sis_apic_bug = 1;
781 }
782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_ANY_ID,			quirk_ioapic_rmw);
783 #endif /* CONFIG_X86_IO_APIC */
784 
785 /*
786  * Some settings of MMRBC can lead to data corruption so block changes.
787  * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
788  */
789 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
790 {
791 	if (dev->subordinate && dev->revision <= 0x12) {
792 		dev_info(&dev->dev, "AMD8131 rev %x detected; "
793 			"disabling PCI-X MMRBC\n", dev->revision);
794 		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
795 	}
796 }
797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
798 
799 /*
800  * FIXME: it is questionable that quirk_via_acpi
801  * is needed.  It shows up as an ISA bridge, and does not
802  * support the PCI_INTERRUPT_LINE register at all.  Therefore
803  * it seems like setting the pci_dev's 'irq' to the
804  * value of the ACPI SCI interrupt is only done for convenience.
805  *	-jgarzik
806  */
807 static void __devinit quirk_via_acpi(struct pci_dev *d)
808 {
809 	/*
810 	 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
811 	 */
812 	u8 irq;
813 	pci_read_config_byte(d, 0x42, &irq);
814 	irq &= 0xf;
815 	if (irq && (irq != 2))
816 		d->irq = irq;
817 }
818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi);
819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi);
820 
821 
822 /*
823  *	VIA bridges which have VLink
824  */
825 
826 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
827 
828 static void quirk_via_bridge(struct pci_dev *dev)
829 {
830 	/* See what bridge we have and find the device ranges */
831 	switch (dev->device) {
832 	case PCI_DEVICE_ID_VIA_82C686:
833 		/* The VT82C686 is special, it attaches to PCI and can have
834 		   any device number. All its subdevices are functions of
835 		   that single device. */
836 		via_vlink_dev_lo = PCI_SLOT(dev->devfn);
837 		via_vlink_dev_hi = PCI_SLOT(dev->devfn);
838 		break;
839 	case PCI_DEVICE_ID_VIA_8237:
840 	case PCI_DEVICE_ID_VIA_8237A:
841 		via_vlink_dev_lo = 15;
842 		break;
843 	case PCI_DEVICE_ID_VIA_8235:
844 		via_vlink_dev_lo = 16;
845 		break;
846 	case PCI_DEVICE_ID_VIA_8231:
847 	case PCI_DEVICE_ID_VIA_8233_0:
848 	case PCI_DEVICE_ID_VIA_8233A:
849 	case PCI_DEVICE_ID_VIA_8233C_0:
850 		via_vlink_dev_lo = 17;
851 		break;
852 	}
853 }
854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_bridge);
855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8231,		quirk_via_bridge);
856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233_0,	quirk_via_bridge);
857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233A,	quirk_via_bridge);
858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233C_0,	quirk_via_bridge);
859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,		quirk_via_bridge);
860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_bridge);
861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237A,	quirk_via_bridge);
862 
863 /**
864  *	quirk_via_vlink		-	VIA VLink IRQ number update
865  *	@dev: PCI device
866  *
867  *	If the device we are dealing with is on a PIC IRQ we need to
868  *	ensure that the IRQ line register which usually is not relevant
869  *	for PCI cards, is actually written so that interrupts get sent
870  *	to the right place.
871  *	We only do this on systems where a VIA south bridge was detected,
872  *	and only for VIA devices on the motherboard (see quirk_via_bridge
873  *	above).
874  */
875 
876 static void quirk_via_vlink(struct pci_dev *dev)
877 {
878 	u8 irq, new_irq;
879 
880 	/* Check if we have VLink at all */
881 	if (via_vlink_dev_lo == -1)
882 		return;
883 
884 	new_irq = dev->irq;
885 
886 	/* Don't quirk interrupts outside the legacy IRQ range */
887 	if (!new_irq || new_irq > 15)
888 		return;
889 
890 	/* Internal device ? */
891 	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
892 	    PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
893 		return;
894 
895 	/* This is an internal VLink device on a PIC interrupt. The BIOS
896 	   ought to have set this but may not have, so we redo it */
897 
898 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
899 	if (new_irq != irq) {
900 		dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
901 			irq, new_irq);
902 		udelay(15);	/* unknown if delay really needed */
903 		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
904 	}
905 }
906 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
907 
908 /*
909  * VIA VT82C598 has its device ID settable and many BIOSes
910  * set it to the ID of VT82C597 for backward compatibility.
911  * We need to switch it off to be able to recognize the real
912  * type of the chip.
913  */
914 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
915 {
916 	pci_write_config_byte(dev, 0xfc, 0);
917 	pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
918 }
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_vt82c598_id);
920 
921 /*
922  * CardBus controllers have a legacy base address that enables them
923  * to respond as i82365 pcmcia controllers.  We don't want them to
924  * do this even if the Linux CardBus driver is not loaded, because
925  * the Linux i82365 driver does not (and should not) handle CardBus.
926  */
927 static void quirk_cardbus_legacy(struct pci_dev *dev)
928 {
929 	if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
930 		return;
931 	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
932 }
933 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
934 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
935 
936 /*
937  * Following the PCI ordering rules is optional on the AMD762. I'm not
938  * sure what the designers were smoking but let's not inhale...
939  *
940  * To be fair to AMD, it follows the spec by default, its BIOS people
941  * who turn it off!
942  */
943 static void quirk_amd_ordering(struct pci_dev *dev)
944 {
945 	u32 pcic;
946 	pci_read_config_dword(dev, 0x4C, &pcic);
947 	if ((pcic&6)!=6) {
948 		pcic |= 6;
949 		dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
950 		pci_write_config_dword(dev, 0x4C, pcic);
951 		pci_read_config_dword(dev, 0x84, &pcic);
952 		pcic |= (1<<23);	/* Required in this mode */
953 		pci_write_config_dword(dev, 0x84, pcic);
954 	}
955 }
956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
957 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
958 
959 /*
960  *	DreamWorks provided workaround for Dunord I-3000 problem
961  *
962  *	This card decodes and responds to addresses not apparently
963  *	assigned to it. We force a larger allocation to ensure that
964  *	nothing gets put too close to it.
965  */
966 static void __devinit quirk_dunord ( struct pci_dev * dev )
967 {
968 	struct resource *r = &dev->resource [1];
969 	r->start = 0;
970 	r->end = 0xffffff;
971 }
972 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,	PCI_DEVICE_ID_DUNORD_I3000,	quirk_dunord);
973 
974 /*
975  * i82380FB mobile docking controller: its PCI-to-PCI bridge
976  * is subtractive decoding (transparent), and does indicate this
977  * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
978  * instead of 0x01.
979  */
980 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
981 {
982 	dev->transparent = 1;
983 }
984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82380FB,	quirk_transparent_bridge);
985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA,	0x605,	quirk_transparent_bridge);
986 
987 /*
988  * Common misconfiguration of the MediaGX/Geode PCI master that will
989  * reduce PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1
990  * datasheets found at http://www.national.com/ds/GX for info on what
991  * these bits do.  <christer@weinigel.se>
992  */
993 static void quirk_mediagx_master(struct pci_dev *dev)
994 {
995 	u8 reg;
996 	pci_read_config_byte(dev, 0x41, &reg);
997 	if (reg & 2) {
998 		reg &= ~2;
999 		dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1000                 pci_write_config_byte(dev, 0x41, reg);
1001 	}
1002 }
1003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1004 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1005 
1006 /*
1007  *	Ensure C0 rev restreaming is off. This is normally done by
1008  *	the BIOS but in the odd case it is not the results are corruption
1009  *	hence the presence of a Linux check
1010  */
1011 static void quirk_disable_pxb(struct pci_dev *pdev)
1012 {
1013 	u16 config;
1014 
1015 	if (pdev->revision != 0x04)		/* Only C0 requires this */
1016 		return;
1017 	pci_read_config_word(pdev, 0x40, &config);
1018 	if (config & (1<<6)) {
1019 		config &= ~(1<<6);
1020 		pci_write_config_word(pdev, 0x40, config);
1021 		dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1022 	}
1023 }
1024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
1025 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
1026 
1027 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1028 {
1029 	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1030 	u8 tmp;
1031 
1032 	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1033 	if (tmp == 0x01) {
1034 		pci_read_config_byte(pdev, 0x40, &tmp);
1035 		pci_write_config_byte(pdev, 0x40, tmp|1);
1036 		pci_write_config_byte(pdev, 0x9, 1);
1037 		pci_write_config_byte(pdev, 0xa, 6);
1038 		pci_write_config_byte(pdev, 0x40, tmp);
1039 
1040 		pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1041 		dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1042 	}
1043 }
1044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1045 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1047 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1049 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1050 
1051 /*
1052  *	Serverworks CSB5 IDE does not fully support native mode
1053  */
1054 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1055 {
1056 	u8 prog;
1057 	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1058 	if (prog & 5) {
1059 		prog &= ~5;
1060 		pdev->class &= ~5;
1061 		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1062 		/* PCI layer will sort out resources */
1063 	}
1064 }
1065 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1066 
1067 /*
1068  *	Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1069  */
1070 static void __init quirk_ide_samemode(struct pci_dev *pdev)
1071 {
1072 	u8 prog;
1073 
1074 	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1075 
1076 	if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1077 		dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1078 		prog &= ~5;
1079 		pdev->class &= ~5;
1080 		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1081 	}
1082 }
1083 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1084 
1085 /*
1086  * Some ATA devices break if put into D3
1087  */
1088 
1089 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1090 {
1091 	/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1092 	if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1093 		pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1094 }
1095 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1096 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1097 /* ALi loses some register settings that we cannot then restore */
1098 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1099 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1100    occur when mode detecting */
1101 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1102 
1103 /* This was originally an Alpha specific thing, but it really fits here.
1104  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1105  */
1106 static void __init quirk_eisa_bridge(struct pci_dev *dev)
1107 {
1108 	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1109 }
1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82375,	quirk_eisa_bridge);
1111 
1112 
1113 /*
1114  * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1115  * is not activated. The myth is that Asus said that they do not want the
1116  * users to be irritated by just another PCI Device in the Win98 device
1117  * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1118  * package 2.7.0 for details)
1119  *
1120  * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1121  * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1122  * becomes necessary to do this tweak in two steps -- the chosen trigger
1123  * is either the Host bridge (preferred) or on-board VGA controller.
1124  *
1125  * Note that we used to unhide the SMBus that way on Toshiba laptops
1126  * (Satellite A40 and Tecra M2) but then found that the thermal management
1127  * was done by SMM code, which could cause unsynchronized concurrent
1128  * accesses to the SMBus registers, with potentially bad effects. Thus you
1129  * should be very careful when adding new entries: if SMM is accessing the
1130  * Intel SMBus, this is a very good reason to leave it hidden.
1131  *
1132  * Likewise, many recent laptops use ACPI for thermal management. If the
1133  * ACPI DSDT code accesses the SMBus, then Linux should not access it
1134  * natively, and keeping the SMBus hidden is the right thing to do. If you
1135  * are about to add an entry in the table below, please first disassemble
1136  * the DSDT and double-check that there is no code accessing the SMBus.
1137  */
1138 static int asus_hides_smbus;
1139 
1140 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1141 {
1142 	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1143 		if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1144 			switch(dev->subsystem_device) {
1145 			case 0x8025: /* P4B-LX */
1146 			case 0x8070: /* P4B */
1147 			case 0x8088: /* P4B533 */
1148 			case 0x1626: /* L3C notebook */
1149 				asus_hides_smbus = 1;
1150 			}
1151 		else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1152 			switch(dev->subsystem_device) {
1153 			case 0x80b1: /* P4GE-V */
1154 			case 0x80b2: /* P4PE */
1155 			case 0x8093: /* P4B533-V */
1156 				asus_hides_smbus = 1;
1157 			}
1158 		else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1159 			switch(dev->subsystem_device) {
1160 			case 0x8030: /* P4T533 */
1161 				asus_hides_smbus = 1;
1162 			}
1163 		else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1164 			switch (dev->subsystem_device) {
1165 			case 0x8070: /* P4G8X Deluxe */
1166 				asus_hides_smbus = 1;
1167 			}
1168 		else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1169 			switch (dev->subsystem_device) {
1170 			case 0x80c9: /* PU-DLS */
1171 				asus_hides_smbus = 1;
1172 			}
1173 		else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1174 			switch (dev->subsystem_device) {
1175 			case 0x1751: /* M2N notebook */
1176 			case 0x1821: /* M5N notebook */
1177 			case 0x1897: /* A6L notebook */
1178 				asus_hides_smbus = 1;
1179 			}
1180 		else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1181 			switch (dev->subsystem_device) {
1182 			case 0x184b: /* W1N notebook */
1183 			case 0x186a: /* M6Ne notebook */
1184 				asus_hides_smbus = 1;
1185 			}
1186 		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1187 			switch (dev->subsystem_device) {
1188 			case 0x80f2: /* P4P800-X */
1189 				asus_hides_smbus = 1;
1190 			}
1191 		else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1192 			switch (dev->subsystem_device) {
1193 			case 0x1882: /* M6V notebook */
1194 			case 0x1977: /* A6VA notebook */
1195 				asus_hides_smbus = 1;
1196 			}
1197 	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1198 		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1199 			switch(dev->subsystem_device) {
1200 			case 0x088C: /* HP Compaq nc8000 */
1201 			case 0x0890: /* HP Compaq nc6000 */
1202 				asus_hides_smbus = 1;
1203 			}
1204 		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1205 			switch (dev->subsystem_device) {
1206 			case 0x12bc: /* HP D330L */
1207 			case 0x12bd: /* HP D530 */
1208 			case 0x006a: /* HP Compaq nx9500 */
1209 				asus_hides_smbus = 1;
1210 			}
1211 		else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1212 			switch (dev->subsystem_device) {
1213 			case 0x12bf: /* HP xw4100 */
1214 				asus_hides_smbus = 1;
1215 			}
1216        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1217                if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1218                        switch(dev->subsystem_device) {
1219                        case 0xC00C: /* Samsung P35 notebook */
1220                                asus_hides_smbus = 1;
1221                        }
1222 	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1223 		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1224 			switch(dev->subsystem_device) {
1225 			case 0x0058: /* Compaq Evo N620c */
1226 				asus_hides_smbus = 1;
1227 			}
1228 		else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1229 			switch(dev->subsystem_device) {
1230 			case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1231 				/* Motherboard doesn't have Host bridge
1232 				 * subvendor/subdevice IDs, therefore checking
1233 				 * its on-board VGA controller */
1234 				asus_hides_smbus = 1;
1235 			}
1236 		else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1237 			switch(dev->subsystem_device) {
1238 			case 0x00b8: /* Compaq Evo D510 CMT */
1239 			case 0x00b9: /* Compaq Evo D510 SFF */
1240 			case 0x00ba: /* Compaq Evo D510 USDT */
1241 				/* Motherboard doesn't have Host bridge
1242 				 * subvendor/subdevice IDs and on-board VGA
1243 				 * controller is disabled if an AGP card is
1244 				 * inserted, therefore checking USB UHCI
1245 				 * Controller #1 */
1246 				asus_hides_smbus = 1;
1247 			}
1248 		else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1249 			switch (dev->subsystem_device) {
1250 			case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1251 				/* Motherboard doesn't have host bridge
1252 				 * subvendor/subdevice IDs, therefore checking
1253 				 * its on-board VGA controller */
1254 				asus_hides_smbus = 1;
1255 			}
1256 	}
1257 }
1258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845_HB,	asus_hides_smbus_hostbridge);
1259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845G_HB,	asus_hides_smbus_hostbridge);
1260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82850_HB,	asus_hides_smbus_hostbridge);
1261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82865_HB,	asus_hides_smbus_hostbridge);
1262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82875_HB,	asus_hides_smbus_hostbridge);
1263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_7205_0,	asus_hides_smbus_hostbridge);
1264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7501_MCH,	asus_hides_smbus_hostbridge);
1265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855PM_HB,	asus_hides_smbus_hostbridge);
1266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge);
1267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1268 
1269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82810_IG3,	asus_hides_smbus_hostbridge);
1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_2,	asus_hides_smbus_hostbridge);
1271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82815_CGC,	asus_hides_smbus_hostbridge);
1272 
1273 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1274 {
1275 	u16 val;
1276 
1277 	if (likely(!asus_hides_smbus))
1278 		return;
1279 
1280 	pci_read_config_word(dev, 0xF2, &val);
1281 	if (val & 0x8) {
1282 		pci_write_config_word(dev, 0xF2, val & (~0x8));
1283 		pci_read_config_word(dev, 0xF2, &val);
1284 		if (val & 0x8)
1285 			dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1286 		else
1287 			dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1288 	}
1289 }
1290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
1291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
1292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
1293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
1294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
1295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
1296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
1297 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
1298 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
1300 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
1301 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
1302 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
1304 
1305 /* It appears we just have one such device. If not, we have a warning */
1306 static void __iomem *asus_rcba_base;
1307 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1308 {
1309 	u32 rcba;
1310 
1311 	if (likely(!asus_hides_smbus))
1312 		return;
1313 	WARN_ON(asus_rcba_base);
1314 
1315 	pci_read_config_dword(dev, 0xF0, &rcba);
1316 	/* use bits 31:14, 16 kB aligned */
1317 	asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1318 	if (asus_rcba_base == NULL)
1319 		return;
1320 }
1321 
1322 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1323 {
1324 	u32 val;
1325 
1326 	if (likely(!asus_hides_smbus || !asus_rcba_base))
1327 		return;
1328 	/* read the Function Disable register, dword mode only */
1329 	val = readl(asus_rcba_base + 0x3418);
1330 	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1331 }
1332 
1333 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1334 {
1335 	if (likely(!asus_hides_smbus || !asus_rcba_base))
1336 		return;
1337 	iounmap(asus_rcba_base);
1338 	asus_rcba_base = NULL;
1339 	dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1340 }
1341 
1342 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1343 {
1344 	asus_hides_smbus_lpc_ich6_suspend(dev);
1345 	asus_hides_smbus_lpc_ich6_resume_early(dev);
1346 	asus_hides_smbus_lpc_ich6_resume(dev);
1347 }
1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6);
1349 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_suspend);
1350 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume);
1351 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume_early);
1352 
1353 /*
1354  * SiS 96x south bridge: BIOS typically hides SMBus device...
1355  */
1356 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1357 {
1358 	u8 val = 0;
1359 	pci_read_config_byte(dev, 0x77, &val);
1360 	if (val & 0x10) {
1361 		dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1362 		pci_write_config_byte(dev, 0x77, val & ~0x10);
1363 	}
1364 }
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
1369 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
1373 
1374 /*
1375  * ... This is further complicated by the fact that some SiS96x south
1376  * bridges pretend to be 85C503/5513 instead.  In that case see if we
1377  * spotted a compatible north bridge to make sure.
1378  * (pci_find_device doesn't work yet)
1379  *
1380  * We can also enable the sis96x bit in the discovery register..
1381  */
1382 #define SIS_DETECT_REGISTER 0x40
1383 
1384 static void quirk_sis_503(struct pci_dev *dev)
1385 {
1386 	u8 reg;
1387 	u16 devid;
1388 
1389 	pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1390 	pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1391 	pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1392 	if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1393 		pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1394 		return;
1395 	}
1396 
1397 	/*
1398 	 * Ok, it now shows up as a 96x.. run the 96x quirk by
1399 	 * hand in case it has already been processed.
1400 	 * (depends on link order, which is apparently not guaranteed)
1401 	 */
1402 	dev->device = devid;
1403 	quirk_sis_96x_smbus(dev);
1404 }
1405 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
1406 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
1407 
1408 
1409 /*
1410  * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1411  * and MC97 modem controller are disabled when a second PCI soundcard is
1412  * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1413  * -- bjd
1414  */
1415 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1416 {
1417 	u8 val;
1418 	int asus_hides_ac97 = 0;
1419 
1420 	if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1421 		if (dev->device == PCI_DEVICE_ID_VIA_8237)
1422 			asus_hides_ac97 = 1;
1423 	}
1424 
1425 	if (!asus_hides_ac97)
1426 		return;
1427 
1428 	pci_read_config_byte(dev, 0x50, &val);
1429 	if (val & 0xc0) {
1430 		pci_write_config_byte(dev, 0x50, val & (~0xc0));
1431 		pci_read_config_byte(dev, 0x50, &val);
1432 		if (val & 0xc0)
1433 			dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1434 		else
1435 			dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1436 	}
1437 }
1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1439 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1440 
1441 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1442 
1443 /*
1444  *	If we are using libata we can drive this chip properly but must
1445  *	do this early on to make the additional device appear during
1446  *	the PCI scanning.
1447  */
1448 static void quirk_jmicron_ata(struct pci_dev *pdev)
1449 {
1450 	u32 conf1, conf5, class;
1451 	u8 hdr;
1452 
1453 	/* Only poke fn 0 */
1454 	if (PCI_FUNC(pdev->devfn))
1455 		return;
1456 
1457 	pci_read_config_dword(pdev, 0x40, &conf1);
1458 	pci_read_config_dword(pdev, 0x80, &conf5);
1459 
1460 	conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1461 	conf5 &= ~(1 << 24);  /* Clear bit 24 */
1462 
1463 	switch (pdev->device) {
1464 	case PCI_DEVICE_ID_JMICRON_JMB360:
1465 		/* The controller should be in single function ahci mode */
1466 		conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1467 		break;
1468 
1469 	case PCI_DEVICE_ID_JMICRON_JMB365:
1470 	case PCI_DEVICE_ID_JMICRON_JMB366:
1471 		/* Redirect IDE second PATA port to the right spot */
1472 		conf5 |= (1 << 24);
1473 		/* Fall through */
1474 	case PCI_DEVICE_ID_JMICRON_JMB361:
1475 	case PCI_DEVICE_ID_JMICRON_JMB363:
1476 		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1477 		/* Set the class codes correctly and then direct IDE 0 */
1478 		conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1479 		break;
1480 
1481 	case PCI_DEVICE_ID_JMICRON_JMB368:
1482 		/* The controller should be in single function IDE mode */
1483 		conf1 |= 0x00C00000; /* Set 22, 23 */
1484 		break;
1485 	}
1486 
1487 	pci_write_config_dword(pdev, 0x40, conf1);
1488 	pci_write_config_dword(pdev, 0x80, conf5);
1489 
1490 	/* Update pdev accordingly */
1491 	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1492 	pdev->hdr_type = hdr & 0x7f;
1493 	pdev->multifunction = !!(hdr & 0x80);
1494 
1495 	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1496 	pdev->class = class >> 8;
1497 }
1498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1500 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1502 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1503 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1504 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1505 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1506 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1507 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1508 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1509 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1510 
1511 #endif
1512 
1513 #ifdef CONFIG_X86_IO_APIC
1514 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1515 {
1516 	int i;
1517 
1518 	if ((pdev->class >> 8) != 0xff00)
1519 		return;
1520 
1521 	/* the first BAR is the location of the IO APIC...we must
1522 	 * not touch this (and it's already covered by the fixmap), so
1523 	 * forcibly insert it into the resource tree */
1524 	if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1525 		insert_resource(&iomem_resource, &pdev->resource[0]);
1526 
1527 	/* The next five BARs all seem to be rubbish, so just clean
1528 	 * them out */
1529 	for (i=1; i < 6; i++) {
1530 		memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1531 	}
1532 
1533 }
1534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_EESSC,	quirk_alder_ioapic);
1535 #endif
1536 
1537 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1538 {
1539 	pci_msi_off(pdev);
1540 	pdev->no_msi = 1;
1541 }
1542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7520_MCH,	quirk_pcie_mch);
1543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7320_MCH,	quirk_pcie_mch);
1544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7525_MCH,	quirk_pcie_mch);
1545 
1546 
1547 /*
1548  * It's possible for the MSI to get corrupted if shpc and acpi
1549  * are used together on certain PXH-based systems.
1550  */
1551 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1552 {
1553 	pci_msi_off(dev);
1554 	dev->no_msi = 1;
1555 	dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1556 }
1557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_0,	quirk_pcie_pxh);
1558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_1,	quirk_pcie_pxh);
1559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_pcie_pxh);
1560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_pcie_pxh);
1561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_pcie_pxh);
1562 
1563 /*
1564  * Some Intel PCI Express chipsets have trouble with downstream
1565  * device power management.
1566  */
1567 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1568 {
1569 	pci_pm_d3_delay = 120;
1570 	dev->no_d1d2 = 1;
1571 }
1572 
1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e2, quirk_intel_pcie_pm);
1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e3, quirk_intel_pcie_pm);
1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e4, quirk_intel_pcie_pm);
1576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e5, quirk_intel_pcie_pm);
1577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e6, quirk_intel_pcie_pm);
1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e7, quirk_intel_pcie_pm);
1579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f7, quirk_intel_pcie_pm);
1580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f8, quirk_intel_pcie_pm);
1581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f9, quirk_intel_pcie_pm);
1582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25fa, quirk_intel_pcie_pm);
1583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2601, quirk_intel_pcie_pm);
1584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2602, quirk_intel_pcie_pm);
1585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2603, quirk_intel_pcie_pm);
1586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2604, quirk_intel_pcie_pm);
1587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2605, quirk_intel_pcie_pm);
1588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2606, quirk_intel_pcie_pm);
1589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2607, quirk_intel_pcie_pm);
1590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2608, quirk_intel_pcie_pm);
1591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
1592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);
1593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);
1594 
1595 #ifdef CONFIG_X86_IO_APIC
1596 /*
1597  * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1598  * remap the original interrupt in the linux kernel to the boot interrupt, so
1599  * that a PCI device's interrupt handler is installed on the boot interrupt
1600  * line instead.
1601  */
1602 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1603 {
1604 	if (noioapicquirk || noioapicreroute)
1605 		return;
1606 
1607 	dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1608 	dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1609 		 dev->vendor, dev->device);
1610 }
1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
1614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
1615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
1616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
1617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
1618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
1619 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
1620 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
1621 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
1622 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
1623 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
1624 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
1625 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
1626 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
1627 
1628 /*
1629  * On some chipsets we can disable the generation of legacy INTx boot
1630  * interrupts.
1631  */
1632 
1633 /*
1634  * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1635  * 300641-004US, section 5.7.3.
1636  */
1637 #define INTEL_6300_IOAPIC_ABAR		0x40
1638 #define INTEL_6300_DISABLE_BOOT_IRQ	(1<<14)
1639 
1640 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1641 {
1642 	u16 pci_config_word;
1643 
1644 	if (noioapicquirk)
1645 		return;
1646 
1647 	pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1648 	pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1649 	pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1650 
1651 	dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1652 		 dev->vendor, dev->device);
1653 }
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10, 	quirk_disable_intel_boot_interrupt);
1655 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10, 	quirk_disable_intel_boot_interrupt);
1656 
1657 /*
1658  * disable boot interrupts on HT-1000
1659  */
1660 #define BC_HT1000_FEATURE_REG		0x64
1661 #define BC_HT1000_PIC_REGS_ENABLE	(1<<0)
1662 #define BC_HT1000_MAP_IDX		0xC00
1663 #define BC_HT1000_MAP_DATA		0xC01
1664 
1665 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1666 {
1667 	u32 pci_config_dword;
1668 	u8 irq;
1669 
1670 	if (noioapicquirk)
1671 		return;
1672 
1673 	pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1674 	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1675 			BC_HT1000_PIC_REGS_ENABLE);
1676 
1677 	for (irq = 0x10; irq < 0x10 + 32; irq++) {
1678 		outb(irq, BC_HT1000_MAP_IDX);
1679 		outb(0x00, BC_HT1000_MAP_DATA);
1680 	}
1681 
1682 	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1683 
1684 	dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1685 		 dev->vendor, dev->device);
1686 }
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB, 	quirk_disable_broadcom_boot_interrupt);
1688 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB, 	quirk_disable_broadcom_boot_interrupt);
1689 
1690 /*
1691  * disable boot interrupts on AMD and ATI chipsets
1692  */
1693 /*
1694  * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1695  * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1696  * (due to an erratum).
1697  */
1698 #define AMD_813X_MISC			0x40
1699 #define AMD_813X_NOIOAMODE		(1<<0)
1700 #define AMD_813X_REV_B1			0x12
1701 #define AMD_813X_REV_B2			0x13
1702 
1703 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1704 {
1705 	u32 pci_config_dword;
1706 
1707 	if (noioapicquirk)
1708 		return;
1709 	if ((dev->revision == AMD_813X_REV_B1) ||
1710 	    (dev->revision == AMD_813X_REV_B2))
1711 		return;
1712 
1713 	pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1714 	pci_config_dword &= ~AMD_813X_NOIOAMODE;
1715 	pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1716 
1717 	dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1718 		 dev->vendor, dev->device);
1719 }
1720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
1721 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
1722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
1723 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
1724 
1725 #define AMD_8111_PCI_IRQ_ROUTING	0x56
1726 
1727 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1728 {
1729 	u16 pci_config_word;
1730 
1731 	if (noioapicquirk)
1732 		return;
1733 
1734 	pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1735 	if (!pci_config_word) {
1736 		dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1737 			 "already disabled\n", dev->vendor, dev->device);
1738 		return;
1739 	}
1740 	pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1741 	dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1742 		 dev->vendor, dev->device);
1743 }
1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS, 	quirk_disable_amd_8111_boot_interrupt);
1745 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS, 	quirk_disable_amd_8111_boot_interrupt);
1746 #endif /* CONFIG_X86_IO_APIC */
1747 
1748 /*
1749  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1750  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1751  * Re-allocate the region if needed...
1752  */
1753 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1754 {
1755 	struct resource *r = &dev->resource[0];
1756 
1757 	if (r->start & 0x8) {
1758 		r->start = 0;
1759 		r->end = 0xf;
1760 	}
1761 }
1762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1763 			 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1764 			 quirk_tc86c001_ide);
1765 
1766 static void __devinit quirk_netmos(struct pci_dev *dev)
1767 {
1768 	unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1769 	unsigned int num_serial = dev->subsystem_device & 0xf;
1770 
1771 	/*
1772 	 * These Netmos parts are multiport serial devices with optional
1773 	 * parallel ports.  Even when parallel ports are present, they
1774 	 * are identified as class SERIAL, which means the serial driver
1775 	 * will claim them.  To prevent this, mark them as class OTHER.
1776 	 * These combo devices should be claimed by parport_serial.
1777 	 *
1778 	 * The subdevice ID is of the form 0x00PS, where <P> is the number
1779 	 * of parallel ports and <S> is the number of serial ports.
1780 	 */
1781 	switch (dev->device) {
1782 	case PCI_DEVICE_ID_NETMOS_9835:
1783 		/* Well, this rule doesn't hold for the following 9835 device */
1784 		if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1785 				dev->subsystem_device == 0x0299)
1786 			return;
1787 	case PCI_DEVICE_ID_NETMOS_9735:
1788 	case PCI_DEVICE_ID_NETMOS_9745:
1789 	case PCI_DEVICE_ID_NETMOS_9845:
1790 	case PCI_DEVICE_ID_NETMOS_9855:
1791 		if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1792 		    num_parallel) {
1793 			dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1794 				"%u serial); changing class SERIAL to OTHER "
1795 				"(use parport_serial)\n",
1796 				dev->device, num_parallel, num_serial);
1797 			dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1798 			    (dev->class & 0xff);
1799 		}
1800 	}
1801 }
1802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1803 
1804 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1805 {
1806 	u16 command, pmcsr;
1807 	u8 __iomem *csr;
1808 	u8 cmd_hi;
1809 	int pm;
1810 
1811 	switch (dev->device) {
1812 	/* PCI IDs taken from drivers/net/e100.c */
1813 	case 0x1029:
1814 	case 0x1030 ... 0x1034:
1815 	case 0x1038 ... 0x103E:
1816 	case 0x1050 ... 0x1057:
1817 	case 0x1059:
1818 	case 0x1064 ... 0x106B:
1819 	case 0x1091 ... 0x1095:
1820 	case 0x1209:
1821 	case 0x1229:
1822 	case 0x2449:
1823 	case 0x2459:
1824 	case 0x245D:
1825 	case 0x27DC:
1826 		break;
1827 	default:
1828 		return;
1829 	}
1830 
1831 	/*
1832 	 * Some firmware hands off the e100 with interrupts enabled,
1833 	 * which can cause a flood of interrupts if packets are
1834 	 * received before the driver attaches to the device.  So
1835 	 * disable all e100 interrupts here.  The driver will
1836 	 * re-enable them when it's ready.
1837 	 */
1838 	pci_read_config_word(dev, PCI_COMMAND, &command);
1839 
1840 	if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1841 		return;
1842 
1843 	/*
1844 	 * Check that the device is in the D0 power state. If it's not,
1845 	 * there is no point to look any further.
1846 	 */
1847 	pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1848 	if (pm) {
1849 		pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1850 		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1851 			return;
1852 	}
1853 
1854 	/* Convert from PCI bus to resource space.  */
1855 	csr = ioremap(pci_resource_start(dev, 0), 8);
1856 	if (!csr) {
1857 		dev_warn(&dev->dev, "Can't map e100 registers\n");
1858 		return;
1859 	}
1860 
1861 	cmd_hi = readb(csr + 3);
1862 	if (cmd_hi == 0) {
1863 		dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1864 			"disabling\n");
1865 		writeb(1, csr + 3);
1866 	}
1867 
1868 	iounmap(csr);
1869 }
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1871 
1872 /*
1873  * The 82575 and 82598 may experience data corruption issues when transitioning
1874  * out of L0S.  To prevent this we need to disable L0S on the pci-e link
1875  */
1876 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1877 {
1878 	dev_info(&dev->dev, "Disabling L0s\n");
1879 	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1880 }
1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1891 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1892 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1893 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1894 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1895 
1896 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1897 {
1898 	/* rev 1 ncr53c810 chips don't set the class at all which means
1899 	 * they don't get their resources remapped. Fix that here.
1900 	 */
1901 
1902 	if (dev->class == PCI_CLASS_NOT_DEFINED) {
1903 		dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1904 		dev->class = PCI_CLASS_STORAGE_SCSI;
1905 	}
1906 }
1907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1908 
1909 /* Enable 1k I/O space granularity on the Intel P64H2 */
1910 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1911 {
1912 	u16 en1k;
1913 	u8 io_base_lo, io_limit_lo;
1914 	unsigned long base, limit;
1915 	struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1916 
1917 	pci_read_config_word(dev, 0x40, &en1k);
1918 
1919 	if (en1k & 0x200) {
1920 		dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1921 
1922 		pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1923 		pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1924 		base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1925 		limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1926 
1927 		if (base <= limit) {
1928 			res->start = base;
1929 			res->end = limit + 0x3ff;
1930 		}
1931 	}
1932 }
1933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	0x1460,		quirk_p64h2_1k_io);
1934 
1935 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1936  * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1937  * in drivers/pci/setup-bus.c
1938  */
1939 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1940 {
1941 	u16 en1k, iobl_adr, iobl_adr_1k;
1942 	struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1943 
1944 	pci_read_config_word(dev, 0x40, &en1k);
1945 
1946 	if (en1k & 0x200) {
1947 		pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1948 
1949 		iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1950 
1951 		if (iobl_adr != iobl_adr_1k) {
1952 			dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1953 				iobl_adr,iobl_adr_1k);
1954 			pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1955 		}
1956 	}
1957 }
1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x1460,		quirk_p64h2_1k_io_fix_iobl);
1959 
1960 /* Under some circumstances, AER is not linked with extended capabilities.
1961  * Force it to be linked by setting the corresponding control bit in the
1962  * config space.
1963  */
1964 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1965 {
1966 	uint8_t b;
1967 	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1968 		if (!(b & 0x20)) {
1969 			pci_write_config_byte(dev, 0xf41, b | 0x20);
1970 			dev_info(&dev->dev,
1971 			       "Linking AER extended capability\n");
1972 		}
1973 	}
1974 }
1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1976 			quirk_nvidia_ck804_pcie_aer_ext_cap);
1977 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1978 			quirk_nvidia_ck804_pcie_aer_ext_cap);
1979 
1980 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1981 {
1982 	/*
1983 	 * Disable PCI Bus Parking and PCI Master read caching on CX700
1984 	 * which causes unspecified timing errors with a VT6212L on the PCI
1985 	 * bus leading to USB2.0 packet loss. The defaults are that these
1986 	 * features are turned off but some BIOSes turn them on.
1987 	 */
1988 
1989 	uint8_t b;
1990 	if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1991 		if (b & 0x40) {
1992 			/* Turn off PCI Bus Parking */
1993 			pci_write_config_byte(dev, 0x76, b ^ 0x40);
1994 
1995 			dev_info(&dev->dev,
1996 				"Disabling VIA CX700 PCI parking\n");
1997 		}
1998 	}
1999 
2000 	if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2001 		if (b != 0) {
2002 			/* Turn off PCI Master read caching */
2003 			pci_write_config_byte(dev, 0x72, 0x0);
2004 
2005 			/* Set PCI Master Bus time-out to "1x16 PCLK" */
2006 			pci_write_config_byte(dev, 0x75, 0x1);
2007 
2008 			/* Disable "Read FIFO Timer" */
2009 			pci_write_config_byte(dev, 0x77, 0x0);
2010 
2011 			dev_info(&dev->dev,
2012 				"Disabling VIA CX700 PCI caching\n");
2013 		}
2014 	}
2015 }
2016 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2017 
2018 /*
2019  * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2020  * VPD end tag will hang the device.  This problem was initially
2021  * observed when a vpd entry was created in sysfs
2022  * ('/sys/bus/pci/devices/<id>/vpd').   A read to this sysfs entry
2023  * will dump 32k of data.  Reading a full 32k will cause an access
2024  * beyond the VPD end tag causing the device to hang.  Once the device
2025  * is hung, the bnx2 driver will not be able to reset the device.
2026  * We believe that it is legal to read beyond the end tag and
2027  * therefore the solution is to limit the read/write length.
2028  */
2029 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2030 {
2031 	/*
2032 	 * Only disable the VPD capability for 5706, 5706S, 5708,
2033 	 * 5708S and 5709 rev. A
2034 	 */
2035 	if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2036 	    (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2037 	    (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2038 	    (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2039 	    ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2040 	     (dev->revision & 0xf0) == 0x0)) {
2041 		if (dev->vpd)
2042 			dev->vpd->len = 0x80;
2043 	}
2044 }
2045 
2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2047 			PCI_DEVICE_ID_NX2_5706,
2048 			quirk_brcm_570x_limit_vpd);
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2050 			PCI_DEVICE_ID_NX2_5706S,
2051 			quirk_brcm_570x_limit_vpd);
2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2053 			PCI_DEVICE_ID_NX2_5708,
2054 			quirk_brcm_570x_limit_vpd);
2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2056 			PCI_DEVICE_ID_NX2_5708S,
2057 			quirk_brcm_570x_limit_vpd);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2059 			PCI_DEVICE_ID_NX2_5709,
2060 			quirk_brcm_570x_limit_vpd);
2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2062 			PCI_DEVICE_ID_NX2_5709S,
2063 			quirk_brcm_570x_limit_vpd);
2064 
2065 /* Originally in EDAC sources for i82875P:
2066  * Intel tells BIOS developers to hide device 6 which
2067  * configures the overflow device access containing
2068  * the DRBs - this is where we expose device 6.
2069  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2070  */
2071 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2072 {
2073 	u8 reg;
2074 
2075 	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2076 		dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2077 		pci_write_config_byte(dev, 0xF4, reg | 0x02);
2078 	}
2079 }
2080 
2081 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2082 			quirk_unhide_mch_dev6);
2083 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2084 			quirk_unhide_mch_dev6);
2085 
2086 
2087 #ifdef CONFIG_PCI_MSI
2088 /* Some chipsets do not support MSI. We cannot easily rely on setting
2089  * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2090  * some other busses controlled by the chipset even if Linux is not
2091  * aware of it.  Instead of setting the flag on all busses in the
2092  * machine, simply disable MSI globally.
2093  */
2094 static void __init quirk_disable_all_msi(struct pci_dev *dev)
2095 {
2096 	pci_no_msi();
2097 	dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2098 }
2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2105 
2106 /* Disable MSI on chipsets that are known to not support it */
2107 static void __devinit quirk_disable_msi(struct pci_dev *dev)
2108 {
2109 	if (dev->subordinate) {
2110 		dev_warn(&dev->dev, "MSI quirk detected; "
2111 			"subordinate MSI disabled\n");
2112 		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2113 	}
2114 }
2115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2116 
2117 /* Go through the list of Hypertransport capabilities and
2118  * return 1 if a HT MSI capability is found and enabled */
2119 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2120 {
2121 	int pos, ttl = 48;
2122 
2123 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2124 	while (pos && ttl--) {
2125 		u8 flags;
2126 
2127 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2128 					 &flags) == 0)
2129 		{
2130 			dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2131 				flags & HT_MSI_FLAGS_ENABLE ?
2132 				"enabled" : "disabled");
2133 			return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2134 		}
2135 
2136 		pos = pci_find_next_ht_capability(dev, pos,
2137 						  HT_CAPTYPE_MSI_MAPPING);
2138 	}
2139 	return 0;
2140 }
2141 
2142 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2143 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2144 {
2145 	if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2146 		dev_warn(&dev->dev, "MSI quirk detected; "
2147 			"subordinate MSI disabled\n");
2148 		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2149 	}
2150 }
2151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2152 			quirk_msi_ht_cap);
2153 
2154 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2155  * MSI are supported if the MSI capability set in any of these mappings.
2156  */
2157 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2158 {
2159 	struct pci_dev *pdev;
2160 
2161 	if (!dev->subordinate)
2162 		return;
2163 
2164 	/* check HT MSI cap on this chipset and the root one.
2165 	 * a single one having MSI is enough to be sure that MSI are supported.
2166 	 */
2167 	pdev = pci_get_slot(dev->bus, 0);
2168 	if (!pdev)
2169 		return;
2170 	if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2171 		dev_warn(&dev->dev, "MSI quirk detected; "
2172 			"subordinate MSI disabled\n");
2173 		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2174 	}
2175 	pci_dev_put(pdev);
2176 }
2177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2178 			quirk_nvidia_ck804_msi_ht_cap);
2179 
2180 /* Force enable MSI mapping capability on HT bridges */
2181 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2182 {
2183 	int pos, ttl = 48;
2184 
2185 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2186 	while (pos && ttl--) {
2187 		u8 flags;
2188 
2189 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2190 					 &flags) == 0) {
2191 			dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2192 
2193 			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2194 					      flags | HT_MSI_FLAGS_ENABLE);
2195 		}
2196 		pos = pci_find_next_ht_capability(dev, pos,
2197 						  HT_CAPTYPE_MSI_MAPPING);
2198 	}
2199 }
2200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2201 			 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2202 			 ht_enable_msi_mapping);
2203 
2204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2205 			 ht_enable_msi_mapping);
2206 
2207 /* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2208  * for the MCP55 NIC. It is not yet determined whether the msi problem
2209  * also affects other devices. As for now, turn off msi for this device.
2210  */
2211 static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2212 {
2213 	if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2214 		dev_info(&dev->dev,
2215 			 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2216 		dev->no_msi = 1;
2217 	}
2218 }
2219 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2220 			PCI_DEVICE_ID_NVIDIA_NVENET_15,
2221 			nvenet_msi_disable);
2222 
2223 static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2224 {
2225 	int pos, ttl = 48;
2226 	int found = 0;
2227 
2228 	/* check if there is HT MSI cap or enabled on this device */
2229 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2230 	while (pos && ttl--) {
2231 		u8 flags;
2232 
2233 		if (found < 1)
2234 			found = 1;
2235 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2236 					 &flags) == 0) {
2237 			if (flags & HT_MSI_FLAGS_ENABLE) {
2238 				if (found < 2) {
2239 					found = 2;
2240 					break;
2241 				}
2242 			}
2243 		}
2244 		pos = pci_find_next_ht_capability(dev, pos,
2245 						  HT_CAPTYPE_MSI_MAPPING);
2246 	}
2247 
2248 	return found;
2249 }
2250 
2251 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2252 {
2253 	struct pci_dev *dev;
2254 	int pos;
2255 	int i, dev_no;
2256 	int found = 0;
2257 
2258 	dev_no = host_bridge->devfn >> 3;
2259 	for (i = dev_no + 1; i < 0x20; i++) {
2260 		dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2261 		if (!dev)
2262 			continue;
2263 
2264 		/* found next host bridge ?*/
2265 		pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2266 		if (pos != 0) {
2267 			pci_dev_put(dev);
2268 			break;
2269 		}
2270 
2271 		if (ht_check_msi_mapping(dev)) {
2272 			found = 1;
2273 			pci_dev_put(dev);
2274 			break;
2275 		}
2276 		pci_dev_put(dev);
2277 	}
2278 
2279 	return found;
2280 }
2281 
2282 #define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
2283 #define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */
2284 
2285 static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2286 {
2287 	int pos, ctrl_off;
2288 	int end = 0;
2289 	u16 flags, ctrl;
2290 
2291 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2292 
2293 	if (!pos)
2294 		goto out;
2295 
2296 	pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2297 
2298 	ctrl_off = ((flags >> 10) & 1) ?
2299 			PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2300 	pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2301 
2302 	if (ctrl & (1 << 6))
2303 		end = 1;
2304 
2305 out:
2306 	return end;
2307 }
2308 
2309 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2310 {
2311 	struct pci_dev *host_bridge;
2312 	int pos;
2313 	int i, dev_no;
2314 	int found = 0;
2315 
2316 	dev_no = dev->devfn >> 3;
2317 	for (i = dev_no; i >= 0; i--) {
2318 		host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2319 		if (!host_bridge)
2320 			continue;
2321 
2322 		pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2323 		if (pos != 0) {
2324 			found = 1;
2325 			break;
2326 		}
2327 		pci_dev_put(host_bridge);
2328 	}
2329 
2330 	if (!found)
2331 		return;
2332 
2333 	/* don't enable end_device/host_bridge with leaf directly here */
2334 	if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2335 	    host_bridge_with_leaf(host_bridge))
2336 		goto out;
2337 
2338 	/* root did that ! */
2339 	if (msi_ht_cap_enabled(host_bridge))
2340 		goto out;
2341 
2342 	ht_enable_msi_mapping(dev);
2343 
2344 out:
2345 	pci_dev_put(host_bridge);
2346 }
2347 
2348 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2349 {
2350 	int pos, ttl = 48;
2351 
2352 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2353 	while (pos && ttl--) {
2354 		u8 flags;
2355 
2356 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2357 					 &flags) == 0) {
2358 			dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2359 
2360 			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2361 					      flags & ~HT_MSI_FLAGS_ENABLE);
2362 		}
2363 		pos = pci_find_next_ht_capability(dev, pos,
2364 						  HT_CAPTYPE_MSI_MAPPING);
2365 	}
2366 }
2367 
2368 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2369 {
2370 	struct pci_dev *host_bridge;
2371 	int pos;
2372 	int found;
2373 
2374 	/* check if there is HT MSI cap or enabled on this device */
2375 	found = ht_check_msi_mapping(dev);
2376 
2377 	/* no HT MSI CAP */
2378 	if (found == 0)
2379 		return;
2380 
2381 	/*
2382 	 * HT MSI mapping should be disabled on devices that are below
2383 	 * a non-Hypertransport host bridge. Locate the host bridge...
2384 	 */
2385 	host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2386 	if (host_bridge == NULL) {
2387 		dev_warn(&dev->dev,
2388 			 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2389 		return;
2390 	}
2391 
2392 	pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2393 	if (pos != 0) {
2394 		/* Host bridge is to HT */
2395 		if (found == 1) {
2396 			/* it is not enabled, try to enable it */
2397 			if (all)
2398 				ht_enable_msi_mapping(dev);
2399 			else
2400 				nv_ht_enable_msi_mapping(dev);
2401 		}
2402 		return;
2403 	}
2404 
2405 	/* HT MSI is not enabled */
2406 	if (found == 1)
2407 		return;
2408 
2409 	/* Host bridge is not to HT, disable HT MSI mapping on this device */
2410 	ht_disable_msi_mapping(dev);
2411 }
2412 
2413 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2414 {
2415 	return __nv_msi_ht_cap_quirk(dev, 1);
2416 }
2417 
2418 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2419 {
2420 	return __nv_msi_ht_cap_quirk(dev, 0);
2421 }
2422 
2423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2425 
2426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2428 
2429 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2430 {
2431 	dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2432 }
2433 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2434 {
2435 	struct pci_dev *p;
2436 
2437 	/* SB700 MSI issue will be fixed at HW level from revision A21,
2438 	 * we need check PCI REVISION ID of SMBus controller to get SB700
2439 	 * revision.
2440 	 */
2441 	p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2442 			   NULL);
2443 	if (!p)
2444 		return;
2445 
2446 	if ((p->revision < 0x3B) && (p->revision >= 0x30))
2447 		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2448 	pci_dev_put(p);
2449 }
2450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2451 			PCI_DEVICE_ID_TIGON3_5780,
2452 			quirk_msi_intx_disable_bug);
2453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2454 			PCI_DEVICE_ID_TIGON3_5780S,
2455 			quirk_msi_intx_disable_bug);
2456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2457 			PCI_DEVICE_ID_TIGON3_5714,
2458 			quirk_msi_intx_disable_bug);
2459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2460 			PCI_DEVICE_ID_TIGON3_5714S,
2461 			quirk_msi_intx_disable_bug);
2462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2463 			PCI_DEVICE_ID_TIGON3_5715,
2464 			quirk_msi_intx_disable_bug);
2465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2466 			PCI_DEVICE_ID_TIGON3_5715S,
2467 			quirk_msi_intx_disable_bug);
2468 
2469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2470 			quirk_msi_intx_disable_ati_bug);
2471 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2472 			quirk_msi_intx_disable_ati_bug);
2473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2474 			quirk_msi_intx_disable_ati_bug);
2475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2476 			quirk_msi_intx_disable_ati_bug);
2477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2478 			quirk_msi_intx_disable_ati_bug);
2479 
2480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2481 			quirk_msi_intx_disable_bug);
2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2483 			quirk_msi_intx_disable_bug);
2484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2485 			quirk_msi_intx_disable_bug);
2486 
2487 #endif /* CONFIG_PCI_MSI */
2488 
2489 #ifdef CONFIG_PCI_IOV
2490 
2491 /*
2492  * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2493  * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2494  * old Flash Memory Space.
2495  */
2496 static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2497 {
2498 	int pos, flags;
2499 	u32 bar, start, size;
2500 
2501 	if (PAGE_SIZE > 0x10000)
2502 		return;
2503 
2504 	flags = pci_resource_flags(dev, 0);
2505 	if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2506 			PCI_BASE_ADDRESS_SPACE_MEMORY ||
2507 	    (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2508 			PCI_BASE_ADDRESS_MEM_TYPE_32)
2509 		return;
2510 
2511 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2512 	if (!pos)
2513 		return;
2514 
2515 	pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2516 	if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2517 		return;
2518 
2519 	start = pci_resource_start(dev, 1);
2520 	size = pci_resource_len(dev, 1);
2521 	if (!start || size != 0x400000 || start & (size - 1))
2522 		return;
2523 
2524 	pci_resource_flags(dev, 1) = 0;
2525 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2526 	pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2527 	pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2528 
2529 	dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2530 }
2531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2537 
2538 #endif	/* CONFIG_PCI_IOV */
2539 
2540 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2541 			  struct pci_fixup *end)
2542 {
2543 	while (f < end) {
2544 		if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2545 		    (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2546 			dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2547 			f->hook(dev);
2548 		}
2549 		f++;
2550 	}
2551 }
2552 
2553 extern struct pci_fixup __start_pci_fixups_early[];
2554 extern struct pci_fixup __end_pci_fixups_early[];
2555 extern struct pci_fixup __start_pci_fixups_header[];
2556 extern struct pci_fixup __end_pci_fixups_header[];
2557 extern struct pci_fixup __start_pci_fixups_final[];
2558 extern struct pci_fixup __end_pci_fixups_final[];
2559 extern struct pci_fixup __start_pci_fixups_enable[];
2560 extern struct pci_fixup __end_pci_fixups_enable[];
2561 extern struct pci_fixup __start_pci_fixups_resume[];
2562 extern struct pci_fixup __end_pci_fixups_resume[];
2563 extern struct pci_fixup __start_pci_fixups_resume_early[];
2564 extern struct pci_fixup __end_pci_fixups_resume_early[];
2565 extern struct pci_fixup __start_pci_fixups_suspend[];
2566 extern struct pci_fixup __end_pci_fixups_suspend[];
2567 
2568 
2569 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2570 {
2571 	struct pci_fixup *start, *end;
2572 
2573 	switch(pass) {
2574 	case pci_fixup_early:
2575 		start = __start_pci_fixups_early;
2576 		end = __end_pci_fixups_early;
2577 		break;
2578 
2579 	case pci_fixup_header:
2580 		start = __start_pci_fixups_header;
2581 		end = __end_pci_fixups_header;
2582 		break;
2583 
2584 	case pci_fixup_final:
2585 		start = __start_pci_fixups_final;
2586 		end = __end_pci_fixups_final;
2587 		break;
2588 
2589 	case pci_fixup_enable:
2590 		start = __start_pci_fixups_enable;
2591 		end = __end_pci_fixups_enable;
2592 		break;
2593 
2594 	case pci_fixup_resume:
2595 		start = __start_pci_fixups_resume;
2596 		end = __end_pci_fixups_resume;
2597 		break;
2598 
2599 	case pci_fixup_resume_early:
2600 		start = __start_pci_fixups_resume_early;
2601 		end = __end_pci_fixups_resume_early;
2602 		break;
2603 
2604 	case pci_fixup_suspend:
2605 		start = __start_pci_fixups_suspend;
2606 		end = __end_pci_fixups_suspend;
2607 		break;
2608 
2609 	default:
2610 		/* stupid compiler warning, you would think with an enum... */
2611 		return;
2612 	}
2613 	pci_do_fixups(dev, start, end);
2614 }
2615 
2616 static int __init pci_apply_final_quirks(void)
2617 {
2618 	struct pci_dev *dev = NULL;
2619 	u8 cls = 0;
2620 	u8 tmp;
2621 
2622 	if (pci_cache_line_size)
2623 		printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2624 		       pci_cache_line_size << 2);
2625 
2626 	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2627 		pci_fixup_device(pci_fixup_final, dev);
2628 		/*
2629 		 * If arch hasn't set it explicitly yet, use the CLS
2630 		 * value shared by all PCI devices.  If there's a
2631 		 * mismatch, fall back to the default value.
2632 		 */
2633 		if (!pci_cache_line_size) {
2634 			pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2635 			if (!cls)
2636 				cls = tmp;
2637 			if (!tmp || cls == tmp)
2638 				continue;
2639 
2640 			printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2641 			       "using %u bytes\n", cls << 2, tmp << 2,
2642 			       pci_dfl_cache_line_size << 2);
2643 			pci_cache_line_size = pci_dfl_cache_line_size;
2644 		}
2645 	}
2646 	if (!pci_cache_line_size) {
2647 		printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2648 		       cls << 2, pci_dfl_cache_line_size << 2);
2649 		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
2650 	}
2651 
2652 	return 0;
2653 }
2654 
2655 fs_initcall_sync(pci_apply_final_quirks);
2656 
2657 /*
2658  * Followings are device-specific reset methods which can be used to
2659  * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2660  * not available.
2661  */
2662 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2663 {
2664 	int pos;
2665 
2666 	/* only implement PCI_CLASS_SERIAL_USB at present */
2667 	if (dev->class == PCI_CLASS_SERIAL_USB) {
2668 		pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2669 		if (!pos)
2670 			return -ENOTTY;
2671 
2672 		if (probe)
2673 			return 0;
2674 
2675 		pci_write_config_byte(dev, pos + 0x4, 1);
2676 		msleep(100);
2677 
2678 		return 0;
2679 	} else {
2680 		return -ENOTTY;
2681 	}
2682 }
2683 
2684 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2685 {
2686 	int pos;
2687 
2688 	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2689 	if (!pos)
2690 		return -ENOTTY;
2691 
2692 	if (probe)
2693 		return 0;
2694 
2695 	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2696 				PCI_EXP_DEVCTL_BCR_FLR);
2697 	msleep(100);
2698 
2699 	return 0;
2700 }
2701 
2702 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
2703 
2704 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
2705 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2706 		 reset_intel_82599_sfp_virtfn },
2707 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2708 		reset_intel_generic_dev },
2709 	{ 0 }
2710 };
2711 
2712 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2713 {
2714 	const struct pci_dev_reset_methods *i;
2715 
2716 	for (i = pci_dev_reset_methods; i->reset; i++) {
2717 		if ((i->vendor == dev->vendor ||
2718 		     i->vendor == (u16)PCI_ANY_ID) &&
2719 		    (i->device == dev->device ||
2720 		     i->device == (u16)PCI_ANY_ID))
2721 			return i->reset(dev, probe);
2722 	}
2723 
2724 	return -ENOTTY;
2725 }
2726 
2727 #else
2728 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2729 int pci_dev_specific_reset(struct pci_dev *dev, int probe) { return -ENOTTY; }
2730 #endif
2731 EXPORT_SYMBOL(pci_fixup_device);
2732