1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/acpi.h> 21 #include <linux/kallsyms.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 28 #include "pci.h" 29 30 /* 31 * Decoding should be disabled for a PCI device during BAR sizing to avoid 32 * conflict. But doing so may cause problems on host bridge and perhaps other 33 * key system devices. For devices that need to have mmio decoding always-on, 34 * we need to set the dev->mmio_always_on bit. 35 */ 36 static void quirk_mmio_always_on(struct pci_dev *dev) 37 { 38 dev->mmio_always_on = 1; 39 } 40 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 41 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 42 43 /* The Mellanox Tavor device gives false positive parity errors 44 * Mark this device with a broken_parity_status, to allow 45 * PCI scanning code to "skip" this now blacklisted device. 46 */ 47 static void quirk_mellanox_tavor(struct pci_dev *dev) 48 { 49 dev->broken_parity_status = 1; /* This device gives false positives */ 50 } 51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 53 54 /* Deal with broken BIOSes that neglect to enable passive release, 55 which can cause problems in combination with the 82441FX/PPro MTRRs */ 56 static void quirk_passive_release(struct pci_dev *dev) 57 { 58 struct pci_dev *d = NULL; 59 unsigned char dlc; 60 61 /* We have to make sure a particular bit is set in the PIIX3 62 ISA bridge, so we have to go out and find it. */ 63 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 64 pci_read_config_byte(d, 0x82, &dlc); 65 if (!(dlc & 1<<1)) { 66 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 67 dlc |= 1<<1; 68 pci_write_config_byte(d, 0x82, dlc); 69 } 70 } 71 } 72 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 73 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 74 75 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 76 but VIA don't answer queries. If you happen to have good contacts at VIA 77 ask them for me please -- Alan 78 79 This appears to be BIOS not version dependent. So presumably there is a 80 chipset level fix */ 81 82 static void quirk_isa_dma_hangs(struct pci_dev *dev) 83 { 84 if (!isa_dma_bridge_buggy) { 85 isa_dma_bridge_buggy = 1; 86 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 87 } 88 } 89 /* 90 * Its not totally clear which chipsets are the problematic ones 91 * We know 82C586 and 82C596 variants are affected. 92 */ 93 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 100 101 /* 102 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 103 * for some HT machines to use C4 w/o hanging. 104 */ 105 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 106 { 107 u32 pmbase; 108 u16 pm1a; 109 110 pci_read_config_dword(dev, 0x40, &pmbase); 111 pmbase = pmbase & 0xff80; 112 pm1a = inw(pmbase); 113 114 if (pm1a & 0x10) { 115 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 116 outw(0x10, pmbase); 117 } 118 } 119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 120 121 /* 122 * Chipsets where PCI->PCI transfers vanish or hang 123 */ 124 static void quirk_nopcipci(struct pci_dev *dev) 125 { 126 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 127 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 128 pci_pci_problems |= PCIPCI_FAIL; 129 } 130 } 131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 133 134 static void quirk_nopciamd(struct pci_dev *dev) 135 { 136 u8 rev; 137 pci_read_config_byte(dev, 0x08, &rev); 138 if (rev == 0x13) { 139 /* Erratum 24 */ 140 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 141 pci_pci_problems |= PCIAGP_FAIL; 142 } 143 } 144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 145 146 /* 147 * Triton requires workarounds to be used by the drivers 148 */ 149 static void quirk_triton(struct pci_dev *dev) 150 { 151 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 152 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 153 pci_pci_problems |= PCIPCI_TRITON; 154 } 155 } 156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 160 161 /* 162 * VIA Apollo KT133 needs PCI latency patch 163 * Made according to a windows driver based patch by George E. Breese 164 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 165 * and http://www.georgebreese.com/net/software/#PCI 166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 167 * the info on which Mr Breese based his work. 168 * 169 * Updated based on further information from the site and also on 170 * information provided by VIA 171 */ 172 static void quirk_vialatency(struct pci_dev *dev) 173 { 174 struct pci_dev *p; 175 u8 busarb; 176 /* Ok we have a potential problem chipset here. Now see if we have 177 a buggy southbridge */ 178 179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 180 if (p != NULL) { 181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 182 /* Check for buggy part revisions */ 183 if (p->revision < 0x40 || p->revision > 0x42) 184 goto exit; 185 } else { 186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 187 if (p == NULL) /* No problem parts */ 188 goto exit; 189 /* Check for buggy part revisions */ 190 if (p->revision < 0x10 || p->revision > 0x12) 191 goto exit; 192 } 193 194 /* 195 * Ok we have the problem. Now set the PCI master grant to 196 * occur every master grant. The apparent bug is that under high 197 * PCI load (quite common in Linux of course) you can get data 198 * loss when the CPU is held off the bus for 3 bus master requests 199 * This happens to include the IDE controllers.... 200 * 201 * VIA only apply this fix when an SB Live! is present but under 202 * both Linux and Windows this isn't enough, and we have seen 203 * corruption without SB Live! but with things like 3 UDMA IDE 204 * controllers. So we ignore that bit of the VIA recommendation.. 205 */ 206 207 pci_read_config_byte(dev, 0x76, &busarb); 208 /* Set bit 4 and bi 5 of byte 76 to 0x01 209 "Master priority rotation on every PCI master grant */ 210 busarb &= ~(1<<5); 211 busarb |= (1<<4); 212 pci_write_config_byte(dev, 0x76, busarb); 213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 214 exit: 215 pci_dev_put(p); 216 } 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 220 /* Must restore this on a resume from RAM */ 221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 224 225 /* 226 * VIA Apollo VP3 needs ETBF on BT848/878 227 */ 228 static void quirk_viaetbf(struct pci_dev *dev) 229 { 230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 232 pci_pci_problems |= PCIPCI_VIAETBF; 233 } 234 } 235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 236 237 static void quirk_vsfx(struct pci_dev *dev) 238 { 239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 241 pci_pci_problems |= PCIPCI_VSFX; 242 } 243 } 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 245 246 /* 247 * Ali Magik requires workarounds to be used by the drivers 248 * that DMA to AGP space. Latency must be set to 0xA and triton 249 * workaround applied too 250 * [Info kindly provided by ALi] 251 */ 252 static void quirk_alimagik(struct pci_dev *dev) 253 { 254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 257 } 258 } 259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 261 262 /* 263 * Natoma has some interesting boundary conditions with Zoran stuff 264 * at least 265 */ 266 static void quirk_natoma(struct pci_dev *dev) 267 { 268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 270 pci_pci_problems |= PCIPCI_NATOMA; 271 } 272 } 273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 279 280 /* 281 * This chip can cause PCI parity errors if config register 0xA0 is read 282 * while DMAs are occurring. 283 */ 284 static void quirk_citrine(struct pci_dev *dev) 285 { 286 dev->cfg_size = 0xA0; 287 } 288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 289 290 /* 291 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 292 * If it's needed, re-allocate the region. 293 */ 294 static void quirk_s3_64M(struct pci_dev *dev) 295 { 296 struct resource *r = &dev->resource[0]; 297 298 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 299 r->flags |= IORESOURCE_UNSET; 300 r->start = 0; 301 r->end = 0x3ffffff; 302 } 303 } 304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 306 307 /* 308 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 309 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 310 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 311 * (which conflicts w/ BAR1's memory range). 312 */ 313 static void quirk_cs5536_vsa(struct pci_dev *dev) 314 { 315 if (pci_resource_len(dev, 0) != 8) { 316 struct resource *res = &dev->resource[0]; 317 res->end = res->start + 8 - 1; 318 dev_info(&dev->dev, "CS5536 ISA bridge bug detected (incorrect header); workaround applied\n"); 319 } 320 } 321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 322 323 static void quirk_io_region(struct pci_dev *dev, int port, 324 unsigned size, int nr, const char *name) 325 { 326 u16 region; 327 struct pci_bus_region bus_region; 328 struct resource *res = dev->resource + nr; 329 330 pci_read_config_word(dev, port, ®ion); 331 region &= ~(size - 1); 332 333 if (!region) 334 return; 335 336 res->name = pci_name(dev); 337 res->flags = IORESOURCE_IO; 338 339 /* Convert from PCI bus to resource space */ 340 bus_region.start = region; 341 bus_region.end = region + size - 1; 342 pcibios_bus_to_resource(dev->bus, res, &bus_region); 343 344 if (!pci_claim_resource(dev, nr)) 345 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 346 } 347 348 /* 349 * ATI Northbridge setups MCE the processor if you even 350 * read somewhere between 0x3b0->0x3bb or read 0x3d3 351 */ 352 static void quirk_ati_exploding_mce(struct pci_dev *dev) 353 { 354 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 355 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 356 request_region(0x3b0, 0x0C, "RadeonIGP"); 357 request_region(0x3d3, 0x01, "RadeonIGP"); 358 } 359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 360 361 /* 362 * Let's make the southbridge information explicit instead 363 * of having to worry about people probing the ACPI areas, 364 * for example.. (Yes, it happens, and if you read the wrong 365 * ACPI register it will put the machine to sleep with no 366 * way of waking it up again. Bummer). 367 * 368 * ALI M7101: Two IO regions pointed to by words at 369 * 0xE0 (64 bytes of ACPI registers) 370 * 0xE2 (32 bytes of SMB registers) 371 */ 372 static void quirk_ali7101_acpi(struct pci_dev *dev) 373 { 374 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 375 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 376 } 377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 378 379 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 380 { 381 u32 devres; 382 u32 mask, size, base; 383 384 pci_read_config_dword(dev, port, &devres); 385 if ((devres & enable) != enable) 386 return; 387 mask = (devres >> 16) & 15; 388 base = devres & 0xffff; 389 size = 16; 390 for (;;) { 391 unsigned bit = size >> 1; 392 if ((bit & mask) == bit) 393 break; 394 size = bit; 395 } 396 /* 397 * For now we only print it out. Eventually we'll want to 398 * reserve it (at least if it's in the 0x1000+ range), but 399 * let's get enough confirmation reports first. 400 */ 401 base &= -size; 402 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 403 base + size - 1); 404 } 405 406 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 407 { 408 u32 devres; 409 u32 mask, size, base; 410 411 pci_read_config_dword(dev, port, &devres); 412 if ((devres & enable) != enable) 413 return; 414 base = devres & 0xffff0000; 415 mask = (devres & 0x3f) << 16; 416 size = 128 << 16; 417 for (;;) { 418 unsigned bit = size >> 1; 419 if ((bit & mask) == bit) 420 break; 421 size = bit; 422 } 423 /* 424 * For now we only print it out. Eventually we'll want to 425 * reserve it, but let's get enough confirmation reports first. 426 */ 427 base &= -size; 428 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 429 base + size - 1); 430 } 431 432 /* 433 * PIIX4 ACPI: Two IO regions pointed to by longwords at 434 * 0x40 (64 bytes of ACPI registers) 435 * 0x90 (16 bytes of SMB registers) 436 * and a few strange programmable PIIX4 device resources. 437 */ 438 static void quirk_piix4_acpi(struct pci_dev *dev) 439 { 440 u32 res_a; 441 442 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 443 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 444 445 /* Device resource A has enables for some of the other ones */ 446 pci_read_config_dword(dev, 0x5c, &res_a); 447 448 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 449 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 450 451 /* Device resource D is just bitfields for static resources */ 452 453 /* Device 12 enabled? */ 454 if (res_a & (1 << 29)) { 455 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 456 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 457 } 458 /* Device 13 enabled? */ 459 if (res_a & (1 << 30)) { 460 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 461 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 462 } 463 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 464 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 465 } 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 468 469 #define ICH_PMBASE 0x40 470 #define ICH_ACPI_CNTL 0x44 471 #define ICH4_ACPI_EN 0x10 472 #define ICH6_ACPI_EN 0x80 473 #define ICH4_GPIOBASE 0x58 474 #define ICH4_GPIO_CNTL 0x5c 475 #define ICH4_GPIO_EN 0x10 476 #define ICH6_GPIOBASE 0x48 477 #define ICH6_GPIO_CNTL 0x4c 478 #define ICH6_GPIO_EN 0x10 479 480 /* 481 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 482 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 483 * 0x58 (64 bytes of GPIO I/O space) 484 */ 485 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 486 { 487 u8 enable; 488 489 /* 490 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 491 * with low legacy (and fixed) ports. We don't know the decoding 492 * priority and can't tell whether the legacy device or the one created 493 * here is really at that address. This happens on boards with broken 494 * BIOSes. 495 */ 496 497 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 498 if (enable & ICH4_ACPI_EN) 499 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 500 "ICH4 ACPI/GPIO/TCO"); 501 502 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 503 if (enable & ICH4_GPIO_EN) 504 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 505 "ICH4 GPIO"); 506 } 507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 517 518 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 519 { 520 u8 enable; 521 522 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 523 if (enable & ICH6_ACPI_EN) 524 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 525 "ICH6 ACPI/GPIO/TCO"); 526 527 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 528 if (enable & ICH6_GPIO_EN) 529 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 530 "ICH6 GPIO"); 531 } 532 533 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 534 { 535 u32 val; 536 u32 size, base; 537 538 pci_read_config_dword(dev, reg, &val); 539 540 /* Enabled? */ 541 if (!(val & 1)) 542 return; 543 base = val & 0xfffc; 544 if (dynsize) { 545 /* 546 * This is not correct. It is 16, 32 or 64 bytes depending on 547 * register D31:F0:ADh bits 5:4. 548 * 549 * But this gets us at least _part_ of it. 550 */ 551 size = 16; 552 } else { 553 size = 128; 554 } 555 base &= ~(size-1); 556 557 /* Just print it out for now. We should reserve it after more debugging */ 558 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 559 } 560 561 static void quirk_ich6_lpc(struct pci_dev *dev) 562 { 563 /* Shared ACPI/GPIO decode with all ICH6+ */ 564 ich6_lpc_acpi_gpio(dev); 565 566 /* ICH6-specific generic IO decode */ 567 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 568 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 569 } 570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 572 573 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 574 { 575 u32 val; 576 u32 mask, base; 577 578 pci_read_config_dword(dev, reg, &val); 579 580 /* Enabled? */ 581 if (!(val & 1)) 582 return; 583 584 /* 585 * IO base in bits 15:2, mask in bits 23:18, both 586 * are dword-based 587 */ 588 base = val & 0xfffc; 589 mask = (val >> 16) & 0xfc; 590 mask |= 3; 591 592 /* Just print it out for now. We should reserve it after more debugging */ 593 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 594 } 595 596 /* ICH7-10 has the same common LPC generic IO decode registers */ 597 static void quirk_ich7_lpc(struct pci_dev *dev) 598 { 599 /* We share the common ACPI/GPIO decode with ICH6 */ 600 ich6_lpc_acpi_gpio(dev); 601 602 /* And have 4 ICH7+ generic decodes */ 603 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 604 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 605 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 606 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 607 } 608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 621 622 /* 623 * VIA ACPI: One IO region pointed to by longword at 624 * 0x48 or 0x20 (256 bytes of ACPI registers) 625 */ 626 static void quirk_vt82c586_acpi(struct pci_dev *dev) 627 { 628 if (dev->revision & 0x10) 629 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 630 "vt82c586 ACPI"); 631 } 632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 633 634 /* 635 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 636 * 0x48 (256 bytes of ACPI registers) 637 * 0x70 (128 bytes of hardware monitoring register) 638 * 0x90 (16 bytes of SMB registers) 639 */ 640 static void quirk_vt82c686_acpi(struct pci_dev *dev) 641 { 642 quirk_vt82c586_acpi(dev); 643 644 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 645 "vt82c686 HW-mon"); 646 647 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 648 } 649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 650 651 /* 652 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 653 * 0x88 (128 bytes of power management registers) 654 * 0xd0 (16 bytes of SMB registers) 655 */ 656 static void quirk_vt8235_acpi(struct pci_dev *dev) 657 { 658 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 659 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 660 } 661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 662 663 /* 664 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 665 * Disable fast back-to-back on the secondary bus segment 666 */ 667 static void quirk_xio2000a(struct pci_dev *dev) 668 { 669 struct pci_dev *pdev; 670 u16 command; 671 672 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 673 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 674 pci_read_config_word(pdev, PCI_COMMAND, &command); 675 if (command & PCI_COMMAND_FAST_BACK) 676 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 677 } 678 } 679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 680 quirk_xio2000a); 681 682 #ifdef CONFIG_X86_IO_APIC 683 684 #include <asm/io_apic.h> 685 686 /* 687 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 688 * devices to the external APIC. 689 * 690 * TODO: When we have device-specific interrupt routers, 691 * this code will go away from quirks. 692 */ 693 static void quirk_via_ioapic(struct pci_dev *dev) 694 { 695 u8 tmp; 696 697 if (nr_ioapics < 1) 698 tmp = 0; /* nothing routed to external APIC */ 699 else 700 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 701 702 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 703 tmp == 0 ? "Disa" : "Ena"); 704 705 /* Offset 0x58: External APIC IRQ output control */ 706 pci_write_config_byte(dev, 0x58, tmp); 707 } 708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 709 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 710 711 /* 712 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 713 * This leads to doubled level interrupt rates. 714 * Set this bit to get rid of cycle wastage. 715 * Otherwise uncritical. 716 */ 717 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 718 { 719 u8 misc_control2; 720 #define BYPASS_APIC_DEASSERT 8 721 722 pci_read_config_byte(dev, 0x5B, &misc_control2); 723 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 724 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 725 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 726 } 727 } 728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 729 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 730 731 /* 732 * The AMD io apic can hang the box when an apic irq is masked. 733 * We check all revs >= B0 (yet not in the pre production!) as the bug 734 * is currently marked NoFix 735 * 736 * We have multiple reports of hangs with this chipset that went away with 737 * noapic specified. For the moment we assume it's the erratum. We may be wrong 738 * of course. However the advice is demonstrably good even if so.. 739 */ 740 static void quirk_amd_ioapic(struct pci_dev *dev) 741 { 742 if (dev->revision >= 0x02) { 743 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 744 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 745 } 746 } 747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 748 749 static void quirk_ioapic_rmw(struct pci_dev *dev) 750 { 751 if (dev->devfn == 0 && dev->bus->number == 0) 752 sis_apic_bug = 1; 753 } 754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 755 #endif /* CONFIG_X86_IO_APIC */ 756 757 /* 758 * Some settings of MMRBC can lead to data corruption so block changes. 759 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 760 */ 761 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 762 { 763 if (dev->subordinate && dev->revision <= 0x12) { 764 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 765 dev->revision); 766 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 767 } 768 } 769 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 770 771 /* 772 * FIXME: it is questionable that quirk_via_acpi 773 * is needed. It shows up as an ISA bridge, and does not 774 * support the PCI_INTERRUPT_LINE register at all. Therefore 775 * it seems like setting the pci_dev's 'irq' to the 776 * value of the ACPI SCI interrupt is only done for convenience. 777 * -jgarzik 778 */ 779 static void quirk_via_acpi(struct pci_dev *d) 780 { 781 /* 782 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 783 */ 784 u8 irq; 785 pci_read_config_byte(d, 0x42, &irq); 786 irq &= 0xf; 787 if (irq && (irq != 2)) 788 d->irq = irq; 789 } 790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 792 793 794 /* 795 * VIA bridges which have VLink 796 */ 797 798 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 799 800 static void quirk_via_bridge(struct pci_dev *dev) 801 { 802 /* See what bridge we have and find the device ranges */ 803 switch (dev->device) { 804 case PCI_DEVICE_ID_VIA_82C686: 805 /* The VT82C686 is special, it attaches to PCI and can have 806 any device number. All its subdevices are functions of 807 that single device. */ 808 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 809 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 810 break; 811 case PCI_DEVICE_ID_VIA_8237: 812 case PCI_DEVICE_ID_VIA_8237A: 813 via_vlink_dev_lo = 15; 814 break; 815 case PCI_DEVICE_ID_VIA_8235: 816 via_vlink_dev_lo = 16; 817 break; 818 case PCI_DEVICE_ID_VIA_8231: 819 case PCI_DEVICE_ID_VIA_8233_0: 820 case PCI_DEVICE_ID_VIA_8233A: 821 case PCI_DEVICE_ID_VIA_8233C_0: 822 via_vlink_dev_lo = 17; 823 break; 824 } 825 } 826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 834 835 /** 836 * quirk_via_vlink - VIA VLink IRQ number update 837 * @dev: PCI device 838 * 839 * If the device we are dealing with is on a PIC IRQ we need to 840 * ensure that the IRQ line register which usually is not relevant 841 * for PCI cards, is actually written so that interrupts get sent 842 * to the right place. 843 * We only do this on systems where a VIA south bridge was detected, 844 * and only for VIA devices on the motherboard (see quirk_via_bridge 845 * above). 846 */ 847 848 static void quirk_via_vlink(struct pci_dev *dev) 849 { 850 u8 irq, new_irq; 851 852 /* Check if we have VLink at all */ 853 if (via_vlink_dev_lo == -1) 854 return; 855 856 new_irq = dev->irq; 857 858 /* Don't quirk interrupts outside the legacy IRQ range */ 859 if (!new_irq || new_irq > 15) 860 return; 861 862 /* Internal device ? */ 863 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 864 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 865 return; 866 867 /* This is an internal VLink device on a PIC interrupt. The BIOS 868 ought to have set this but may not have, so we redo it */ 869 870 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 871 if (new_irq != irq) { 872 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 873 irq, new_irq); 874 udelay(15); /* unknown if delay really needed */ 875 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 876 } 877 } 878 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 879 880 /* 881 * VIA VT82C598 has its device ID settable and many BIOSes 882 * set it to the ID of VT82C597 for backward compatibility. 883 * We need to switch it off to be able to recognize the real 884 * type of the chip. 885 */ 886 static void quirk_vt82c598_id(struct pci_dev *dev) 887 { 888 pci_write_config_byte(dev, 0xfc, 0); 889 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 890 } 891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 892 893 /* 894 * CardBus controllers have a legacy base address that enables them 895 * to respond as i82365 pcmcia controllers. We don't want them to 896 * do this even if the Linux CardBus driver is not loaded, because 897 * the Linux i82365 driver does not (and should not) handle CardBus. 898 */ 899 static void quirk_cardbus_legacy(struct pci_dev *dev) 900 { 901 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 902 } 903 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 904 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 905 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 906 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 907 908 /* 909 * Following the PCI ordering rules is optional on the AMD762. I'm not 910 * sure what the designers were smoking but let's not inhale... 911 * 912 * To be fair to AMD, it follows the spec by default, its BIOS people 913 * who turn it off! 914 */ 915 static void quirk_amd_ordering(struct pci_dev *dev) 916 { 917 u32 pcic; 918 pci_read_config_dword(dev, 0x4C, &pcic); 919 if ((pcic & 6) != 6) { 920 pcic |= 6; 921 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 922 pci_write_config_dword(dev, 0x4C, pcic); 923 pci_read_config_dword(dev, 0x84, &pcic); 924 pcic |= (1 << 23); /* Required in this mode */ 925 pci_write_config_dword(dev, 0x84, pcic); 926 } 927 } 928 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 929 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 930 931 /* 932 * DreamWorks provided workaround for Dunord I-3000 problem 933 * 934 * This card decodes and responds to addresses not apparently 935 * assigned to it. We force a larger allocation to ensure that 936 * nothing gets put too close to it. 937 */ 938 static void quirk_dunord(struct pci_dev *dev) 939 { 940 struct resource *r = &dev->resource[1]; 941 942 r->flags |= IORESOURCE_UNSET; 943 r->start = 0; 944 r->end = 0xffffff; 945 } 946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 947 948 /* 949 * i82380FB mobile docking controller: its PCI-to-PCI bridge 950 * is subtractive decoding (transparent), and does indicate this 951 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 952 * instead of 0x01. 953 */ 954 static void quirk_transparent_bridge(struct pci_dev *dev) 955 { 956 dev->transparent = 1; 957 } 958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 959 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 960 961 /* 962 * Common misconfiguration of the MediaGX/Geode PCI master that will 963 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 964 * datasheets found at http://www.national.com/analog for info on what 965 * these bits do. <christer@weinigel.se> 966 */ 967 static void quirk_mediagx_master(struct pci_dev *dev) 968 { 969 u8 reg; 970 971 pci_read_config_byte(dev, 0x41, ®); 972 if (reg & 2) { 973 reg &= ~2; 974 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 975 reg); 976 pci_write_config_byte(dev, 0x41, reg); 977 } 978 } 979 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 980 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 981 982 /* 983 * Ensure C0 rev restreaming is off. This is normally done by 984 * the BIOS but in the odd case it is not the results are corruption 985 * hence the presence of a Linux check 986 */ 987 static void quirk_disable_pxb(struct pci_dev *pdev) 988 { 989 u16 config; 990 991 if (pdev->revision != 0x04) /* Only C0 requires this */ 992 return; 993 pci_read_config_word(pdev, 0x40, &config); 994 if (config & (1<<6)) { 995 config &= ~(1<<6); 996 pci_write_config_word(pdev, 0x40, config); 997 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 998 } 999 } 1000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1001 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1002 1003 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1004 { 1005 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1006 u8 tmp; 1007 1008 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1009 if (tmp == 0x01) { 1010 pci_read_config_byte(pdev, 0x40, &tmp); 1011 pci_write_config_byte(pdev, 0x40, tmp|1); 1012 pci_write_config_byte(pdev, 0x9, 1); 1013 pci_write_config_byte(pdev, 0xa, 6); 1014 pci_write_config_byte(pdev, 0x40, tmp); 1015 1016 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1017 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1018 } 1019 } 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1021 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1023 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1025 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1027 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1028 1029 /* 1030 * Serverworks CSB5 IDE does not fully support native mode 1031 */ 1032 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1033 { 1034 u8 prog; 1035 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1036 if (prog & 5) { 1037 prog &= ~5; 1038 pdev->class &= ~5; 1039 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1040 /* PCI layer will sort out resources */ 1041 } 1042 } 1043 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1044 1045 /* 1046 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1047 */ 1048 static void quirk_ide_samemode(struct pci_dev *pdev) 1049 { 1050 u8 prog; 1051 1052 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1053 1054 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1055 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1056 prog &= ~5; 1057 pdev->class &= ~5; 1058 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1059 } 1060 } 1061 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1062 1063 /* 1064 * Some ATA devices break if put into D3 1065 */ 1066 1067 static void quirk_no_ata_d3(struct pci_dev *pdev) 1068 { 1069 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1070 } 1071 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1072 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1073 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1074 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1075 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1076 /* ALi loses some register settings that we cannot then restore */ 1077 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1078 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1079 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1080 occur when mode detecting */ 1081 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1082 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1083 1084 /* This was originally an Alpha specific thing, but it really fits here. 1085 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1086 */ 1087 static void quirk_eisa_bridge(struct pci_dev *dev) 1088 { 1089 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1090 } 1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1092 1093 1094 /* 1095 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1096 * is not activated. The myth is that Asus said that they do not want the 1097 * users to be irritated by just another PCI Device in the Win98 device 1098 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1099 * package 2.7.0 for details) 1100 * 1101 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1102 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1103 * becomes necessary to do this tweak in two steps -- the chosen trigger 1104 * is either the Host bridge (preferred) or on-board VGA controller. 1105 * 1106 * Note that we used to unhide the SMBus that way on Toshiba laptops 1107 * (Satellite A40 and Tecra M2) but then found that the thermal management 1108 * was done by SMM code, which could cause unsynchronized concurrent 1109 * accesses to the SMBus registers, with potentially bad effects. Thus you 1110 * should be very careful when adding new entries: if SMM is accessing the 1111 * Intel SMBus, this is a very good reason to leave it hidden. 1112 * 1113 * Likewise, many recent laptops use ACPI for thermal management. If the 1114 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1115 * natively, and keeping the SMBus hidden is the right thing to do. If you 1116 * are about to add an entry in the table below, please first disassemble 1117 * the DSDT and double-check that there is no code accessing the SMBus. 1118 */ 1119 static int asus_hides_smbus; 1120 1121 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1122 { 1123 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1124 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1125 switch (dev->subsystem_device) { 1126 case 0x8025: /* P4B-LX */ 1127 case 0x8070: /* P4B */ 1128 case 0x8088: /* P4B533 */ 1129 case 0x1626: /* L3C notebook */ 1130 asus_hides_smbus = 1; 1131 } 1132 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1133 switch (dev->subsystem_device) { 1134 case 0x80b1: /* P4GE-V */ 1135 case 0x80b2: /* P4PE */ 1136 case 0x8093: /* P4B533-V */ 1137 asus_hides_smbus = 1; 1138 } 1139 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1140 switch (dev->subsystem_device) { 1141 case 0x8030: /* P4T533 */ 1142 asus_hides_smbus = 1; 1143 } 1144 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1145 switch (dev->subsystem_device) { 1146 case 0x8070: /* P4G8X Deluxe */ 1147 asus_hides_smbus = 1; 1148 } 1149 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1150 switch (dev->subsystem_device) { 1151 case 0x80c9: /* PU-DLS */ 1152 asus_hides_smbus = 1; 1153 } 1154 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1155 switch (dev->subsystem_device) { 1156 case 0x1751: /* M2N notebook */ 1157 case 0x1821: /* M5N notebook */ 1158 case 0x1897: /* A6L notebook */ 1159 asus_hides_smbus = 1; 1160 } 1161 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1162 switch (dev->subsystem_device) { 1163 case 0x184b: /* W1N notebook */ 1164 case 0x186a: /* M6Ne notebook */ 1165 asus_hides_smbus = 1; 1166 } 1167 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1168 switch (dev->subsystem_device) { 1169 case 0x80f2: /* P4P800-X */ 1170 asus_hides_smbus = 1; 1171 } 1172 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1173 switch (dev->subsystem_device) { 1174 case 0x1882: /* M6V notebook */ 1175 case 0x1977: /* A6VA notebook */ 1176 asus_hides_smbus = 1; 1177 } 1178 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1179 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1180 switch (dev->subsystem_device) { 1181 case 0x088C: /* HP Compaq nc8000 */ 1182 case 0x0890: /* HP Compaq nc6000 */ 1183 asus_hides_smbus = 1; 1184 } 1185 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1186 switch (dev->subsystem_device) { 1187 case 0x12bc: /* HP D330L */ 1188 case 0x12bd: /* HP D530 */ 1189 case 0x006a: /* HP Compaq nx9500 */ 1190 asus_hides_smbus = 1; 1191 } 1192 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1193 switch (dev->subsystem_device) { 1194 case 0x12bf: /* HP xw4100 */ 1195 asus_hides_smbus = 1; 1196 } 1197 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1198 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1199 switch (dev->subsystem_device) { 1200 case 0xC00C: /* Samsung P35 notebook */ 1201 asus_hides_smbus = 1; 1202 } 1203 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1204 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1205 switch (dev->subsystem_device) { 1206 case 0x0058: /* Compaq Evo N620c */ 1207 asus_hides_smbus = 1; 1208 } 1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1210 switch (dev->subsystem_device) { 1211 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1212 /* Motherboard doesn't have Host bridge 1213 * subvendor/subdevice IDs, therefore checking 1214 * its on-board VGA controller */ 1215 asus_hides_smbus = 1; 1216 } 1217 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1218 switch (dev->subsystem_device) { 1219 case 0x00b8: /* Compaq Evo D510 CMT */ 1220 case 0x00b9: /* Compaq Evo D510 SFF */ 1221 case 0x00ba: /* Compaq Evo D510 USDT */ 1222 /* Motherboard doesn't have Host bridge 1223 * subvendor/subdevice IDs and on-board VGA 1224 * controller is disabled if an AGP card is 1225 * inserted, therefore checking USB UHCI 1226 * Controller #1 */ 1227 asus_hides_smbus = 1; 1228 } 1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1230 switch (dev->subsystem_device) { 1231 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1232 /* Motherboard doesn't have host bridge 1233 * subvendor/subdevice IDs, therefore checking 1234 * its on-board VGA controller */ 1235 asus_hides_smbus = 1; 1236 } 1237 } 1238 } 1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1249 1250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1253 1254 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1255 { 1256 u16 val; 1257 1258 if (likely(!asus_hides_smbus)) 1259 return; 1260 1261 pci_read_config_word(dev, 0xF2, &val); 1262 if (val & 0x8) { 1263 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1264 pci_read_config_word(dev, 0xF2, &val); 1265 if (val & 0x8) 1266 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1267 val); 1268 else 1269 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1270 } 1271 } 1272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1279 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1280 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1281 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1282 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1283 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1284 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1285 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1286 1287 /* It appears we just have one such device. If not, we have a warning */ 1288 static void __iomem *asus_rcba_base; 1289 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1290 { 1291 u32 rcba; 1292 1293 if (likely(!asus_hides_smbus)) 1294 return; 1295 WARN_ON(asus_rcba_base); 1296 1297 pci_read_config_dword(dev, 0xF0, &rcba); 1298 /* use bits 31:14, 16 kB aligned */ 1299 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1300 if (asus_rcba_base == NULL) 1301 return; 1302 } 1303 1304 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1305 { 1306 u32 val; 1307 1308 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1309 return; 1310 /* read the Function Disable register, dword mode only */ 1311 val = readl(asus_rcba_base + 0x3418); 1312 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1313 } 1314 1315 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1316 { 1317 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1318 return; 1319 iounmap(asus_rcba_base); 1320 asus_rcba_base = NULL; 1321 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1322 } 1323 1324 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1325 { 1326 asus_hides_smbus_lpc_ich6_suspend(dev); 1327 asus_hides_smbus_lpc_ich6_resume_early(dev); 1328 asus_hides_smbus_lpc_ich6_resume(dev); 1329 } 1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1331 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1332 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1333 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1334 1335 /* 1336 * SiS 96x south bridge: BIOS typically hides SMBus device... 1337 */ 1338 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1339 { 1340 u8 val = 0; 1341 pci_read_config_byte(dev, 0x77, &val); 1342 if (val & 0x10) { 1343 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1344 pci_write_config_byte(dev, 0x77, val & ~0x10); 1345 } 1346 } 1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1351 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1352 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1353 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1354 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1355 1356 /* 1357 * ... This is further complicated by the fact that some SiS96x south 1358 * bridges pretend to be 85C503/5513 instead. In that case see if we 1359 * spotted a compatible north bridge to make sure. 1360 * (pci_find_device doesn't work yet) 1361 * 1362 * We can also enable the sis96x bit in the discovery register.. 1363 */ 1364 #define SIS_DETECT_REGISTER 0x40 1365 1366 static void quirk_sis_503(struct pci_dev *dev) 1367 { 1368 u8 reg; 1369 u16 devid; 1370 1371 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1372 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1373 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1374 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1375 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1376 return; 1377 } 1378 1379 /* 1380 * Ok, it now shows up as a 96x.. run the 96x quirk by 1381 * hand in case it has already been processed. 1382 * (depends on link order, which is apparently not guaranteed) 1383 */ 1384 dev->device = devid; 1385 quirk_sis_96x_smbus(dev); 1386 } 1387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1388 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1389 1390 1391 /* 1392 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1393 * and MC97 modem controller are disabled when a second PCI soundcard is 1394 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1395 * -- bjd 1396 */ 1397 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1398 { 1399 u8 val; 1400 int asus_hides_ac97 = 0; 1401 1402 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1403 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1404 asus_hides_ac97 = 1; 1405 } 1406 1407 if (!asus_hides_ac97) 1408 return; 1409 1410 pci_read_config_byte(dev, 0x50, &val); 1411 if (val & 0xc0) { 1412 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1413 pci_read_config_byte(dev, 0x50, &val); 1414 if (val & 0xc0) 1415 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1416 val); 1417 else 1418 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1419 } 1420 } 1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1422 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1423 1424 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1425 1426 /* 1427 * If we are using libata we can drive this chip properly but must 1428 * do this early on to make the additional device appear during 1429 * the PCI scanning. 1430 */ 1431 static void quirk_jmicron_ata(struct pci_dev *pdev) 1432 { 1433 u32 conf1, conf5, class; 1434 u8 hdr; 1435 1436 /* Only poke fn 0 */ 1437 if (PCI_FUNC(pdev->devfn)) 1438 return; 1439 1440 pci_read_config_dword(pdev, 0x40, &conf1); 1441 pci_read_config_dword(pdev, 0x80, &conf5); 1442 1443 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1444 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1445 1446 switch (pdev->device) { 1447 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1448 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1449 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1450 /* The controller should be in single function ahci mode */ 1451 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1452 break; 1453 1454 case PCI_DEVICE_ID_JMICRON_JMB365: 1455 case PCI_DEVICE_ID_JMICRON_JMB366: 1456 /* Redirect IDE second PATA port to the right spot */ 1457 conf5 |= (1 << 24); 1458 /* Fall through */ 1459 case PCI_DEVICE_ID_JMICRON_JMB361: 1460 case PCI_DEVICE_ID_JMICRON_JMB363: 1461 case PCI_DEVICE_ID_JMICRON_JMB369: 1462 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1463 /* Set the class codes correctly and then direct IDE 0 */ 1464 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1465 break; 1466 1467 case PCI_DEVICE_ID_JMICRON_JMB368: 1468 /* The controller should be in single function IDE mode */ 1469 conf1 |= 0x00C00000; /* Set 22, 23 */ 1470 break; 1471 } 1472 1473 pci_write_config_dword(pdev, 0x40, conf1); 1474 pci_write_config_dword(pdev, 0x80, conf5); 1475 1476 /* Update pdev accordingly */ 1477 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1478 pdev->hdr_type = hdr & 0x7f; 1479 pdev->multifunction = !!(hdr & 0x80); 1480 1481 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1482 pdev->class = class >> 8; 1483 } 1484 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1485 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1486 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1487 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1488 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1489 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1490 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1491 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1492 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1493 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1494 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1495 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1496 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1497 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1498 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1499 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1500 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1501 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1502 1503 #endif 1504 1505 #ifdef CONFIG_X86_IO_APIC 1506 static void quirk_alder_ioapic(struct pci_dev *pdev) 1507 { 1508 int i; 1509 1510 if ((pdev->class >> 8) != 0xff00) 1511 return; 1512 1513 /* the first BAR is the location of the IO APIC...we must 1514 * not touch this (and it's already covered by the fixmap), so 1515 * forcibly insert it into the resource tree */ 1516 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1517 insert_resource(&iomem_resource, &pdev->resource[0]); 1518 1519 /* The next five BARs all seem to be rubbish, so just clean 1520 * them out */ 1521 for (i = 1; i < 6; i++) 1522 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1523 } 1524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1525 #endif 1526 1527 static void quirk_pcie_mch(struct pci_dev *pdev) 1528 { 1529 pci_msi_off(pdev); 1530 pdev->no_msi = 1; 1531 } 1532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1535 1536 1537 /* 1538 * It's possible for the MSI to get corrupted if shpc and acpi 1539 * are used together on certain PXH-based systems. 1540 */ 1541 static void quirk_pcie_pxh(struct pci_dev *dev) 1542 { 1543 pci_msi_off(dev); 1544 dev->no_msi = 1; 1545 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1546 } 1547 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1548 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1549 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1550 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1551 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1552 1553 /* 1554 * Some Intel PCI Express chipsets have trouble with downstream 1555 * device power management. 1556 */ 1557 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1558 { 1559 pci_pm_d3_delay = 120; 1560 dev->no_d1d2 = 1; 1561 } 1562 1563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1584 1585 #ifdef CONFIG_X86_IO_APIC 1586 /* 1587 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1588 * remap the original interrupt in the linux kernel to the boot interrupt, so 1589 * that a PCI device's interrupt handler is installed on the boot interrupt 1590 * line instead. 1591 */ 1592 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1593 { 1594 if (noioapicquirk || noioapicreroute) 1595 return; 1596 1597 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1598 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1599 dev->vendor, dev->device); 1600 } 1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1609 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1610 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1612 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1613 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1614 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1615 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1616 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1617 1618 /* 1619 * On some chipsets we can disable the generation of legacy INTx boot 1620 * interrupts. 1621 */ 1622 1623 /* 1624 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1625 * 300641-004US, section 5.7.3. 1626 */ 1627 #define INTEL_6300_IOAPIC_ABAR 0x40 1628 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1629 1630 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1631 { 1632 u16 pci_config_word; 1633 1634 if (noioapicquirk) 1635 return; 1636 1637 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1638 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1639 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1640 1641 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1642 dev->vendor, dev->device); 1643 } 1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1645 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1646 1647 /* 1648 * disable boot interrupts on HT-1000 1649 */ 1650 #define BC_HT1000_FEATURE_REG 0x64 1651 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1652 #define BC_HT1000_MAP_IDX 0xC00 1653 #define BC_HT1000_MAP_DATA 0xC01 1654 1655 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1656 { 1657 u32 pci_config_dword; 1658 u8 irq; 1659 1660 if (noioapicquirk) 1661 return; 1662 1663 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1664 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1665 BC_HT1000_PIC_REGS_ENABLE); 1666 1667 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1668 outb(irq, BC_HT1000_MAP_IDX); 1669 outb(0x00, BC_HT1000_MAP_DATA); 1670 } 1671 1672 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1673 1674 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1675 dev->vendor, dev->device); 1676 } 1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1678 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1679 1680 /* 1681 * disable boot interrupts on AMD and ATI chipsets 1682 */ 1683 /* 1684 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1685 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1686 * (due to an erratum). 1687 */ 1688 #define AMD_813X_MISC 0x40 1689 #define AMD_813X_NOIOAMODE (1<<0) 1690 #define AMD_813X_REV_B1 0x12 1691 #define AMD_813X_REV_B2 0x13 1692 1693 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1694 { 1695 u32 pci_config_dword; 1696 1697 if (noioapicquirk) 1698 return; 1699 if ((dev->revision == AMD_813X_REV_B1) || 1700 (dev->revision == AMD_813X_REV_B2)) 1701 return; 1702 1703 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1704 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1705 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1706 1707 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1708 dev->vendor, dev->device); 1709 } 1710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1711 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1713 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1714 1715 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1716 1717 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1718 { 1719 u16 pci_config_word; 1720 1721 if (noioapicquirk) 1722 return; 1723 1724 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1725 if (!pci_config_word) { 1726 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1727 dev->vendor, dev->device); 1728 return; 1729 } 1730 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1731 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1732 dev->vendor, dev->device); 1733 } 1734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1735 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1736 #endif /* CONFIG_X86_IO_APIC */ 1737 1738 /* 1739 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1740 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1741 * Re-allocate the region if needed... 1742 */ 1743 static void quirk_tc86c001_ide(struct pci_dev *dev) 1744 { 1745 struct resource *r = &dev->resource[0]; 1746 1747 if (r->start & 0x8) { 1748 r->flags |= IORESOURCE_UNSET; 1749 r->start = 0; 1750 r->end = 0xf; 1751 } 1752 } 1753 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1754 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1755 quirk_tc86c001_ide); 1756 1757 /* 1758 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1759 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1760 * being read correctly if bit 7 of the base address is set. 1761 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1762 * Re-allocate the regions to a 256-byte boundary if necessary. 1763 */ 1764 static void quirk_plx_pci9050(struct pci_dev *dev) 1765 { 1766 unsigned int bar; 1767 1768 /* Fixed in revision 2 (PCI 9052). */ 1769 if (dev->revision >= 2) 1770 return; 1771 for (bar = 0; bar <= 1; bar++) 1772 if (pci_resource_len(dev, bar) == 0x80 && 1773 (pci_resource_start(dev, bar) & 0x80)) { 1774 struct resource *r = &dev->resource[bar]; 1775 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1776 bar); 1777 r->flags |= IORESOURCE_UNSET; 1778 r->start = 0; 1779 r->end = 0xff; 1780 } 1781 } 1782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1783 quirk_plx_pci9050); 1784 /* 1785 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1786 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1787 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1788 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1789 * 1790 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1791 * driver. 1792 */ 1793 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1794 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1795 1796 static void quirk_netmos(struct pci_dev *dev) 1797 { 1798 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1799 unsigned int num_serial = dev->subsystem_device & 0xf; 1800 1801 /* 1802 * These Netmos parts are multiport serial devices with optional 1803 * parallel ports. Even when parallel ports are present, they 1804 * are identified as class SERIAL, which means the serial driver 1805 * will claim them. To prevent this, mark them as class OTHER. 1806 * These combo devices should be claimed by parport_serial. 1807 * 1808 * The subdevice ID is of the form 0x00PS, where <P> is the number 1809 * of parallel ports and <S> is the number of serial ports. 1810 */ 1811 switch (dev->device) { 1812 case PCI_DEVICE_ID_NETMOS_9835: 1813 /* Well, this rule doesn't hold for the following 9835 device */ 1814 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1815 dev->subsystem_device == 0x0299) 1816 return; 1817 case PCI_DEVICE_ID_NETMOS_9735: 1818 case PCI_DEVICE_ID_NETMOS_9745: 1819 case PCI_DEVICE_ID_NETMOS_9845: 1820 case PCI_DEVICE_ID_NETMOS_9855: 1821 if (num_parallel) { 1822 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1823 dev->device, num_parallel, num_serial); 1824 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1825 (dev->class & 0xff); 1826 } 1827 } 1828 } 1829 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1830 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1831 1832 static void quirk_e100_interrupt(struct pci_dev *dev) 1833 { 1834 u16 command, pmcsr; 1835 u8 __iomem *csr; 1836 u8 cmd_hi; 1837 1838 switch (dev->device) { 1839 /* PCI IDs taken from drivers/net/e100.c */ 1840 case 0x1029: 1841 case 0x1030 ... 0x1034: 1842 case 0x1038 ... 0x103E: 1843 case 0x1050 ... 0x1057: 1844 case 0x1059: 1845 case 0x1064 ... 0x106B: 1846 case 0x1091 ... 0x1095: 1847 case 0x1209: 1848 case 0x1229: 1849 case 0x2449: 1850 case 0x2459: 1851 case 0x245D: 1852 case 0x27DC: 1853 break; 1854 default: 1855 return; 1856 } 1857 1858 /* 1859 * Some firmware hands off the e100 with interrupts enabled, 1860 * which can cause a flood of interrupts if packets are 1861 * received before the driver attaches to the device. So 1862 * disable all e100 interrupts here. The driver will 1863 * re-enable them when it's ready. 1864 */ 1865 pci_read_config_word(dev, PCI_COMMAND, &command); 1866 1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1868 return; 1869 1870 /* 1871 * Check that the device is in the D0 power state. If it's not, 1872 * there is no point to look any further. 1873 */ 1874 if (dev->pm_cap) { 1875 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1876 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1877 return; 1878 } 1879 1880 /* Convert from PCI bus to resource space. */ 1881 csr = ioremap(pci_resource_start(dev, 0), 8); 1882 if (!csr) { 1883 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1884 return; 1885 } 1886 1887 cmd_hi = readb(csr + 3); 1888 if (cmd_hi == 0) { 1889 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 1890 writeb(1, csr + 3); 1891 } 1892 1893 iounmap(csr); 1894 } 1895 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1896 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 1897 1898 /* 1899 * The 82575 and 82598 may experience data corruption issues when transitioning 1900 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1901 */ 1902 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 1903 { 1904 dev_info(&dev->dev, "Disabling L0s\n"); 1905 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1906 } 1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1914 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1915 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1921 1922 static void fixup_rev1_53c810(struct pci_dev *dev) 1923 { 1924 /* rev 1 ncr53c810 chips don't set the class at all which means 1925 * they don't get their resources remapped. Fix that here. 1926 */ 1927 1928 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1929 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1930 dev->class = PCI_CLASS_STORAGE_SCSI; 1931 } 1932 } 1933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1934 1935 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1936 static void quirk_p64h2_1k_io(struct pci_dev *dev) 1937 { 1938 u16 en1k; 1939 1940 pci_read_config_word(dev, 0x40, &en1k); 1941 1942 if (en1k & 0x200) { 1943 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1944 dev->io_window_1k = 1; 1945 } 1946 } 1947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1948 1949 /* Under some circumstances, AER is not linked with extended capabilities. 1950 * Force it to be linked by setting the corresponding control bit in the 1951 * config space. 1952 */ 1953 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1954 { 1955 uint8_t b; 1956 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1957 if (!(b & 0x20)) { 1958 pci_write_config_byte(dev, 0xf41, b | 0x20); 1959 dev_info(&dev->dev, "Linking AER extended capability\n"); 1960 } 1961 } 1962 } 1963 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1964 quirk_nvidia_ck804_pcie_aer_ext_cap); 1965 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1966 quirk_nvidia_ck804_pcie_aer_ext_cap); 1967 1968 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 1969 { 1970 /* 1971 * Disable PCI Bus Parking and PCI Master read caching on CX700 1972 * which causes unspecified timing errors with a VT6212L on the PCI 1973 * bus leading to USB2.0 packet loss. 1974 * 1975 * This quirk is only enabled if a second (on the external PCI bus) 1976 * VT6212L is found -- the CX700 core itself also contains a USB 1977 * host controller with the same PCI ID as the VT6212L. 1978 */ 1979 1980 /* Count VT6212L instances */ 1981 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 1982 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 1983 uint8_t b; 1984 1985 /* p should contain the first (internal) VT6212L -- see if we have 1986 an external one by searching again */ 1987 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 1988 if (!p) 1989 return; 1990 pci_dev_put(p); 1991 1992 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 1993 if (b & 0x40) { 1994 /* Turn off PCI Bus Parking */ 1995 pci_write_config_byte(dev, 0x76, b ^ 0x40); 1996 1997 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 1998 } 1999 } 2000 2001 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2002 if (b != 0) { 2003 /* Turn off PCI Master read caching */ 2004 pci_write_config_byte(dev, 0x72, 0x0); 2005 2006 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2007 pci_write_config_byte(dev, 0x75, 0x1); 2008 2009 /* Disable "Read FIFO Timer" */ 2010 pci_write_config_byte(dev, 0x77, 0x0); 2011 2012 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2013 } 2014 } 2015 } 2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2017 2018 /* 2019 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2020 * VPD end tag will hang the device. This problem was initially 2021 * observed when a vpd entry was created in sysfs 2022 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2023 * will dump 32k of data. Reading a full 32k will cause an access 2024 * beyond the VPD end tag causing the device to hang. Once the device 2025 * is hung, the bnx2 driver will not be able to reset the device. 2026 * We believe that it is legal to read beyond the end tag and 2027 * therefore the solution is to limit the read/write length. 2028 */ 2029 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2030 { 2031 /* 2032 * Only disable the VPD capability for 5706, 5706S, 5708, 2033 * 5708S and 5709 rev. A 2034 */ 2035 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2036 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2037 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2038 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2039 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2040 (dev->revision & 0xf0) == 0x0)) { 2041 if (dev->vpd) 2042 dev->vpd->len = 0x80; 2043 } 2044 } 2045 2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2047 PCI_DEVICE_ID_NX2_5706, 2048 quirk_brcm_570x_limit_vpd); 2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2050 PCI_DEVICE_ID_NX2_5706S, 2051 quirk_brcm_570x_limit_vpd); 2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2053 PCI_DEVICE_ID_NX2_5708, 2054 quirk_brcm_570x_limit_vpd); 2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2056 PCI_DEVICE_ID_NX2_5708S, 2057 quirk_brcm_570x_limit_vpd); 2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2059 PCI_DEVICE_ID_NX2_5709, 2060 quirk_brcm_570x_limit_vpd); 2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2062 PCI_DEVICE_ID_NX2_5709S, 2063 quirk_brcm_570x_limit_vpd); 2064 2065 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2066 { 2067 u32 rev; 2068 2069 pci_read_config_dword(dev, 0xf4, &rev); 2070 2071 /* Only CAP the MRRS if the device is a 5719 A0 */ 2072 if (rev == 0x05719000) { 2073 int readrq = pcie_get_readrq(dev); 2074 if (readrq > 2048) 2075 pcie_set_readrq(dev, 2048); 2076 } 2077 } 2078 2079 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2080 PCI_DEVICE_ID_TIGON3_5719, 2081 quirk_brcm_5719_limit_mrrs); 2082 2083 /* Originally in EDAC sources for i82875P: 2084 * Intel tells BIOS developers to hide device 6 which 2085 * configures the overflow device access containing 2086 * the DRBs - this is where we expose device 6. 2087 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2088 */ 2089 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2090 { 2091 u8 reg; 2092 2093 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2094 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2095 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2096 } 2097 } 2098 2099 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2100 quirk_unhide_mch_dev6); 2101 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2102 quirk_unhide_mch_dev6); 2103 2104 #ifdef CONFIG_TILEPRO 2105 /* 2106 * The Tilera TILEmpower tilepro platform needs to set the link speed 2107 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2108 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2109 * capability register of the PEX8624 PCIe switch. The switch 2110 * supports link speed auto negotiation, but falsely sets 2111 * the link speed to 5GT/s. 2112 */ 2113 static void quirk_tile_plx_gen1(struct pci_dev *dev) 2114 { 2115 if (tile_plx_gen1) { 2116 pci_write_config_dword(dev, 0x98, 0x1); 2117 mdelay(50); 2118 } 2119 } 2120 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2121 #endif /* CONFIG_TILEPRO */ 2122 2123 #ifdef CONFIG_PCI_MSI 2124 /* Some chipsets do not support MSI. We cannot easily rely on setting 2125 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2126 * some other buses controlled by the chipset even if Linux is not 2127 * aware of it. Instead of setting the flag on all buses in the 2128 * machine, simply disable MSI globally. 2129 */ 2130 static void quirk_disable_all_msi(struct pci_dev *dev) 2131 { 2132 pci_no_msi(); 2133 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2134 } 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2142 2143 /* Disable MSI on chipsets that are known to not support it */ 2144 static void quirk_disable_msi(struct pci_dev *dev) 2145 { 2146 if (dev->subordinate) { 2147 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2148 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2149 } 2150 } 2151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2154 2155 /* 2156 * The APC bridge device in AMD 780 family northbridges has some random 2157 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2158 * we use the possible vendor/device IDs of the host bridge for the 2159 * declared quirk, and search for the APC bridge by slot number. 2160 */ 2161 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2162 { 2163 struct pci_dev *apc_bridge; 2164 2165 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2166 if (apc_bridge) { 2167 if (apc_bridge->device == 0x9602) 2168 quirk_disable_msi(apc_bridge); 2169 pci_dev_put(apc_bridge); 2170 } 2171 } 2172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2174 2175 /* Go through the list of Hypertransport capabilities and 2176 * return 1 if a HT MSI capability is found and enabled */ 2177 static int msi_ht_cap_enabled(struct pci_dev *dev) 2178 { 2179 int pos, ttl = 48; 2180 2181 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2182 while (pos && ttl--) { 2183 u8 flags; 2184 2185 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2186 &flags) == 0) { 2187 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2188 flags & HT_MSI_FLAGS_ENABLE ? 2189 "enabled" : "disabled"); 2190 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2191 } 2192 2193 pos = pci_find_next_ht_capability(dev, pos, 2194 HT_CAPTYPE_MSI_MAPPING); 2195 } 2196 return 0; 2197 } 2198 2199 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2200 static void quirk_msi_ht_cap(struct pci_dev *dev) 2201 { 2202 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2203 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2204 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2205 } 2206 } 2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2208 quirk_msi_ht_cap); 2209 2210 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2211 * MSI are supported if the MSI capability set in any of these mappings. 2212 */ 2213 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2214 { 2215 struct pci_dev *pdev; 2216 2217 if (!dev->subordinate) 2218 return; 2219 2220 /* check HT MSI cap on this chipset and the root one. 2221 * a single one having MSI is enough to be sure that MSI are supported. 2222 */ 2223 pdev = pci_get_slot(dev->bus, 0); 2224 if (!pdev) 2225 return; 2226 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2227 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2228 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2229 } 2230 pci_dev_put(pdev); 2231 } 2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2233 quirk_nvidia_ck804_msi_ht_cap); 2234 2235 /* Force enable MSI mapping capability on HT bridges */ 2236 static void ht_enable_msi_mapping(struct pci_dev *dev) 2237 { 2238 int pos, ttl = 48; 2239 2240 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2241 while (pos && ttl--) { 2242 u8 flags; 2243 2244 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2245 &flags) == 0) { 2246 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2247 2248 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2249 flags | HT_MSI_FLAGS_ENABLE); 2250 } 2251 pos = pci_find_next_ht_capability(dev, pos, 2252 HT_CAPTYPE_MSI_MAPPING); 2253 } 2254 } 2255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2256 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2257 ht_enable_msi_mapping); 2258 2259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2260 ht_enable_msi_mapping); 2261 2262 /* The P5N32-SLI motherboards from Asus have a problem with msi 2263 * for the MCP55 NIC. It is not yet determined whether the msi problem 2264 * also affects other devices. As for now, turn off msi for this device. 2265 */ 2266 static void nvenet_msi_disable(struct pci_dev *dev) 2267 { 2268 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2269 2270 if (board_name && 2271 (strstr(board_name, "P5N32-SLI PREMIUM") || 2272 strstr(board_name, "P5N32-E SLI"))) { 2273 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2274 dev->no_msi = 1; 2275 } 2276 } 2277 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2278 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2279 nvenet_msi_disable); 2280 2281 /* 2282 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2283 * config register. This register controls the routing of legacy 2284 * interrupts from devices that route through the MCP55. If this register 2285 * is misprogrammed, interrupts are only sent to the BSP, unlike 2286 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2287 * having this register set properly prevents kdump from booting up 2288 * properly, so let's make sure that we have it set correctly. 2289 * Note that this is an undocumented register. 2290 */ 2291 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2292 { 2293 u32 cfg; 2294 2295 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2296 return; 2297 2298 pci_read_config_dword(dev, 0x74, &cfg); 2299 2300 if (cfg & ((1 << 2) | (1 << 15))) { 2301 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2302 cfg &= ~((1 << 2) | (1 << 15)); 2303 pci_write_config_dword(dev, 0x74, cfg); 2304 } 2305 } 2306 2307 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2308 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2309 nvbridge_check_legacy_irq_routing); 2310 2311 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2312 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2313 nvbridge_check_legacy_irq_routing); 2314 2315 static int ht_check_msi_mapping(struct pci_dev *dev) 2316 { 2317 int pos, ttl = 48; 2318 int found = 0; 2319 2320 /* check if there is HT MSI cap or enabled on this device */ 2321 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2322 while (pos && ttl--) { 2323 u8 flags; 2324 2325 if (found < 1) 2326 found = 1; 2327 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2328 &flags) == 0) { 2329 if (flags & HT_MSI_FLAGS_ENABLE) { 2330 if (found < 2) { 2331 found = 2; 2332 break; 2333 } 2334 } 2335 } 2336 pos = pci_find_next_ht_capability(dev, pos, 2337 HT_CAPTYPE_MSI_MAPPING); 2338 } 2339 2340 return found; 2341 } 2342 2343 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2344 { 2345 struct pci_dev *dev; 2346 int pos; 2347 int i, dev_no; 2348 int found = 0; 2349 2350 dev_no = host_bridge->devfn >> 3; 2351 for (i = dev_no + 1; i < 0x20; i++) { 2352 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2353 if (!dev) 2354 continue; 2355 2356 /* found next host bridge ?*/ 2357 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2358 if (pos != 0) { 2359 pci_dev_put(dev); 2360 break; 2361 } 2362 2363 if (ht_check_msi_mapping(dev)) { 2364 found = 1; 2365 pci_dev_put(dev); 2366 break; 2367 } 2368 pci_dev_put(dev); 2369 } 2370 2371 return found; 2372 } 2373 2374 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2375 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2376 2377 static int is_end_of_ht_chain(struct pci_dev *dev) 2378 { 2379 int pos, ctrl_off; 2380 int end = 0; 2381 u16 flags, ctrl; 2382 2383 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2384 2385 if (!pos) 2386 goto out; 2387 2388 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2389 2390 ctrl_off = ((flags >> 10) & 1) ? 2391 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2392 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2393 2394 if (ctrl & (1 << 6)) 2395 end = 1; 2396 2397 out: 2398 return end; 2399 } 2400 2401 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2402 { 2403 struct pci_dev *host_bridge; 2404 int pos; 2405 int i, dev_no; 2406 int found = 0; 2407 2408 dev_no = dev->devfn >> 3; 2409 for (i = dev_no; i >= 0; i--) { 2410 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2411 if (!host_bridge) 2412 continue; 2413 2414 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2415 if (pos != 0) { 2416 found = 1; 2417 break; 2418 } 2419 pci_dev_put(host_bridge); 2420 } 2421 2422 if (!found) 2423 return; 2424 2425 /* don't enable end_device/host_bridge with leaf directly here */ 2426 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2427 host_bridge_with_leaf(host_bridge)) 2428 goto out; 2429 2430 /* root did that ! */ 2431 if (msi_ht_cap_enabled(host_bridge)) 2432 goto out; 2433 2434 ht_enable_msi_mapping(dev); 2435 2436 out: 2437 pci_dev_put(host_bridge); 2438 } 2439 2440 static void ht_disable_msi_mapping(struct pci_dev *dev) 2441 { 2442 int pos, ttl = 48; 2443 2444 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2445 while (pos && ttl--) { 2446 u8 flags; 2447 2448 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2449 &flags) == 0) { 2450 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2451 2452 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2453 flags & ~HT_MSI_FLAGS_ENABLE); 2454 } 2455 pos = pci_find_next_ht_capability(dev, pos, 2456 HT_CAPTYPE_MSI_MAPPING); 2457 } 2458 } 2459 2460 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2461 { 2462 struct pci_dev *host_bridge; 2463 int pos; 2464 int found; 2465 2466 if (!pci_msi_enabled()) 2467 return; 2468 2469 /* check if there is HT MSI cap or enabled on this device */ 2470 found = ht_check_msi_mapping(dev); 2471 2472 /* no HT MSI CAP */ 2473 if (found == 0) 2474 return; 2475 2476 /* 2477 * HT MSI mapping should be disabled on devices that are below 2478 * a non-Hypertransport host bridge. Locate the host bridge... 2479 */ 2480 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2481 if (host_bridge == NULL) { 2482 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2483 return; 2484 } 2485 2486 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2487 if (pos != 0) { 2488 /* Host bridge is to HT */ 2489 if (found == 1) { 2490 /* it is not enabled, try to enable it */ 2491 if (all) 2492 ht_enable_msi_mapping(dev); 2493 else 2494 nv_ht_enable_msi_mapping(dev); 2495 } 2496 goto out; 2497 } 2498 2499 /* HT MSI is not enabled */ 2500 if (found == 1) 2501 goto out; 2502 2503 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2504 ht_disable_msi_mapping(dev); 2505 2506 out: 2507 pci_dev_put(host_bridge); 2508 } 2509 2510 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2511 { 2512 return __nv_msi_ht_cap_quirk(dev, 1); 2513 } 2514 2515 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2516 { 2517 return __nv_msi_ht_cap_quirk(dev, 0); 2518 } 2519 2520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2521 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2522 2523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2524 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2525 2526 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2527 { 2528 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2529 } 2530 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2531 { 2532 struct pci_dev *p; 2533 2534 /* SB700 MSI issue will be fixed at HW level from revision A21, 2535 * we need check PCI REVISION ID of SMBus controller to get SB700 2536 * revision. 2537 */ 2538 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2539 NULL); 2540 if (!p) 2541 return; 2542 2543 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2544 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2545 pci_dev_put(p); 2546 } 2547 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2548 { 2549 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2550 if (dev->revision < 0x18) { 2551 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2552 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2553 } 2554 } 2555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2556 PCI_DEVICE_ID_TIGON3_5780, 2557 quirk_msi_intx_disable_bug); 2558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2559 PCI_DEVICE_ID_TIGON3_5780S, 2560 quirk_msi_intx_disable_bug); 2561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2562 PCI_DEVICE_ID_TIGON3_5714, 2563 quirk_msi_intx_disable_bug); 2564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2565 PCI_DEVICE_ID_TIGON3_5714S, 2566 quirk_msi_intx_disable_bug); 2567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2568 PCI_DEVICE_ID_TIGON3_5715, 2569 quirk_msi_intx_disable_bug); 2570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2571 PCI_DEVICE_ID_TIGON3_5715S, 2572 quirk_msi_intx_disable_bug); 2573 2574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2575 quirk_msi_intx_disable_ati_bug); 2576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2577 quirk_msi_intx_disable_ati_bug); 2578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2579 quirk_msi_intx_disable_ati_bug); 2580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2581 quirk_msi_intx_disable_ati_bug); 2582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2583 quirk_msi_intx_disable_ati_bug); 2584 2585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2586 quirk_msi_intx_disable_bug); 2587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2588 quirk_msi_intx_disable_bug); 2589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2590 quirk_msi_intx_disable_bug); 2591 2592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2593 quirk_msi_intx_disable_bug); 2594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2595 quirk_msi_intx_disable_bug); 2596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2597 quirk_msi_intx_disable_bug); 2598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2599 quirk_msi_intx_disable_bug); 2600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2601 quirk_msi_intx_disable_bug); 2602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2603 quirk_msi_intx_disable_bug); 2604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2605 quirk_msi_intx_disable_qca_bug); 2606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2607 quirk_msi_intx_disable_qca_bug); 2608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2609 quirk_msi_intx_disable_qca_bug); 2610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2611 quirk_msi_intx_disable_qca_bug); 2612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2613 quirk_msi_intx_disable_qca_bug); 2614 #endif /* CONFIG_PCI_MSI */ 2615 2616 /* Allow manual resource allocation for PCI hotplug bridges 2617 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2618 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2619 * kernel fails to allocate resources when hotplug device is 2620 * inserted and PCI bus is rescanned. 2621 */ 2622 static void quirk_hotplug_bridge(struct pci_dev *dev) 2623 { 2624 dev->is_hotplug_bridge = 1; 2625 } 2626 2627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2628 2629 /* 2630 * This is a quirk for the Ricoh MMC controller found as a part of 2631 * some mulifunction chips. 2632 2633 * This is very similar and based on the ricoh_mmc driver written by 2634 * Philip Langdale. Thank you for these magic sequences. 2635 * 2636 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2637 * and one or both of cardbus or firewire. 2638 * 2639 * It happens that they implement SD and MMC 2640 * support as separate controllers (and PCI functions). The linux SDHCI 2641 * driver supports MMC cards but the chip detects MMC cards in hardware 2642 * and directs them to the MMC controller - so the SDHCI driver never sees 2643 * them. 2644 * 2645 * To get around this, we must disable the useless MMC controller. 2646 * At that point, the SDHCI controller will start seeing them 2647 * It seems to be the case that the relevant PCI registers to deactivate the 2648 * MMC controller live on PCI function 0, which might be the cardbus controller 2649 * or the firewire controller, depending on the particular chip in question 2650 * 2651 * This has to be done early, because as soon as we disable the MMC controller 2652 * other pci functions shift up one level, e.g. function #2 becomes function 2653 * #1, and this will confuse the pci core. 2654 */ 2655 2656 #ifdef CONFIG_MMC_RICOH_MMC 2657 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2658 { 2659 /* disable via cardbus interface */ 2660 u8 write_enable; 2661 u8 write_target; 2662 u8 disable; 2663 2664 /* disable must be done via function #0 */ 2665 if (PCI_FUNC(dev->devfn)) 2666 return; 2667 2668 pci_read_config_byte(dev, 0xB7, &disable); 2669 if (disable & 0x02) 2670 return; 2671 2672 pci_read_config_byte(dev, 0x8E, &write_enable); 2673 pci_write_config_byte(dev, 0x8E, 0xAA); 2674 pci_read_config_byte(dev, 0x8D, &write_target); 2675 pci_write_config_byte(dev, 0x8D, 0xB7); 2676 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2677 pci_write_config_byte(dev, 0x8E, write_enable); 2678 pci_write_config_byte(dev, 0x8D, write_target); 2679 2680 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2681 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2682 } 2683 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2684 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2685 2686 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2687 { 2688 /* disable via firewire interface */ 2689 u8 write_enable; 2690 u8 disable; 2691 2692 /* disable must be done via function #0 */ 2693 if (PCI_FUNC(dev->devfn)) 2694 return; 2695 /* 2696 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2697 * certain types of SD/MMC cards. Lowering the SD base 2698 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2699 * 2700 * 0x150 - SD2.0 mode enable for changing base clock 2701 * frequency to 50Mhz 2702 * 0xe1 - Base clock frequency 2703 * 0x32 - 50Mhz new clock frequency 2704 * 0xf9 - Key register for 0x150 2705 * 0xfc - key register for 0xe1 2706 */ 2707 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2708 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2709 pci_write_config_byte(dev, 0xf9, 0xfc); 2710 pci_write_config_byte(dev, 0x150, 0x10); 2711 pci_write_config_byte(dev, 0xf9, 0x00); 2712 pci_write_config_byte(dev, 0xfc, 0x01); 2713 pci_write_config_byte(dev, 0xe1, 0x32); 2714 pci_write_config_byte(dev, 0xfc, 0x00); 2715 2716 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2717 } 2718 2719 pci_read_config_byte(dev, 0xCB, &disable); 2720 2721 if (disable & 0x02) 2722 return; 2723 2724 pci_read_config_byte(dev, 0xCA, &write_enable); 2725 pci_write_config_byte(dev, 0xCA, 0x57); 2726 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2727 pci_write_config_byte(dev, 0xCA, write_enable); 2728 2729 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2730 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2731 2732 } 2733 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2734 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2735 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2736 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2737 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2738 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2739 #endif /*CONFIG_MMC_RICOH_MMC*/ 2740 2741 #ifdef CONFIG_DMAR_TABLE 2742 #define VTUNCERRMSK_REG 0x1ac 2743 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2744 /* 2745 * This is a quirk for masking vt-d spec defined errors to platform error 2746 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2747 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2748 * on the RAS config settings of the platform) when a vt-d fault happens. 2749 * The resulting SMI caused the system to hang. 2750 * 2751 * VT-d spec related errors are already handled by the VT-d OS code, so no 2752 * need to report the same error through other channels. 2753 */ 2754 static void vtd_mask_spec_errors(struct pci_dev *dev) 2755 { 2756 u32 word; 2757 2758 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2759 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2760 } 2761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2763 #endif 2764 2765 static void fixup_ti816x_class(struct pci_dev *dev) 2766 { 2767 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2768 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); 2769 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; 2770 } 2771 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2772 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); 2773 2774 /* Some PCIe devices do not work reliably with the claimed maximum 2775 * payload size supported. 2776 */ 2777 static void fixup_mpss_256(struct pci_dev *dev) 2778 { 2779 dev->pcie_mpss = 1; /* 256 bytes */ 2780 } 2781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2782 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2784 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2786 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2787 2788 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2789 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2790 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2791 * until all of the devices are discovered and buses walked, read completion 2792 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2793 * it is possible to hotplug a device with MPS of 256B. 2794 */ 2795 static void quirk_intel_mc_errata(struct pci_dev *dev) 2796 { 2797 int err; 2798 u16 rcc; 2799 2800 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 2801 return; 2802 2803 /* Intel errata specifies bits to change but does not say what they are. 2804 * Keeping them magical until such time as the registers and values can 2805 * be explained. 2806 */ 2807 err = pci_read_config_word(dev, 0x48, &rcc); 2808 if (err) { 2809 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 2810 return; 2811 } 2812 2813 if (!(rcc & (1 << 10))) 2814 return; 2815 2816 rcc &= ~(1 << 10); 2817 2818 err = pci_write_config_word(dev, 0x48, rcc); 2819 if (err) { 2820 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 2821 return; 2822 } 2823 2824 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 2825 } 2826 /* Intel 5000 series memory controllers and ports 2-7 */ 2827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2836 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2837 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2838 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2839 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2841 /* Intel 5100 series memory controllers and ports 2-7 */ 2842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2853 2854 2855 /* 2856 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 2857 * work around this, query the size it should be configured to by the device and 2858 * modify the resource end to correspond to this new size. 2859 */ 2860 static void quirk_intel_ntb(struct pci_dev *dev) 2861 { 2862 int rc; 2863 u8 val; 2864 2865 rc = pci_read_config_byte(dev, 0x00D0, &val); 2866 if (rc) 2867 return; 2868 2869 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 2870 2871 rc = pci_read_config_byte(dev, 0x00D1, &val); 2872 if (rc) 2873 return; 2874 2875 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 2876 } 2877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 2878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 2879 2880 static ktime_t fixup_debug_start(struct pci_dev *dev, 2881 void (*fn)(struct pci_dev *dev)) 2882 { 2883 ktime_t calltime = ktime_set(0, 0); 2884 2885 dev_dbg(&dev->dev, "calling %pF\n", fn); 2886 if (initcall_debug) { 2887 pr_debug("calling %pF @ %i for %s\n", 2888 fn, task_pid_nr(current), dev_name(&dev->dev)); 2889 calltime = ktime_get(); 2890 } 2891 2892 return calltime; 2893 } 2894 2895 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 2896 void (*fn)(struct pci_dev *dev)) 2897 { 2898 ktime_t delta, rettime; 2899 unsigned long long duration; 2900 2901 if (initcall_debug) { 2902 rettime = ktime_get(); 2903 delta = ktime_sub(rettime, calltime); 2904 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 2905 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 2906 fn, duration, dev_name(&dev->dev)); 2907 } 2908 } 2909 2910 /* 2911 * Some BIOS implementations leave the Intel GPU interrupts enabled, 2912 * even though no one is handling them (f.e. i915 driver is never loaded). 2913 * Additionally the interrupt destination is not set up properly 2914 * and the interrupt ends up -somewhere-. 2915 * 2916 * These spurious interrupts are "sticky" and the kernel disables 2917 * the (shared) interrupt line after 100.000+ generated interrupts. 2918 * 2919 * Fix it by disabling the still enabled interrupts. 2920 * This resolves crashes often seen on monitor unplug. 2921 */ 2922 #define I915_DEIER_REG 0x4400c 2923 static void disable_igfx_irq(struct pci_dev *dev) 2924 { 2925 void __iomem *regs = pci_iomap(dev, 0, 0); 2926 if (regs == NULL) { 2927 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 2928 return; 2929 } 2930 2931 /* Check if any interrupt line is still enabled */ 2932 if (readl(regs + I915_DEIER_REG) != 0) { 2933 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 2934 2935 writel(0, regs + I915_DEIER_REG); 2936 } 2937 2938 pci_iounmap(dev, regs); 2939 } 2940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 2941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 2942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 2943 2944 /* 2945 * PCI devices which are on Intel chips can skip the 10ms delay 2946 * before entering D3 mode. 2947 */ 2948 static void quirk_remove_d3_delay(struct pci_dev *dev) 2949 { 2950 dev->d3_delay = 0; 2951 } 2952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 2953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 2954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 2955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 2956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 2957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 2958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 2959 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 2960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 2961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 2962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 2963 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 2964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 2965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 2966 2967 /* 2968 * Some devices may pass our check in pci_intx_mask_supported if 2969 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 2970 * support this feature. 2971 */ 2972 static void quirk_broken_intx_masking(struct pci_dev *dev) 2973 { 2974 dev->broken_intx_masking = 1; 2975 } 2976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, 2977 quirk_broken_intx_masking); 2978 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 2979 quirk_broken_intx_masking); 2980 /* 2981 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 2982 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 2983 * 2984 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 2985 */ 2986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169, 2987 quirk_broken_intx_masking); 2988 2989 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2990 struct pci_fixup *end) 2991 { 2992 ktime_t calltime; 2993 2994 for (; f < end; f++) 2995 if ((f->class == (u32) (dev->class >> f->class_shift) || 2996 f->class == (u32) PCI_ANY_ID) && 2997 (f->vendor == dev->vendor || 2998 f->vendor == (u16) PCI_ANY_ID) && 2999 (f->device == dev->device || 3000 f->device == (u16) PCI_ANY_ID)) { 3001 calltime = fixup_debug_start(dev, f->hook); 3002 f->hook(dev); 3003 fixup_debug_report(dev, calltime, f->hook); 3004 } 3005 } 3006 3007 extern struct pci_fixup __start_pci_fixups_early[]; 3008 extern struct pci_fixup __end_pci_fixups_early[]; 3009 extern struct pci_fixup __start_pci_fixups_header[]; 3010 extern struct pci_fixup __end_pci_fixups_header[]; 3011 extern struct pci_fixup __start_pci_fixups_final[]; 3012 extern struct pci_fixup __end_pci_fixups_final[]; 3013 extern struct pci_fixup __start_pci_fixups_enable[]; 3014 extern struct pci_fixup __end_pci_fixups_enable[]; 3015 extern struct pci_fixup __start_pci_fixups_resume[]; 3016 extern struct pci_fixup __end_pci_fixups_resume[]; 3017 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3018 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3019 extern struct pci_fixup __start_pci_fixups_suspend[]; 3020 extern struct pci_fixup __end_pci_fixups_suspend[]; 3021 3022 static bool pci_apply_fixup_final_quirks; 3023 3024 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3025 { 3026 struct pci_fixup *start, *end; 3027 3028 switch (pass) { 3029 case pci_fixup_early: 3030 start = __start_pci_fixups_early; 3031 end = __end_pci_fixups_early; 3032 break; 3033 3034 case pci_fixup_header: 3035 start = __start_pci_fixups_header; 3036 end = __end_pci_fixups_header; 3037 break; 3038 3039 case pci_fixup_final: 3040 if (!pci_apply_fixup_final_quirks) 3041 return; 3042 start = __start_pci_fixups_final; 3043 end = __end_pci_fixups_final; 3044 break; 3045 3046 case pci_fixup_enable: 3047 start = __start_pci_fixups_enable; 3048 end = __end_pci_fixups_enable; 3049 break; 3050 3051 case pci_fixup_resume: 3052 start = __start_pci_fixups_resume; 3053 end = __end_pci_fixups_resume; 3054 break; 3055 3056 case pci_fixup_resume_early: 3057 start = __start_pci_fixups_resume_early; 3058 end = __end_pci_fixups_resume_early; 3059 break; 3060 3061 case pci_fixup_suspend: 3062 start = __start_pci_fixups_suspend; 3063 end = __end_pci_fixups_suspend; 3064 break; 3065 3066 default: 3067 /* stupid compiler warning, you would think with an enum... */ 3068 return; 3069 } 3070 pci_do_fixups(dev, start, end); 3071 } 3072 EXPORT_SYMBOL(pci_fixup_device); 3073 3074 3075 static int __init pci_apply_final_quirks(void) 3076 { 3077 struct pci_dev *dev = NULL; 3078 u8 cls = 0; 3079 u8 tmp; 3080 3081 if (pci_cache_line_size) 3082 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3083 pci_cache_line_size << 2); 3084 3085 pci_apply_fixup_final_quirks = true; 3086 for_each_pci_dev(dev) { 3087 pci_fixup_device(pci_fixup_final, dev); 3088 /* 3089 * If arch hasn't set it explicitly yet, use the CLS 3090 * value shared by all PCI devices. If there's a 3091 * mismatch, fall back to the default value. 3092 */ 3093 if (!pci_cache_line_size) { 3094 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3095 if (!cls) 3096 cls = tmp; 3097 if (!tmp || cls == tmp) 3098 continue; 3099 3100 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3101 cls << 2, tmp << 2, 3102 pci_dfl_cache_line_size << 2); 3103 pci_cache_line_size = pci_dfl_cache_line_size; 3104 } 3105 } 3106 3107 if (!pci_cache_line_size) { 3108 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3109 cls << 2, pci_dfl_cache_line_size << 2); 3110 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3111 } 3112 3113 return 0; 3114 } 3115 3116 fs_initcall_sync(pci_apply_final_quirks); 3117 3118 /* 3119 * Followings are device-specific reset methods which can be used to 3120 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3121 * not available. 3122 */ 3123 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 3124 { 3125 int pos; 3126 3127 /* only implement PCI_CLASS_SERIAL_USB at present */ 3128 if (dev->class == PCI_CLASS_SERIAL_USB) { 3129 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 3130 if (!pos) 3131 return -ENOTTY; 3132 3133 if (probe) 3134 return 0; 3135 3136 pci_write_config_byte(dev, pos + 0x4, 1); 3137 msleep(100); 3138 3139 return 0; 3140 } else { 3141 return -ENOTTY; 3142 } 3143 } 3144 3145 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3146 { 3147 /* 3148 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3149 * 3150 * The 82599 supports FLR on VFs, but FLR support is reported only 3151 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3152 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP. 3153 */ 3154 3155 if (probe) 3156 return 0; 3157 3158 if (!pci_wait_for_pending_transaction(dev)) 3159 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3160 3161 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3162 3163 msleep(100); 3164 3165 return 0; 3166 } 3167 3168 #include "../gpu/drm/i915/i915_reg.h" 3169 #define MSG_CTL 0x45010 3170 #define NSDE_PWR_STATE 0xd0100 3171 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3172 3173 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3174 { 3175 void __iomem *mmio_base; 3176 unsigned long timeout; 3177 u32 val; 3178 3179 if (probe) 3180 return 0; 3181 3182 mmio_base = pci_iomap(dev, 0, 0); 3183 if (!mmio_base) 3184 return -ENOMEM; 3185 3186 iowrite32(0x00000002, mmio_base + MSG_CTL); 3187 3188 /* 3189 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3190 * driver loaded sets the right bits. However, this's a reset and 3191 * the bits have been set by i915 previously, so we clobber 3192 * SOUTH_CHICKEN2 register directly here. 3193 */ 3194 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3195 3196 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3197 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3198 3199 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3200 do { 3201 val = ioread32(mmio_base + PCH_PP_STATUS); 3202 if ((val & 0xb0000000) == 0) 3203 goto reset_complete; 3204 msleep(10); 3205 } while (time_before(jiffies, timeout)); 3206 dev_warn(&dev->dev, "timeout during reset\n"); 3207 3208 reset_complete: 3209 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3210 3211 pci_iounmap(dev, mmio_base); 3212 return 0; 3213 } 3214 3215 /* 3216 * Device-specific reset method for Chelsio T4-based adapters. 3217 */ 3218 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3219 { 3220 u16 old_command; 3221 u16 msix_flags; 3222 3223 /* 3224 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3225 * that we have no device-specific reset method. 3226 */ 3227 if ((dev->device & 0xf000) != 0x4000) 3228 return -ENOTTY; 3229 3230 /* 3231 * If this is the "probe" phase, return 0 indicating that we can 3232 * reset this device. 3233 */ 3234 if (probe) 3235 return 0; 3236 3237 /* 3238 * T4 can wedge if there are DMAs in flight within the chip and Bus 3239 * Master has been disabled. We need to have it on till the Function 3240 * Level Reset completes. (BUS_MASTER is disabled in 3241 * pci_reset_function()). 3242 */ 3243 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3244 pci_write_config_word(dev, PCI_COMMAND, 3245 old_command | PCI_COMMAND_MASTER); 3246 3247 /* 3248 * Perform the actual device function reset, saving and restoring 3249 * configuration information around the reset. 3250 */ 3251 pci_save_state(dev); 3252 3253 /* 3254 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3255 * are disabled when an MSI-X interrupt message needs to be delivered. 3256 * So we briefly re-enable MSI-X interrupts for the duration of the 3257 * FLR. The pci_restore_state() below will restore the original 3258 * MSI-X state. 3259 */ 3260 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3261 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3262 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3263 msix_flags | 3264 PCI_MSIX_FLAGS_ENABLE | 3265 PCI_MSIX_FLAGS_MASKALL); 3266 3267 /* 3268 * Start of pcie_flr() code sequence. This reset code is a copy of 3269 * the guts of pcie_flr() because that's not an exported function. 3270 */ 3271 3272 if (!pci_wait_for_pending_transaction(dev)) 3273 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3274 3275 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3276 msleep(100); 3277 3278 /* 3279 * End of pcie_flr() code sequence. 3280 */ 3281 3282 /* 3283 * Restore the configuration information (BAR values, etc.) including 3284 * the original PCI Configuration Space Command word, and return 3285 * success. 3286 */ 3287 pci_restore_state(dev); 3288 pci_write_config_word(dev, PCI_COMMAND, old_command); 3289 return 0; 3290 } 3291 3292 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3293 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3294 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3295 3296 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3297 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3298 reset_intel_82599_sfp_virtfn }, 3299 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3300 reset_ivb_igd }, 3301 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3302 reset_ivb_igd }, 3303 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3304 reset_intel_generic_dev }, 3305 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3306 reset_chelsio_generic_dev }, 3307 { 0 } 3308 }; 3309 3310 /* 3311 * These device-specific reset methods are here rather than in a driver 3312 * because when a host assigns a device to a guest VM, the host may need 3313 * to reset the device but probably doesn't have a driver for it. 3314 */ 3315 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3316 { 3317 const struct pci_dev_reset_methods *i; 3318 3319 for (i = pci_dev_reset_methods; i->reset; i++) { 3320 if ((i->vendor == dev->vendor || 3321 i->vendor == (u16)PCI_ANY_ID) && 3322 (i->device == dev->device || 3323 i->device == (u16)PCI_ANY_ID)) 3324 return i->reset(dev, probe); 3325 } 3326 3327 return -ENOTTY; 3328 } 3329 3330 static void quirk_dma_func0_alias(struct pci_dev *dev) 3331 { 3332 if (PCI_FUNC(dev->devfn) != 0) { 3333 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); 3334 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3335 } 3336 } 3337 3338 /* 3339 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3340 * 3341 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3342 */ 3343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3345 3346 static void quirk_dma_func1_alias(struct pci_dev *dev) 3347 { 3348 if (PCI_FUNC(dev->devfn) != 1) { 3349 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); 3350 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3351 } 3352 } 3353 3354 /* 3355 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3356 * SKUs function 1 is present and is a legacy IDE controller, in other 3357 * SKUs this function is not present, making this a ghost requester. 3358 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3359 */ 3360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3361 quirk_dma_func1_alias); 3362 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3364 quirk_dma_func1_alias); 3365 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3367 quirk_dma_func1_alias); 3368 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3370 quirk_dma_func1_alias); 3371 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3373 quirk_dma_func1_alias); 3374 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3376 quirk_dma_func1_alias); 3377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3378 quirk_dma_func1_alias); 3379 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3381 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3382 quirk_dma_func1_alias); 3383 3384 /* 3385 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3386 * using the wrong DMA alias for the device. Some of these devices can be 3387 * used as either forward or reverse bridges, so we need to test whether the 3388 * device is operating in the correct mode. We could probably apply this 3389 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3390 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3391 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3392 */ 3393 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3394 { 3395 if (!pci_is_root_bus(pdev->bus) && 3396 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3397 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3398 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3399 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3400 } 3401 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3403 quirk_use_pcie_bridge_dma_alias); 3404 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3405 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3406 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3407 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3408 3409 static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev) 3410 { 3411 if (!PCI_FUNC(dev->devfn)) 3412 return pci_dev_get(dev); 3413 3414 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3415 } 3416 3417 static const struct pci_dev_dma_source { 3418 u16 vendor; 3419 u16 device; 3420 struct pci_dev *(*dma_source)(struct pci_dev *dev); 3421 } pci_dev_dma_source[] = { 3422 /* 3423 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3424 * 3425 * Some Ricoh devices use the function 0 source ID for DMA on 3426 * other functions of a multifunction device. The DMA devices 3427 * is therefore function 0, which will have implications of the 3428 * iommu grouping of these devices. 3429 */ 3430 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source }, 3431 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source }, 3432 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source }, 3433 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source }, 3434 { 0 } 3435 }; 3436 3437 /* 3438 * IOMMUs with isolation capabilities need to be programmed with the 3439 * correct source ID of a device. In most cases, the source ID matches 3440 * the device doing the DMA, but sometimes hardware is broken and will 3441 * tag the DMA as being sourced from a different device. This function 3442 * allows that translation. Note that the reference count of the 3443 * returned device is incremented on all paths. 3444 */ 3445 struct pci_dev *pci_get_dma_source(struct pci_dev *dev) 3446 { 3447 const struct pci_dev_dma_source *i; 3448 3449 for (i = pci_dev_dma_source; i->dma_source; i++) { 3450 if ((i->vendor == dev->vendor || 3451 i->vendor == (u16)PCI_ANY_ID) && 3452 (i->device == dev->device || 3453 i->device == (u16)PCI_ANY_ID)) 3454 return i->dma_source(dev); 3455 } 3456 3457 return pci_dev_get(dev); 3458 } 3459 3460 /* 3461 * AMD has indicated that the devices below do not support peer-to-peer 3462 * in any system where they are found in the southbridge with an AMD 3463 * IOMMU in the system. Multifunction devices that do not support 3464 * peer-to-peer between functions can claim to support a subset of ACS. 3465 * Such devices effectively enable request redirect (RR) and completion 3466 * redirect (CR) since all transactions are redirected to the upstream 3467 * root complex. 3468 * 3469 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 3470 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 3471 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 3472 * 3473 * 1002:4385 SBx00 SMBus Controller 3474 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 3475 * 1002:4383 SBx00 Azalia (Intel HDA) 3476 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 3477 * 1002:4384 SBx00 PCI to PCI Bridge 3478 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 3479 */ 3480 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 3481 { 3482 #ifdef CONFIG_ACPI 3483 struct acpi_table_header *header = NULL; 3484 acpi_status status; 3485 3486 /* Targeting multifunction devices on the SB (appears on root bus) */ 3487 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 3488 return -ENODEV; 3489 3490 /* The IVRS table describes the AMD IOMMU */ 3491 status = acpi_get_table("IVRS", 0, &header); 3492 if (ACPI_FAILURE(status)) 3493 return -ENODEV; 3494 3495 /* Filter out flags not applicable to multifunction */ 3496 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 3497 3498 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 3499 #else 3500 return -ENODEV; 3501 #endif 3502 } 3503 3504 /* 3505 * Many Intel PCH root ports do provide ACS-like features to disable peer 3506 * transactions and validate bus numbers in requests, but do not provide an 3507 * actual PCIe ACS capability. This is the list of device IDs known to fall 3508 * into that category as provided by Intel in Red Hat bugzilla 1037684. 3509 */ 3510 static const u16 pci_quirk_intel_pch_acs_ids[] = { 3511 /* Ibexpeak PCH */ 3512 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 3513 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 3514 /* Cougarpoint PCH */ 3515 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 3516 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 3517 /* Pantherpoint PCH */ 3518 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 3519 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 3520 /* Lynxpoint-H PCH */ 3521 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 3522 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 3523 /* Lynxpoint-LP PCH */ 3524 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 3525 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 3526 /* Wildcat PCH */ 3527 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 3528 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 3529 /* Patsburg (X79) PCH */ 3530 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 3531 }; 3532 3533 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 3534 { 3535 int i; 3536 3537 /* Filter out a few obvious non-matches first */ 3538 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 3539 return false; 3540 3541 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 3542 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 3543 return true; 3544 3545 return false; 3546 } 3547 3548 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 3549 3550 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 3551 { 3552 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 3553 INTEL_PCH_ACS_FLAGS : 0; 3554 3555 if (!pci_quirk_intel_pch_acs_match(dev)) 3556 return -ENOTTY; 3557 3558 return acs_flags & ~flags ? 0 : 1; 3559 } 3560 3561 static const struct pci_dev_acs_enabled { 3562 u16 vendor; 3563 u16 device; 3564 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 3565 } pci_dev_acs_enabled[] = { 3566 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 3567 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 3568 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 3569 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 3570 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 3571 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 3572 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 3573 { 0 } 3574 }; 3575 3576 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 3577 { 3578 const struct pci_dev_acs_enabled *i; 3579 int ret; 3580 3581 /* 3582 * Allow devices that do not expose standard PCIe ACS capabilities 3583 * or control to indicate their support here. Multi-function express 3584 * devices which do not allow internal peer-to-peer between functions, 3585 * but do not implement PCIe ACS may wish to return true here. 3586 */ 3587 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 3588 if ((i->vendor == dev->vendor || 3589 i->vendor == (u16)PCI_ANY_ID) && 3590 (i->device == dev->device || 3591 i->device == (u16)PCI_ANY_ID)) { 3592 ret = i->acs_enabled(dev, acs_flags); 3593 if (ret >= 0) 3594 return ret; 3595 } 3596 } 3597 3598 return -ENOTTY; 3599 } 3600 3601 /* Config space offset of Root Complex Base Address register */ 3602 #define INTEL_LPC_RCBA_REG 0xf0 3603 /* 31:14 RCBA address */ 3604 #define INTEL_LPC_RCBA_MASK 0xffffc000 3605 /* RCBA Enable */ 3606 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 3607 3608 /* Backbone Scratch Pad Register */ 3609 #define INTEL_BSPR_REG 0x1104 3610 /* Backbone Peer Non-Posted Disable */ 3611 #define INTEL_BSPR_REG_BPNPD (1 << 8) 3612 /* Backbone Peer Posted Disable */ 3613 #define INTEL_BSPR_REG_BPPD (1 << 9) 3614 3615 /* Upstream Peer Decode Configuration Register */ 3616 #define INTEL_UPDCR_REG 0x1114 3617 /* 5:0 Peer Decode Enable bits */ 3618 #define INTEL_UPDCR_REG_MASK 0x3f 3619 3620 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 3621 { 3622 u32 rcba, bspr, updcr; 3623 void __iomem *rcba_mem; 3624 3625 /* 3626 * Read the RCBA register from the LPC (D31:F0). PCH root ports 3627 * are D28:F* and therefore get probed before LPC, thus we can't 3628 * use pci_get_slot/pci_read_config_dword here. 3629 */ 3630 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 3631 INTEL_LPC_RCBA_REG, &rcba); 3632 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 3633 return -EINVAL; 3634 3635 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 3636 PAGE_ALIGN(INTEL_UPDCR_REG)); 3637 if (!rcba_mem) 3638 return -ENOMEM; 3639 3640 /* 3641 * The BSPR can disallow peer cycles, but it's set by soft strap and 3642 * therefore read-only. If both posted and non-posted peer cycles are 3643 * disallowed, we're ok. If either are allowed, then we need to use 3644 * the UPDCR to disable peer decodes for each port. This provides the 3645 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 3646 */ 3647 bspr = readl(rcba_mem + INTEL_BSPR_REG); 3648 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 3649 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 3650 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 3651 if (updcr & INTEL_UPDCR_REG_MASK) { 3652 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 3653 updcr &= ~INTEL_UPDCR_REG_MASK; 3654 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 3655 } 3656 } 3657 3658 iounmap(rcba_mem); 3659 return 0; 3660 } 3661 3662 /* Miscellaneous Port Configuration register */ 3663 #define INTEL_MPC_REG 0xd8 3664 /* MPC: Invalid Receive Bus Number Check Enable */ 3665 #define INTEL_MPC_REG_IRBNCE (1 << 26) 3666 3667 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 3668 { 3669 u32 mpc; 3670 3671 /* 3672 * When enabled, the IRBNCE bit of the MPC register enables the 3673 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 3674 * ensures that requester IDs fall within the bus number range 3675 * of the bridge. Enable if not already. 3676 */ 3677 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 3678 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 3679 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 3680 mpc |= INTEL_MPC_REG_IRBNCE; 3681 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 3682 } 3683 } 3684 3685 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 3686 { 3687 if (!pci_quirk_intel_pch_acs_match(dev)) 3688 return -ENOTTY; 3689 3690 if (pci_quirk_enable_intel_lpc_acs(dev)) { 3691 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 3692 return 0; 3693 } 3694 3695 pci_quirk_enable_intel_rp_mpc_acs(dev); 3696 3697 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 3698 3699 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 3700 3701 return 0; 3702 } 3703 3704 static const struct pci_dev_enable_acs { 3705 u16 vendor; 3706 u16 device; 3707 int (*enable_acs)(struct pci_dev *dev); 3708 } pci_dev_enable_acs[] = { 3709 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 3710 { 0 } 3711 }; 3712 3713 void pci_dev_specific_enable_acs(struct pci_dev *dev) 3714 { 3715 const struct pci_dev_enable_acs *i; 3716 int ret; 3717 3718 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 3719 if ((i->vendor == dev->vendor || 3720 i->vendor == (u16)PCI_ANY_ID) && 3721 (i->device == dev->device || 3722 i->device == (u16)PCI_ANY_ID)) { 3723 ret = i->enable_acs(dev); 3724 if (ret >= 0) 3725 return; 3726 } 3727 } 3728 } 3729