1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/config.h> 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/acpi.h> 25 #include "pci.h" 26 27 /* Deal with broken BIOS'es that neglect to enable passive release, 28 which can cause problems in combination with the 82441FX/PPro MTRRs */ 29 static void __devinit quirk_passive_release(struct pci_dev *dev) 30 { 31 struct pci_dev *d = NULL; 32 unsigned char dlc; 33 34 /* We have to make sure a particular bit is set in the PIIX3 35 ISA bridge, so we have to go out and find it. */ 36 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 37 pci_read_config_byte(d, 0x82, &dlc); 38 if (!(dlc & 1<<1)) { 39 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 40 dlc |= 1<<1; 41 pci_write_config_byte(d, 0x82, dlc); 42 } 43 } 44 } 45 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 46 47 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 48 but VIA don't answer queries. If you happen to have good contacts at VIA 49 ask them for me please -- Alan 50 51 This appears to be BIOS not version dependent. So presumably there is a 52 chipset level fix */ 53 int isa_dma_bridge_buggy; /* Exported */ 54 55 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 56 { 57 if (!isa_dma_bridge_buggy) { 58 isa_dma_bridge_buggy=1; 59 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 60 } 61 } 62 /* 63 * Its not totally clear which chipsets are the problematic ones 64 * We know 82C586 and 82C596 variants are affected. 65 */ 66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 70 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 71 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 72 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 73 74 int pci_pci_problems; 75 76 /* 77 * Chipsets where PCI->PCI transfers vanish or hang 78 */ 79 static void __devinit quirk_nopcipci(struct pci_dev *dev) 80 { 81 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 82 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 83 pci_pci_problems |= PCIPCI_FAIL; 84 } 85 } 86 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 87 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 88 89 /* 90 * Triton requires workarounds to be used by the drivers 91 */ 92 static void __devinit quirk_triton(struct pci_dev *dev) 93 { 94 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 95 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 96 pci_pci_problems |= PCIPCI_TRITON; 97 } 98 } 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 103 104 /* 105 * VIA Apollo KT133 needs PCI latency patch 106 * Made according to a windows driver based patch by George E. Breese 107 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 108 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 109 * the info on which Mr Breese based his work. 110 * 111 * Updated based on further information from the site and also on 112 * information provided by VIA 113 */ 114 static void __devinit quirk_vialatency(struct pci_dev *dev) 115 { 116 struct pci_dev *p; 117 u8 rev; 118 u8 busarb; 119 /* Ok we have a potential problem chipset here. Now see if we have 120 a buggy southbridge */ 121 122 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 123 if (p!=NULL) { 124 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 125 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 126 /* Check for buggy part revisions */ 127 if (rev < 0x40 || rev > 0x42) 128 goto exit; 129 } else { 130 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 131 if (p==NULL) /* No problem parts */ 132 goto exit; 133 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 134 /* Check for buggy part revisions */ 135 if (rev < 0x10 || rev > 0x12) 136 goto exit; 137 } 138 139 /* 140 * Ok we have the problem. Now set the PCI master grant to 141 * occur every master grant. The apparent bug is that under high 142 * PCI load (quite common in Linux of course) you can get data 143 * loss when the CPU is held off the bus for 3 bus master requests 144 * This happens to include the IDE controllers.... 145 * 146 * VIA only apply this fix when an SB Live! is present but under 147 * both Linux and Windows this isnt enough, and we have seen 148 * corruption without SB Live! but with things like 3 UDMA IDE 149 * controllers. So we ignore that bit of the VIA recommendation.. 150 */ 151 152 pci_read_config_byte(dev, 0x76, &busarb); 153 /* Set bit 4 and bi 5 of byte 76 to 0x01 154 "Master priority rotation on every PCI master grant */ 155 busarb &= ~(1<<5); 156 busarb |= (1<<4); 157 pci_write_config_byte(dev, 0x76, busarb); 158 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 159 exit: 160 pci_dev_put(p); 161 } 162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 165 166 /* 167 * VIA Apollo VP3 needs ETBF on BT848/878 168 */ 169 static void __devinit quirk_viaetbf(struct pci_dev *dev) 170 { 171 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 172 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 173 pci_pci_problems |= PCIPCI_VIAETBF; 174 } 175 } 176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 177 178 static void __devinit quirk_vsfx(struct pci_dev *dev) 179 { 180 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 181 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 182 pci_pci_problems |= PCIPCI_VSFX; 183 } 184 } 185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 186 187 /* 188 * Ali Magik requires workarounds to be used by the drivers 189 * that DMA to AGP space. Latency must be set to 0xA and triton 190 * workaround applied too 191 * [Info kindly provided by ALi] 192 */ 193 static void __init quirk_alimagik(struct pci_dev *dev) 194 { 195 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 196 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 197 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 198 } 199 } 200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 202 203 /* 204 * Natoma has some interesting boundary conditions with Zoran stuff 205 * at least 206 */ 207 static void __devinit quirk_natoma(struct pci_dev *dev) 208 { 209 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 210 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 211 pci_pci_problems |= PCIPCI_NATOMA; 212 } 213 } 214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 220 221 /* 222 * This chip can cause PCI parity errors if config register 0xA0 is read 223 * while DMAs are occurring. 224 */ 225 static void __devinit quirk_citrine(struct pci_dev *dev) 226 { 227 dev->cfg_size = 0xA0; 228 } 229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 230 231 /* 232 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 233 * If it's needed, re-allocate the region. 234 */ 235 static void __devinit quirk_s3_64M(struct pci_dev *dev) 236 { 237 struct resource *r = &dev->resource[0]; 238 239 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 240 r->start = 0; 241 r->end = 0x3ffffff; 242 } 243 } 244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 246 247 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 248 unsigned size, int nr, const char *name) 249 { 250 region &= ~(size-1); 251 if (region) { 252 struct pci_bus_region bus_region; 253 struct resource *res = dev->resource + nr; 254 255 res->name = pci_name(dev); 256 res->start = region; 257 res->end = region + size - 1; 258 res->flags = IORESOURCE_IO; 259 260 /* Convert from PCI bus to resource space. */ 261 bus_region.start = res->start; 262 bus_region.end = res->end; 263 pcibios_bus_to_resource(dev, res, &bus_region); 264 265 pci_claim_resource(dev, nr); 266 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 267 } 268 } 269 270 /* 271 * ATI Northbridge setups MCE the processor if you even 272 * read somewhere between 0x3b0->0x3bb or read 0x3d3 273 */ 274 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 275 { 276 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 277 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 278 request_region(0x3b0, 0x0C, "RadeonIGP"); 279 request_region(0x3d3, 0x01, "RadeonIGP"); 280 } 281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 282 283 /* 284 * Let's make the southbridge information explicit instead 285 * of having to worry about people probing the ACPI areas, 286 * for example.. (Yes, it happens, and if you read the wrong 287 * ACPI register it will put the machine to sleep with no 288 * way of waking it up again. Bummer). 289 * 290 * ALI M7101: Two IO regions pointed to by words at 291 * 0xE0 (64 bytes of ACPI registers) 292 * 0xE2 (32 bytes of SMB registers) 293 */ 294 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 295 { 296 u16 region; 297 298 pci_read_config_word(dev, 0xE0, ®ion); 299 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 300 pci_read_config_word(dev, 0xE2, ®ion); 301 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 302 } 303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 304 305 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 306 { 307 u32 devres; 308 u32 mask, size, base; 309 310 pci_read_config_dword(dev, port, &devres); 311 if ((devres & enable) != enable) 312 return; 313 mask = (devres >> 16) & 15; 314 base = devres & 0xffff; 315 size = 16; 316 for (;;) { 317 unsigned bit = size >> 1; 318 if ((bit & mask) == bit) 319 break; 320 size = bit; 321 } 322 /* 323 * For now we only print it out. Eventually we'll want to 324 * reserve it (at least if it's in the 0x1000+ range), but 325 * let's get enough confirmation reports first. 326 */ 327 base &= -size; 328 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 329 } 330 331 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 332 { 333 u32 devres; 334 u32 mask, size, base; 335 336 pci_read_config_dword(dev, port, &devres); 337 if ((devres & enable) != enable) 338 return; 339 base = devres & 0xffff0000; 340 mask = (devres & 0x3f) << 16; 341 size = 128 << 16; 342 for (;;) { 343 unsigned bit = size >> 1; 344 if ((bit & mask) == bit) 345 break; 346 size = bit; 347 } 348 /* 349 * For now we only print it out. Eventually we'll want to 350 * reserve it, but let's get enough confirmation reports first. 351 */ 352 base &= -size; 353 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 354 } 355 356 /* 357 * PIIX4 ACPI: Two IO regions pointed to by longwords at 358 * 0x40 (64 bytes of ACPI registers) 359 * 0x90 (16 bytes of SMB registers) 360 * and a few strange programmable PIIX4 device resources. 361 */ 362 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 363 { 364 u32 region, res_a; 365 366 pci_read_config_dword(dev, 0x40, ®ion); 367 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 368 pci_read_config_dword(dev, 0x90, ®ion); 369 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 370 371 /* Device resource A has enables for some of the other ones */ 372 pci_read_config_dword(dev, 0x5c, &res_a); 373 374 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 375 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 376 377 /* Device resource D is just bitfields for static resources */ 378 379 /* Device 12 enabled? */ 380 if (res_a & (1 << 29)) { 381 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 382 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 383 } 384 /* Device 13 enabled? */ 385 if (res_a & (1 << 30)) { 386 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 387 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 388 } 389 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 390 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 391 } 392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 393 394 /* 395 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 396 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 397 * 0x58 (64 bytes of GPIO I/O space) 398 */ 399 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 400 { 401 u32 region; 402 403 pci_read_config_dword(dev, 0x40, ®ion); 404 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 405 406 pci_read_config_dword(dev, 0x58, ®ion); 407 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 408 } 409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 419 420 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 421 { 422 u32 region; 423 424 pci_read_config_dword(dev, 0x40, ®ion); 425 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 426 427 pci_read_config_dword(dev, 0x48, ®ion); 428 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 429 } 430 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 431 432 /* 433 * VIA ACPI: One IO region pointed to by longword at 434 * 0x48 or 0x20 (256 bytes of ACPI registers) 435 */ 436 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 437 { 438 u8 rev; 439 u32 region; 440 441 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 442 if (rev & 0x10) { 443 pci_read_config_dword(dev, 0x48, ®ion); 444 region &= PCI_BASE_ADDRESS_IO_MASK; 445 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 446 } 447 } 448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 449 450 /* 451 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 452 * 0x48 (256 bytes of ACPI registers) 453 * 0x70 (128 bytes of hardware monitoring register) 454 * 0x90 (16 bytes of SMB registers) 455 */ 456 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 457 { 458 u16 hm; 459 u32 smb; 460 461 quirk_vt82c586_acpi(dev); 462 463 pci_read_config_word(dev, 0x70, &hm); 464 hm &= PCI_BASE_ADDRESS_IO_MASK; 465 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 466 467 pci_read_config_dword(dev, 0x90, &smb); 468 smb &= PCI_BASE_ADDRESS_IO_MASK; 469 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 470 } 471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 472 473 /* 474 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 475 * 0x88 (128 bytes of power management registers) 476 * 0xd0 (16 bytes of SMB registers) 477 */ 478 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 479 { 480 u16 pm, smb; 481 482 pci_read_config_word(dev, 0x88, &pm); 483 pm &= PCI_BASE_ADDRESS_IO_MASK; 484 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 485 486 pci_read_config_word(dev, 0xd0, &smb); 487 smb &= PCI_BASE_ADDRESS_IO_MASK; 488 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 489 } 490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 491 492 493 #ifdef CONFIG_X86_IO_APIC 494 495 #include <asm/io_apic.h> 496 497 /* 498 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 499 * devices to the external APIC. 500 * 501 * TODO: When we have device-specific interrupt routers, 502 * this code will go away from quirks. 503 */ 504 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 505 { 506 u8 tmp; 507 508 if (nr_ioapics < 1) 509 tmp = 0; /* nothing routed to external APIC */ 510 else 511 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 512 513 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 514 tmp == 0 ? "Disa" : "Ena"); 515 516 /* Offset 0x58: External APIC IRQ output control */ 517 pci_write_config_byte (dev, 0x58, tmp); 518 } 519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 520 521 /* 522 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 523 * This leads to doubled level interrupt rates. 524 * Set this bit to get rid of cycle wastage. 525 * Otherwise uncritical. 526 */ 527 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 528 { 529 u8 misc_control2; 530 #define BYPASS_APIC_DEASSERT 8 531 532 pci_read_config_byte(dev, 0x5B, &misc_control2); 533 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 534 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 535 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 536 } 537 } 538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 539 540 /* 541 * The AMD io apic can hang the box when an apic irq is masked. 542 * We check all revs >= B0 (yet not in the pre production!) as the bug 543 * is currently marked NoFix 544 * 545 * We have multiple reports of hangs with this chipset that went away with 546 * noapic specified. For the moment we assume its the errata. We may be wrong 547 * of course. However the advice is demonstrably good even if so.. 548 */ 549 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 550 { 551 u8 rev; 552 553 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 554 if (rev >= 0x02) { 555 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 556 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 557 } 558 } 559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 560 561 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 562 { 563 if (dev->devfn == 0 && dev->bus->number == 0) 564 sis_apic_bug = 1; 565 } 566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 567 568 int pci_msi_quirk; 569 570 #define AMD8131_revA0 0x01 571 #define AMD8131_revB0 0x11 572 #define AMD8131_MISC 0x40 573 #define AMD8131_NIOAMODE_BIT 0 574 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 575 { 576 unsigned char revid, tmp; 577 578 pci_msi_quirk = 1; 579 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 580 581 if (nr_ioapics == 0) 582 return; 583 584 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 585 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 586 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 587 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 588 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 589 pci_write_config_byte( dev, AMD8131_MISC, tmp); 590 } 591 } 592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic ); 593 594 static void __init quirk_svw_msi(struct pci_dev *dev) 595 { 596 pci_msi_quirk = 1; 597 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 598 } 599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 600 #endif /* CONFIG_X86_IO_APIC */ 601 602 603 /* 604 * FIXME: it is questionable that quirk_via_acpi 605 * is needed. It shows up as an ISA bridge, and does not 606 * support the PCI_INTERRUPT_LINE register at all. Therefore 607 * it seems like setting the pci_dev's 'irq' to the 608 * value of the ACPI SCI interrupt is only done for convenience. 609 * -jgarzik 610 */ 611 static void __devinit quirk_via_acpi(struct pci_dev *d) 612 { 613 /* 614 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 615 */ 616 u8 irq; 617 pci_read_config_byte(d, 0x42, &irq); 618 irq &= 0xf; 619 if (irq && (irq != 2)) 620 d->irq = irq; 621 } 622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 624 625 /* 626 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 627 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 628 * when written, it makes an internal connection to the PIC. 629 * For these devices, this register is defined to be 4 bits wide. 630 * Normally this is fine. However for IO-APIC motherboards, or 631 * non-x86 architectures (yes Via exists on PPC among other places), 632 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 633 * interrupts delivered properly. 634 */ 635 static void quirk_via_irq(struct pci_dev *dev) 636 { 637 u8 irq, new_irq; 638 639 new_irq = dev->irq & 0xf; 640 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 641 if (new_irq != irq) { 642 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n", 643 pci_name(dev), irq, new_irq); 644 udelay(15); /* unknown if delay really needed */ 645 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 646 } 647 } 648 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq); 649 650 /* 651 * VIA VT82C598 has its device ID settable and many BIOSes 652 * set it to the ID of VT82C597 for backward compatibility. 653 * We need to switch it off to be able to recognize the real 654 * type of the chip. 655 */ 656 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 657 { 658 pci_write_config_byte(dev, 0xfc, 0); 659 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 660 } 661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 662 663 /* 664 * CardBus controllers have a legacy base address that enables them 665 * to respond as i82365 pcmcia controllers. We don't want them to 666 * do this even if the Linux CardBus driver is not loaded, because 667 * the Linux i82365 driver does not (and should not) handle CardBus. 668 */ 669 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 670 { 671 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 672 return; 673 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 674 } 675 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 676 677 /* 678 * Following the PCI ordering rules is optional on the AMD762. I'm not 679 * sure what the designers were smoking but let's not inhale... 680 * 681 * To be fair to AMD, it follows the spec by default, its BIOS people 682 * who turn it off! 683 */ 684 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 685 { 686 u32 pcic; 687 pci_read_config_dword(dev, 0x4C, &pcic); 688 if ((pcic&6)!=6) { 689 pcic |= 6; 690 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 691 pci_write_config_dword(dev, 0x4C, pcic); 692 pci_read_config_dword(dev, 0x84, &pcic); 693 pcic |= (1<<23); /* Required in this mode */ 694 pci_write_config_dword(dev, 0x84, pcic); 695 } 696 } 697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 698 699 /* 700 * DreamWorks provided workaround for Dunord I-3000 problem 701 * 702 * This card decodes and responds to addresses not apparently 703 * assigned to it. We force a larger allocation to ensure that 704 * nothing gets put too close to it. 705 */ 706 static void __devinit quirk_dunord ( struct pci_dev * dev ) 707 { 708 struct resource *r = &dev->resource [1]; 709 r->start = 0; 710 r->end = 0xffffff; 711 } 712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 713 714 /* 715 * i82380FB mobile docking controller: its PCI-to-PCI bridge 716 * is subtractive decoding (transparent), and does indicate this 717 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 718 * instead of 0x01. 719 */ 720 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 721 { 722 dev->transparent = 1; 723 } 724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 725 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 726 727 /* 728 * Common misconfiguration of the MediaGX/Geode PCI master that will 729 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 730 * datasheets found at http://www.national.com/ds/GX for info on what 731 * these bits do. <christer@weinigel.se> 732 */ 733 static void __init quirk_mediagx_master(struct pci_dev *dev) 734 { 735 u8 reg; 736 pci_read_config_byte(dev, 0x41, ®); 737 if (reg & 2) { 738 reg &= ~2; 739 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 740 pci_write_config_byte(dev, 0x41, reg); 741 } 742 } 743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 744 745 /* 746 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 747 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 748 * secondary channels respectively). If the device reports Compatible mode 749 * but does use BAR0-3 for address decoding, we assume that firmware has 750 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 751 * Exceptions (if they exist) must be handled in chip/architecture specific 752 * fixups. 753 * 754 * Note: for non x86 people. You may need an arch specific quirk to handle 755 * moving IDE devices to native mode as well. Some plug in card devices power 756 * up in compatible mode and assume the BIOS will adjust them. 757 * 758 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 759 * we do now ? We don't want is pci_enable_device to come along 760 * and assign new resources. Both approaches work for that. 761 */ 762 static void __devinit quirk_ide_bases(struct pci_dev *dev) 763 { 764 struct resource *res; 765 int first_bar = 2, last_bar = 0; 766 767 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 768 return; 769 770 res = &dev->resource[0]; 771 772 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 773 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 774 res[0].start = res[0].end = res[0].flags = 0; 775 res[1].start = res[1].end = res[1].flags = 0; 776 first_bar = 0; 777 last_bar = 1; 778 } 779 780 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 781 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 782 res[2].start = res[2].end = res[2].flags = 0; 783 res[3].start = res[3].end = res[3].flags = 0; 784 last_bar = 3; 785 } 786 787 if (!last_bar) 788 return; 789 790 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 791 first_bar, last_bar, pci_name(dev)); 792 } 793 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 794 795 /* 796 * Ensure C0 rev restreaming is off. This is normally done by 797 * the BIOS but in the odd case it is not the results are corruption 798 * hence the presence of a Linux check 799 */ 800 static void __init quirk_disable_pxb(struct pci_dev *pdev) 801 { 802 u16 config; 803 u8 rev; 804 805 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 806 if (rev != 0x04) /* Only C0 requires this */ 807 return; 808 pci_read_config_word(pdev, 0x40, &config); 809 if (config & (1<<6)) { 810 config &= ~(1<<6); 811 pci_write_config_word(pdev, 0x40, config); 812 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 813 } 814 } 815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 816 817 818 /* 819 * Serverworks CSB5 IDE does not fully support native mode 820 */ 821 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 822 { 823 u8 prog; 824 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 825 if (prog & 5) { 826 prog &= ~5; 827 pdev->class &= ~5; 828 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 829 /* need to re-assign BARs for compat mode */ 830 quirk_ide_bases(pdev); 831 } 832 } 833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 834 835 /* 836 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 837 */ 838 static void __init quirk_ide_samemode(struct pci_dev *pdev) 839 { 840 u8 prog; 841 842 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 843 844 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 845 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 846 prog &= ~5; 847 pdev->class &= ~5; 848 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 849 /* need to re-assign BARs for compat mode */ 850 quirk_ide_bases(pdev); 851 } 852 } 853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 854 855 /* This was originally an Alpha specific thing, but it really fits here. 856 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 857 */ 858 static void __init quirk_eisa_bridge(struct pci_dev *dev) 859 { 860 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 861 } 862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 863 864 /* 865 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 866 * is not activated. The myth is that Asus said that they do not want the 867 * users to be irritated by just another PCI Device in the Win98 device 868 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 869 * package 2.7.0 for details) 870 * 871 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 872 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 873 * becomes necessary to do this tweak in two steps -- I've chosen the Host 874 * bridge as trigger. 875 */ 876 static int __initdata asus_hides_smbus = 0; 877 878 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 879 { 880 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 881 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 882 switch(dev->subsystem_device) { 883 case 0x8025: /* P4B-LX */ 884 case 0x8070: /* P4B */ 885 case 0x8088: /* P4B533 */ 886 case 0x1626: /* L3C notebook */ 887 asus_hides_smbus = 1; 888 } 889 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 890 switch(dev->subsystem_device) { 891 case 0x80b1: /* P4GE-V */ 892 case 0x80b2: /* P4PE */ 893 case 0x8093: /* P4B533-V */ 894 asus_hides_smbus = 1; 895 } 896 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 897 switch(dev->subsystem_device) { 898 case 0x8030: /* P4T533 */ 899 asus_hides_smbus = 1; 900 } 901 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 902 switch (dev->subsystem_device) { 903 case 0x8070: /* P4G8X Deluxe */ 904 asus_hides_smbus = 1; 905 } 906 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 907 switch (dev->subsystem_device) { 908 case 0x1751: /* M2N notebook */ 909 case 0x1821: /* M5N notebook */ 910 asus_hides_smbus = 1; 911 } 912 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 913 switch (dev->subsystem_device) { 914 case 0x184b: /* W1N notebook */ 915 case 0x186a: /* M6Ne notebook */ 916 asus_hides_smbus = 1; 917 } 918 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { 919 switch (dev->subsystem_device) { 920 case 0x1882: /* M6V notebook */ 921 asus_hides_smbus = 1; 922 } 923 } 924 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 925 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 926 switch(dev->subsystem_device) { 927 case 0x088C: /* HP Compaq nc8000 */ 928 case 0x0890: /* HP Compaq nc6000 */ 929 asus_hides_smbus = 1; 930 } 931 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 932 switch (dev->subsystem_device) { 933 case 0x12bc: /* HP D330L */ 934 case 0x12bd: /* HP D530 */ 935 asus_hides_smbus = 1; 936 } 937 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 938 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 939 switch(dev->subsystem_device) { 940 case 0x0001: /* Toshiba Satellite A40 */ 941 asus_hides_smbus = 1; 942 } 943 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 944 switch(dev->subsystem_device) { 945 case 0x0001: /* Toshiba Tecra M2 */ 946 asus_hides_smbus = 1; 947 } 948 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 949 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 950 switch(dev->subsystem_device) { 951 case 0xC00C: /* Samsung P35 notebook */ 952 asus_hides_smbus = 1; 953 } 954 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 955 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 956 switch(dev->subsystem_device) { 957 case 0x0058: /* Compaq Evo N620c */ 958 asus_hides_smbus = 1; 959 } 960 } 961 } 962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 964 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 966 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 969 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 970 971 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 972 { 973 u16 val; 974 975 if (likely(!asus_hides_smbus)) 976 return; 977 978 pci_read_config_word(dev, 0xF2, &val); 979 if (val & 0x8) { 980 pci_write_config_word(dev, 0xF2, val & (~0x8)); 981 pci_read_config_word(dev, 0xF2, &val); 982 if (val & 0x8) 983 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 984 else 985 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 986 } 987 } 988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 993 994 static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 995 { 996 u32 val, rcba; 997 void __iomem *base; 998 999 if (likely(!asus_hides_smbus)) 1000 return; 1001 pci_read_config_dword(dev, 0xF0, &rcba); 1002 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ 1003 if (base == NULL) return; 1004 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1005 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1006 iounmap(base); 1007 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1008 } 1009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1010 1011 /* 1012 * SiS 96x south bridge: BIOS typically hides SMBus device... 1013 */ 1014 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 1015 { 1016 u8 val = 0; 1017 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1018 pci_read_config_byte(dev, 0x77, &val); 1019 pci_write_config_byte(dev, 0x77, val & ~0x10); 1020 pci_read_config_byte(dev, 0x77, &val); 1021 } 1022 1023 /* 1024 * ... This is further complicated by the fact that some SiS96x south 1025 * bridges pretend to be 85C503/5513 instead. In that case see if we 1026 * spotted a compatible north bridge to make sure. 1027 * (pci_find_device doesn't work yet) 1028 * 1029 * We can also enable the sis96x bit in the discovery register.. 1030 */ 1031 static int __devinitdata sis_96x_compatible = 0; 1032 1033 #define SIS_DETECT_REGISTER 0x40 1034 1035 static void __init quirk_sis_503(struct pci_dev *dev) 1036 { 1037 u8 reg; 1038 u16 devid; 1039 1040 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1041 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1042 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1043 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1044 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1045 return; 1046 } 1047 1048 /* Make people aware that we changed the config.. */ 1049 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1050 1051 /* 1052 * Ok, it now shows up as a 96x.. The 96x quirks are after 1053 * the 503 quirk in the quirk table, so they'll automatically 1054 * run and enable things like the SMBus device 1055 */ 1056 dev->device = devid; 1057 } 1058 1059 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1060 { 1061 sis_96x_compatible = 1; 1062 } 1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1069 1070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1071 1072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1076 1077 #ifdef CONFIG_X86_IO_APIC 1078 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1079 { 1080 int i; 1081 1082 if ((pdev->class >> 8) != 0xff00) 1083 return; 1084 1085 /* the first BAR is the location of the IO APIC...we must 1086 * not touch this (and it's already covered by the fixmap), so 1087 * forcibly insert it into the resource tree */ 1088 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1089 insert_resource(&iomem_resource, &pdev->resource[0]); 1090 1091 /* The next five BARs all seem to be rubbish, so just clean 1092 * them out */ 1093 for (i=1; i < 6; i++) { 1094 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1095 } 1096 1097 } 1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1099 #endif 1100 1101 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; 1102 /* Defaults to combined */ 1103 static enum ide_combined_type combined_mode; 1104 1105 static int __init combined_setup(char *str) 1106 { 1107 if (!strncmp(str, "ide", 3)) 1108 combined_mode = IDE; 1109 else if (!strncmp(str, "libata", 6)) 1110 combined_mode = LIBATA; 1111 else /* "combined" or anything else defaults to old behavior */ 1112 combined_mode = COMBINED; 1113 1114 return 1; 1115 } 1116 __setup("combined_mode=", combined_setup); 1117 1118 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED 1119 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1120 { 1121 u8 prog, comb, tmp; 1122 int ich = 0; 1123 1124 /* 1125 * Narrow down to Intel SATA PCI devices. 1126 */ 1127 switch (pdev->device) { 1128 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1129 case 0x24d1: 1130 case 0x24df: 1131 case 0x25a3: 1132 case 0x25b0: 1133 ich = 5; 1134 break; 1135 case 0x2651: 1136 case 0x2652: 1137 case 0x2653: 1138 case 0x2680: /* ESB2 */ 1139 ich = 6; 1140 break; 1141 case 0x27c0: 1142 case 0x27c4: 1143 ich = 7; 1144 break; 1145 default: 1146 /* we do not handle this PCI device */ 1147 return; 1148 } 1149 1150 /* 1151 * Read combined mode register. 1152 */ 1153 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1154 1155 if (ich == 5) { 1156 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1157 if (tmp == 0x4) /* bits 10x */ 1158 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1159 else if (tmp == 0x6) /* bits 11x */ 1160 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1161 else 1162 return; /* not in combined mode */ 1163 } else { 1164 WARN_ON((ich != 6) && (ich != 7)); 1165 tmp &= 0x3; /* interesting bits 1:0 */ 1166 if (tmp & (1 << 0)) 1167 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1168 else if (tmp & (1 << 1)) 1169 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1170 else 1171 return; /* not in combined mode */ 1172 } 1173 1174 /* 1175 * Read programming interface register. 1176 * (Tells us if it's legacy or native mode) 1177 */ 1178 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1179 1180 /* if SATA port is in native mode, we're ok. */ 1181 if (prog & comb) 1182 return; 1183 1184 /* Don't reserve any so the IDE driver can get them (but only if 1185 * combined_mode=ide). 1186 */ 1187 if (combined_mode == IDE) 1188 return; 1189 1190 /* Grab them both for libata if combined_mode=libata. */ 1191 if (combined_mode == LIBATA) { 1192 request_region(0x1f0, 8, "libata"); /* port 0 */ 1193 request_region(0x170, 8, "libata"); /* port 1 */ 1194 return; 1195 } 1196 1197 /* SATA port is in legacy mode. Reserve port so that 1198 * IDE driver does not attempt to use it. If request_region 1199 * fails, it will be obvious at boot time, so we don't bother 1200 * checking return values. 1201 */ 1202 if (comb == (1 << 0)) 1203 request_region(0x1f0, 8, "libata"); /* port 0 */ 1204 else 1205 request_region(0x170, 8, "libata"); /* port 1 */ 1206 } 1207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1208 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */ 1209 1210 1211 int pcie_mch_quirk; 1212 1213 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1214 { 1215 pcie_mch_quirk = 1; 1216 } 1217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1220 1221 1222 /* 1223 * It's possible for the MSI to get corrupted if shpc and acpi 1224 * are used together on certain PXH-based systems. 1225 */ 1226 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1227 { 1228 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1229 PCI_CAP_ID_MSI); 1230 dev->no_msi = 1; 1231 1232 printk(KERN_WARNING "PCI: PXH quirk detected, " 1233 "disabling MSI for SHPC device\n"); 1234 } 1235 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1236 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1237 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1238 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1239 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1240 1241 1242 static void __devinit quirk_netmos(struct pci_dev *dev) 1243 { 1244 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1245 unsigned int num_serial = dev->subsystem_device & 0xf; 1246 1247 /* 1248 * These Netmos parts are multiport serial devices with optional 1249 * parallel ports. Even when parallel ports are present, they 1250 * are identified as class SERIAL, which means the serial driver 1251 * will claim them. To prevent this, mark them as class OTHER. 1252 * These combo devices should be claimed by parport_serial. 1253 * 1254 * The subdevice ID is of the form 0x00PS, where <P> is the number 1255 * of parallel ports and <S> is the number of serial ports. 1256 */ 1257 switch (dev->device) { 1258 case PCI_DEVICE_ID_NETMOS_9735: 1259 case PCI_DEVICE_ID_NETMOS_9745: 1260 case PCI_DEVICE_ID_NETMOS_9835: 1261 case PCI_DEVICE_ID_NETMOS_9845: 1262 case PCI_DEVICE_ID_NETMOS_9855: 1263 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1264 num_parallel) { 1265 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1266 "%u serial); changing class SERIAL to OTHER " 1267 "(use parport_serial)\n", 1268 dev->device, num_parallel, num_serial); 1269 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1270 (dev->class & 0xff); 1271 } 1272 } 1273 } 1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1275 1276 1277 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1278 { 1279 /* rev 1 ncr53c810 chips don't set the class at all which means 1280 * they don't get their resources remapped. Fix that here. 1281 */ 1282 1283 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1284 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1285 dev->class = PCI_CLASS_STORAGE_SCSI; 1286 } 1287 } 1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1289 1290 1291 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1292 { 1293 while (f < end) { 1294 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1295 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1296 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1297 f->hook(dev); 1298 } 1299 f++; 1300 } 1301 } 1302 1303 extern struct pci_fixup __start_pci_fixups_early[]; 1304 extern struct pci_fixup __end_pci_fixups_early[]; 1305 extern struct pci_fixup __start_pci_fixups_header[]; 1306 extern struct pci_fixup __end_pci_fixups_header[]; 1307 extern struct pci_fixup __start_pci_fixups_final[]; 1308 extern struct pci_fixup __end_pci_fixups_final[]; 1309 extern struct pci_fixup __start_pci_fixups_enable[]; 1310 extern struct pci_fixup __end_pci_fixups_enable[]; 1311 1312 1313 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1314 { 1315 struct pci_fixup *start, *end; 1316 1317 switch(pass) { 1318 case pci_fixup_early: 1319 start = __start_pci_fixups_early; 1320 end = __end_pci_fixups_early; 1321 break; 1322 1323 case pci_fixup_header: 1324 start = __start_pci_fixups_header; 1325 end = __end_pci_fixups_header; 1326 break; 1327 1328 case pci_fixup_final: 1329 start = __start_pci_fixups_final; 1330 end = __end_pci_fixups_final; 1331 break; 1332 1333 case pci_fixup_enable: 1334 start = __start_pci_fixups_enable; 1335 end = __end_pci_fixups_enable; 1336 break; 1337 1338 default: 1339 /* stupid compiler warning, you would think with an enum... */ 1340 return; 1341 } 1342 pci_do_fixups(dev, start, end); 1343 } 1344 1345 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1346 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1347 { 1348 u16 en1k; 1349 u8 io_base_lo, io_limit_lo; 1350 unsigned long base, limit; 1351 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1352 1353 pci_read_config_word(dev, 0x40, &en1k); 1354 1355 if (en1k & 0x200) { 1356 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1357 1358 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1359 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1360 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1361 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1362 1363 if (base <= limit) { 1364 res->start = base; 1365 res->end = limit + 0x3ff; 1366 } 1367 } 1368 } 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1370 1371 EXPORT_SYMBOL(pcie_mch_quirk); 1372 #ifdef CONFIG_HOTPLUG 1373 EXPORT_SYMBOL(pci_fixup_device); 1374 #endif 1375