1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/acpi.h> 25 #include <linux/kallsyms.h> 26 #include <linux/dmi.h> 27 #include <linux/pci-aspm.h> 28 #include <linux/ioport.h> 29 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 30 #include "pci.h" 31 32 /* 33 * This quirk function disables memory decoding and releases memory resources 34 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 35 * It also rounds up size to specified alignment. 36 * Later on, the kernel will assign page-aligned memory resource back 37 * to the device. 38 */ 39 static void __devinit quirk_resource_alignment(struct pci_dev *dev) 40 { 41 int i; 42 struct resource *r; 43 resource_size_t align, size; 44 u16 command; 45 46 if (!pci_is_reassigndev(dev)) 47 return; 48 49 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 50 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 51 dev_warn(&dev->dev, 52 "Can't reassign resources to host bridge.\n"); 53 return; 54 } 55 56 dev_info(&dev->dev, 57 "Disabling memory decoding and releasing memory resources.\n"); 58 pci_read_config_word(dev, PCI_COMMAND, &command); 59 command &= ~PCI_COMMAND_MEMORY; 60 pci_write_config_word(dev, PCI_COMMAND, command); 61 62 align = pci_specified_resource_alignment(dev); 63 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { 64 r = &dev->resource[i]; 65 if (!(r->flags & IORESOURCE_MEM)) 66 continue; 67 size = resource_size(r); 68 if (size < align) { 69 size = align; 70 dev_info(&dev->dev, 71 "Rounding up size of resource #%d to %#llx.\n", 72 i, (unsigned long long)size); 73 } 74 r->end = size - 1; 75 r->start = 0; 76 } 77 /* Need to disable bridge's resource window, 78 * to enable the kernel to reassign new resource 79 * window later on. 80 */ 81 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 82 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 83 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 84 r = &dev->resource[i]; 85 if (!(r->flags & IORESOURCE_MEM)) 86 continue; 87 r->end = resource_size(r) - 1; 88 r->start = 0; 89 } 90 pci_disable_bridge_window(dev); 91 } 92 } 93 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); 94 95 /* 96 * Decoding should be disabled for a PCI device during BAR sizing to avoid 97 * conflict. But doing so may cause problems on host bridge and perhaps other 98 * key system devices. For devices that need to have mmio decoding always-on, 99 * we need to set the dev->mmio_always_on bit. 100 */ 101 static void __devinit quirk_mmio_always_on(struct pci_dev *dev) 102 { 103 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) 104 dev->mmio_always_on = 1; 105 } 106 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on); 107 108 /* The Mellanox Tavor device gives false positive parity errors 109 * Mark this device with a broken_parity_status, to allow 110 * PCI scanning code to "skip" this now blacklisted device. 111 */ 112 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 113 { 114 dev->broken_parity_status = 1; /* This device gives false positives */ 115 } 116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 118 119 /* Deal with broken BIOS'es that neglect to enable passive release, 120 which can cause problems in combination with the 82441FX/PPro MTRRs */ 121 static void quirk_passive_release(struct pci_dev *dev) 122 { 123 struct pci_dev *d = NULL; 124 unsigned char dlc; 125 126 /* We have to make sure a particular bit is set in the PIIX3 127 ISA bridge, so we have to go out and find it. */ 128 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 129 pci_read_config_byte(d, 0x82, &dlc); 130 if (!(dlc & 1<<1)) { 131 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 132 dlc |= 1<<1; 133 pci_write_config_byte(d, 0x82, dlc); 134 } 135 } 136 } 137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 138 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 139 140 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 141 but VIA don't answer queries. If you happen to have good contacts at VIA 142 ask them for me please -- Alan 143 144 This appears to be BIOS not version dependent. So presumably there is a 145 chipset level fix */ 146 147 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 148 { 149 if (!isa_dma_bridge_buggy) { 150 isa_dma_bridge_buggy=1; 151 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 152 } 153 } 154 /* 155 * Its not totally clear which chipsets are the problematic ones 156 * We know 82C586 and 82C596 variants are affected. 157 */ 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 165 166 /* 167 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 168 * for some HT machines to use C4 w/o hanging. 169 */ 170 static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev) 171 { 172 u32 pmbase; 173 u16 pm1a; 174 175 pci_read_config_dword(dev, 0x40, &pmbase); 176 pmbase = pmbase & 0xff80; 177 pm1a = inw(pmbase); 178 179 if (pm1a & 0x10) { 180 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 181 outw(0x10, pmbase); 182 } 183 } 184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 185 186 /* 187 * Chipsets where PCI->PCI transfers vanish or hang 188 */ 189 static void __devinit quirk_nopcipci(struct pci_dev *dev) 190 { 191 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 192 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 193 pci_pci_problems |= PCIPCI_FAIL; 194 } 195 } 196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 198 199 static void __devinit quirk_nopciamd(struct pci_dev *dev) 200 { 201 u8 rev; 202 pci_read_config_byte(dev, 0x08, &rev); 203 if (rev == 0x13) { 204 /* Erratum 24 */ 205 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 206 pci_pci_problems |= PCIAGP_FAIL; 207 } 208 } 209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 210 211 /* 212 * Triton requires workarounds to be used by the drivers 213 */ 214 static void __devinit quirk_triton(struct pci_dev *dev) 215 { 216 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 217 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 218 pci_pci_problems |= PCIPCI_TRITON; 219 } 220 } 221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 225 226 /* 227 * VIA Apollo KT133 needs PCI latency patch 228 * Made according to a windows driver based patch by George E. Breese 229 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 230 * and http://www.georgebreese.com/net/software/#PCI 231 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 232 * the info on which Mr Breese based his work. 233 * 234 * Updated based on further information from the site and also on 235 * information provided by VIA 236 */ 237 static void quirk_vialatency(struct pci_dev *dev) 238 { 239 struct pci_dev *p; 240 u8 busarb; 241 /* Ok we have a potential problem chipset here. Now see if we have 242 a buggy southbridge */ 243 244 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 245 if (p!=NULL) { 246 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 247 /* Check for buggy part revisions */ 248 if (p->revision < 0x40 || p->revision > 0x42) 249 goto exit; 250 } else { 251 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 252 if (p==NULL) /* No problem parts */ 253 goto exit; 254 /* Check for buggy part revisions */ 255 if (p->revision < 0x10 || p->revision > 0x12) 256 goto exit; 257 } 258 259 /* 260 * Ok we have the problem. Now set the PCI master grant to 261 * occur every master grant. The apparent bug is that under high 262 * PCI load (quite common in Linux of course) you can get data 263 * loss when the CPU is held off the bus for 3 bus master requests 264 * This happens to include the IDE controllers.... 265 * 266 * VIA only apply this fix when an SB Live! is present but under 267 * both Linux and Windows this isn't enough, and we have seen 268 * corruption without SB Live! but with things like 3 UDMA IDE 269 * controllers. So we ignore that bit of the VIA recommendation.. 270 */ 271 272 pci_read_config_byte(dev, 0x76, &busarb); 273 /* Set bit 4 and bi 5 of byte 76 to 0x01 274 "Master priority rotation on every PCI master grant */ 275 busarb &= ~(1<<5); 276 busarb |= (1<<4); 277 pci_write_config_byte(dev, 0x76, busarb); 278 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 279 exit: 280 pci_dev_put(p); 281 } 282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 285 /* Must restore this on a resume from RAM */ 286 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 287 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 288 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 289 290 /* 291 * VIA Apollo VP3 needs ETBF on BT848/878 292 */ 293 static void __devinit quirk_viaetbf(struct pci_dev *dev) 294 { 295 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 296 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 297 pci_pci_problems |= PCIPCI_VIAETBF; 298 } 299 } 300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 301 302 static void __devinit quirk_vsfx(struct pci_dev *dev) 303 { 304 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 305 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 306 pci_pci_problems |= PCIPCI_VSFX; 307 } 308 } 309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 310 311 /* 312 * Ali Magik requires workarounds to be used by the drivers 313 * that DMA to AGP space. Latency must be set to 0xA and triton 314 * workaround applied too 315 * [Info kindly provided by ALi] 316 */ 317 static void __init quirk_alimagik(struct pci_dev *dev) 318 { 319 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 320 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 321 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 322 } 323 } 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 326 327 /* 328 * Natoma has some interesting boundary conditions with Zoran stuff 329 * at least 330 */ 331 static void __devinit quirk_natoma(struct pci_dev *dev) 332 { 333 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 334 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 335 pci_pci_problems |= PCIPCI_NATOMA; 336 } 337 } 338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 344 345 /* 346 * This chip can cause PCI parity errors if config register 0xA0 is read 347 * while DMAs are occurring. 348 */ 349 static void __devinit quirk_citrine(struct pci_dev *dev) 350 { 351 dev->cfg_size = 0xA0; 352 } 353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 354 355 /* 356 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 357 * If it's needed, re-allocate the region. 358 */ 359 static void __devinit quirk_s3_64M(struct pci_dev *dev) 360 { 361 struct resource *r = &dev->resource[0]; 362 363 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 364 r->start = 0; 365 r->end = 0x3ffffff; 366 } 367 } 368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 370 371 /* 372 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 373 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 374 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 375 * (which conflicts w/ BAR1's memory range). 376 */ 377 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) 378 { 379 if (pci_resource_len(dev, 0) != 8) { 380 struct resource *res = &dev->resource[0]; 381 res->end = res->start + 8 - 1; 382 dev_info(&dev->dev, "CS5536 ISA bridge bug detected " 383 "(incorrect header); workaround applied.\n"); 384 } 385 } 386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 387 388 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 389 unsigned size, int nr, const char *name) 390 { 391 region &= ~(size-1); 392 if (region) { 393 struct pci_bus_region bus_region; 394 struct resource *res = dev->resource + nr; 395 396 res->name = pci_name(dev); 397 res->start = region; 398 res->end = region + size - 1; 399 res->flags = IORESOURCE_IO; 400 401 /* Convert from PCI bus to resource space. */ 402 bus_region.start = res->start; 403 bus_region.end = res->end; 404 pcibios_bus_to_resource(dev, res, &bus_region); 405 406 if (pci_claim_resource(dev, nr) == 0) 407 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", 408 res, name); 409 } 410 } 411 412 /* 413 * ATI Northbridge setups MCE the processor if you even 414 * read somewhere between 0x3b0->0x3bb or read 0x3d3 415 */ 416 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 417 { 418 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 419 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 420 request_region(0x3b0, 0x0C, "RadeonIGP"); 421 request_region(0x3d3, 0x01, "RadeonIGP"); 422 } 423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 424 425 /* 426 * Let's make the southbridge information explicit instead 427 * of having to worry about people probing the ACPI areas, 428 * for example.. (Yes, it happens, and if you read the wrong 429 * ACPI register it will put the machine to sleep with no 430 * way of waking it up again. Bummer). 431 * 432 * ALI M7101: Two IO regions pointed to by words at 433 * 0xE0 (64 bytes of ACPI registers) 434 * 0xE2 (32 bytes of SMB registers) 435 */ 436 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 437 { 438 u16 region; 439 440 pci_read_config_word(dev, 0xE0, ®ion); 441 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 442 pci_read_config_word(dev, 0xE2, ®ion); 443 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 444 } 445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 446 447 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 448 { 449 u32 devres; 450 u32 mask, size, base; 451 452 pci_read_config_dword(dev, port, &devres); 453 if ((devres & enable) != enable) 454 return; 455 mask = (devres >> 16) & 15; 456 base = devres & 0xffff; 457 size = 16; 458 for (;;) { 459 unsigned bit = size >> 1; 460 if ((bit & mask) == bit) 461 break; 462 size = bit; 463 } 464 /* 465 * For now we only print it out. Eventually we'll want to 466 * reserve it (at least if it's in the 0x1000+ range), but 467 * let's get enough confirmation reports first. 468 */ 469 base &= -size; 470 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 471 } 472 473 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 474 { 475 u32 devres; 476 u32 mask, size, base; 477 478 pci_read_config_dword(dev, port, &devres); 479 if ((devres & enable) != enable) 480 return; 481 base = devres & 0xffff0000; 482 mask = (devres & 0x3f) << 16; 483 size = 128 << 16; 484 for (;;) { 485 unsigned bit = size >> 1; 486 if ((bit & mask) == bit) 487 break; 488 size = bit; 489 } 490 /* 491 * For now we only print it out. Eventually we'll want to 492 * reserve it, but let's get enough confirmation reports first. 493 */ 494 base &= -size; 495 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 496 } 497 498 /* 499 * PIIX4 ACPI: Two IO regions pointed to by longwords at 500 * 0x40 (64 bytes of ACPI registers) 501 * 0x90 (16 bytes of SMB registers) 502 * and a few strange programmable PIIX4 device resources. 503 */ 504 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 505 { 506 u32 region, res_a; 507 508 pci_read_config_dword(dev, 0x40, ®ion); 509 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 510 pci_read_config_dword(dev, 0x90, ®ion); 511 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 512 513 /* Device resource A has enables for some of the other ones */ 514 pci_read_config_dword(dev, 0x5c, &res_a); 515 516 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 517 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 518 519 /* Device resource D is just bitfields for static resources */ 520 521 /* Device 12 enabled? */ 522 if (res_a & (1 << 29)) { 523 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 524 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 525 } 526 /* Device 13 enabled? */ 527 if (res_a & (1 << 30)) { 528 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 529 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 530 } 531 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 532 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 533 } 534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 536 537 #define ICH_PMBASE 0x40 538 #define ICH_ACPI_CNTL 0x44 539 #define ICH4_ACPI_EN 0x10 540 #define ICH6_ACPI_EN 0x80 541 #define ICH4_GPIOBASE 0x58 542 #define ICH4_GPIO_CNTL 0x5c 543 #define ICH4_GPIO_EN 0x10 544 #define ICH6_GPIOBASE 0x48 545 #define ICH6_GPIO_CNTL 0x4c 546 #define ICH6_GPIO_EN 0x10 547 548 /* 549 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 550 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 551 * 0x58 (64 bytes of GPIO I/O space) 552 */ 553 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 554 { 555 u32 region; 556 u8 enable; 557 558 /* 559 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 560 * with low legacy (and fixed) ports. We don't know the decoding 561 * priority and can't tell whether the legacy device or the one created 562 * here is really at that address. This happens on boards with broken 563 * BIOSes. 564 */ 565 566 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 567 if (enable & ICH4_ACPI_EN) { 568 pci_read_config_dword(dev, ICH_PMBASE, ®ion); 569 region &= PCI_BASE_ADDRESS_IO_MASK; 570 if (region >= PCIBIOS_MIN_IO) 571 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, 572 "ICH4 ACPI/GPIO/TCO"); 573 } 574 575 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 576 if (enable & ICH4_GPIO_EN) { 577 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion); 578 region &= PCI_BASE_ADDRESS_IO_MASK; 579 if (region >= PCIBIOS_MIN_IO) 580 quirk_io_region(dev, region, 64, 581 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO"); 582 } 583 } 584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 594 595 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) 596 { 597 u32 region; 598 u8 enable; 599 600 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 601 if (enable & ICH6_ACPI_EN) { 602 pci_read_config_dword(dev, ICH_PMBASE, ®ion); 603 region &= PCI_BASE_ADDRESS_IO_MASK; 604 if (region >= PCIBIOS_MIN_IO) 605 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, 606 "ICH6 ACPI/GPIO/TCO"); 607 } 608 609 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 610 if (enable & ICH6_GPIO_EN) { 611 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion); 612 region &= PCI_BASE_ADDRESS_IO_MASK; 613 if (region >= PCIBIOS_MIN_IO) 614 quirk_io_region(dev, region, 64, 615 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO"); 616 } 617 } 618 619 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 620 { 621 u32 val; 622 u32 size, base; 623 624 pci_read_config_dword(dev, reg, &val); 625 626 /* Enabled? */ 627 if (!(val & 1)) 628 return; 629 base = val & 0xfffc; 630 if (dynsize) { 631 /* 632 * This is not correct. It is 16, 32 or 64 bytes depending on 633 * register D31:F0:ADh bits 5:4. 634 * 635 * But this gets us at least _part_ of it. 636 */ 637 size = 16; 638 } else { 639 size = 128; 640 } 641 base &= ~(size-1); 642 643 /* Just print it out for now. We should reserve it after more debugging */ 644 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 645 } 646 647 static void __devinit quirk_ich6_lpc(struct pci_dev *dev) 648 { 649 /* Shared ACPI/GPIO decode with all ICH6+ */ 650 ich6_lpc_acpi_gpio(dev); 651 652 /* ICH6-specific generic IO decode */ 653 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 654 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 655 } 656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 658 659 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 660 { 661 u32 val; 662 u32 mask, base; 663 664 pci_read_config_dword(dev, reg, &val); 665 666 /* Enabled? */ 667 if (!(val & 1)) 668 return; 669 670 /* 671 * IO base in bits 15:2, mask in bits 23:18, both 672 * are dword-based 673 */ 674 base = val & 0xfffc; 675 mask = (val >> 16) & 0xfc; 676 mask |= 3; 677 678 /* Just print it out for now. We should reserve it after more debugging */ 679 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 680 } 681 682 /* ICH7-10 has the same common LPC generic IO decode registers */ 683 static void __devinit quirk_ich7_lpc(struct pci_dev *dev) 684 { 685 /* We share the common ACPI/GPIO decode with ICH6 */ 686 ich6_lpc_acpi_gpio(dev); 687 688 /* And have 4 ICH7+ generic decodes */ 689 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 690 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 691 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 692 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 693 } 694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 707 708 /* 709 * VIA ACPI: One IO region pointed to by longword at 710 * 0x48 or 0x20 (256 bytes of ACPI registers) 711 */ 712 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 713 { 714 u32 region; 715 716 if (dev->revision & 0x10) { 717 pci_read_config_dword(dev, 0x48, ®ion); 718 region &= PCI_BASE_ADDRESS_IO_MASK; 719 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 720 } 721 } 722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 723 724 /* 725 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 726 * 0x48 (256 bytes of ACPI registers) 727 * 0x70 (128 bytes of hardware monitoring register) 728 * 0x90 (16 bytes of SMB registers) 729 */ 730 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 731 { 732 u16 hm; 733 u32 smb; 734 735 quirk_vt82c586_acpi(dev); 736 737 pci_read_config_word(dev, 0x70, &hm); 738 hm &= PCI_BASE_ADDRESS_IO_MASK; 739 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 740 741 pci_read_config_dword(dev, 0x90, &smb); 742 smb &= PCI_BASE_ADDRESS_IO_MASK; 743 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 744 } 745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 746 747 /* 748 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 749 * 0x88 (128 bytes of power management registers) 750 * 0xd0 (16 bytes of SMB registers) 751 */ 752 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 753 { 754 u16 pm, smb; 755 756 pci_read_config_word(dev, 0x88, &pm); 757 pm &= PCI_BASE_ADDRESS_IO_MASK; 758 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 759 760 pci_read_config_word(dev, 0xd0, &smb); 761 smb &= PCI_BASE_ADDRESS_IO_MASK; 762 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 763 } 764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 765 766 /* 767 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 768 * Disable fast back-to-back on the secondary bus segment 769 */ 770 static void __devinit quirk_xio2000a(struct pci_dev *dev) 771 { 772 struct pci_dev *pdev; 773 u16 command; 774 775 dev_warn(&dev->dev, "TI XIO2000a quirk detected; " 776 "secondary bus fast back-to-back transfers disabled\n"); 777 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 778 pci_read_config_word(pdev, PCI_COMMAND, &command); 779 if (command & PCI_COMMAND_FAST_BACK) 780 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 781 } 782 } 783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 784 quirk_xio2000a); 785 786 #ifdef CONFIG_X86_IO_APIC 787 788 #include <asm/io_apic.h> 789 790 /* 791 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 792 * devices to the external APIC. 793 * 794 * TODO: When we have device-specific interrupt routers, 795 * this code will go away from quirks. 796 */ 797 static void quirk_via_ioapic(struct pci_dev *dev) 798 { 799 u8 tmp; 800 801 if (nr_ioapics < 1) 802 tmp = 0; /* nothing routed to external APIC */ 803 else 804 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 805 806 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 807 tmp == 0 ? "Disa" : "Ena"); 808 809 /* Offset 0x58: External APIC IRQ output control */ 810 pci_write_config_byte (dev, 0x58, tmp); 811 } 812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 813 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 814 815 /* 816 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 817 * This leads to doubled level interrupt rates. 818 * Set this bit to get rid of cycle wastage. 819 * Otherwise uncritical. 820 */ 821 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 822 { 823 u8 misc_control2; 824 #define BYPASS_APIC_DEASSERT 8 825 826 pci_read_config_byte(dev, 0x5B, &misc_control2); 827 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 828 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 829 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 830 } 831 } 832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 833 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 834 835 /* 836 * The AMD io apic can hang the box when an apic irq is masked. 837 * We check all revs >= B0 (yet not in the pre production!) as the bug 838 * is currently marked NoFix 839 * 840 * We have multiple reports of hangs with this chipset that went away with 841 * noapic specified. For the moment we assume it's the erratum. We may be wrong 842 * of course. However the advice is demonstrably good even if so.. 843 */ 844 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 845 { 846 if (dev->revision >= 0x02) { 847 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 848 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 849 } 850 } 851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 852 853 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 854 { 855 if (dev->devfn == 0 && dev->bus->number == 0) 856 sis_apic_bug = 1; 857 } 858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 859 #endif /* CONFIG_X86_IO_APIC */ 860 861 /* 862 * Some settings of MMRBC can lead to data corruption so block changes. 863 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 864 */ 865 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 866 { 867 if (dev->subordinate && dev->revision <= 0x12) { 868 dev_info(&dev->dev, "AMD8131 rev %x detected; " 869 "disabling PCI-X MMRBC\n", dev->revision); 870 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 871 } 872 } 873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 874 875 /* 876 * FIXME: it is questionable that quirk_via_acpi 877 * is needed. It shows up as an ISA bridge, and does not 878 * support the PCI_INTERRUPT_LINE register at all. Therefore 879 * it seems like setting the pci_dev's 'irq' to the 880 * value of the ACPI SCI interrupt is only done for convenience. 881 * -jgarzik 882 */ 883 static void __devinit quirk_via_acpi(struct pci_dev *d) 884 { 885 /* 886 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 887 */ 888 u8 irq; 889 pci_read_config_byte(d, 0x42, &irq); 890 irq &= 0xf; 891 if (irq && (irq != 2)) 892 d->irq = irq; 893 } 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 896 897 898 /* 899 * VIA bridges which have VLink 900 */ 901 902 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 903 904 static void quirk_via_bridge(struct pci_dev *dev) 905 { 906 /* See what bridge we have and find the device ranges */ 907 switch (dev->device) { 908 case PCI_DEVICE_ID_VIA_82C686: 909 /* The VT82C686 is special, it attaches to PCI and can have 910 any device number. All its subdevices are functions of 911 that single device. */ 912 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 913 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 914 break; 915 case PCI_DEVICE_ID_VIA_8237: 916 case PCI_DEVICE_ID_VIA_8237A: 917 via_vlink_dev_lo = 15; 918 break; 919 case PCI_DEVICE_ID_VIA_8235: 920 via_vlink_dev_lo = 16; 921 break; 922 case PCI_DEVICE_ID_VIA_8231: 923 case PCI_DEVICE_ID_VIA_8233_0: 924 case PCI_DEVICE_ID_VIA_8233A: 925 case PCI_DEVICE_ID_VIA_8233C_0: 926 via_vlink_dev_lo = 17; 927 break; 928 } 929 } 930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 931 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 938 939 /** 940 * quirk_via_vlink - VIA VLink IRQ number update 941 * @dev: PCI device 942 * 943 * If the device we are dealing with is on a PIC IRQ we need to 944 * ensure that the IRQ line register which usually is not relevant 945 * for PCI cards, is actually written so that interrupts get sent 946 * to the right place. 947 * We only do this on systems where a VIA south bridge was detected, 948 * and only for VIA devices on the motherboard (see quirk_via_bridge 949 * above). 950 */ 951 952 static void quirk_via_vlink(struct pci_dev *dev) 953 { 954 u8 irq, new_irq; 955 956 /* Check if we have VLink at all */ 957 if (via_vlink_dev_lo == -1) 958 return; 959 960 new_irq = dev->irq; 961 962 /* Don't quirk interrupts outside the legacy IRQ range */ 963 if (!new_irq || new_irq > 15) 964 return; 965 966 /* Internal device ? */ 967 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 968 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 969 return; 970 971 /* This is an internal VLink device on a PIC interrupt. The BIOS 972 ought to have set this but may not have, so we redo it */ 973 974 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 975 if (new_irq != irq) { 976 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 977 irq, new_irq); 978 udelay(15); /* unknown if delay really needed */ 979 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 980 } 981 } 982 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 983 984 /* 985 * VIA VT82C598 has its device ID settable and many BIOSes 986 * set it to the ID of VT82C597 for backward compatibility. 987 * We need to switch it off to be able to recognize the real 988 * type of the chip. 989 */ 990 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 991 { 992 pci_write_config_byte(dev, 0xfc, 0); 993 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 994 } 995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 996 997 /* 998 * CardBus controllers have a legacy base address that enables them 999 * to respond as i82365 pcmcia controllers. We don't want them to 1000 * do this even if the Linux CardBus driver is not loaded, because 1001 * the Linux i82365 driver does not (and should not) handle CardBus. 1002 */ 1003 static void quirk_cardbus_legacy(struct pci_dev *dev) 1004 { 1005 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 1006 return; 1007 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1008 } 1009 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 1010 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 1011 1012 /* 1013 * Following the PCI ordering rules is optional on the AMD762. I'm not 1014 * sure what the designers were smoking but let's not inhale... 1015 * 1016 * To be fair to AMD, it follows the spec by default, its BIOS people 1017 * who turn it off! 1018 */ 1019 static void quirk_amd_ordering(struct pci_dev *dev) 1020 { 1021 u32 pcic; 1022 pci_read_config_dword(dev, 0x4C, &pcic); 1023 if ((pcic&6)!=6) { 1024 pcic |= 6; 1025 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1026 pci_write_config_dword(dev, 0x4C, pcic); 1027 pci_read_config_dword(dev, 0x84, &pcic); 1028 pcic |= (1<<23); /* Required in this mode */ 1029 pci_write_config_dword(dev, 0x84, pcic); 1030 } 1031 } 1032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1033 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1034 1035 /* 1036 * DreamWorks provided workaround for Dunord I-3000 problem 1037 * 1038 * This card decodes and responds to addresses not apparently 1039 * assigned to it. We force a larger allocation to ensure that 1040 * nothing gets put too close to it. 1041 */ 1042 static void __devinit quirk_dunord ( struct pci_dev * dev ) 1043 { 1044 struct resource *r = &dev->resource [1]; 1045 r->start = 0; 1046 r->end = 0xffffff; 1047 } 1048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1049 1050 /* 1051 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1052 * is subtractive decoding (transparent), and does indicate this 1053 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1054 * instead of 0x01. 1055 */ 1056 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 1057 { 1058 dev->transparent = 1; 1059 } 1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1062 1063 /* 1064 * Common misconfiguration of the MediaGX/Geode PCI master that will 1065 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1066 * datasheets found at http://www.national.com/analog for info on what 1067 * these bits do. <christer@weinigel.se> 1068 */ 1069 static void quirk_mediagx_master(struct pci_dev *dev) 1070 { 1071 u8 reg; 1072 pci_read_config_byte(dev, 0x41, ®); 1073 if (reg & 2) { 1074 reg &= ~2; 1075 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 1076 pci_write_config_byte(dev, 0x41, reg); 1077 } 1078 } 1079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1080 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1081 1082 /* 1083 * Ensure C0 rev restreaming is off. This is normally done by 1084 * the BIOS but in the odd case it is not the results are corruption 1085 * hence the presence of a Linux check 1086 */ 1087 static void quirk_disable_pxb(struct pci_dev *pdev) 1088 { 1089 u16 config; 1090 1091 if (pdev->revision != 0x04) /* Only C0 requires this */ 1092 return; 1093 pci_read_config_word(pdev, 0x40, &config); 1094 if (config & (1<<6)) { 1095 config &= ~(1<<6); 1096 pci_write_config_word(pdev, 0x40, config); 1097 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1098 } 1099 } 1100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1101 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1102 1103 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 1104 { 1105 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1106 u8 tmp; 1107 1108 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1109 if (tmp == 0x01) { 1110 pci_read_config_byte(pdev, 0x40, &tmp); 1111 pci_write_config_byte(pdev, 0x40, tmp|1); 1112 pci_write_config_byte(pdev, 0x9, 1); 1113 pci_write_config_byte(pdev, 0xa, 6); 1114 pci_write_config_byte(pdev, 0x40, tmp); 1115 1116 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1117 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1118 } 1119 } 1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1121 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1123 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1125 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1126 1127 /* 1128 * Serverworks CSB5 IDE does not fully support native mode 1129 */ 1130 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 1131 { 1132 u8 prog; 1133 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1134 if (prog & 5) { 1135 prog &= ~5; 1136 pdev->class &= ~5; 1137 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1138 /* PCI layer will sort out resources */ 1139 } 1140 } 1141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1142 1143 /* 1144 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1145 */ 1146 static void __init quirk_ide_samemode(struct pci_dev *pdev) 1147 { 1148 u8 prog; 1149 1150 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1151 1152 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1153 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1154 prog &= ~5; 1155 pdev->class &= ~5; 1156 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1157 } 1158 } 1159 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1160 1161 /* 1162 * Some ATA devices break if put into D3 1163 */ 1164 1165 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) 1166 { 1167 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1168 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) 1169 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1170 } 1171 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); 1172 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); 1173 /* ALi loses some register settings that we cannot then restore */ 1174 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3); 1175 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1176 occur when mode detecting */ 1177 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3); 1178 1179 /* This was originally an Alpha specific thing, but it really fits here. 1180 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1181 */ 1182 static void __init quirk_eisa_bridge(struct pci_dev *dev) 1183 { 1184 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1185 } 1186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1187 1188 1189 /* 1190 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1191 * is not activated. The myth is that Asus said that they do not want the 1192 * users to be irritated by just another PCI Device in the Win98 device 1193 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1194 * package 2.7.0 for details) 1195 * 1196 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1197 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1198 * becomes necessary to do this tweak in two steps -- the chosen trigger 1199 * is either the Host bridge (preferred) or on-board VGA controller. 1200 * 1201 * Note that we used to unhide the SMBus that way on Toshiba laptops 1202 * (Satellite A40 and Tecra M2) but then found that the thermal management 1203 * was done by SMM code, which could cause unsynchronized concurrent 1204 * accesses to the SMBus registers, with potentially bad effects. Thus you 1205 * should be very careful when adding new entries: if SMM is accessing the 1206 * Intel SMBus, this is a very good reason to leave it hidden. 1207 * 1208 * Likewise, many recent laptops use ACPI for thermal management. If the 1209 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1210 * natively, and keeping the SMBus hidden is the right thing to do. If you 1211 * are about to add an entry in the table below, please first disassemble 1212 * the DSDT and double-check that there is no code accessing the SMBus. 1213 */ 1214 static int asus_hides_smbus; 1215 1216 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1217 { 1218 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1219 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1220 switch(dev->subsystem_device) { 1221 case 0x8025: /* P4B-LX */ 1222 case 0x8070: /* P4B */ 1223 case 0x8088: /* P4B533 */ 1224 case 0x1626: /* L3C notebook */ 1225 asus_hides_smbus = 1; 1226 } 1227 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1228 switch(dev->subsystem_device) { 1229 case 0x80b1: /* P4GE-V */ 1230 case 0x80b2: /* P4PE */ 1231 case 0x8093: /* P4B533-V */ 1232 asus_hides_smbus = 1; 1233 } 1234 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1235 switch(dev->subsystem_device) { 1236 case 0x8030: /* P4T533 */ 1237 asus_hides_smbus = 1; 1238 } 1239 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1240 switch (dev->subsystem_device) { 1241 case 0x8070: /* P4G8X Deluxe */ 1242 asus_hides_smbus = 1; 1243 } 1244 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1245 switch (dev->subsystem_device) { 1246 case 0x80c9: /* PU-DLS */ 1247 asus_hides_smbus = 1; 1248 } 1249 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1250 switch (dev->subsystem_device) { 1251 case 0x1751: /* M2N notebook */ 1252 case 0x1821: /* M5N notebook */ 1253 case 0x1897: /* A6L notebook */ 1254 asus_hides_smbus = 1; 1255 } 1256 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1257 switch (dev->subsystem_device) { 1258 case 0x184b: /* W1N notebook */ 1259 case 0x186a: /* M6Ne notebook */ 1260 asus_hides_smbus = 1; 1261 } 1262 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1263 switch (dev->subsystem_device) { 1264 case 0x80f2: /* P4P800-X */ 1265 asus_hides_smbus = 1; 1266 } 1267 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1268 switch (dev->subsystem_device) { 1269 case 0x1882: /* M6V notebook */ 1270 case 0x1977: /* A6VA notebook */ 1271 asus_hides_smbus = 1; 1272 } 1273 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1274 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1275 switch(dev->subsystem_device) { 1276 case 0x088C: /* HP Compaq nc8000 */ 1277 case 0x0890: /* HP Compaq nc6000 */ 1278 asus_hides_smbus = 1; 1279 } 1280 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1281 switch (dev->subsystem_device) { 1282 case 0x12bc: /* HP D330L */ 1283 case 0x12bd: /* HP D530 */ 1284 case 0x006a: /* HP Compaq nx9500 */ 1285 asus_hides_smbus = 1; 1286 } 1287 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1288 switch (dev->subsystem_device) { 1289 case 0x12bf: /* HP xw4100 */ 1290 asus_hides_smbus = 1; 1291 } 1292 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1293 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1294 switch(dev->subsystem_device) { 1295 case 0xC00C: /* Samsung P35 notebook */ 1296 asus_hides_smbus = 1; 1297 } 1298 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1299 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1300 switch(dev->subsystem_device) { 1301 case 0x0058: /* Compaq Evo N620c */ 1302 asus_hides_smbus = 1; 1303 } 1304 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1305 switch(dev->subsystem_device) { 1306 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1307 /* Motherboard doesn't have Host bridge 1308 * subvendor/subdevice IDs, therefore checking 1309 * its on-board VGA controller */ 1310 asus_hides_smbus = 1; 1311 } 1312 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1313 switch(dev->subsystem_device) { 1314 case 0x00b8: /* Compaq Evo D510 CMT */ 1315 case 0x00b9: /* Compaq Evo D510 SFF */ 1316 case 0x00ba: /* Compaq Evo D510 USDT */ 1317 /* Motherboard doesn't have Host bridge 1318 * subvendor/subdevice IDs and on-board VGA 1319 * controller is disabled if an AGP card is 1320 * inserted, therefore checking USB UHCI 1321 * Controller #1 */ 1322 asus_hides_smbus = 1; 1323 } 1324 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1325 switch (dev->subsystem_device) { 1326 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1327 /* Motherboard doesn't have host bridge 1328 * subvendor/subdevice IDs, therefore checking 1329 * its on-board VGA controller */ 1330 asus_hides_smbus = 1; 1331 } 1332 } 1333 } 1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1344 1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1348 1349 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1350 { 1351 u16 val; 1352 1353 if (likely(!asus_hides_smbus)) 1354 return; 1355 1356 pci_read_config_word(dev, 0xF2, &val); 1357 if (val & 0x8) { 1358 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1359 pci_read_config_word(dev, 0xF2, &val); 1360 if (val & 0x8) 1361 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1362 else 1363 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1364 } 1365 } 1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1377 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1378 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1379 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1380 1381 /* It appears we just have one such device. If not, we have a warning */ 1382 static void __iomem *asus_rcba_base; 1383 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1384 { 1385 u32 rcba; 1386 1387 if (likely(!asus_hides_smbus)) 1388 return; 1389 WARN_ON(asus_rcba_base); 1390 1391 pci_read_config_dword(dev, 0xF0, &rcba); 1392 /* use bits 31:14, 16 kB aligned */ 1393 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1394 if (asus_rcba_base == NULL) 1395 return; 1396 } 1397 1398 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1399 { 1400 u32 val; 1401 1402 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1403 return; 1404 /* read the Function Disable register, dword mode only */ 1405 val = readl(asus_rcba_base + 0x3418); 1406 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1407 } 1408 1409 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1410 { 1411 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1412 return; 1413 iounmap(asus_rcba_base); 1414 asus_rcba_base = NULL; 1415 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1416 } 1417 1418 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1419 { 1420 asus_hides_smbus_lpc_ich6_suspend(dev); 1421 asus_hides_smbus_lpc_ich6_resume_early(dev); 1422 asus_hides_smbus_lpc_ich6_resume(dev); 1423 } 1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1425 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1426 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1428 1429 /* 1430 * SiS 96x south bridge: BIOS typically hides SMBus device... 1431 */ 1432 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1433 { 1434 u8 val = 0; 1435 pci_read_config_byte(dev, 0x77, &val); 1436 if (val & 0x10) { 1437 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1438 pci_write_config_byte(dev, 0x77, val & ~0x10); 1439 } 1440 } 1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1446 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1447 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1448 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1449 1450 /* 1451 * ... This is further complicated by the fact that some SiS96x south 1452 * bridges pretend to be 85C503/5513 instead. In that case see if we 1453 * spotted a compatible north bridge to make sure. 1454 * (pci_find_device doesn't work yet) 1455 * 1456 * We can also enable the sis96x bit in the discovery register.. 1457 */ 1458 #define SIS_DETECT_REGISTER 0x40 1459 1460 static void quirk_sis_503(struct pci_dev *dev) 1461 { 1462 u8 reg; 1463 u16 devid; 1464 1465 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1467 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1468 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1469 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1470 return; 1471 } 1472 1473 /* 1474 * Ok, it now shows up as a 96x.. run the 96x quirk by 1475 * hand in case it has already been processed. 1476 * (depends on link order, which is apparently not guaranteed) 1477 */ 1478 dev->device = devid; 1479 quirk_sis_96x_smbus(dev); 1480 } 1481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1482 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1483 1484 1485 /* 1486 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1487 * and MC97 modem controller are disabled when a second PCI soundcard is 1488 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1489 * -- bjd 1490 */ 1491 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1492 { 1493 u8 val; 1494 int asus_hides_ac97 = 0; 1495 1496 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1497 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1498 asus_hides_ac97 = 1; 1499 } 1500 1501 if (!asus_hides_ac97) 1502 return; 1503 1504 pci_read_config_byte(dev, 0x50, &val); 1505 if (val & 0xc0) { 1506 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1507 pci_read_config_byte(dev, 0x50, &val); 1508 if (val & 0xc0) 1509 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1510 else 1511 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1512 } 1513 } 1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1515 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1516 1517 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1518 1519 /* 1520 * If we are using libata we can drive this chip properly but must 1521 * do this early on to make the additional device appear during 1522 * the PCI scanning. 1523 */ 1524 static void quirk_jmicron_ata(struct pci_dev *pdev) 1525 { 1526 u32 conf1, conf5, class; 1527 u8 hdr; 1528 1529 /* Only poke fn 0 */ 1530 if (PCI_FUNC(pdev->devfn)) 1531 return; 1532 1533 pci_read_config_dword(pdev, 0x40, &conf1); 1534 pci_read_config_dword(pdev, 0x80, &conf5); 1535 1536 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1537 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1538 1539 switch (pdev->device) { 1540 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1541 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1542 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1543 /* The controller should be in single function ahci mode */ 1544 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1545 break; 1546 1547 case PCI_DEVICE_ID_JMICRON_JMB365: 1548 case PCI_DEVICE_ID_JMICRON_JMB366: 1549 /* Redirect IDE second PATA port to the right spot */ 1550 conf5 |= (1 << 24); 1551 /* Fall through */ 1552 case PCI_DEVICE_ID_JMICRON_JMB361: 1553 case PCI_DEVICE_ID_JMICRON_JMB363: 1554 case PCI_DEVICE_ID_JMICRON_JMB369: 1555 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1556 /* Set the class codes correctly and then direct IDE 0 */ 1557 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1558 break; 1559 1560 case PCI_DEVICE_ID_JMICRON_JMB368: 1561 /* The controller should be in single function IDE mode */ 1562 conf1 |= 0x00C00000; /* Set 22, 23 */ 1563 break; 1564 } 1565 1566 pci_write_config_dword(pdev, 0x40, conf1); 1567 pci_write_config_dword(pdev, 0x80, conf5); 1568 1569 /* Update pdev accordingly */ 1570 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1571 pdev->hdr_type = hdr & 0x7f; 1572 pdev->multifunction = !!(hdr & 0x80); 1573 1574 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1575 pdev->class = class >> 8; 1576 } 1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1593 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1594 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1595 1596 #endif 1597 1598 #ifdef CONFIG_X86_IO_APIC 1599 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1600 { 1601 int i; 1602 1603 if ((pdev->class >> 8) != 0xff00) 1604 return; 1605 1606 /* the first BAR is the location of the IO APIC...we must 1607 * not touch this (and it's already covered by the fixmap), so 1608 * forcibly insert it into the resource tree */ 1609 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1610 insert_resource(&iomem_resource, &pdev->resource[0]); 1611 1612 /* The next five BARs all seem to be rubbish, so just clean 1613 * them out */ 1614 for (i=1; i < 6; i++) { 1615 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1616 } 1617 1618 } 1619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1620 #endif 1621 1622 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1623 { 1624 pci_msi_off(pdev); 1625 pdev->no_msi = 1; 1626 } 1627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1630 1631 1632 /* 1633 * It's possible for the MSI to get corrupted if shpc and acpi 1634 * are used together on certain PXH-based systems. 1635 */ 1636 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1637 { 1638 pci_msi_off(dev); 1639 dev->no_msi = 1; 1640 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1641 } 1642 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1643 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1644 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1645 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1646 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1647 1648 /* 1649 * Some Intel PCI Express chipsets have trouble with downstream 1650 * device power management. 1651 */ 1652 static void quirk_intel_pcie_pm(struct pci_dev * dev) 1653 { 1654 pci_pm_d3_delay = 120; 1655 dev->no_d1d2 = 1; 1656 } 1657 1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1679 1680 #ifdef CONFIG_X86_IO_APIC 1681 /* 1682 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1683 * remap the original interrupt in the linux kernel to the boot interrupt, so 1684 * that a PCI device's interrupt handler is installed on the boot interrupt 1685 * line instead. 1686 */ 1687 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1688 { 1689 if (noioapicquirk || noioapicreroute) 1690 return; 1691 1692 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1693 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1694 dev->vendor, dev->device); 1695 } 1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1704 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1705 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1706 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1707 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1708 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1709 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1710 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1711 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1712 1713 /* 1714 * On some chipsets we can disable the generation of legacy INTx boot 1715 * interrupts. 1716 */ 1717 1718 /* 1719 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1720 * 300641-004US, section 5.7.3. 1721 */ 1722 #define INTEL_6300_IOAPIC_ABAR 0x40 1723 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1724 1725 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1726 { 1727 u16 pci_config_word; 1728 1729 if (noioapicquirk) 1730 return; 1731 1732 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1733 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1734 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1735 1736 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1737 dev->vendor, dev->device); 1738 } 1739 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1740 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1741 1742 /* 1743 * disable boot interrupts on HT-1000 1744 */ 1745 #define BC_HT1000_FEATURE_REG 0x64 1746 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1747 #define BC_HT1000_MAP_IDX 0xC00 1748 #define BC_HT1000_MAP_DATA 0xC01 1749 1750 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1751 { 1752 u32 pci_config_dword; 1753 u8 irq; 1754 1755 if (noioapicquirk) 1756 return; 1757 1758 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1759 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1760 BC_HT1000_PIC_REGS_ENABLE); 1761 1762 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1763 outb(irq, BC_HT1000_MAP_IDX); 1764 outb(0x00, BC_HT1000_MAP_DATA); 1765 } 1766 1767 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1768 1769 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1770 dev->vendor, dev->device); 1771 } 1772 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1773 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1774 1775 /* 1776 * disable boot interrupts on AMD and ATI chipsets 1777 */ 1778 /* 1779 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1780 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1781 * (due to an erratum). 1782 */ 1783 #define AMD_813X_MISC 0x40 1784 #define AMD_813X_NOIOAMODE (1<<0) 1785 #define AMD_813X_REV_B1 0x12 1786 #define AMD_813X_REV_B2 0x13 1787 1788 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1789 { 1790 u32 pci_config_dword; 1791 1792 if (noioapicquirk) 1793 return; 1794 if ((dev->revision == AMD_813X_REV_B1) || 1795 (dev->revision == AMD_813X_REV_B2)) 1796 return; 1797 1798 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1799 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1800 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1801 1802 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1803 dev->vendor, dev->device); 1804 } 1805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1806 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1808 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1809 1810 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1811 1812 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1813 { 1814 u16 pci_config_word; 1815 1816 if (noioapicquirk) 1817 return; 1818 1819 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1820 if (!pci_config_word) { 1821 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " 1822 "already disabled\n", dev->vendor, dev->device); 1823 return; 1824 } 1825 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1826 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1827 dev->vendor, dev->device); 1828 } 1829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1830 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1831 #endif /* CONFIG_X86_IO_APIC */ 1832 1833 /* 1834 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1835 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1836 * Re-allocate the region if needed... 1837 */ 1838 static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1839 { 1840 struct resource *r = &dev->resource[0]; 1841 1842 if (r->start & 0x8) { 1843 r->start = 0; 1844 r->end = 0xf; 1845 } 1846 } 1847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1848 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1849 quirk_tc86c001_ide); 1850 1851 static void __devinit quirk_netmos(struct pci_dev *dev) 1852 { 1853 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1854 unsigned int num_serial = dev->subsystem_device & 0xf; 1855 1856 /* 1857 * These Netmos parts are multiport serial devices with optional 1858 * parallel ports. Even when parallel ports are present, they 1859 * are identified as class SERIAL, which means the serial driver 1860 * will claim them. To prevent this, mark them as class OTHER. 1861 * These combo devices should be claimed by parport_serial. 1862 * 1863 * The subdevice ID is of the form 0x00PS, where <P> is the number 1864 * of parallel ports and <S> is the number of serial ports. 1865 */ 1866 switch (dev->device) { 1867 case PCI_DEVICE_ID_NETMOS_9835: 1868 /* Well, this rule doesn't hold for the following 9835 device */ 1869 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1870 dev->subsystem_device == 0x0299) 1871 return; 1872 case PCI_DEVICE_ID_NETMOS_9735: 1873 case PCI_DEVICE_ID_NETMOS_9745: 1874 case PCI_DEVICE_ID_NETMOS_9845: 1875 case PCI_DEVICE_ID_NETMOS_9855: 1876 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1877 num_parallel) { 1878 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1879 "%u serial); changing class SERIAL to OTHER " 1880 "(use parport_serial)\n", 1881 dev->device, num_parallel, num_serial); 1882 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1883 (dev->class & 0xff); 1884 } 1885 } 1886 } 1887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1888 1889 static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1890 { 1891 u16 command, pmcsr; 1892 u8 __iomem *csr; 1893 u8 cmd_hi; 1894 int pm; 1895 1896 switch (dev->device) { 1897 /* PCI IDs taken from drivers/net/e100.c */ 1898 case 0x1029: 1899 case 0x1030 ... 0x1034: 1900 case 0x1038 ... 0x103E: 1901 case 0x1050 ... 0x1057: 1902 case 0x1059: 1903 case 0x1064 ... 0x106B: 1904 case 0x1091 ... 0x1095: 1905 case 0x1209: 1906 case 0x1229: 1907 case 0x2449: 1908 case 0x2459: 1909 case 0x245D: 1910 case 0x27DC: 1911 break; 1912 default: 1913 return; 1914 } 1915 1916 /* 1917 * Some firmware hands off the e100 with interrupts enabled, 1918 * which can cause a flood of interrupts if packets are 1919 * received before the driver attaches to the device. So 1920 * disable all e100 interrupts here. The driver will 1921 * re-enable them when it's ready. 1922 */ 1923 pci_read_config_word(dev, PCI_COMMAND, &command); 1924 1925 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1926 return; 1927 1928 /* 1929 * Check that the device is in the D0 power state. If it's not, 1930 * there is no point to look any further. 1931 */ 1932 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1933 if (pm) { 1934 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 1935 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1936 return; 1937 } 1938 1939 /* Convert from PCI bus to resource space. */ 1940 csr = ioremap(pci_resource_start(dev, 0), 8); 1941 if (!csr) { 1942 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1943 return; 1944 } 1945 1946 cmd_hi = readb(csr + 3); 1947 if (cmd_hi == 0) { 1948 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1949 "disabling\n"); 1950 writeb(1, csr + 3); 1951 } 1952 1953 iounmap(csr); 1954 } 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1956 1957 /* 1958 * The 82575 and 82598 may experience data corruption issues when transitioning 1959 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1960 */ 1961 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) 1962 { 1963 dev_info(&dev->dev, "Disabling L0s\n"); 1964 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1965 } 1966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1967 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1977 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1979 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1980 1981 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1982 { 1983 /* rev 1 ncr53c810 chips don't set the class at all which means 1984 * they don't get their resources remapped. Fix that here. 1985 */ 1986 1987 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1988 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1989 dev->class = PCI_CLASS_STORAGE_SCSI; 1990 } 1991 } 1992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1993 1994 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1995 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1996 { 1997 u16 en1k; 1998 u8 io_base_lo, io_limit_lo; 1999 unsigned long base, limit; 2000 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 2001 2002 pci_read_config_word(dev, 0x40, &en1k); 2003 2004 if (en1k & 0x200) { 2005 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2006 2007 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 2008 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 2009 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 2010 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 2011 2012 if (base <= limit) { 2013 res->start = base; 2014 res->end = limit + 0x3ff; 2015 } 2016 } 2017 } 2018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2019 2020 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 2021 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 2022 * in drivers/pci/setup-bus.c 2023 */ 2024 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 2025 { 2026 u16 en1k, iobl_adr, iobl_adr_1k; 2027 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 2028 2029 pci_read_config_word(dev, 0x40, &en1k); 2030 2031 if (en1k & 0x200) { 2032 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 2033 2034 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 2035 2036 if (iobl_adr != iobl_adr_1k) { 2037 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", 2038 iobl_adr,iobl_adr_1k); 2039 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 2040 } 2041 } 2042 } 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 2044 2045 /* Under some circumstances, AER is not linked with extended capabilities. 2046 * Force it to be linked by setting the corresponding control bit in the 2047 * config space. 2048 */ 2049 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2050 { 2051 uint8_t b; 2052 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2053 if (!(b & 0x20)) { 2054 pci_write_config_byte(dev, 0xf41, b | 0x20); 2055 dev_info(&dev->dev, 2056 "Linking AER extended capability\n"); 2057 } 2058 } 2059 } 2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2061 quirk_nvidia_ck804_pcie_aer_ext_cap); 2062 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2063 quirk_nvidia_ck804_pcie_aer_ext_cap); 2064 2065 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2066 { 2067 /* 2068 * Disable PCI Bus Parking and PCI Master read caching on CX700 2069 * which causes unspecified timing errors with a VT6212L on the PCI 2070 * bus leading to USB2.0 packet loss. 2071 * 2072 * This quirk is only enabled if a second (on the external PCI bus) 2073 * VT6212L is found -- the CX700 core itself also contains a USB 2074 * host controller with the same PCI ID as the VT6212L. 2075 */ 2076 2077 /* Count VT6212L instances */ 2078 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2079 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2080 uint8_t b; 2081 2082 /* p should contain the first (internal) VT6212L -- see if we have 2083 an external one by searching again */ 2084 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2085 if (!p) 2086 return; 2087 pci_dev_put(p); 2088 2089 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2090 if (b & 0x40) { 2091 /* Turn off PCI Bus Parking */ 2092 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2093 2094 dev_info(&dev->dev, 2095 "Disabling VIA CX700 PCI parking\n"); 2096 } 2097 } 2098 2099 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2100 if (b != 0) { 2101 /* Turn off PCI Master read caching */ 2102 pci_write_config_byte(dev, 0x72, 0x0); 2103 2104 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2105 pci_write_config_byte(dev, 0x75, 0x1); 2106 2107 /* Disable "Read FIFO Timer" */ 2108 pci_write_config_byte(dev, 0x77, 0x0); 2109 2110 dev_info(&dev->dev, 2111 "Disabling VIA CX700 PCI caching\n"); 2112 } 2113 } 2114 } 2115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2116 2117 /* 2118 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2119 * VPD end tag will hang the device. This problem was initially 2120 * observed when a vpd entry was created in sysfs 2121 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2122 * will dump 32k of data. Reading a full 32k will cause an access 2123 * beyond the VPD end tag causing the device to hang. Once the device 2124 * is hung, the bnx2 driver will not be able to reset the device. 2125 * We believe that it is legal to read beyond the end tag and 2126 * therefore the solution is to limit the read/write length. 2127 */ 2128 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2129 { 2130 /* 2131 * Only disable the VPD capability for 5706, 5706S, 5708, 2132 * 5708S and 5709 rev. A 2133 */ 2134 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2135 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2136 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2137 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2138 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2139 (dev->revision & 0xf0) == 0x0)) { 2140 if (dev->vpd) 2141 dev->vpd->len = 0x80; 2142 } 2143 } 2144 2145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2146 PCI_DEVICE_ID_NX2_5706, 2147 quirk_brcm_570x_limit_vpd); 2148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2149 PCI_DEVICE_ID_NX2_5706S, 2150 quirk_brcm_570x_limit_vpd); 2151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2152 PCI_DEVICE_ID_NX2_5708, 2153 quirk_brcm_570x_limit_vpd); 2154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2155 PCI_DEVICE_ID_NX2_5708S, 2156 quirk_brcm_570x_limit_vpd); 2157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2158 PCI_DEVICE_ID_NX2_5709, 2159 quirk_brcm_570x_limit_vpd); 2160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2161 PCI_DEVICE_ID_NX2_5709S, 2162 quirk_brcm_570x_limit_vpd); 2163 2164 /* Originally in EDAC sources for i82875P: 2165 * Intel tells BIOS developers to hide device 6 which 2166 * configures the overflow device access containing 2167 * the DRBs - this is where we expose device 6. 2168 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2169 */ 2170 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) 2171 { 2172 u8 reg; 2173 2174 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2175 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2176 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2177 } 2178 } 2179 2180 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2181 quirk_unhide_mch_dev6); 2182 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2183 quirk_unhide_mch_dev6); 2184 2185 #ifdef CONFIG_TILE 2186 /* 2187 * The Tilera TILEmpower platform needs to set the link speed 2188 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2189 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2190 * capability register of the PEX8624 PCIe switch. The switch 2191 * supports link speed auto negotiation, but falsely sets 2192 * the link speed to 5GT/s. 2193 */ 2194 static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev) 2195 { 2196 if (tile_plx_gen1) { 2197 pci_write_config_dword(dev, 0x98, 0x1); 2198 mdelay(50); 2199 } 2200 } 2201 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2202 #endif /* CONFIG_TILE */ 2203 2204 #ifdef CONFIG_PCI_MSI 2205 /* Some chipsets do not support MSI. We cannot easily rely on setting 2206 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2207 * some other busses controlled by the chipset even if Linux is not 2208 * aware of it. Instead of setting the flag on all busses in the 2209 * machine, simply disable MSI globally. 2210 */ 2211 static void __init quirk_disable_all_msi(struct pci_dev *dev) 2212 { 2213 pci_no_msi(); 2214 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2215 } 2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2223 2224 /* Disable MSI on chipsets that are known to not support it */ 2225 static void __devinit quirk_disable_msi(struct pci_dev *dev) 2226 { 2227 if (dev->subordinate) { 2228 dev_warn(&dev->dev, "MSI quirk detected; " 2229 "subordinate MSI disabled\n"); 2230 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2231 } 2232 } 2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2236 2237 /* 2238 * The APC bridge device in AMD 780 family northbridges has some random 2239 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2240 * we use the possible vendor/device IDs of the host bridge for the 2241 * declared quirk, and search for the APC bridge by slot number. 2242 */ 2243 static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2244 { 2245 struct pci_dev *apc_bridge; 2246 2247 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2248 if (apc_bridge) { 2249 if (apc_bridge->device == 0x9602) 2250 quirk_disable_msi(apc_bridge); 2251 pci_dev_put(apc_bridge); 2252 } 2253 } 2254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2256 2257 /* Go through the list of Hypertransport capabilities and 2258 * return 1 if a HT MSI capability is found and enabled */ 2259 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 2260 { 2261 int pos, ttl = 48; 2262 2263 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2264 while (pos && ttl--) { 2265 u8 flags; 2266 2267 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2268 &flags) == 0) 2269 { 2270 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2271 flags & HT_MSI_FLAGS_ENABLE ? 2272 "enabled" : "disabled"); 2273 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2274 } 2275 2276 pos = pci_find_next_ht_capability(dev, pos, 2277 HT_CAPTYPE_MSI_MAPPING); 2278 } 2279 return 0; 2280 } 2281 2282 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2283 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 2284 { 2285 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2286 dev_warn(&dev->dev, "MSI quirk detected; " 2287 "subordinate MSI disabled\n"); 2288 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2289 } 2290 } 2291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2292 quirk_msi_ht_cap); 2293 2294 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2295 * MSI are supported if the MSI capability set in any of these mappings. 2296 */ 2297 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2298 { 2299 struct pci_dev *pdev; 2300 2301 if (!dev->subordinate) 2302 return; 2303 2304 /* check HT MSI cap on this chipset and the root one. 2305 * a single one having MSI is enough to be sure that MSI are supported. 2306 */ 2307 pdev = pci_get_slot(dev->bus, 0); 2308 if (!pdev) 2309 return; 2310 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2311 dev_warn(&dev->dev, "MSI quirk detected; " 2312 "subordinate MSI disabled\n"); 2313 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2314 } 2315 pci_dev_put(pdev); 2316 } 2317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2318 quirk_nvidia_ck804_msi_ht_cap); 2319 2320 /* Force enable MSI mapping capability on HT bridges */ 2321 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 2322 { 2323 int pos, ttl = 48; 2324 2325 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2326 while (pos && ttl--) { 2327 u8 flags; 2328 2329 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2330 &flags) == 0) { 2331 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2332 2333 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2334 flags | HT_MSI_FLAGS_ENABLE); 2335 } 2336 pos = pci_find_next_ht_capability(dev, pos, 2337 HT_CAPTYPE_MSI_MAPPING); 2338 } 2339 } 2340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2341 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2342 ht_enable_msi_mapping); 2343 2344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2345 ht_enable_msi_mapping); 2346 2347 /* The P5N32-SLI motherboards from Asus have a problem with msi 2348 * for the MCP55 NIC. It is not yet determined whether the msi problem 2349 * also affects other devices. As for now, turn off msi for this device. 2350 */ 2351 static void __devinit nvenet_msi_disable(struct pci_dev *dev) 2352 { 2353 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2354 2355 if (board_name && 2356 (strstr(board_name, "P5N32-SLI PREMIUM") || 2357 strstr(board_name, "P5N32-E SLI"))) { 2358 dev_info(&dev->dev, 2359 "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2360 dev->no_msi = 1; 2361 } 2362 } 2363 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2364 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2365 nvenet_msi_disable); 2366 2367 /* 2368 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing 2369 * config register. This register controls the routing of legacy interrupts 2370 * from devices that route through the MCP55. If this register is misprogramed 2371 * interrupts are only sent to the bsp, unlike conventional systems where the 2372 * irq is broadxast to all online cpus. Not having this register set 2373 * properly prevents kdump from booting up properly, so lets make sure that 2374 * we have it set correctly. 2375 * Note this is an undocumented register. 2376 */ 2377 static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2378 { 2379 u32 cfg; 2380 2381 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2382 return; 2383 2384 pci_read_config_dword(dev, 0x74, &cfg); 2385 2386 if (cfg & ((1 << 2) | (1 << 15))) { 2387 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2388 cfg &= ~((1 << 2) | (1 << 15)); 2389 pci_write_config_dword(dev, 0x74, cfg); 2390 } 2391 } 2392 2393 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2394 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2395 nvbridge_check_legacy_irq_routing); 2396 2397 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2398 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2399 nvbridge_check_legacy_irq_routing); 2400 2401 static int __devinit ht_check_msi_mapping(struct pci_dev *dev) 2402 { 2403 int pos, ttl = 48; 2404 int found = 0; 2405 2406 /* check if there is HT MSI cap or enabled on this device */ 2407 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2408 while (pos && ttl--) { 2409 u8 flags; 2410 2411 if (found < 1) 2412 found = 1; 2413 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2414 &flags) == 0) { 2415 if (flags & HT_MSI_FLAGS_ENABLE) { 2416 if (found < 2) { 2417 found = 2; 2418 break; 2419 } 2420 } 2421 } 2422 pos = pci_find_next_ht_capability(dev, pos, 2423 HT_CAPTYPE_MSI_MAPPING); 2424 } 2425 2426 return found; 2427 } 2428 2429 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) 2430 { 2431 struct pci_dev *dev; 2432 int pos; 2433 int i, dev_no; 2434 int found = 0; 2435 2436 dev_no = host_bridge->devfn >> 3; 2437 for (i = dev_no + 1; i < 0x20; i++) { 2438 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2439 if (!dev) 2440 continue; 2441 2442 /* found next host bridge ?*/ 2443 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2444 if (pos != 0) { 2445 pci_dev_put(dev); 2446 break; 2447 } 2448 2449 if (ht_check_msi_mapping(dev)) { 2450 found = 1; 2451 pci_dev_put(dev); 2452 break; 2453 } 2454 pci_dev_put(dev); 2455 } 2456 2457 return found; 2458 } 2459 2460 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2461 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2462 2463 static int __devinit is_end_of_ht_chain(struct pci_dev *dev) 2464 { 2465 int pos, ctrl_off; 2466 int end = 0; 2467 u16 flags, ctrl; 2468 2469 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2470 2471 if (!pos) 2472 goto out; 2473 2474 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2475 2476 ctrl_off = ((flags >> 10) & 1) ? 2477 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2478 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2479 2480 if (ctrl & (1 << 6)) 2481 end = 1; 2482 2483 out: 2484 return end; 2485 } 2486 2487 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) 2488 { 2489 struct pci_dev *host_bridge; 2490 int pos; 2491 int i, dev_no; 2492 int found = 0; 2493 2494 dev_no = dev->devfn >> 3; 2495 for (i = dev_no; i >= 0; i--) { 2496 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2497 if (!host_bridge) 2498 continue; 2499 2500 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2501 if (pos != 0) { 2502 found = 1; 2503 break; 2504 } 2505 pci_dev_put(host_bridge); 2506 } 2507 2508 if (!found) 2509 return; 2510 2511 /* don't enable end_device/host_bridge with leaf directly here */ 2512 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2513 host_bridge_with_leaf(host_bridge)) 2514 goto out; 2515 2516 /* root did that ! */ 2517 if (msi_ht_cap_enabled(host_bridge)) 2518 goto out; 2519 2520 ht_enable_msi_mapping(dev); 2521 2522 out: 2523 pci_dev_put(host_bridge); 2524 } 2525 2526 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) 2527 { 2528 int pos, ttl = 48; 2529 2530 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2531 while (pos && ttl--) { 2532 u8 flags; 2533 2534 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2535 &flags) == 0) { 2536 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2537 2538 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2539 flags & ~HT_MSI_FLAGS_ENABLE); 2540 } 2541 pos = pci_find_next_ht_capability(dev, pos, 2542 HT_CAPTYPE_MSI_MAPPING); 2543 } 2544 } 2545 2546 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2547 { 2548 struct pci_dev *host_bridge; 2549 int pos; 2550 int found; 2551 2552 if (!pci_msi_enabled()) 2553 return; 2554 2555 /* check if there is HT MSI cap or enabled on this device */ 2556 found = ht_check_msi_mapping(dev); 2557 2558 /* no HT MSI CAP */ 2559 if (found == 0) 2560 return; 2561 2562 /* 2563 * HT MSI mapping should be disabled on devices that are below 2564 * a non-Hypertransport host bridge. Locate the host bridge... 2565 */ 2566 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2567 if (host_bridge == NULL) { 2568 dev_warn(&dev->dev, 2569 "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2570 return; 2571 } 2572 2573 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2574 if (pos != 0) { 2575 /* Host bridge is to HT */ 2576 if (found == 1) { 2577 /* it is not enabled, try to enable it */ 2578 if (all) 2579 ht_enable_msi_mapping(dev); 2580 else 2581 nv_ht_enable_msi_mapping(dev); 2582 } 2583 return; 2584 } 2585 2586 /* HT MSI is not enabled */ 2587 if (found == 1) 2588 return; 2589 2590 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2591 ht_disable_msi_mapping(dev); 2592 } 2593 2594 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2595 { 2596 return __nv_msi_ht_cap_quirk(dev, 1); 2597 } 2598 2599 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2600 { 2601 return __nv_msi_ht_cap_quirk(dev, 0); 2602 } 2603 2604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2605 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2606 2607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2609 2610 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) 2611 { 2612 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2613 } 2614 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2615 { 2616 struct pci_dev *p; 2617 2618 /* SB700 MSI issue will be fixed at HW level from revision A21, 2619 * we need check PCI REVISION ID of SMBus controller to get SB700 2620 * revision. 2621 */ 2622 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2623 NULL); 2624 if (!p) 2625 return; 2626 2627 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2628 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2629 pci_dev_put(p); 2630 } 2631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2632 PCI_DEVICE_ID_TIGON3_5780, 2633 quirk_msi_intx_disable_bug); 2634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2635 PCI_DEVICE_ID_TIGON3_5780S, 2636 quirk_msi_intx_disable_bug); 2637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2638 PCI_DEVICE_ID_TIGON3_5714, 2639 quirk_msi_intx_disable_bug); 2640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2641 PCI_DEVICE_ID_TIGON3_5714S, 2642 quirk_msi_intx_disable_bug); 2643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2644 PCI_DEVICE_ID_TIGON3_5715, 2645 quirk_msi_intx_disable_bug); 2646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2647 PCI_DEVICE_ID_TIGON3_5715S, 2648 quirk_msi_intx_disable_bug); 2649 2650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2651 quirk_msi_intx_disable_ati_bug); 2652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2653 quirk_msi_intx_disable_ati_bug); 2654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2655 quirk_msi_intx_disable_ati_bug); 2656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2657 quirk_msi_intx_disable_ati_bug); 2658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2659 quirk_msi_intx_disable_ati_bug); 2660 2661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2662 quirk_msi_intx_disable_bug); 2663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2664 quirk_msi_intx_disable_bug); 2665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2666 quirk_msi_intx_disable_bug); 2667 2668 #endif /* CONFIG_PCI_MSI */ 2669 2670 /* Allow manual resource allocation for PCI hotplug bridges 2671 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2672 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2673 * kernel fails to allocate resources when hotplug device is 2674 * inserted and PCI bus is rescanned. 2675 */ 2676 static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) 2677 { 2678 dev->is_hotplug_bridge = 1; 2679 } 2680 2681 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2682 2683 /* 2684 * This is a quirk for the Ricoh MMC controller found as a part of 2685 * some mulifunction chips. 2686 2687 * This is very similar and based on the ricoh_mmc driver written by 2688 * Philip Langdale. Thank you for these magic sequences. 2689 * 2690 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2691 * and one or both of cardbus or firewire. 2692 * 2693 * It happens that they implement SD and MMC 2694 * support as separate controllers (and PCI functions). The linux SDHCI 2695 * driver supports MMC cards but the chip detects MMC cards in hardware 2696 * and directs them to the MMC controller - so the SDHCI driver never sees 2697 * them. 2698 * 2699 * To get around this, we must disable the useless MMC controller. 2700 * At that point, the SDHCI controller will start seeing them 2701 * It seems to be the case that the relevant PCI registers to deactivate the 2702 * MMC controller live on PCI function 0, which might be the cardbus controller 2703 * or the firewire controller, depending on the particular chip in question 2704 * 2705 * This has to be done early, because as soon as we disable the MMC controller 2706 * other pci functions shift up one level, e.g. function #2 becomes function 2707 * #1, and this will confuse the pci core. 2708 */ 2709 2710 #ifdef CONFIG_MMC_RICOH_MMC 2711 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2712 { 2713 /* disable via cardbus interface */ 2714 u8 write_enable; 2715 u8 write_target; 2716 u8 disable; 2717 2718 /* disable must be done via function #0 */ 2719 if (PCI_FUNC(dev->devfn)) 2720 return; 2721 2722 pci_read_config_byte(dev, 0xB7, &disable); 2723 if (disable & 0x02) 2724 return; 2725 2726 pci_read_config_byte(dev, 0x8E, &write_enable); 2727 pci_write_config_byte(dev, 0x8E, 0xAA); 2728 pci_read_config_byte(dev, 0x8D, &write_target); 2729 pci_write_config_byte(dev, 0x8D, 0xB7); 2730 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2731 pci_write_config_byte(dev, 0x8E, write_enable); 2732 pci_write_config_byte(dev, 0x8D, write_target); 2733 2734 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2735 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2736 } 2737 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2738 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2739 2740 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2741 { 2742 /* disable via firewire interface */ 2743 u8 write_enable; 2744 u8 disable; 2745 2746 /* disable must be done via function #0 */ 2747 if (PCI_FUNC(dev->devfn)) 2748 return; 2749 /* 2750 * RICOH 0xe823 SD/MMC card reader fails to recognize 2751 * certain types of SD/MMC cards. Lowering the SD base 2752 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2753 * 2754 * 0x150 - SD2.0 mode enable for changing base clock 2755 * frequency to 50Mhz 2756 * 0xe1 - Base clock frequency 2757 * 0x32 - 50Mhz new clock frequency 2758 * 0xf9 - Key register for 0x150 2759 * 0xfc - key register for 0xe1 2760 */ 2761 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2762 pci_write_config_byte(dev, 0xf9, 0xfc); 2763 pci_write_config_byte(dev, 0x150, 0x10); 2764 pci_write_config_byte(dev, 0xf9, 0x00); 2765 pci_write_config_byte(dev, 0xfc, 0x01); 2766 pci_write_config_byte(dev, 0xe1, 0x32); 2767 pci_write_config_byte(dev, 0xfc, 0x00); 2768 2769 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2770 } 2771 2772 pci_read_config_byte(dev, 0xCB, &disable); 2773 2774 if (disable & 0x02) 2775 return; 2776 2777 pci_read_config_byte(dev, 0xCA, &write_enable); 2778 pci_write_config_byte(dev, 0xCA, 0x57); 2779 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2780 pci_write_config_byte(dev, 0xCA, write_enable); 2781 2782 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2783 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2784 2785 } 2786 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2787 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2788 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2789 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2790 #endif /*CONFIG_MMC_RICOH_MMC*/ 2791 2792 #ifdef CONFIG_DMAR_TABLE 2793 #define VTUNCERRMSK_REG 0x1ac 2794 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2795 /* 2796 * This is a quirk for masking vt-d spec defined errors to platform error 2797 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2798 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2799 * on the RAS config settings of the platform) when a vt-d fault happens. 2800 * The resulting SMI caused the system to hang. 2801 * 2802 * VT-d spec related errors are already handled by the VT-d OS code, so no 2803 * need to report the same error through other channels. 2804 */ 2805 static void vtd_mask_spec_errors(struct pci_dev *dev) 2806 { 2807 u32 word; 2808 2809 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2810 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2811 } 2812 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2813 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2814 #endif 2815 2816 static void __devinit fixup_ti816x_class(struct pci_dev* dev) 2817 { 2818 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2819 if (dev->class == PCI_CLASS_NOT_DEFINED) { 2820 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); 2821 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; 2822 } 2823 } 2824 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class); 2825 2826 /* Some PCIe devices do not work reliably with the claimed maximum 2827 * payload size supported. 2828 */ 2829 static void __devinit fixup_mpss_256(struct pci_dev *dev) 2830 { 2831 dev->pcie_mpss = 1; /* 256 bytes */ 2832 } 2833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2834 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2836 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2837 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2838 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2839 2840 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2841 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2842 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2843 * until all of the devices are discovered and buses walked, read completion 2844 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2845 * it is possible to hotplug a device with MPS of 256B. 2846 */ 2847 static void __devinit quirk_intel_mc_errata(struct pci_dev *dev) 2848 { 2849 int err; 2850 u16 rcc; 2851 2852 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 2853 return; 2854 2855 /* Intel errata specifies bits to change but does not say what they are. 2856 * Keeping them magical until such time as the registers and values can 2857 * be explained. 2858 */ 2859 err = pci_read_config_word(dev, 0x48, &rcc); 2860 if (err) { 2861 dev_err(&dev->dev, "Error attempting to read the read " 2862 "completion coalescing register.\n"); 2863 return; 2864 } 2865 2866 if (!(rcc & (1 << 10))) 2867 return; 2868 2869 rcc &= ~(1 << 10); 2870 2871 err = pci_write_config_word(dev, 0x48, rcc); 2872 if (err) { 2873 dev_err(&dev->dev, "Error attempting to write the read " 2874 "completion coalescing register.\n"); 2875 return; 2876 } 2877 2878 pr_info_once("Read completion coalescing disabled due to hardware " 2879 "errata relating to 256B MPS.\n"); 2880 } 2881 /* Intel 5000 series memory controllers and ports 2-7 */ 2882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2896 /* Intel 5100 series memory controllers and ports 2-7 */ 2897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2908 2909 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2910 struct pci_fixup *end) 2911 { 2912 while (f < end) { 2913 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 2914 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 2915 dev_dbg(&dev->dev, "calling %pF\n", f->hook); 2916 f->hook(dev); 2917 } 2918 f++; 2919 } 2920 } 2921 2922 extern struct pci_fixup __start_pci_fixups_early[]; 2923 extern struct pci_fixup __end_pci_fixups_early[]; 2924 extern struct pci_fixup __start_pci_fixups_header[]; 2925 extern struct pci_fixup __end_pci_fixups_header[]; 2926 extern struct pci_fixup __start_pci_fixups_final[]; 2927 extern struct pci_fixup __end_pci_fixups_final[]; 2928 extern struct pci_fixup __start_pci_fixups_enable[]; 2929 extern struct pci_fixup __end_pci_fixups_enable[]; 2930 extern struct pci_fixup __start_pci_fixups_resume[]; 2931 extern struct pci_fixup __end_pci_fixups_resume[]; 2932 extern struct pci_fixup __start_pci_fixups_resume_early[]; 2933 extern struct pci_fixup __end_pci_fixups_resume_early[]; 2934 extern struct pci_fixup __start_pci_fixups_suspend[]; 2935 extern struct pci_fixup __end_pci_fixups_suspend[]; 2936 2937 2938 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2939 { 2940 struct pci_fixup *start, *end; 2941 2942 switch(pass) { 2943 case pci_fixup_early: 2944 start = __start_pci_fixups_early; 2945 end = __end_pci_fixups_early; 2946 break; 2947 2948 case pci_fixup_header: 2949 start = __start_pci_fixups_header; 2950 end = __end_pci_fixups_header; 2951 break; 2952 2953 case pci_fixup_final: 2954 start = __start_pci_fixups_final; 2955 end = __end_pci_fixups_final; 2956 break; 2957 2958 case pci_fixup_enable: 2959 start = __start_pci_fixups_enable; 2960 end = __end_pci_fixups_enable; 2961 break; 2962 2963 case pci_fixup_resume: 2964 start = __start_pci_fixups_resume; 2965 end = __end_pci_fixups_resume; 2966 break; 2967 2968 case pci_fixup_resume_early: 2969 start = __start_pci_fixups_resume_early; 2970 end = __end_pci_fixups_resume_early; 2971 break; 2972 2973 case pci_fixup_suspend: 2974 start = __start_pci_fixups_suspend; 2975 end = __end_pci_fixups_suspend; 2976 break; 2977 2978 default: 2979 /* stupid compiler warning, you would think with an enum... */ 2980 return; 2981 } 2982 pci_do_fixups(dev, start, end); 2983 } 2984 EXPORT_SYMBOL(pci_fixup_device); 2985 2986 static int __init pci_apply_final_quirks(void) 2987 { 2988 struct pci_dev *dev = NULL; 2989 u8 cls = 0; 2990 u8 tmp; 2991 2992 if (pci_cache_line_size) 2993 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 2994 pci_cache_line_size << 2); 2995 2996 for_each_pci_dev(dev) { 2997 pci_fixup_device(pci_fixup_final, dev); 2998 /* 2999 * If arch hasn't set it explicitly yet, use the CLS 3000 * value shared by all PCI devices. If there's a 3001 * mismatch, fall back to the default value. 3002 */ 3003 if (!pci_cache_line_size) { 3004 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3005 if (!cls) 3006 cls = tmp; 3007 if (!tmp || cls == tmp) 3008 continue; 3009 3010 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " 3011 "using %u bytes\n", cls << 2, tmp << 2, 3012 pci_dfl_cache_line_size << 2); 3013 pci_cache_line_size = pci_dfl_cache_line_size; 3014 } 3015 } 3016 if (!pci_cache_line_size) { 3017 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3018 cls << 2, pci_dfl_cache_line_size << 2); 3019 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3020 } 3021 3022 return 0; 3023 } 3024 3025 fs_initcall_sync(pci_apply_final_quirks); 3026 3027 /* 3028 * Followings are device-specific reset methods which can be used to 3029 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3030 * not available. 3031 */ 3032 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 3033 { 3034 int pos; 3035 3036 /* only implement PCI_CLASS_SERIAL_USB at present */ 3037 if (dev->class == PCI_CLASS_SERIAL_USB) { 3038 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 3039 if (!pos) 3040 return -ENOTTY; 3041 3042 if (probe) 3043 return 0; 3044 3045 pci_write_config_byte(dev, pos + 0x4, 1); 3046 msleep(100); 3047 3048 return 0; 3049 } else { 3050 return -ENOTTY; 3051 } 3052 } 3053 3054 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3055 { 3056 int pos; 3057 3058 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 3059 if (!pos) 3060 return -ENOTTY; 3061 3062 if (probe) 3063 return 0; 3064 3065 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, 3066 PCI_EXP_DEVCTL_BCR_FLR); 3067 msleep(100); 3068 3069 return 0; 3070 } 3071 3072 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3073 3074 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3075 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3076 reset_intel_82599_sfp_virtfn }, 3077 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3078 reset_intel_generic_dev }, 3079 { 0 } 3080 }; 3081 3082 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3083 { 3084 const struct pci_dev_reset_methods *i; 3085 3086 for (i = pci_dev_reset_methods; i->reset; i++) { 3087 if ((i->vendor == dev->vendor || 3088 i->vendor == (u16)PCI_ANY_ID) && 3089 (i->device == dev->device || 3090 i->device == (u16)PCI_ANY_ID)) 3091 return i->reset(dev, probe); 3092 } 3093 3094 return -ENOTTY; 3095 } 3096