1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/pci.h> 20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include <linux/dmi.h> 25 #include <linux/ioport.h> 26 #include <linux/sched.h> 27 #include <linux/ktime.h> 28 #include <linux/mm.h> 29 #include <linux/nvme.h> 30 #include <linux/platform_data/x86/apple.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/suspend.h> 33 #include <linux/switchtec.h> 34 #include "pci.h" 35 36 /* 37 * Retrain the link of a downstream PCIe port by hand if necessary. 38 * 39 * This is needed at least where a downstream port of the ASMedia ASM2824 40 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 41 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 42 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 43 * board. 44 * 45 * In such a configuration the switches are supposed to negotiate the link 46 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 47 * continues switching between the two speeds indefinitely and the data 48 * link layer never reaches the active state, with link training reported 49 * repeatedly active ~84% of the time. Forcing the target link speed to 50 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 51 * each other correctly however. And more interestingly retraining with a 52 * higher target link speed afterwards lets the two successfully negotiate 53 * 5.0GT/s. 54 * 55 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 56 * Link Active status bit and in the failed link training scenario it will 57 * be off along with the Link Bandwidth Management Status indicating that 58 * hardware has changed the link speed or width in an attempt to correct 59 * unreliable link operation. For a port that has been left unconnected 60 * both bits will be clear. So use this information to detect the problem 61 * rather than polling the Link Training bit and watching out for flips or 62 * at least the active status. 63 * 64 * Since the exact nature of the problem isn't known and in principle this 65 * could trigger where an ASM2824 device is downstream rather upstream, 66 * apply this erratum workaround to any downstream ports as long as they 67 * support Link Active reporting and have the Link Control 2 register. 68 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 69 * request a retrain and check the result. 70 * 71 * If this turns out successful and we know by the Vendor:Device ID it is 72 * safe to do so, then lift the restriction, letting the devices negotiate 73 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 74 * firmware may have already arranged and lift it with ports that already 75 * report their data link being up. 76 * 77 * Otherwise revert the speed to the original setting and request a retrain 78 * again to remove any residual state, ignoring the result as it's supposed 79 * to fail anyway. 80 * 81 * Return 0 if the link has been successfully retrained. Return an error 82 * if retraining was not needed or we attempted a retrain and it failed. 83 */ 84 int pcie_failed_link_retrain(struct pci_dev *dev) 85 { 86 static const struct pci_device_id ids[] = { 87 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 88 {} 89 }; 90 u16 lnksta, lnkctl2; 91 int ret = -ENOTTY; 92 93 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 94 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 95 return ret; 96 97 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 98 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 99 if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) == 100 PCI_EXP_LNKSTA_LBMS) { 101 u16 oldlnkctl2 = lnkctl2; 102 103 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 104 105 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 106 lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT; 107 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 108 109 ret = pcie_retrain_link(dev, false); 110 if (ret) { 111 pci_info(dev, "retraining failed\n"); 112 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, 113 oldlnkctl2); 114 pcie_retrain_link(dev, true); 115 return ret; 116 } 117 118 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 119 } 120 121 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 122 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 123 pci_match_id(ids, dev)) { 124 u32 lnkcap; 125 126 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 127 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 128 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 129 lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS; 130 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 131 132 ret = pcie_retrain_link(dev, false); 133 if (ret) { 134 pci_info(dev, "retraining failed\n"); 135 return ret; 136 } 137 } 138 139 return ret; 140 } 141 142 static ktime_t fixup_debug_start(struct pci_dev *dev, 143 void (*fn)(struct pci_dev *dev)) 144 { 145 if (initcall_debug) 146 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 147 148 return ktime_get(); 149 } 150 151 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 152 void (*fn)(struct pci_dev *dev)) 153 { 154 ktime_t delta, rettime; 155 unsigned long long duration; 156 157 rettime = ktime_get(); 158 delta = ktime_sub(rettime, calltime); 159 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 160 if (initcall_debug || duration > 10000) 161 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 162 } 163 164 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 165 struct pci_fixup *end) 166 { 167 ktime_t calltime; 168 169 for (; f < end; f++) 170 if ((f->class == (u32) (dev->class >> f->class_shift) || 171 f->class == (u32) PCI_ANY_ID) && 172 (f->vendor == dev->vendor || 173 f->vendor == (u16) PCI_ANY_ID) && 174 (f->device == dev->device || 175 f->device == (u16) PCI_ANY_ID)) { 176 void (*hook)(struct pci_dev *dev); 177 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 178 hook = offset_to_ptr(&f->hook_offset); 179 #else 180 hook = f->hook; 181 #endif 182 calltime = fixup_debug_start(dev, hook); 183 hook(dev); 184 fixup_debug_report(dev, calltime, hook); 185 } 186 } 187 188 extern struct pci_fixup __start_pci_fixups_early[]; 189 extern struct pci_fixup __end_pci_fixups_early[]; 190 extern struct pci_fixup __start_pci_fixups_header[]; 191 extern struct pci_fixup __end_pci_fixups_header[]; 192 extern struct pci_fixup __start_pci_fixups_final[]; 193 extern struct pci_fixup __end_pci_fixups_final[]; 194 extern struct pci_fixup __start_pci_fixups_enable[]; 195 extern struct pci_fixup __end_pci_fixups_enable[]; 196 extern struct pci_fixup __start_pci_fixups_resume[]; 197 extern struct pci_fixup __end_pci_fixups_resume[]; 198 extern struct pci_fixup __start_pci_fixups_resume_early[]; 199 extern struct pci_fixup __end_pci_fixups_resume_early[]; 200 extern struct pci_fixup __start_pci_fixups_suspend[]; 201 extern struct pci_fixup __end_pci_fixups_suspend[]; 202 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 203 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 204 205 static bool pci_apply_fixup_final_quirks; 206 207 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 208 { 209 struct pci_fixup *start, *end; 210 211 switch (pass) { 212 case pci_fixup_early: 213 start = __start_pci_fixups_early; 214 end = __end_pci_fixups_early; 215 break; 216 217 case pci_fixup_header: 218 start = __start_pci_fixups_header; 219 end = __end_pci_fixups_header; 220 break; 221 222 case pci_fixup_final: 223 if (!pci_apply_fixup_final_quirks) 224 return; 225 start = __start_pci_fixups_final; 226 end = __end_pci_fixups_final; 227 break; 228 229 case pci_fixup_enable: 230 start = __start_pci_fixups_enable; 231 end = __end_pci_fixups_enable; 232 break; 233 234 case pci_fixup_resume: 235 start = __start_pci_fixups_resume; 236 end = __end_pci_fixups_resume; 237 break; 238 239 case pci_fixup_resume_early: 240 start = __start_pci_fixups_resume_early; 241 end = __end_pci_fixups_resume_early; 242 break; 243 244 case pci_fixup_suspend: 245 start = __start_pci_fixups_suspend; 246 end = __end_pci_fixups_suspend; 247 break; 248 249 case pci_fixup_suspend_late: 250 start = __start_pci_fixups_suspend_late; 251 end = __end_pci_fixups_suspend_late; 252 break; 253 254 default: 255 /* stupid compiler warning, you would think with an enum... */ 256 return; 257 } 258 pci_do_fixups(dev, start, end); 259 } 260 EXPORT_SYMBOL(pci_fixup_device); 261 262 static int __init pci_apply_final_quirks(void) 263 { 264 struct pci_dev *dev = NULL; 265 u8 cls = 0; 266 u8 tmp; 267 268 if (pci_cache_line_size) 269 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 270 271 pci_apply_fixup_final_quirks = true; 272 for_each_pci_dev(dev) { 273 pci_fixup_device(pci_fixup_final, dev); 274 /* 275 * If arch hasn't set it explicitly yet, use the CLS 276 * value shared by all PCI devices. If there's a 277 * mismatch, fall back to the default value. 278 */ 279 if (!pci_cache_line_size) { 280 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 281 if (!cls) 282 cls = tmp; 283 if (!tmp || cls == tmp) 284 continue; 285 286 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 287 cls << 2, tmp << 2, 288 pci_dfl_cache_line_size << 2); 289 pci_cache_line_size = pci_dfl_cache_line_size; 290 } 291 } 292 293 if (!pci_cache_line_size) { 294 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 295 pci_dfl_cache_line_size << 2); 296 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 297 } 298 299 return 0; 300 } 301 fs_initcall_sync(pci_apply_final_quirks); 302 303 /* 304 * Decoding should be disabled for a PCI device during BAR sizing to avoid 305 * conflict. But doing so may cause problems on host bridge and perhaps other 306 * key system devices. For devices that need to have mmio decoding always-on, 307 * we need to set the dev->mmio_always_on bit. 308 */ 309 static void quirk_mmio_always_on(struct pci_dev *dev) 310 { 311 dev->mmio_always_on = 1; 312 } 313 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 314 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 315 316 /* 317 * The Mellanox Tavor device gives false positive parity errors. Disable 318 * parity error reporting. 319 */ 320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 322 323 /* 324 * Deal with broken BIOSes that neglect to enable passive release, 325 * which can cause problems in combination with the 82441FX/PPro MTRRs 326 */ 327 static void quirk_passive_release(struct pci_dev *dev) 328 { 329 struct pci_dev *d = NULL; 330 unsigned char dlc; 331 332 /* 333 * We have to make sure a particular bit is set in the PIIX3 334 * ISA bridge, so we have to go out and find it. 335 */ 336 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 337 pci_read_config_byte(d, 0x82, &dlc); 338 if (!(dlc & 1<<1)) { 339 pci_info(d, "PIIX3: Enabling Passive Release\n"); 340 dlc |= 1<<1; 341 pci_write_config_byte(d, 0x82, dlc); 342 } 343 } 344 } 345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 346 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 347 348 #ifdef CONFIG_X86_32 349 /* 350 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 351 * workaround but VIA don't answer queries. If you happen to have good 352 * contacts at VIA ask them for me please -- Alan 353 * 354 * This appears to be BIOS not version dependent. So presumably there is a 355 * chipset level fix. 356 */ 357 static void quirk_isa_dma_hangs(struct pci_dev *dev) 358 { 359 if (!isa_dma_bridge_buggy) { 360 isa_dma_bridge_buggy = 1; 361 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 362 } 363 } 364 /* 365 * It's not totally clear which chipsets are the problematic ones. We know 366 * 82C586 and 82C596 variants are affected. 367 */ 368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 375 #endif 376 377 #ifdef CONFIG_HAS_IOPORT 378 /* 379 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 380 * for some HT machines to use C4 w/o hanging. 381 */ 382 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 383 { 384 u32 pmbase; 385 u16 pm1a; 386 387 pci_read_config_dword(dev, 0x40, &pmbase); 388 pmbase = pmbase & 0xff80; 389 pm1a = inw(pmbase); 390 391 if (pm1a & 0x10) { 392 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 393 outw(0x10, pmbase); 394 } 395 } 396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 397 #endif 398 399 /* Chipsets where PCI->PCI transfers vanish or hang */ 400 static void quirk_nopcipci(struct pci_dev *dev) 401 { 402 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 403 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 404 pci_pci_problems |= PCIPCI_FAIL; 405 } 406 } 407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 409 410 static void quirk_nopciamd(struct pci_dev *dev) 411 { 412 u8 rev; 413 pci_read_config_byte(dev, 0x08, &rev); 414 if (rev == 0x13) { 415 /* Erratum 24 */ 416 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 417 pci_pci_problems |= PCIAGP_FAIL; 418 } 419 } 420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 421 422 /* Triton requires workarounds to be used by the drivers */ 423 static void quirk_triton(struct pci_dev *dev) 424 { 425 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 426 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 427 pci_pci_problems |= PCIPCI_TRITON; 428 } 429 } 430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 434 435 /* 436 * VIA Apollo KT133 needs PCI latency patch 437 * Made according to a Windows driver-based patch by George E. Breese; 438 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 439 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 440 * which Mr Breese based his work. 441 * 442 * Updated based on further information from the site and also on 443 * information provided by VIA 444 */ 445 static void quirk_vialatency(struct pci_dev *dev) 446 { 447 struct pci_dev *p; 448 u8 busarb; 449 450 /* 451 * Ok, we have a potential problem chipset here. Now see if we have 452 * a buggy southbridge. 453 */ 454 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 455 if (p != NULL) { 456 457 /* 458 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 459 * thanks Dan Hollis. 460 * Check for buggy part revisions 461 */ 462 if (p->revision < 0x40 || p->revision > 0x42) 463 goto exit; 464 } else { 465 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 466 if (p == NULL) /* No problem parts */ 467 goto exit; 468 469 /* Check for buggy part revisions */ 470 if (p->revision < 0x10 || p->revision > 0x12) 471 goto exit; 472 } 473 474 /* 475 * Ok we have the problem. Now set the PCI master grant to occur 476 * every master grant. The apparent bug is that under high PCI load 477 * (quite common in Linux of course) you can get data loss when the 478 * CPU is held off the bus for 3 bus master requests. This happens 479 * to include the IDE controllers.... 480 * 481 * VIA only apply this fix when an SB Live! is present but under 482 * both Linux and Windows this isn't enough, and we have seen 483 * corruption without SB Live! but with things like 3 UDMA IDE 484 * controllers. So we ignore that bit of the VIA recommendation.. 485 */ 486 pci_read_config_byte(dev, 0x76, &busarb); 487 488 /* 489 * Set bit 4 and bit 5 of byte 76 to 0x01 490 * "Master priority rotation on every PCI master grant" 491 */ 492 busarb &= ~(1<<5); 493 busarb |= (1<<4); 494 pci_write_config_byte(dev, 0x76, busarb); 495 pci_info(dev, "Applying VIA southbridge workaround\n"); 496 exit: 497 pci_dev_put(p); 498 } 499 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 502 /* Must restore this on a resume from RAM */ 503 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 504 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 505 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 506 507 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 508 static void quirk_viaetbf(struct pci_dev *dev) 509 { 510 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 511 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 512 pci_pci_problems |= PCIPCI_VIAETBF; 513 } 514 } 515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 516 517 static void quirk_vsfx(struct pci_dev *dev) 518 { 519 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 520 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 521 pci_pci_problems |= PCIPCI_VSFX; 522 } 523 } 524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 525 526 /* 527 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 528 * space. Latency must be set to 0xA and Triton workaround applied too. 529 * [Info kindly provided by ALi] 530 */ 531 static void quirk_alimagik(struct pci_dev *dev) 532 { 533 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 534 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 535 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 536 } 537 } 538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 540 541 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 542 static void quirk_natoma(struct pci_dev *dev) 543 { 544 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 545 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 546 pci_pci_problems |= PCIPCI_NATOMA; 547 } 548 } 549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 555 556 /* 557 * This chip can cause PCI parity errors if config register 0xA0 is read 558 * while DMAs are occurring. 559 */ 560 static void quirk_citrine(struct pci_dev *dev) 561 { 562 dev->cfg_size = 0xA0; 563 } 564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 565 566 /* 567 * This chip can cause bus lockups if config addresses above 0x600 568 * are read or written. 569 */ 570 static void quirk_nfp6000(struct pci_dev *dev) 571 { 572 dev->cfg_size = 0x600; 573 } 574 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 575 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 577 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 578 579 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 580 static void quirk_extend_bar_to_page(struct pci_dev *dev) 581 { 582 int i; 583 584 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 585 struct resource *r = &dev->resource[i]; 586 587 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 588 r->end = PAGE_SIZE - 1; 589 r->start = 0; 590 r->flags |= IORESOURCE_UNSET; 591 pci_info(dev, "expanded BAR %d to page size: %pR\n", 592 i, r); 593 } 594 } 595 } 596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 597 598 /* 599 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 600 * If it's needed, re-allocate the region. 601 */ 602 static void quirk_s3_64M(struct pci_dev *dev) 603 { 604 struct resource *r = &dev->resource[0]; 605 606 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 607 r->flags |= IORESOURCE_UNSET; 608 r->start = 0; 609 r->end = 0x3ffffff; 610 } 611 } 612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 614 615 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 616 const char *name) 617 { 618 u32 region; 619 struct pci_bus_region bus_region; 620 struct resource *res = dev->resource + pos; 621 622 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 623 624 if (!region) 625 return; 626 627 res->name = pci_name(dev); 628 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 629 res->flags |= 630 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 631 region &= ~(size - 1); 632 633 /* Convert from PCI bus to resource space */ 634 bus_region.start = region; 635 bus_region.end = region + size - 1; 636 pcibios_bus_to_resource(dev->bus, res, &bus_region); 637 638 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 639 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 640 } 641 642 /* 643 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 644 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 645 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 646 * (which conflicts w/ BAR1's memory range). 647 * 648 * CS553x's ISA PCI BARs may also be read-only (ref: 649 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 650 */ 651 static void quirk_cs5536_vsa(struct pci_dev *dev) 652 { 653 static char *name = "CS5536 ISA bridge"; 654 655 if (pci_resource_len(dev, 0) != 8) { 656 quirk_io(dev, 0, 8, name); /* SMB */ 657 quirk_io(dev, 1, 256, name); /* GPIO */ 658 quirk_io(dev, 2, 64, name); /* MFGPT */ 659 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 660 name); 661 } 662 } 663 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 664 665 static void quirk_io_region(struct pci_dev *dev, int port, 666 unsigned int size, int nr, const char *name) 667 { 668 u16 region; 669 struct pci_bus_region bus_region; 670 struct resource *res = dev->resource + nr; 671 672 pci_read_config_word(dev, port, ®ion); 673 region &= ~(size - 1); 674 675 if (!region) 676 return; 677 678 res->name = pci_name(dev); 679 res->flags = IORESOURCE_IO; 680 681 /* Convert from PCI bus to resource space */ 682 bus_region.start = region; 683 bus_region.end = region + size - 1; 684 pcibios_bus_to_resource(dev->bus, res, &bus_region); 685 686 if (!pci_claim_resource(dev, nr)) 687 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 688 } 689 690 /* 691 * ATI Northbridge setups MCE the processor if you even read somewhere 692 * between 0x3b0->0x3bb or read 0x3d3 693 */ 694 static void quirk_ati_exploding_mce(struct pci_dev *dev) 695 { 696 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 697 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 698 request_region(0x3b0, 0x0C, "RadeonIGP"); 699 request_region(0x3d3, 0x01, "RadeonIGP"); 700 } 701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 702 703 /* 704 * In the AMD NL platform, this device ([1022:7912]) has a class code of 705 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 706 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 707 * 708 * But the dwc3 driver is a more specific driver for this device, and we'd 709 * prefer to use it instead of xhci. To prevent xhci from claiming the 710 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 711 * defines as "USB device (not host controller)". The dwc3 driver can then 712 * claim it based on its Vendor and Device ID. 713 */ 714 static void quirk_amd_dwc_class(struct pci_dev *pdev) 715 { 716 u32 class = pdev->class; 717 718 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 719 /* Use "USB Device (not host controller)" class */ 720 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 721 pci_info(pdev, 722 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 723 class, pdev->class); 724 } 725 } 726 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 727 quirk_amd_dwc_class); 728 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 729 quirk_amd_dwc_class); 730 731 /* 732 * Synopsys USB 3.x host HAPS platform has a class code of 733 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 734 * devices should use dwc3-haps driver. Change these devices' class code to 735 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 736 * them. 737 */ 738 static void quirk_synopsys_haps(struct pci_dev *pdev) 739 { 740 u32 class = pdev->class; 741 742 switch (pdev->device) { 743 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 744 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 745 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 746 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 747 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 748 class, pdev->class); 749 break; 750 } 751 } 752 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 753 PCI_CLASS_SERIAL_USB_XHCI, 0, 754 quirk_synopsys_haps); 755 756 /* 757 * Let's make the southbridge information explicit instead of having to 758 * worry about people probing the ACPI areas, for example.. (Yes, it 759 * happens, and if you read the wrong ACPI register it will put the machine 760 * to sleep with no way of waking it up again. Bummer). 761 * 762 * ALI M7101: Two IO regions pointed to by words at 763 * 0xE0 (64 bytes of ACPI registers) 764 * 0xE2 (32 bytes of SMB registers) 765 */ 766 static void quirk_ali7101_acpi(struct pci_dev *dev) 767 { 768 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 769 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 770 } 771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 772 773 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 774 { 775 u32 devres; 776 u32 mask, size, base; 777 778 pci_read_config_dword(dev, port, &devres); 779 if ((devres & enable) != enable) 780 return; 781 mask = (devres >> 16) & 15; 782 base = devres & 0xffff; 783 size = 16; 784 for (;;) { 785 unsigned int bit = size >> 1; 786 if ((bit & mask) == bit) 787 break; 788 size = bit; 789 } 790 /* 791 * For now we only print it out. Eventually we'll want to 792 * reserve it (at least if it's in the 0x1000+ range), but 793 * let's get enough confirmation reports first. 794 */ 795 base &= -size; 796 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 797 } 798 799 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 800 { 801 u32 devres; 802 u32 mask, size, base; 803 804 pci_read_config_dword(dev, port, &devres); 805 if ((devres & enable) != enable) 806 return; 807 base = devres & 0xffff0000; 808 mask = (devres & 0x3f) << 16; 809 size = 128 << 16; 810 for (;;) { 811 unsigned int bit = size >> 1; 812 if ((bit & mask) == bit) 813 break; 814 size = bit; 815 } 816 817 /* 818 * For now we only print it out. Eventually we'll want to 819 * reserve it, but let's get enough confirmation reports first. 820 */ 821 base &= -size; 822 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 823 } 824 825 /* 826 * PIIX4 ACPI: Two IO regions pointed to by longwords at 827 * 0x40 (64 bytes of ACPI registers) 828 * 0x90 (16 bytes of SMB registers) 829 * and a few strange programmable PIIX4 device resources. 830 */ 831 static void quirk_piix4_acpi(struct pci_dev *dev) 832 { 833 u32 res_a; 834 835 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 836 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 837 838 /* Device resource A has enables for some of the other ones */ 839 pci_read_config_dword(dev, 0x5c, &res_a); 840 841 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 842 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 843 844 /* Device resource D is just bitfields for static resources */ 845 846 /* Device 12 enabled? */ 847 if (res_a & (1 << 29)) { 848 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 849 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 850 } 851 /* Device 13 enabled? */ 852 if (res_a & (1 << 30)) { 853 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 854 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 855 } 856 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 857 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 858 } 859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 861 862 #define ICH_PMBASE 0x40 863 #define ICH_ACPI_CNTL 0x44 864 #define ICH4_ACPI_EN 0x10 865 #define ICH6_ACPI_EN 0x80 866 #define ICH4_GPIOBASE 0x58 867 #define ICH4_GPIO_CNTL 0x5c 868 #define ICH4_GPIO_EN 0x10 869 #define ICH6_GPIOBASE 0x48 870 #define ICH6_GPIO_CNTL 0x4c 871 #define ICH6_GPIO_EN 0x10 872 873 /* 874 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 875 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 876 * 0x58 (64 bytes of GPIO I/O space) 877 */ 878 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 879 { 880 u8 enable; 881 882 /* 883 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 884 * with low legacy (and fixed) ports. We don't know the decoding 885 * priority and can't tell whether the legacy device or the one created 886 * here is really at that address. This happens on boards with broken 887 * BIOSes. 888 */ 889 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 890 if (enable & ICH4_ACPI_EN) 891 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 892 "ICH4 ACPI/GPIO/TCO"); 893 894 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 895 if (enable & ICH4_GPIO_EN) 896 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 897 "ICH4 GPIO"); 898 } 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 909 910 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 911 { 912 u8 enable; 913 914 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 915 if (enable & ICH6_ACPI_EN) 916 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 917 "ICH6 ACPI/GPIO/TCO"); 918 919 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 920 if (enable & ICH6_GPIO_EN) 921 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 922 "ICH6 GPIO"); 923 } 924 925 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 926 const char *name, int dynsize) 927 { 928 u32 val; 929 u32 size, base; 930 931 pci_read_config_dword(dev, reg, &val); 932 933 /* Enabled? */ 934 if (!(val & 1)) 935 return; 936 base = val & 0xfffc; 937 if (dynsize) { 938 /* 939 * This is not correct. It is 16, 32 or 64 bytes depending on 940 * register D31:F0:ADh bits 5:4. 941 * 942 * But this gets us at least _part_ of it. 943 */ 944 size = 16; 945 } else { 946 size = 128; 947 } 948 base &= ~(size-1); 949 950 /* 951 * Just print it out for now. We should reserve it after more 952 * debugging. 953 */ 954 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 955 } 956 957 static void quirk_ich6_lpc(struct pci_dev *dev) 958 { 959 /* Shared ACPI/GPIO decode with all ICH6+ */ 960 ich6_lpc_acpi_gpio(dev); 961 962 /* ICH6-specific generic IO decode */ 963 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 964 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 965 } 966 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 968 969 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 970 const char *name) 971 { 972 u32 val; 973 u32 mask, base; 974 975 pci_read_config_dword(dev, reg, &val); 976 977 /* Enabled? */ 978 if (!(val & 1)) 979 return; 980 981 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 982 base = val & 0xfffc; 983 mask = (val >> 16) & 0xfc; 984 mask |= 3; 985 986 /* 987 * Just print it out for now. We should reserve it after more 988 * debugging. 989 */ 990 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 991 } 992 993 /* ICH7-10 has the same common LPC generic IO decode registers */ 994 static void quirk_ich7_lpc(struct pci_dev *dev) 995 { 996 /* We share the common ACPI/GPIO decode with ICH6 */ 997 ich6_lpc_acpi_gpio(dev); 998 999 /* And have 4 ICH7+ generic decodes */ 1000 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1001 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1002 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1003 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1004 } 1005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1010 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1018 1019 /* 1020 * VIA ACPI: One IO region pointed to by longword at 1021 * 0x48 or 0x20 (256 bytes of ACPI registers) 1022 */ 1023 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1024 { 1025 if (dev->revision & 0x10) 1026 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1027 "vt82c586 ACPI"); 1028 } 1029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1030 1031 /* 1032 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1033 * 0x48 (256 bytes of ACPI registers) 1034 * 0x70 (128 bytes of hardware monitoring register) 1035 * 0x90 (16 bytes of SMB registers) 1036 */ 1037 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1038 { 1039 quirk_vt82c586_acpi(dev); 1040 1041 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1042 "vt82c686 HW-mon"); 1043 1044 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1045 } 1046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1047 1048 /* 1049 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1050 * 0x88 (128 bytes of power management registers) 1051 * 0xd0 (16 bytes of SMB registers) 1052 */ 1053 static void quirk_vt8235_acpi(struct pci_dev *dev) 1054 { 1055 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1056 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1057 } 1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1059 1060 /* 1061 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1062 * back-to-back: Disable fast back-to-back on the secondary bus segment 1063 */ 1064 static void quirk_xio2000a(struct pci_dev *dev) 1065 { 1066 struct pci_dev *pdev; 1067 u16 command; 1068 1069 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1070 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1071 pci_read_config_word(pdev, PCI_COMMAND, &command); 1072 if (command & PCI_COMMAND_FAST_BACK) 1073 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1074 } 1075 } 1076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1077 quirk_xio2000a); 1078 1079 #ifdef CONFIG_X86_IO_APIC 1080 1081 #include <asm/io_apic.h> 1082 1083 /* 1084 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1085 * devices to the external APIC. 1086 * 1087 * TODO: When we have device-specific interrupt routers, this code will go 1088 * away from quirks. 1089 */ 1090 static void quirk_via_ioapic(struct pci_dev *dev) 1091 { 1092 u8 tmp; 1093 1094 if (nr_ioapics < 1) 1095 tmp = 0; /* nothing routed to external APIC */ 1096 else 1097 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1098 1099 pci_info(dev, "%s VIA external APIC routing\n", 1100 tmp ? "Enabling" : "Disabling"); 1101 1102 /* Offset 0x58: External APIC IRQ output control */ 1103 pci_write_config_byte(dev, 0x58, tmp); 1104 } 1105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1106 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1107 1108 /* 1109 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1110 * This leads to doubled level interrupt rates. 1111 * Set this bit to get rid of cycle wastage. 1112 * Otherwise uncritical. 1113 */ 1114 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1115 { 1116 u8 misc_control2; 1117 #define BYPASS_APIC_DEASSERT 8 1118 1119 pci_read_config_byte(dev, 0x5B, &misc_control2); 1120 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1121 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1122 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1123 } 1124 } 1125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1126 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1127 1128 /* 1129 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1130 * We check all revs >= B0 (yet not in the pre production!) as the bug 1131 * is currently marked NoFix 1132 * 1133 * We have multiple reports of hangs with this chipset that went away with 1134 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1135 * of course. However the advice is demonstrably good even if so. 1136 */ 1137 static void quirk_amd_ioapic(struct pci_dev *dev) 1138 { 1139 if (dev->revision >= 0x02) { 1140 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1141 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1142 } 1143 } 1144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1145 #endif /* CONFIG_X86_IO_APIC */ 1146 1147 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1148 1149 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1150 { 1151 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1152 if (dev->subsystem_device == 0xa118) 1153 dev->sriov->link = dev->devfn; 1154 } 1155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1156 #endif 1157 1158 /* 1159 * Some settings of MMRBC can lead to data corruption so block changes. 1160 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1161 */ 1162 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1163 { 1164 if (dev->subordinate && dev->revision <= 0x12) { 1165 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1166 dev->revision); 1167 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1168 } 1169 } 1170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1171 1172 /* 1173 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1174 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1175 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1176 * of the ACPI SCI interrupt is only done for convenience. 1177 * -jgarzik 1178 */ 1179 static void quirk_via_acpi(struct pci_dev *d) 1180 { 1181 u8 irq; 1182 1183 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1184 pci_read_config_byte(d, 0x42, &irq); 1185 irq &= 0xf; 1186 if (irq && (irq != 2)) 1187 d->irq = irq; 1188 } 1189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1191 1192 /* VIA bridges which have VLink */ 1193 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1194 1195 static void quirk_via_bridge(struct pci_dev *dev) 1196 { 1197 /* See what bridge we have and find the device ranges */ 1198 switch (dev->device) { 1199 case PCI_DEVICE_ID_VIA_82C686: 1200 /* 1201 * The VT82C686 is special; it attaches to PCI and can have 1202 * any device number. All its subdevices are functions of 1203 * that single device. 1204 */ 1205 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1206 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1207 break; 1208 case PCI_DEVICE_ID_VIA_8237: 1209 case PCI_DEVICE_ID_VIA_8237A: 1210 via_vlink_dev_lo = 15; 1211 break; 1212 case PCI_DEVICE_ID_VIA_8235: 1213 via_vlink_dev_lo = 16; 1214 break; 1215 case PCI_DEVICE_ID_VIA_8231: 1216 case PCI_DEVICE_ID_VIA_8233_0: 1217 case PCI_DEVICE_ID_VIA_8233A: 1218 case PCI_DEVICE_ID_VIA_8233C_0: 1219 via_vlink_dev_lo = 17; 1220 break; 1221 } 1222 } 1223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1231 1232 /* 1233 * quirk_via_vlink - VIA VLink IRQ number update 1234 * @dev: PCI device 1235 * 1236 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1237 * the IRQ line register which usually is not relevant for PCI cards, is 1238 * actually written so that interrupts get sent to the right place. 1239 * 1240 * We only do this on systems where a VIA south bridge was detected, and 1241 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1242 */ 1243 static void quirk_via_vlink(struct pci_dev *dev) 1244 { 1245 u8 irq, new_irq; 1246 1247 /* Check if we have VLink at all */ 1248 if (via_vlink_dev_lo == -1) 1249 return; 1250 1251 new_irq = dev->irq; 1252 1253 /* Don't quirk interrupts outside the legacy IRQ range */ 1254 if (!new_irq || new_irq > 15) 1255 return; 1256 1257 /* Internal device ? */ 1258 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1259 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1260 return; 1261 1262 /* 1263 * This is an internal VLink device on a PIC interrupt. The BIOS 1264 * ought to have set this but may not have, so we redo it. 1265 */ 1266 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1267 if (new_irq != irq) { 1268 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1269 irq, new_irq); 1270 udelay(15); /* unknown if delay really needed */ 1271 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1272 } 1273 } 1274 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1275 1276 /* 1277 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1278 * of VT82C597 for backward compatibility. We need to switch it off to be 1279 * able to recognize the real type of the chip. 1280 */ 1281 static void quirk_vt82c598_id(struct pci_dev *dev) 1282 { 1283 pci_write_config_byte(dev, 0xfc, 0); 1284 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1285 } 1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1287 1288 /* 1289 * CardBus controllers have a legacy base address that enables them to 1290 * respond as i82365 pcmcia controllers. We don't want them to do this 1291 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1292 * driver does not (and should not) handle CardBus. 1293 */ 1294 static void quirk_cardbus_legacy(struct pci_dev *dev) 1295 { 1296 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1297 } 1298 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1299 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1300 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1301 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1302 1303 /* 1304 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1305 * what the designers were smoking but let's not inhale... 1306 * 1307 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1308 * turn it off! 1309 */ 1310 static void quirk_amd_ordering(struct pci_dev *dev) 1311 { 1312 u32 pcic; 1313 pci_read_config_dword(dev, 0x4C, &pcic); 1314 if ((pcic & 6) != 6) { 1315 pcic |= 6; 1316 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1317 pci_write_config_dword(dev, 0x4C, pcic); 1318 pci_read_config_dword(dev, 0x84, &pcic); 1319 pcic |= (1 << 23); /* Required in this mode */ 1320 pci_write_config_dword(dev, 0x84, pcic); 1321 } 1322 } 1323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1324 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1325 1326 /* 1327 * DreamWorks-provided workaround for Dunord I-3000 problem 1328 * 1329 * This card decodes and responds to addresses not apparently assigned to 1330 * it. We force a larger allocation to ensure that nothing gets put too 1331 * close to it. 1332 */ 1333 static void quirk_dunord(struct pci_dev *dev) 1334 { 1335 struct resource *r = &dev->resource[1]; 1336 1337 r->flags |= IORESOURCE_UNSET; 1338 r->start = 0; 1339 r->end = 0xffffff; 1340 } 1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1342 1343 /* 1344 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1345 * decoding (transparent), and does indicate this in the ProgIf. 1346 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1347 */ 1348 static void quirk_transparent_bridge(struct pci_dev *dev) 1349 { 1350 dev->transparent = 1; 1351 } 1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1354 1355 /* 1356 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1357 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1358 * found at http://www.national.com/analog for info on what these bits do. 1359 * <christer@weinigel.se> 1360 */ 1361 static void quirk_mediagx_master(struct pci_dev *dev) 1362 { 1363 u8 reg; 1364 1365 pci_read_config_byte(dev, 0x41, ®); 1366 if (reg & 2) { 1367 reg &= ~2; 1368 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1369 reg); 1370 pci_write_config_byte(dev, 0x41, reg); 1371 } 1372 } 1373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1374 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1375 1376 /* 1377 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1378 * in the odd case it is not the results are corruption hence the presence 1379 * of a Linux check. 1380 */ 1381 static void quirk_disable_pxb(struct pci_dev *pdev) 1382 { 1383 u16 config; 1384 1385 if (pdev->revision != 0x04) /* Only C0 requires this */ 1386 return; 1387 pci_read_config_word(pdev, 0x40, &config); 1388 if (config & (1<<6)) { 1389 config &= ~(1<<6); 1390 pci_write_config_word(pdev, 0x40, config); 1391 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1392 } 1393 } 1394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1396 1397 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1398 { 1399 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1400 u8 tmp; 1401 1402 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1403 if (tmp == 0x01) { 1404 pci_read_config_byte(pdev, 0x40, &tmp); 1405 pci_write_config_byte(pdev, 0x40, tmp|1); 1406 pci_write_config_byte(pdev, 0x9, 1); 1407 pci_write_config_byte(pdev, 0xa, 6); 1408 pci_write_config_byte(pdev, 0x40, tmp); 1409 1410 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1411 pci_info(pdev, "set SATA to AHCI mode\n"); 1412 } 1413 } 1414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1415 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1417 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1419 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1421 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1422 1423 /* Serverworks CSB5 IDE does not fully support native mode */ 1424 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1425 { 1426 u8 prog; 1427 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1428 if (prog & 5) { 1429 prog &= ~5; 1430 pdev->class &= ~5; 1431 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1432 /* PCI layer will sort out resources */ 1433 } 1434 } 1435 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1436 1437 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1438 static void quirk_ide_samemode(struct pci_dev *pdev) 1439 { 1440 u8 prog; 1441 1442 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1443 1444 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1445 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1446 prog &= ~5; 1447 pdev->class &= ~5; 1448 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1449 } 1450 } 1451 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1452 1453 /* Some ATA devices break if put into D3 */ 1454 static void quirk_no_ata_d3(struct pci_dev *pdev) 1455 { 1456 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1457 } 1458 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1459 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1460 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1461 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1462 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1463 /* ALi loses some register settings that we cannot then restore */ 1464 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1465 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1466 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1467 occur when mode detecting */ 1468 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1469 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1470 1471 /* 1472 * This was originally an Alpha-specific thing, but it really fits here. 1473 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1474 */ 1475 static void quirk_eisa_bridge(struct pci_dev *dev) 1476 { 1477 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1478 } 1479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1480 1481 /* 1482 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1483 * is not activated. The myth is that Asus said that they do not want the 1484 * users to be irritated by just another PCI Device in the Win98 device 1485 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1486 * package 2.7.0 for details) 1487 * 1488 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1489 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1490 * becomes necessary to do this tweak in two steps -- the chosen trigger 1491 * is either the Host bridge (preferred) or on-board VGA controller. 1492 * 1493 * Note that we used to unhide the SMBus that way on Toshiba laptops 1494 * (Satellite A40 and Tecra M2) but then found that the thermal management 1495 * was done by SMM code, which could cause unsynchronized concurrent 1496 * accesses to the SMBus registers, with potentially bad effects. Thus you 1497 * should be very careful when adding new entries: if SMM is accessing the 1498 * Intel SMBus, this is a very good reason to leave it hidden. 1499 * 1500 * Likewise, many recent laptops use ACPI for thermal management. If the 1501 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1502 * natively, and keeping the SMBus hidden is the right thing to do. If you 1503 * are about to add an entry in the table below, please first disassemble 1504 * the DSDT and double-check that there is no code accessing the SMBus. 1505 */ 1506 static int asus_hides_smbus; 1507 1508 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1509 { 1510 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1511 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1512 switch (dev->subsystem_device) { 1513 case 0x8025: /* P4B-LX */ 1514 case 0x8070: /* P4B */ 1515 case 0x8088: /* P4B533 */ 1516 case 0x1626: /* L3C notebook */ 1517 asus_hides_smbus = 1; 1518 } 1519 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1520 switch (dev->subsystem_device) { 1521 case 0x80b1: /* P4GE-V */ 1522 case 0x80b2: /* P4PE */ 1523 case 0x8093: /* P4B533-V */ 1524 asus_hides_smbus = 1; 1525 } 1526 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1527 switch (dev->subsystem_device) { 1528 case 0x8030: /* P4T533 */ 1529 asus_hides_smbus = 1; 1530 } 1531 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1532 switch (dev->subsystem_device) { 1533 case 0x8070: /* P4G8X Deluxe */ 1534 asus_hides_smbus = 1; 1535 } 1536 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1537 switch (dev->subsystem_device) { 1538 case 0x80c9: /* PU-DLS */ 1539 asus_hides_smbus = 1; 1540 } 1541 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1542 switch (dev->subsystem_device) { 1543 case 0x1751: /* M2N notebook */ 1544 case 0x1821: /* M5N notebook */ 1545 case 0x1897: /* A6L notebook */ 1546 asus_hides_smbus = 1; 1547 } 1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1549 switch (dev->subsystem_device) { 1550 case 0x184b: /* W1N notebook */ 1551 case 0x186a: /* M6Ne notebook */ 1552 asus_hides_smbus = 1; 1553 } 1554 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1555 switch (dev->subsystem_device) { 1556 case 0x80f2: /* P4P800-X */ 1557 asus_hides_smbus = 1; 1558 } 1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1560 switch (dev->subsystem_device) { 1561 case 0x1882: /* M6V notebook */ 1562 case 0x1977: /* A6VA notebook */ 1563 asus_hides_smbus = 1; 1564 } 1565 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1566 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1567 switch (dev->subsystem_device) { 1568 case 0x088C: /* HP Compaq nc8000 */ 1569 case 0x0890: /* HP Compaq nc6000 */ 1570 asus_hides_smbus = 1; 1571 } 1572 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1573 switch (dev->subsystem_device) { 1574 case 0x12bc: /* HP D330L */ 1575 case 0x12bd: /* HP D530 */ 1576 case 0x006a: /* HP Compaq nx9500 */ 1577 asus_hides_smbus = 1; 1578 } 1579 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1580 switch (dev->subsystem_device) { 1581 case 0x12bf: /* HP xw4100 */ 1582 asus_hides_smbus = 1; 1583 } 1584 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1585 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1586 switch (dev->subsystem_device) { 1587 case 0xC00C: /* Samsung P35 notebook */ 1588 asus_hides_smbus = 1; 1589 } 1590 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1591 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1592 switch (dev->subsystem_device) { 1593 case 0x0058: /* Compaq Evo N620c */ 1594 asus_hides_smbus = 1; 1595 } 1596 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1597 switch (dev->subsystem_device) { 1598 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1599 /* Motherboard doesn't have Host bridge 1600 * subvendor/subdevice IDs, therefore checking 1601 * its on-board VGA controller */ 1602 asus_hides_smbus = 1; 1603 } 1604 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1605 switch (dev->subsystem_device) { 1606 case 0x00b8: /* Compaq Evo D510 CMT */ 1607 case 0x00b9: /* Compaq Evo D510 SFF */ 1608 case 0x00ba: /* Compaq Evo D510 USDT */ 1609 /* Motherboard doesn't have Host bridge 1610 * subvendor/subdevice IDs and on-board VGA 1611 * controller is disabled if an AGP card is 1612 * inserted, therefore checking USB UHCI 1613 * Controller #1 */ 1614 asus_hides_smbus = 1; 1615 } 1616 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1617 switch (dev->subsystem_device) { 1618 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1619 /* Motherboard doesn't have host bridge 1620 * subvendor/subdevice IDs, therefore checking 1621 * its on-board VGA controller */ 1622 asus_hides_smbus = 1; 1623 } 1624 } 1625 } 1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1636 1637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1640 1641 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1642 { 1643 u16 val; 1644 1645 if (likely(!asus_hides_smbus)) 1646 return; 1647 1648 pci_read_config_word(dev, 0xF2, &val); 1649 if (val & 0x8) { 1650 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1651 pci_read_config_word(dev, 0xF2, &val); 1652 if (val & 0x8) 1653 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1654 val); 1655 else 1656 pci_info(dev, "Enabled i801 SMBus device\n"); 1657 } 1658 } 1659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1662 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1663 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1666 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1667 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1668 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1669 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1670 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1671 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1672 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1673 1674 /* It appears we just have one such device. If not, we have a warning */ 1675 static void __iomem *asus_rcba_base; 1676 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1677 { 1678 u32 rcba; 1679 1680 if (likely(!asus_hides_smbus)) 1681 return; 1682 WARN_ON(asus_rcba_base); 1683 1684 pci_read_config_dword(dev, 0xF0, &rcba); 1685 /* use bits 31:14, 16 kB aligned */ 1686 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1687 if (asus_rcba_base == NULL) 1688 return; 1689 } 1690 1691 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1692 { 1693 u32 val; 1694 1695 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1696 return; 1697 1698 /* read the Function Disable register, dword mode only */ 1699 val = readl(asus_rcba_base + 0x3418); 1700 1701 /* enable the SMBus device */ 1702 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1703 } 1704 1705 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1706 { 1707 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1708 return; 1709 1710 iounmap(asus_rcba_base); 1711 asus_rcba_base = NULL; 1712 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1713 } 1714 1715 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1716 { 1717 asus_hides_smbus_lpc_ich6_suspend(dev); 1718 asus_hides_smbus_lpc_ich6_resume_early(dev); 1719 asus_hides_smbus_lpc_ich6_resume(dev); 1720 } 1721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1722 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1723 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1724 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1725 1726 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1727 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1728 { 1729 u8 val = 0; 1730 pci_read_config_byte(dev, 0x77, &val); 1731 if (val & 0x10) { 1732 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1733 pci_write_config_byte(dev, 0x77, val & ~0x10); 1734 } 1735 } 1736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1739 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1740 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1741 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1742 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1743 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1744 1745 /* 1746 * ... This is further complicated by the fact that some SiS96x south 1747 * bridges pretend to be 85C503/5513 instead. In that case see if we 1748 * spotted a compatible north bridge to make sure. 1749 * (pci_find_device() doesn't work yet) 1750 * 1751 * We can also enable the sis96x bit in the discovery register.. 1752 */ 1753 #define SIS_DETECT_REGISTER 0x40 1754 1755 static void quirk_sis_503(struct pci_dev *dev) 1756 { 1757 u8 reg; 1758 u16 devid; 1759 1760 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1761 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1762 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1763 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1764 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1765 return; 1766 } 1767 1768 /* 1769 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1770 * it has already been processed. (Depends on link order, which is 1771 * apparently not guaranteed) 1772 */ 1773 dev->device = devid; 1774 quirk_sis_96x_smbus(dev); 1775 } 1776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1777 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1778 1779 /* 1780 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1781 * and MC97 modem controller are disabled when a second PCI soundcard is 1782 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1783 * -- bjd 1784 */ 1785 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1786 { 1787 u8 val; 1788 int asus_hides_ac97 = 0; 1789 1790 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1791 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1792 asus_hides_ac97 = 1; 1793 } 1794 1795 if (!asus_hides_ac97) 1796 return; 1797 1798 pci_read_config_byte(dev, 0x50, &val); 1799 if (val & 0xc0) { 1800 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1801 pci_read_config_byte(dev, 0x50, &val); 1802 if (val & 0xc0) 1803 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1804 val); 1805 else 1806 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1807 } 1808 } 1809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1810 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1811 1812 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1813 1814 /* 1815 * If we are using libata we can drive this chip properly but must do this 1816 * early on to make the additional device appear during the PCI scanning. 1817 */ 1818 static void quirk_jmicron_ata(struct pci_dev *pdev) 1819 { 1820 u32 conf1, conf5, class; 1821 u8 hdr; 1822 1823 /* Only poke fn 0 */ 1824 if (PCI_FUNC(pdev->devfn)) 1825 return; 1826 1827 pci_read_config_dword(pdev, 0x40, &conf1); 1828 pci_read_config_dword(pdev, 0x80, &conf5); 1829 1830 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1831 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1832 1833 switch (pdev->device) { 1834 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1835 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1836 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1837 /* The controller should be in single function ahci mode */ 1838 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1839 break; 1840 1841 case PCI_DEVICE_ID_JMICRON_JMB365: 1842 case PCI_DEVICE_ID_JMICRON_JMB366: 1843 /* Redirect IDE second PATA port to the right spot */ 1844 conf5 |= (1 << 24); 1845 fallthrough; 1846 case PCI_DEVICE_ID_JMICRON_JMB361: 1847 case PCI_DEVICE_ID_JMICRON_JMB363: 1848 case PCI_DEVICE_ID_JMICRON_JMB369: 1849 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1850 /* Set the class codes correctly and then direct IDE 0 */ 1851 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1852 break; 1853 1854 case PCI_DEVICE_ID_JMICRON_JMB368: 1855 /* The controller should be in single function IDE mode */ 1856 conf1 |= 0x00C00000; /* Set 22, 23 */ 1857 break; 1858 } 1859 1860 pci_write_config_dword(pdev, 0x40, conf1); 1861 pci_write_config_dword(pdev, 0x80, conf5); 1862 1863 /* Update pdev accordingly */ 1864 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1865 pdev->hdr_type = hdr & 0x7f; 1866 pdev->multifunction = !!(hdr & 0x80); 1867 1868 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1869 pdev->class = class >> 8; 1870 } 1871 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1872 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1873 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1874 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1875 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1876 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1877 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1878 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1880 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1881 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1882 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1883 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1884 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1885 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1886 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1887 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1889 1890 #endif 1891 1892 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1893 { 1894 if (dev->multifunction) { 1895 device_disable_async_suspend(&dev->dev); 1896 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1897 } 1898 } 1899 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1900 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1903 1904 #ifdef CONFIG_X86_IO_APIC 1905 static void quirk_alder_ioapic(struct pci_dev *pdev) 1906 { 1907 int i; 1908 1909 if ((pdev->class >> 8) != 0xff00) 1910 return; 1911 1912 /* 1913 * The first BAR is the location of the IO-APIC... we must 1914 * not touch this (and it's already covered by the fixmap), so 1915 * forcibly insert it into the resource tree. 1916 */ 1917 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1918 insert_resource(&iomem_resource, &pdev->resource[0]); 1919 1920 /* 1921 * The next five BARs all seem to be rubbish, so just clean 1922 * them out. 1923 */ 1924 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1925 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1926 } 1927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1928 #endif 1929 1930 static void quirk_no_msi(struct pci_dev *dev) 1931 { 1932 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1933 dev->no_msi = 1; 1934 } 1935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1937 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1938 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1939 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1941 1942 static void quirk_pcie_mch(struct pci_dev *pdev) 1943 { 1944 pdev->no_msi = 1; 1945 } 1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1949 1950 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1951 1952 /* 1953 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1954 * actually on the AMBA bus. These fake PCI devices can support SVA via 1955 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1956 * 1957 * Normally stalling must not be enabled for PCI devices, since it would 1958 * break the PCI requirement for free-flowing writes and may lead to 1959 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1960 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1961 * even when a "PCI" device turns out to be a regular old SoC device 1962 * dressed up as a RCiEP and normal rules don't apply. 1963 */ 1964 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1965 { 1966 struct property_entry properties[] = { 1967 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1968 {}, 1969 }; 1970 1971 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1972 return; 1973 1974 pdev->pasid_no_tlp = 1; 1975 1976 /* 1977 * Set the dma-can-stall property on ACPI platforms. Device tree 1978 * can set it directly. 1979 */ 1980 if (!pdev->dev.of_node && 1981 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1982 pci_warn(pdev, "could not add stall property"); 1983 } 1984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1987 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1989 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1990 1991 /* 1992 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1993 * together on certain PXH-based systems. 1994 */ 1995 static void quirk_pcie_pxh(struct pci_dev *dev) 1996 { 1997 dev->no_msi = 1; 1998 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1999 } 2000 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2001 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2002 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2003 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2004 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2005 2006 /* 2007 * Some Intel PCI Express chipsets have trouble with downstream device 2008 * power management. 2009 */ 2010 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2011 { 2012 pci_pm_d3hot_delay = 120; 2013 dev->no_d1d2 = 1; 2014 } 2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2036 2037 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2038 { 2039 if (dev->d3hot_delay >= delay) 2040 return; 2041 2042 dev->d3hot_delay = delay; 2043 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2044 dev->d3hot_delay); 2045 } 2046 2047 static void quirk_radeon_pm(struct pci_dev *dev) 2048 { 2049 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2050 dev->subsystem_device == 0x00e2) 2051 quirk_d3hot_delay(dev, 20); 2052 } 2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2054 2055 /* 2056 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2057 * reset is performed too soon after transition to D0, extend d3hot_delay 2058 * to previous effective default for all NVIDIA HDA controllers. 2059 */ 2060 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2061 { 2062 quirk_d3hot_delay(dev, 20); 2063 } 2064 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2065 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2066 quirk_nvidia_hda_pm); 2067 2068 /* 2069 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2070 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2071 * 2072 * The kernel attempts to transition these devices to D3cold, but that seems 2073 * to be ineffective on the platforms in question; the PCI device appears to 2074 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2075 * extended delay in order to succeed. 2076 */ 2077 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2078 { 2079 quirk_d3hot_delay(dev, 20); 2080 } 2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2084 2085 #ifdef CONFIG_X86_IO_APIC 2086 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2087 { 2088 noioapicreroute = 1; 2089 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2090 2091 return 0; 2092 } 2093 2094 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2095 /* 2096 * Systems to exclude from boot interrupt reroute quirks 2097 */ 2098 { 2099 .callback = dmi_disable_ioapicreroute, 2100 .ident = "ASUSTek Computer INC. M2N-LR", 2101 .matches = { 2102 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2103 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2104 }, 2105 }, 2106 {} 2107 }; 2108 2109 /* 2110 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2111 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2112 * that a PCI device's interrupt handler is installed on the boot interrupt 2113 * line instead. 2114 */ 2115 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2116 { 2117 dmi_check_system(boot_interrupt_dmi_table); 2118 if (noioapicquirk || noioapicreroute) 2119 return; 2120 2121 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2122 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2123 dev->vendor, dev->device); 2124 } 2125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2133 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2134 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2135 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2136 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2137 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2138 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2139 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2140 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2141 2142 /* 2143 * On some chipsets we can disable the generation of legacy INTx boot 2144 * interrupts. 2145 */ 2146 2147 /* 2148 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2149 * 300641-004US, section 5.7.3. 2150 * 2151 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2152 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2153 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2154 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2155 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2156 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2157 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2158 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2159 * Core IO on Xeon Scalable, see Intel order no 610950. 2160 */ 2161 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2162 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2163 2164 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2165 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2166 2167 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2168 { 2169 u16 pci_config_word; 2170 u32 pci_config_dword; 2171 2172 if (noioapicquirk) 2173 return; 2174 2175 switch (dev->device) { 2176 case PCI_DEVICE_ID_INTEL_ESB_10: 2177 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2178 &pci_config_word); 2179 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2180 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2181 pci_config_word); 2182 break; 2183 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2184 case 0x0e28: /* Xeon E5/E7 V2 */ 2185 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2186 case 0x6f28: /* Xeon D-1500 */ 2187 case 0x2034: /* Xeon Scalable Family */ 2188 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2189 &pci_config_dword); 2190 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2191 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2192 pci_config_dword); 2193 break; 2194 default: 2195 return; 2196 } 2197 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2198 dev->vendor, dev->device); 2199 } 2200 /* 2201 * Device 29 Func 5 Device IDs of IO-APIC 2202 * containing ABAR—APIC1 Alternate Base Address Register 2203 */ 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2205 quirk_disable_intel_boot_interrupt); 2206 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2207 quirk_disable_intel_boot_interrupt); 2208 2209 /* 2210 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2211 * containing Coherent Interface Protocol Interrupt Control 2212 * 2213 * Device IDs obtained from volume 2 datasheets of commented 2214 * families above. 2215 */ 2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2217 quirk_disable_intel_boot_interrupt); 2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2219 quirk_disable_intel_boot_interrupt); 2220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2221 quirk_disable_intel_boot_interrupt); 2222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2223 quirk_disable_intel_boot_interrupt); 2224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2225 quirk_disable_intel_boot_interrupt); 2226 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2227 quirk_disable_intel_boot_interrupt); 2228 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2229 quirk_disable_intel_boot_interrupt); 2230 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2231 quirk_disable_intel_boot_interrupt); 2232 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2233 quirk_disable_intel_boot_interrupt); 2234 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2235 quirk_disable_intel_boot_interrupt); 2236 2237 /* Disable boot interrupts on HT-1000 */ 2238 #define BC_HT1000_FEATURE_REG 0x64 2239 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2240 #define BC_HT1000_MAP_IDX 0xC00 2241 #define BC_HT1000_MAP_DATA 0xC01 2242 2243 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2244 { 2245 u32 pci_config_dword; 2246 u8 irq; 2247 2248 if (noioapicquirk) 2249 return; 2250 2251 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2252 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2253 BC_HT1000_PIC_REGS_ENABLE); 2254 2255 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2256 outb(irq, BC_HT1000_MAP_IDX); 2257 outb(0x00, BC_HT1000_MAP_DATA); 2258 } 2259 2260 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2261 2262 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2263 dev->vendor, dev->device); 2264 } 2265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2266 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2267 2268 /* Disable boot interrupts on AMD and ATI chipsets */ 2269 2270 /* 2271 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2272 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2273 * (due to an erratum). 2274 */ 2275 #define AMD_813X_MISC 0x40 2276 #define AMD_813X_NOIOAMODE (1<<0) 2277 #define AMD_813X_REV_B1 0x12 2278 #define AMD_813X_REV_B2 0x13 2279 2280 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2281 { 2282 u32 pci_config_dword; 2283 2284 if (noioapicquirk) 2285 return; 2286 if ((dev->revision == AMD_813X_REV_B1) || 2287 (dev->revision == AMD_813X_REV_B2)) 2288 return; 2289 2290 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2291 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2292 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2293 2294 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2295 dev->vendor, dev->device); 2296 } 2297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2298 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2300 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2301 2302 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2303 2304 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2305 { 2306 u16 pci_config_word; 2307 2308 if (noioapicquirk) 2309 return; 2310 2311 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2312 if (!pci_config_word) { 2313 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2314 dev->vendor, dev->device); 2315 return; 2316 } 2317 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2318 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2319 dev->vendor, dev->device); 2320 } 2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2322 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2323 #endif /* CONFIG_X86_IO_APIC */ 2324 2325 /* 2326 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2327 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2328 * Re-allocate the region if needed... 2329 */ 2330 static void quirk_tc86c001_ide(struct pci_dev *dev) 2331 { 2332 struct resource *r = &dev->resource[0]; 2333 2334 if (r->start & 0x8) { 2335 r->flags |= IORESOURCE_UNSET; 2336 r->start = 0; 2337 r->end = 0xf; 2338 } 2339 } 2340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2341 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2342 quirk_tc86c001_ide); 2343 2344 /* 2345 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2346 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2347 * being read correctly if bit 7 of the base address is set. 2348 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2349 * Re-allocate the regions to a 256-byte boundary if necessary. 2350 */ 2351 static void quirk_plx_pci9050(struct pci_dev *dev) 2352 { 2353 unsigned int bar; 2354 2355 /* Fixed in revision 2 (PCI 9052). */ 2356 if (dev->revision >= 2) 2357 return; 2358 for (bar = 0; bar <= 1; bar++) 2359 if (pci_resource_len(dev, bar) == 0x80 && 2360 (pci_resource_start(dev, bar) & 0x80)) { 2361 struct resource *r = &dev->resource[bar]; 2362 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2363 bar); 2364 r->flags |= IORESOURCE_UNSET; 2365 r->start = 0; 2366 r->end = 0xff; 2367 } 2368 } 2369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2370 quirk_plx_pci9050); 2371 /* 2372 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2373 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2374 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2375 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2376 * 2377 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2378 * driver. 2379 */ 2380 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2381 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2382 2383 static void quirk_netmos(struct pci_dev *dev) 2384 { 2385 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2386 unsigned int num_serial = dev->subsystem_device & 0xf; 2387 2388 /* 2389 * These Netmos parts are multiport serial devices with optional 2390 * parallel ports. Even when parallel ports are present, they 2391 * are identified as class SERIAL, which means the serial driver 2392 * will claim them. To prevent this, mark them as class OTHER. 2393 * These combo devices should be claimed by parport_serial. 2394 * 2395 * The subdevice ID is of the form 0x00PS, where <P> is the number 2396 * of parallel ports and <S> is the number of serial ports. 2397 */ 2398 switch (dev->device) { 2399 case PCI_DEVICE_ID_NETMOS_9835: 2400 /* Well, this rule doesn't hold for the following 9835 device */ 2401 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2402 dev->subsystem_device == 0x0299) 2403 return; 2404 fallthrough; 2405 case PCI_DEVICE_ID_NETMOS_9735: 2406 case PCI_DEVICE_ID_NETMOS_9745: 2407 case PCI_DEVICE_ID_NETMOS_9845: 2408 case PCI_DEVICE_ID_NETMOS_9855: 2409 if (num_parallel) { 2410 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2411 dev->device, num_parallel, num_serial); 2412 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2413 (dev->class & 0xff); 2414 } 2415 } 2416 } 2417 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2418 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2419 2420 static void quirk_e100_interrupt(struct pci_dev *dev) 2421 { 2422 u16 command, pmcsr; 2423 u8 __iomem *csr; 2424 u8 cmd_hi; 2425 2426 switch (dev->device) { 2427 /* PCI IDs taken from drivers/net/e100.c */ 2428 case 0x1029: 2429 case 0x1030 ... 0x1034: 2430 case 0x1038 ... 0x103E: 2431 case 0x1050 ... 0x1057: 2432 case 0x1059: 2433 case 0x1064 ... 0x106B: 2434 case 0x1091 ... 0x1095: 2435 case 0x1209: 2436 case 0x1229: 2437 case 0x2449: 2438 case 0x2459: 2439 case 0x245D: 2440 case 0x27DC: 2441 break; 2442 default: 2443 return; 2444 } 2445 2446 /* 2447 * Some firmware hands off the e100 with interrupts enabled, 2448 * which can cause a flood of interrupts if packets are 2449 * received before the driver attaches to the device. So 2450 * disable all e100 interrupts here. The driver will 2451 * re-enable them when it's ready. 2452 */ 2453 pci_read_config_word(dev, PCI_COMMAND, &command); 2454 2455 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2456 return; 2457 2458 /* 2459 * Check that the device is in the D0 power state. If it's not, 2460 * there is no point to look any further. 2461 */ 2462 if (dev->pm_cap) { 2463 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2464 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2465 return; 2466 } 2467 2468 /* Convert from PCI bus to resource space. */ 2469 csr = ioremap(pci_resource_start(dev, 0), 8); 2470 if (!csr) { 2471 pci_warn(dev, "Can't map e100 registers\n"); 2472 return; 2473 } 2474 2475 cmd_hi = readb(csr + 3); 2476 if (cmd_hi == 0) { 2477 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2478 writeb(1, csr + 3); 2479 } 2480 2481 iounmap(csr); 2482 } 2483 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2484 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2485 2486 /* 2487 * The 82575 and 82598 may experience data corruption issues when transitioning 2488 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2489 */ 2490 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2491 { 2492 pci_info(dev, "Disabling L0s\n"); 2493 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2494 } 2495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2497 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2498 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2499 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2507 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2509 2510 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2511 { 2512 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2513 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2514 } 2515 2516 /* 2517 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2518 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2519 * disable both L0s and L1 for now to be safe. 2520 */ 2521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2522 2523 /* 2524 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2525 * Link bit cleared after starting the link retrain process to allow this 2526 * process to finish. 2527 * 2528 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2529 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2530 */ 2531 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2532 { 2533 dev->clear_retrain_link = 1; 2534 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2535 } 2536 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2537 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2538 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2539 2540 static void fixup_rev1_53c810(struct pci_dev *dev) 2541 { 2542 u32 class = dev->class; 2543 2544 /* 2545 * rev 1 ncr53c810 chips don't set the class at all which means 2546 * they don't get their resources remapped. Fix that here. 2547 */ 2548 if (class) 2549 return; 2550 2551 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2552 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2553 class, dev->class); 2554 } 2555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2556 2557 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2558 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2559 { 2560 u16 en1k; 2561 2562 pci_read_config_word(dev, 0x40, &en1k); 2563 2564 if (en1k & 0x200) { 2565 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2566 dev->io_window_1k = 1; 2567 } 2568 } 2569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2570 2571 /* 2572 * Under some circumstances, AER is not linked with extended capabilities. 2573 * Force it to be linked by setting the corresponding control bit in the 2574 * config space. 2575 */ 2576 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2577 { 2578 uint8_t b; 2579 2580 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2581 if (!(b & 0x20)) { 2582 pci_write_config_byte(dev, 0xf41, b | 0x20); 2583 pci_info(dev, "Linking AER extended capability\n"); 2584 } 2585 } 2586 } 2587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2588 quirk_nvidia_ck804_pcie_aer_ext_cap); 2589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2590 quirk_nvidia_ck804_pcie_aer_ext_cap); 2591 2592 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2593 { 2594 /* 2595 * Disable PCI Bus Parking and PCI Master read caching on CX700 2596 * which causes unspecified timing errors with a VT6212L on the PCI 2597 * bus leading to USB2.0 packet loss. 2598 * 2599 * This quirk is only enabled if a second (on the external PCI bus) 2600 * VT6212L is found -- the CX700 core itself also contains a USB 2601 * host controller with the same PCI ID as the VT6212L. 2602 */ 2603 2604 /* Count VT6212L instances */ 2605 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2606 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2607 uint8_t b; 2608 2609 /* 2610 * p should contain the first (internal) VT6212L -- see if we have 2611 * an external one by searching again. 2612 */ 2613 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2614 if (!p) 2615 return; 2616 pci_dev_put(p); 2617 2618 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2619 if (b & 0x40) { 2620 /* Turn off PCI Bus Parking */ 2621 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2622 2623 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2624 } 2625 } 2626 2627 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2628 if (b != 0) { 2629 /* Turn off PCI Master read caching */ 2630 pci_write_config_byte(dev, 0x72, 0x0); 2631 2632 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2633 pci_write_config_byte(dev, 0x75, 0x1); 2634 2635 /* Disable "Read FIFO Timer" */ 2636 pci_write_config_byte(dev, 0x77, 0x0); 2637 2638 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2639 } 2640 } 2641 } 2642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2643 2644 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2645 { 2646 u32 rev; 2647 2648 pci_read_config_dword(dev, 0xf4, &rev); 2649 2650 /* Only CAP the MRRS if the device is a 5719 A0 */ 2651 if (rev == 0x05719000) { 2652 int readrq = pcie_get_readrq(dev); 2653 if (readrq > 2048) 2654 pcie_set_readrq(dev, 2048); 2655 } 2656 } 2657 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2658 PCI_DEVICE_ID_TIGON3_5719, 2659 quirk_brcm_5719_limit_mrrs); 2660 2661 /* 2662 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2663 * hide device 6 which configures the overflow device access containing the 2664 * DRBs - this is where we expose device 6. 2665 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2666 */ 2667 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2668 { 2669 u8 reg; 2670 2671 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2672 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2673 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2674 } 2675 } 2676 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2677 quirk_unhide_mch_dev6); 2678 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2679 quirk_unhide_mch_dev6); 2680 2681 #ifdef CONFIG_PCI_MSI 2682 /* 2683 * Some chipsets do not support MSI. We cannot easily rely on setting 2684 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2685 * other buses controlled by the chipset even if Linux is not aware of it. 2686 * Instead of setting the flag on all buses in the machine, simply disable 2687 * MSI globally. 2688 */ 2689 static void quirk_disable_all_msi(struct pci_dev *dev) 2690 { 2691 pci_no_msi(); 2692 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2693 } 2694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2703 2704 /* Disable MSI on chipsets that are known to not support it */ 2705 static void quirk_disable_msi(struct pci_dev *dev) 2706 { 2707 if (dev->subordinate) { 2708 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2709 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2710 } 2711 } 2712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2715 2716 /* 2717 * The APC bridge device in AMD 780 family northbridges has some random 2718 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2719 * we use the possible vendor/device IDs of the host bridge for the 2720 * declared quirk, and search for the APC bridge by slot number. 2721 */ 2722 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2723 { 2724 struct pci_dev *apc_bridge; 2725 2726 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2727 if (apc_bridge) { 2728 if (apc_bridge->device == 0x9602) 2729 quirk_disable_msi(apc_bridge); 2730 pci_dev_put(apc_bridge); 2731 } 2732 } 2733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2735 2736 /* 2737 * Go through the list of HyperTransport capabilities and return 1 if a HT 2738 * MSI capability is found and enabled. 2739 */ 2740 static int msi_ht_cap_enabled(struct pci_dev *dev) 2741 { 2742 int pos, ttl = PCI_FIND_CAP_TTL; 2743 2744 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2745 while (pos && ttl--) { 2746 u8 flags; 2747 2748 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2749 &flags) == 0) { 2750 pci_info(dev, "Found %s HT MSI Mapping\n", 2751 flags & HT_MSI_FLAGS_ENABLE ? 2752 "enabled" : "disabled"); 2753 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2754 } 2755 2756 pos = pci_find_next_ht_capability(dev, pos, 2757 HT_CAPTYPE_MSI_MAPPING); 2758 } 2759 return 0; 2760 } 2761 2762 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2763 static void quirk_msi_ht_cap(struct pci_dev *dev) 2764 { 2765 if (!msi_ht_cap_enabled(dev)) 2766 quirk_disable_msi(dev); 2767 } 2768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2769 quirk_msi_ht_cap); 2770 2771 /* 2772 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2773 * if the MSI capability is set in any of these mappings. 2774 */ 2775 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2776 { 2777 struct pci_dev *pdev; 2778 2779 /* 2780 * Check HT MSI cap on this chipset and the root one. A single one 2781 * having MSI is enough to be sure that MSI is supported. 2782 */ 2783 pdev = pci_get_slot(dev->bus, 0); 2784 if (!pdev) 2785 return; 2786 if (!msi_ht_cap_enabled(pdev)) 2787 quirk_msi_ht_cap(dev); 2788 pci_dev_put(pdev); 2789 } 2790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2791 quirk_nvidia_ck804_msi_ht_cap); 2792 2793 /* Force enable MSI mapping capability on HT bridges */ 2794 static void ht_enable_msi_mapping(struct pci_dev *dev) 2795 { 2796 int pos, ttl = PCI_FIND_CAP_TTL; 2797 2798 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2799 while (pos && ttl--) { 2800 u8 flags; 2801 2802 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2803 &flags) == 0) { 2804 pci_info(dev, "Enabling HT MSI Mapping\n"); 2805 2806 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2807 flags | HT_MSI_FLAGS_ENABLE); 2808 } 2809 pos = pci_find_next_ht_capability(dev, pos, 2810 HT_CAPTYPE_MSI_MAPPING); 2811 } 2812 } 2813 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2814 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2815 ht_enable_msi_mapping); 2816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2817 ht_enable_msi_mapping); 2818 2819 /* 2820 * The P5N32-SLI motherboards from Asus have a problem with MSI 2821 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2822 * also affects other devices. As for now, turn off MSI for this device. 2823 */ 2824 static void nvenet_msi_disable(struct pci_dev *dev) 2825 { 2826 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2827 2828 if (board_name && 2829 (strstr(board_name, "P5N32-SLI PREMIUM") || 2830 strstr(board_name, "P5N32-E SLI"))) { 2831 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2832 dev->no_msi = 1; 2833 } 2834 } 2835 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2836 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2837 nvenet_msi_disable); 2838 2839 /* 2840 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2841 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2842 * interrupts for PME and AER events; instead only INTx interrupts are 2843 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2844 * for other events, since PCIe specification doesn't support using a mix of 2845 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2846 * service drivers registering their respective ISRs for MSIs. 2847 */ 2848 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2849 { 2850 dev->no_msi = 1; 2851 } 2852 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2853 PCI_CLASS_BRIDGE_PCI, 8, 2854 pci_quirk_nvidia_tegra_disable_rp_msi); 2855 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2856 PCI_CLASS_BRIDGE_PCI, 8, 2857 pci_quirk_nvidia_tegra_disable_rp_msi); 2858 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2859 PCI_CLASS_BRIDGE_PCI, 8, 2860 pci_quirk_nvidia_tegra_disable_rp_msi); 2861 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2862 PCI_CLASS_BRIDGE_PCI, 8, 2863 pci_quirk_nvidia_tegra_disable_rp_msi); 2864 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2865 PCI_CLASS_BRIDGE_PCI, 8, 2866 pci_quirk_nvidia_tegra_disable_rp_msi); 2867 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2868 PCI_CLASS_BRIDGE_PCI, 8, 2869 pci_quirk_nvidia_tegra_disable_rp_msi); 2870 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2871 PCI_CLASS_BRIDGE_PCI, 8, 2872 pci_quirk_nvidia_tegra_disable_rp_msi); 2873 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2874 PCI_CLASS_BRIDGE_PCI, 8, 2875 pci_quirk_nvidia_tegra_disable_rp_msi); 2876 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2877 PCI_CLASS_BRIDGE_PCI, 8, 2878 pci_quirk_nvidia_tegra_disable_rp_msi); 2879 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2880 PCI_CLASS_BRIDGE_PCI, 8, 2881 pci_quirk_nvidia_tegra_disable_rp_msi); 2882 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2883 PCI_CLASS_BRIDGE_PCI, 8, 2884 pci_quirk_nvidia_tegra_disable_rp_msi); 2885 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2886 PCI_CLASS_BRIDGE_PCI, 8, 2887 pci_quirk_nvidia_tegra_disable_rp_msi); 2888 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2889 PCI_CLASS_BRIDGE_PCI, 8, 2890 pci_quirk_nvidia_tegra_disable_rp_msi); 2891 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2892 PCI_CLASS_BRIDGE_PCI, 8, 2893 pci_quirk_nvidia_tegra_disable_rp_msi); 2894 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2895 PCI_CLASS_BRIDGE_PCI, 8, 2896 pci_quirk_nvidia_tegra_disable_rp_msi); 2897 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2898 PCI_CLASS_BRIDGE_PCI, 8, 2899 pci_quirk_nvidia_tegra_disable_rp_msi); 2900 2901 /* 2902 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2903 * config register. This register controls the routing of legacy 2904 * interrupts from devices that route through the MCP55. If this register 2905 * is misprogrammed, interrupts are only sent to the BSP, unlike 2906 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2907 * having this register set properly prevents kdump from booting up 2908 * properly, so let's make sure that we have it set correctly. 2909 * Note that this is an undocumented register. 2910 */ 2911 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2912 { 2913 u32 cfg; 2914 2915 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2916 return; 2917 2918 pci_read_config_dword(dev, 0x74, &cfg); 2919 2920 if (cfg & ((1 << 2) | (1 << 15))) { 2921 pr_info("Rewriting IRQ routing register on MCP55\n"); 2922 cfg &= ~((1 << 2) | (1 << 15)); 2923 pci_write_config_dword(dev, 0x74, cfg); 2924 } 2925 } 2926 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2927 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2928 nvbridge_check_legacy_irq_routing); 2929 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2930 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2931 nvbridge_check_legacy_irq_routing); 2932 2933 static int ht_check_msi_mapping(struct pci_dev *dev) 2934 { 2935 int pos, ttl = PCI_FIND_CAP_TTL; 2936 int found = 0; 2937 2938 /* Check if there is HT MSI cap or enabled on this device */ 2939 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2940 while (pos && ttl--) { 2941 u8 flags; 2942 2943 if (found < 1) 2944 found = 1; 2945 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2946 &flags) == 0) { 2947 if (flags & HT_MSI_FLAGS_ENABLE) { 2948 if (found < 2) { 2949 found = 2; 2950 break; 2951 } 2952 } 2953 } 2954 pos = pci_find_next_ht_capability(dev, pos, 2955 HT_CAPTYPE_MSI_MAPPING); 2956 } 2957 2958 return found; 2959 } 2960 2961 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2962 { 2963 struct pci_dev *dev; 2964 int pos; 2965 int i, dev_no; 2966 int found = 0; 2967 2968 dev_no = host_bridge->devfn >> 3; 2969 for (i = dev_no + 1; i < 0x20; i++) { 2970 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2971 if (!dev) 2972 continue; 2973 2974 /* found next host bridge? */ 2975 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2976 if (pos != 0) { 2977 pci_dev_put(dev); 2978 break; 2979 } 2980 2981 if (ht_check_msi_mapping(dev)) { 2982 found = 1; 2983 pci_dev_put(dev); 2984 break; 2985 } 2986 pci_dev_put(dev); 2987 } 2988 2989 return found; 2990 } 2991 2992 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2993 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2994 2995 static int is_end_of_ht_chain(struct pci_dev *dev) 2996 { 2997 int pos, ctrl_off; 2998 int end = 0; 2999 u16 flags, ctrl; 3000 3001 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3002 3003 if (!pos) 3004 goto out; 3005 3006 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3007 3008 ctrl_off = ((flags >> 10) & 1) ? 3009 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3010 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3011 3012 if (ctrl & (1 << 6)) 3013 end = 1; 3014 3015 out: 3016 return end; 3017 } 3018 3019 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3020 { 3021 struct pci_dev *host_bridge; 3022 int pos; 3023 int i, dev_no; 3024 int found = 0; 3025 3026 dev_no = dev->devfn >> 3; 3027 for (i = dev_no; i >= 0; i--) { 3028 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3029 if (!host_bridge) 3030 continue; 3031 3032 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3033 if (pos != 0) { 3034 found = 1; 3035 break; 3036 } 3037 pci_dev_put(host_bridge); 3038 } 3039 3040 if (!found) 3041 return; 3042 3043 /* don't enable end_device/host_bridge with leaf directly here */ 3044 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3045 host_bridge_with_leaf(host_bridge)) 3046 goto out; 3047 3048 /* root did that ! */ 3049 if (msi_ht_cap_enabled(host_bridge)) 3050 goto out; 3051 3052 ht_enable_msi_mapping(dev); 3053 3054 out: 3055 pci_dev_put(host_bridge); 3056 } 3057 3058 static void ht_disable_msi_mapping(struct pci_dev *dev) 3059 { 3060 int pos, ttl = PCI_FIND_CAP_TTL; 3061 3062 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3063 while (pos && ttl--) { 3064 u8 flags; 3065 3066 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3067 &flags) == 0) { 3068 pci_info(dev, "Disabling HT MSI Mapping\n"); 3069 3070 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3071 flags & ~HT_MSI_FLAGS_ENABLE); 3072 } 3073 pos = pci_find_next_ht_capability(dev, pos, 3074 HT_CAPTYPE_MSI_MAPPING); 3075 } 3076 } 3077 3078 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3079 { 3080 struct pci_dev *host_bridge; 3081 int pos; 3082 int found; 3083 3084 if (!pci_msi_enabled()) 3085 return; 3086 3087 /* check if there is HT MSI cap or enabled on this device */ 3088 found = ht_check_msi_mapping(dev); 3089 3090 /* no HT MSI CAP */ 3091 if (found == 0) 3092 return; 3093 3094 /* 3095 * HT MSI mapping should be disabled on devices that are below 3096 * a non-HyperTransport host bridge. Locate the host bridge. 3097 */ 3098 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3099 PCI_DEVFN(0, 0)); 3100 if (host_bridge == NULL) { 3101 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3102 return; 3103 } 3104 3105 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3106 if (pos != 0) { 3107 /* Host bridge is to HT */ 3108 if (found == 1) { 3109 /* it is not enabled, try to enable it */ 3110 if (all) 3111 ht_enable_msi_mapping(dev); 3112 else 3113 nv_ht_enable_msi_mapping(dev); 3114 } 3115 goto out; 3116 } 3117 3118 /* HT MSI is not enabled */ 3119 if (found == 1) 3120 goto out; 3121 3122 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3123 ht_disable_msi_mapping(dev); 3124 3125 out: 3126 pci_dev_put(host_bridge); 3127 } 3128 3129 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3130 { 3131 return __nv_msi_ht_cap_quirk(dev, 1); 3132 } 3133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3134 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3135 3136 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3137 { 3138 return __nv_msi_ht_cap_quirk(dev, 0); 3139 } 3140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3141 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3142 3143 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3144 { 3145 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3146 } 3147 3148 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3149 { 3150 struct pci_dev *p; 3151 3152 /* 3153 * SB700 MSI issue will be fixed at HW level from revision A21; 3154 * we need check PCI REVISION ID of SMBus controller to get SB700 3155 * revision. 3156 */ 3157 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3158 NULL); 3159 if (!p) 3160 return; 3161 3162 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3163 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3164 pci_dev_put(p); 3165 } 3166 3167 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3168 { 3169 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3170 if (dev->revision < 0x18) { 3171 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3172 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3173 } 3174 } 3175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3176 PCI_DEVICE_ID_TIGON3_5780, 3177 quirk_msi_intx_disable_bug); 3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3179 PCI_DEVICE_ID_TIGON3_5780S, 3180 quirk_msi_intx_disable_bug); 3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3182 PCI_DEVICE_ID_TIGON3_5714, 3183 quirk_msi_intx_disable_bug); 3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3185 PCI_DEVICE_ID_TIGON3_5714S, 3186 quirk_msi_intx_disable_bug); 3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3188 PCI_DEVICE_ID_TIGON3_5715, 3189 quirk_msi_intx_disable_bug); 3190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3191 PCI_DEVICE_ID_TIGON3_5715S, 3192 quirk_msi_intx_disable_bug); 3193 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3195 quirk_msi_intx_disable_ati_bug); 3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3197 quirk_msi_intx_disable_ati_bug); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3199 quirk_msi_intx_disable_ati_bug); 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3201 quirk_msi_intx_disable_ati_bug); 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3203 quirk_msi_intx_disable_ati_bug); 3204 3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3206 quirk_msi_intx_disable_bug); 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3208 quirk_msi_intx_disable_bug); 3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3210 quirk_msi_intx_disable_bug); 3211 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3213 quirk_msi_intx_disable_bug); 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3215 quirk_msi_intx_disable_bug); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3217 quirk_msi_intx_disable_bug); 3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3219 quirk_msi_intx_disable_bug); 3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3221 quirk_msi_intx_disable_bug); 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3223 quirk_msi_intx_disable_bug); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3225 quirk_msi_intx_disable_qca_bug); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3227 quirk_msi_intx_disable_qca_bug); 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3229 quirk_msi_intx_disable_qca_bug); 3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3231 quirk_msi_intx_disable_qca_bug); 3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3233 quirk_msi_intx_disable_qca_bug); 3234 3235 /* 3236 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3237 * should be disabled on platforms where the device (mistakenly) advertises it. 3238 * 3239 * Notice that this quirk also disables MSI (which may work, but hasn't been 3240 * tested), since currently there is no standard way to disable only MSI-X. 3241 * 3242 * The 0031 device id is reused for other non Root Port device types, 3243 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3244 */ 3245 static void quirk_al_msi_disable(struct pci_dev *dev) 3246 { 3247 dev->no_msi = 1; 3248 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3249 } 3250 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3251 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3252 #endif /* CONFIG_PCI_MSI */ 3253 3254 /* 3255 * Allow manual resource allocation for PCI hotplug bridges via 3256 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3257 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3258 * allocate resources when hotplug device is inserted and PCI bus is 3259 * rescanned. 3260 */ 3261 static void quirk_hotplug_bridge(struct pci_dev *dev) 3262 { 3263 dev->is_hotplug_bridge = 1; 3264 } 3265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3266 3267 /* 3268 * This is a quirk for the Ricoh MMC controller found as a part of some 3269 * multifunction chips. 3270 * 3271 * This is very similar and based on the ricoh_mmc driver written by 3272 * Philip Langdale. Thank you for these magic sequences. 3273 * 3274 * These chips implement the four main memory card controllers (SD, MMC, 3275 * MS, xD) and one or both of CardBus or FireWire. 3276 * 3277 * It happens that they implement SD and MMC support as separate 3278 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3279 * cards but the chip detects MMC cards in hardware and directs them to the 3280 * MMC controller - so the SDHCI driver never sees them. 3281 * 3282 * To get around this, we must disable the useless MMC controller. At that 3283 * point, the SDHCI controller will start seeing them. It seems to be the 3284 * case that the relevant PCI registers to deactivate the MMC controller 3285 * live on PCI function 0, which might be the CardBus controller or the 3286 * FireWire controller, depending on the particular chip in question 3287 * 3288 * This has to be done early, because as soon as we disable the MMC controller 3289 * other PCI functions shift up one level, e.g. function #2 becomes function 3290 * #1, and this will confuse the PCI core. 3291 */ 3292 #ifdef CONFIG_MMC_RICOH_MMC 3293 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3294 { 3295 u8 write_enable; 3296 u8 write_target; 3297 u8 disable; 3298 3299 /* 3300 * Disable via CardBus interface 3301 * 3302 * This must be done via function #0 3303 */ 3304 if (PCI_FUNC(dev->devfn)) 3305 return; 3306 3307 pci_read_config_byte(dev, 0xB7, &disable); 3308 if (disable & 0x02) 3309 return; 3310 3311 pci_read_config_byte(dev, 0x8E, &write_enable); 3312 pci_write_config_byte(dev, 0x8E, 0xAA); 3313 pci_read_config_byte(dev, 0x8D, &write_target); 3314 pci_write_config_byte(dev, 0x8D, 0xB7); 3315 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3316 pci_write_config_byte(dev, 0x8E, write_enable); 3317 pci_write_config_byte(dev, 0x8D, write_target); 3318 3319 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3320 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3321 } 3322 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3323 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3324 3325 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3326 { 3327 u8 write_enable; 3328 u8 disable; 3329 3330 /* 3331 * Disable via FireWire interface 3332 * 3333 * This must be done via function #0 3334 */ 3335 if (PCI_FUNC(dev->devfn)) 3336 return; 3337 /* 3338 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3339 * certain types of SD/MMC cards. Lowering the SD base clock 3340 * frequency from 200Mhz to 50Mhz fixes this issue. 3341 * 3342 * 0x150 - SD2.0 mode enable for changing base clock 3343 * frequency to 50Mhz 3344 * 0xe1 - Base clock frequency 3345 * 0x32 - 50Mhz new clock frequency 3346 * 0xf9 - Key register for 0x150 3347 * 0xfc - key register for 0xe1 3348 */ 3349 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3350 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3351 pci_write_config_byte(dev, 0xf9, 0xfc); 3352 pci_write_config_byte(dev, 0x150, 0x10); 3353 pci_write_config_byte(dev, 0xf9, 0x00); 3354 pci_write_config_byte(dev, 0xfc, 0x01); 3355 pci_write_config_byte(dev, 0xe1, 0x32); 3356 pci_write_config_byte(dev, 0xfc, 0x00); 3357 3358 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3359 } 3360 3361 pci_read_config_byte(dev, 0xCB, &disable); 3362 3363 if (disable & 0x02) 3364 return; 3365 3366 pci_read_config_byte(dev, 0xCA, &write_enable); 3367 pci_write_config_byte(dev, 0xCA, 0x57); 3368 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3369 pci_write_config_byte(dev, 0xCA, write_enable); 3370 3371 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3372 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3373 3374 } 3375 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3377 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3378 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3379 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3380 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3381 #endif /*CONFIG_MMC_RICOH_MMC*/ 3382 3383 #ifdef CONFIG_DMAR_TABLE 3384 #define VTUNCERRMSK_REG 0x1ac 3385 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3386 /* 3387 * This is a quirk for masking VT-d spec-defined errors to platform error 3388 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3389 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3390 * on the RAS config settings of the platform) when a VT-d fault happens. 3391 * The resulting SMI caused the system to hang. 3392 * 3393 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3394 * need to report the same error through other channels. 3395 */ 3396 static void vtd_mask_spec_errors(struct pci_dev *dev) 3397 { 3398 u32 word; 3399 3400 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3401 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3402 } 3403 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3404 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3405 #endif 3406 3407 static void fixup_ti816x_class(struct pci_dev *dev) 3408 { 3409 u32 class = dev->class; 3410 3411 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3412 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3413 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3414 class, dev->class); 3415 } 3416 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3417 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3418 3419 /* 3420 * Some PCIe devices do not work reliably with the claimed maximum 3421 * payload size supported. 3422 */ 3423 static void fixup_mpss_256(struct pci_dev *dev) 3424 { 3425 dev->pcie_mpss = 1; /* 256 bytes */ 3426 } 3427 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3428 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3429 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3430 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3431 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3432 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3433 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3434 3435 /* 3436 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3437 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3438 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3439 * until all of the devices are discovered and buses walked, read completion 3440 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3441 * it is possible to hotplug a device with MPS of 256B. 3442 */ 3443 static void quirk_intel_mc_errata(struct pci_dev *dev) 3444 { 3445 int err; 3446 u16 rcc; 3447 3448 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3449 pcie_bus_config == PCIE_BUS_DEFAULT) 3450 return; 3451 3452 /* 3453 * Intel erratum specifies bits to change but does not say what 3454 * they are. Keeping them magical until such time as the registers 3455 * and values can be explained. 3456 */ 3457 err = pci_read_config_word(dev, 0x48, &rcc); 3458 if (err) { 3459 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3460 return; 3461 } 3462 3463 if (!(rcc & (1 << 10))) 3464 return; 3465 3466 rcc &= ~(1 << 10); 3467 3468 err = pci_write_config_word(dev, 0x48, rcc); 3469 if (err) { 3470 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3471 return; 3472 } 3473 3474 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3475 } 3476 /* Intel 5000 series memory controllers and ports 2-7 */ 3477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3491 /* Intel 5100 series memory controllers and ports 2-7 */ 3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3503 3504 /* 3505 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3506 * To work around this, query the size it should be configured to by the 3507 * device and modify the resource end to correspond to this new size. 3508 */ 3509 static void quirk_intel_ntb(struct pci_dev *dev) 3510 { 3511 int rc; 3512 u8 val; 3513 3514 rc = pci_read_config_byte(dev, 0x00D0, &val); 3515 if (rc) 3516 return; 3517 3518 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3519 3520 rc = pci_read_config_byte(dev, 0x00D1, &val); 3521 if (rc) 3522 return; 3523 3524 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3525 } 3526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3528 3529 /* 3530 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3531 * though no one is handling them (e.g., if the i915 driver is never 3532 * loaded). Additionally the interrupt destination is not set up properly 3533 * and the interrupt ends up -somewhere-. 3534 * 3535 * These spurious interrupts are "sticky" and the kernel disables the 3536 * (shared) interrupt line after 100,000+ generated interrupts. 3537 * 3538 * Fix it by disabling the still enabled interrupts. This resolves crashes 3539 * often seen on monitor unplug. 3540 */ 3541 #define I915_DEIER_REG 0x4400c 3542 static void disable_igfx_irq(struct pci_dev *dev) 3543 { 3544 void __iomem *regs = pci_iomap(dev, 0, 0); 3545 if (regs == NULL) { 3546 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3547 return; 3548 } 3549 3550 /* Check if any interrupt line is still enabled */ 3551 if (readl(regs + I915_DEIER_REG) != 0) { 3552 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3553 3554 writel(0, regs + I915_DEIER_REG); 3555 } 3556 3557 pci_iounmap(dev, regs); 3558 } 3559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3566 3567 /* 3568 * PCI devices which are on Intel chips can skip the 10ms delay 3569 * before entering D3 mode. 3570 */ 3571 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3572 { 3573 dev->d3hot_delay = 0; 3574 } 3575 /* C600 Series devices do not need 10ms d3hot_delay */ 3576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3579 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3591 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3601 3602 /* 3603 * Some devices may pass our check in pci_intx_mask_supported() if 3604 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3605 * support this feature. 3606 */ 3607 static void quirk_broken_intx_masking(struct pci_dev *dev) 3608 { 3609 dev->broken_intx_masking = 1; 3610 } 3611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3612 quirk_broken_intx_masking); 3613 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3614 quirk_broken_intx_masking); 3615 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3616 quirk_broken_intx_masking); 3617 3618 /* 3619 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3620 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3621 * 3622 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3623 */ 3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3625 quirk_broken_intx_masking); 3626 3627 /* 3628 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3629 * DisINTx can be set but the interrupt status bit is non-functional. 3630 */ 3631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3647 3648 static u16 mellanox_broken_intx_devs[] = { 3649 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3650 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3651 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3652 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3653 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3654 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3655 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3656 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3657 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3658 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3659 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3660 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3661 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3662 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3663 }; 3664 3665 #define CONNECTX_4_CURR_MAX_MINOR 99 3666 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3667 3668 /* 3669 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3670 * If so, don't mark it as broken. 3671 * FW minor > 99 means older FW version format and no INTx masking support. 3672 * FW minor < 14 means new FW version format and no INTx masking support. 3673 */ 3674 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3675 { 3676 __be32 __iomem *fw_ver; 3677 u16 fw_major; 3678 u16 fw_minor; 3679 u16 fw_subminor; 3680 u32 fw_maj_min; 3681 u32 fw_sub_min; 3682 int i; 3683 3684 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3685 if (pdev->device == mellanox_broken_intx_devs[i]) { 3686 pdev->broken_intx_masking = 1; 3687 return; 3688 } 3689 } 3690 3691 /* 3692 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3693 * support so shouldn't be checked further 3694 */ 3695 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3696 return; 3697 3698 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3699 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3700 return; 3701 3702 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3703 if (pci_enable_device_mem(pdev)) { 3704 pci_warn(pdev, "Can't enable device memory\n"); 3705 return; 3706 } 3707 3708 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3709 if (!fw_ver) { 3710 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3711 goto out; 3712 } 3713 3714 /* Reading from resource space should be 32b aligned */ 3715 fw_maj_min = ioread32be(fw_ver); 3716 fw_sub_min = ioread32be(fw_ver + 1); 3717 fw_major = fw_maj_min & 0xffff; 3718 fw_minor = fw_maj_min >> 16; 3719 fw_subminor = fw_sub_min & 0xffff; 3720 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3721 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3722 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3723 fw_major, fw_minor, fw_subminor, pdev->device == 3724 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3725 pdev->broken_intx_masking = 1; 3726 } 3727 3728 iounmap(fw_ver); 3729 3730 out: 3731 pci_disable_device(pdev); 3732 } 3733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3734 mellanox_check_broken_intx_masking); 3735 3736 static void quirk_no_bus_reset(struct pci_dev *dev) 3737 { 3738 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3739 } 3740 3741 /* 3742 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3743 * prevented for those affected devices. 3744 */ 3745 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3746 { 3747 if ((dev->device & 0xffc0) == 0x2340) 3748 quirk_no_bus_reset(dev); 3749 } 3750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3751 quirk_nvidia_no_bus_reset); 3752 3753 /* 3754 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3755 * The device will throw a Link Down error on AER-capable systems and 3756 * regardless of AER, config space of the device is never accessible again 3757 * and typically causes the system to hang or reset when access is attempted. 3758 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3759 */ 3760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3766 3767 /* 3768 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3769 * reset when used with certain child devices. After the reset, config 3770 * accesses to the child may fail. 3771 */ 3772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3773 3774 /* 3775 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3776 * automatically disables LTSSM when Secondary Bus Reset is received and 3777 * the device stops working. Prevent bus reset for these devices. With 3778 * this change, the device can be assigned to VMs with VFIO, but it will 3779 * leak state between VMs. Reference 3780 * https://e2e.ti.com/support/processors/f/791/t/954382 3781 */ 3782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3783 3784 static void quirk_no_pm_reset(struct pci_dev *dev) 3785 { 3786 /* 3787 * We can't do a bus reset on root bus devices, but an ineffective 3788 * PM reset may be better than nothing. 3789 */ 3790 if (!pci_is_root_bus(dev->bus)) 3791 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3792 } 3793 3794 /* 3795 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3796 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3797 * to have no effect on the device: it retains the framebuffer contents and 3798 * monitor sync. Advertising this support makes other layers, like VFIO, 3799 * assume pci_reset_function() is viable for this device. Mark it as 3800 * unavailable to skip it when testing reset methods. 3801 */ 3802 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3803 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3804 3805 /* 3806 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3807 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3808 * any effect on the device: It continues to be operational and network ports 3809 * remain up. Advertising this support makes it seem as if a PM reset is viable 3810 * for these devices. Mark it as unavailable to skip it when testing reset 3811 * methods. 3812 */ 3813 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3817 3818 /* 3819 * Thunderbolt controllers with broken MSI hotplug signaling: 3820 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3821 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3822 */ 3823 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3824 { 3825 if (pdev->is_hotplug_bridge && 3826 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3827 pdev->revision <= 1)) 3828 pdev->no_msi = 1; 3829 } 3830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3831 quirk_thunderbolt_hotplug_msi); 3832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3833 quirk_thunderbolt_hotplug_msi); 3834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3835 quirk_thunderbolt_hotplug_msi); 3836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3837 quirk_thunderbolt_hotplug_msi); 3838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3839 quirk_thunderbolt_hotplug_msi); 3840 3841 #ifdef CONFIG_ACPI 3842 /* 3843 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3844 * 3845 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3846 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3847 * be present after resume if a device was plugged in before suspend. 3848 * 3849 * The Thunderbolt controller consists of a PCIe switch with downstream 3850 * bridges leading to the NHI and to the tunnel PCI bridges. 3851 * 3852 * This quirk cuts power to the whole chip. Therefore we have to apply it 3853 * during suspend_noirq of the upstream bridge. 3854 * 3855 * Power is automagically restored before resume. No action is needed. 3856 */ 3857 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3858 { 3859 acpi_handle bridge, SXIO, SXFP, SXLV; 3860 3861 if (!x86_apple_machine) 3862 return; 3863 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3864 return; 3865 3866 /* 3867 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3868 * We don't know how to turn it back on again, but firmware does, 3869 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3870 * firmware. 3871 */ 3872 if (!pm_suspend_via_firmware()) 3873 return; 3874 3875 bridge = ACPI_HANDLE(&dev->dev); 3876 if (!bridge) 3877 return; 3878 3879 /* 3880 * SXIO and SXLV are present only on machines requiring this quirk. 3881 * Thunderbolt bridges in external devices might have the same 3882 * device ID as those on the host, but they will not have the 3883 * associated ACPI methods. This implicitly checks that we are at 3884 * the right bridge. 3885 */ 3886 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3887 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3888 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3889 return; 3890 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3891 3892 /* magic sequence */ 3893 acpi_execute_simple_method(SXIO, NULL, 1); 3894 acpi_execute_simple_method(SXFP, NULL, 0); 3895 msleep(300); 3896 acpi_execute_simple_method(SXLV, NULL, 0); 3897 acpi_execute_simple_method(SXIO, NULL, 0); 3898 acpi_execute_simple_method(SXLV, NULL, 0); 3899 } 3900 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3901 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3902 quirk_apple_poweroff_thunderbolt); 3903 #endif 3904 3905 /* 3906 * Following are device-specific reset methods which can be used to 3907 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3908 * not available. 3909 */ 3910 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3911 { 3912 /* 3913 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3914 * 3915 * The 82599 supports FLR on VFs, but FLR support is reported only 3916 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3917 * Thus we must call pcie_flr() directly without first checking if it is 3918 * supported. 3919 */ 3920 if (!probe) 3921 pcie_flr(dev); 3922 return 0; 3923 } 3924 3925 #define SOUTH_CHICKEN2 0xc2004 3926 #define PCH_PP_STATUS 0xc7200 3927 #define PCH_PP_CONTROL 0xc7204 3928 #define MSG_CTL 0x45010 3929 #define NSDE_PWR_STATE 0xd0100 3930 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3931 3932 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3933 { 3934 void __iomem *mmio_base; 3935 unsigned long timeout; 3936 u32 val; 3937 3938 if (probe) 3939 return 0; 3940 3941 mmio_base = pci_iomap(dev, 0, 0); 3942 if (!mmio_base) 3943 return -ENOMEM; 3944 3945 iowrite32(0x00000002, mmio_base + MSG_CTL); 3946 3947 /* 3948 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3949 * driver loaded sets the right bits. However, this's a reset and 3950 * the bits have been set by i915 previously, so we clobber 3951 * SOUTH_CHICKEN2 register directly here. 3952 */ 3953 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3954 3955 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3956 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3957 3958 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3959 do { 3960 val = ioread32(mmio_base + PCH_PP_STATUS); 3961 if ((val & 0xb0000000) == 0) 3962 goto reset_complete; 3963 msleep(10); 3964 } while (time_before(jiffies, timeout)); 3965 pci_warn(dev, "timeout during reset\n"); 3966 3967 reset_complete: 3968 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3969 3970 pci_iounmap(dev, mmio_base); 3971 return 0; 3972 } 3973 3974 /* Device-specific reset method for Chelsio T4-based adapters */ 3975 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3976 { 3977 u16 old_command; 3978 u16 msix_flags; 3979 3980 /* 3981 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3982 * that we have no device-specific reset method. 3983 */ 3984 if ((dev->device & 0xf000) != 0x4000) 3985 return -ENOTTY; 3986 3987 /* 3988 * If this is the "probe" phase, return 0 indicating that we can 3989 * reset this device. 3990 */ 3991 if (probe) 3992 return 0; 3993 3994 /* 3995 * T4 can wedge if there are DMAs in flight within the chip and Bus 3996 * Master has been disabled. We need to have it on till the Function 3997 * Level Reset completes. (BUS_MASTER is disabled in 3998 * pci_reset_function()). 3999 */ 4000 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4001 pci_write_config_word(dev, PCI_COMMAND, 4002 old_command | PCI_COMMAND_MASTER); 4003 4004 /* 4005 * Perform the actual device function reset, saving and restoring 4006 * configuration information around the reset. 4007 */ 4008 pci_save_state(dev); 4009 4010 /* 4011 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4012 * are disabled when an MSI-X interrupt message needs to be delivered. 4013 * So we briefly re-enable MSI-X interrupts for the duration of the 4014 * FLR. The pci_restore_state() below will restore the original 4015 * MSI-X state. 4016 */ 4017 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4018 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4019 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4020 msix_flags | 4021 PCI_MSIX_FLAGS_ENABLE | 4022 PCI_MSIX_FLAGS_MASKALL); 4023 4024 pcie_flr(dev); 4025 4026 /* 4027 * Restore the configuration information (BAR values, etc.) including 4028 * the original PCI Configuration Space Command word, and return 4029 * success. 4030 */ 4031 pci_restore_state(dev); 4032 pci_write_config_word(dev, PCI_COMMAND, old_command); 4033 return 0; 4034 } 4035 4036 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4037 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4038 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4039 4040 /* 4041 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4042 * FLR where config space reads from the device return -1. We seem to be 4043 * able to avoid this condition if we disable the NVMe controller prior to 4044 * FLR. This quirk is generic for any NVMe class device requiring similar 4045 * assistance to quiesce the device prior to FLR. 4046 * 4047 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4048 * Revision 1.0e: 4049 * Chapter 2: Required and optional PCI config registers 4050 * Chapter 3: NVMe control registers 4051 * Chapter 7.3: Reset behavior 4052 */ 4053 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4054 { 4055 void __iomem *bar; 4056 u16 cmd; 4057 u32 cfg; 4058 4059 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4060 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4061 return -ENOTTY; 4062 4063 if (probe) 4064 return 0; 4065 4066 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4067 if (!bar) 4068 return -ENOTTY; 4069 4070 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4071 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4072 4073 cfg = readl(bar + NVME_REG_CC); 4074 4075 /* Disable controller if enabled */ 4076 if (cfg & NVME_CC_ENABLE) { 4077 u32 cap = readl(bar + NVME_REG_CAP); 4078 unsigned long timeout; 4079 4080 /* 4081 * Per nvme_disable_ctrl() skip shutdown notification as it 4082 * could complete commands to the admin queue. We only intend 4083 * to quiesce the device before reset. 4084 */ 4085 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4086 4087 writel(cfg, bar + NVME_REG_CC); 4088 4089 /* 4090 * Some controllers require an additional delay here, see 4091 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4092 * supported by this quirk. 4093 */ 4094 4095 /* Cap register provides max timeout in 500ms increments */ 4096 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4097 4098 for (;;) { 4099 u32 status = readl(bar + NVME_REG_CSTS); 4100 4101 /* Ready status becomes zero on disable complete */ 4102 if (!(status & NVME_CSTS_RDY)) 4103 break; 4104 4105 msleep(100); 4106 4107 if (time_after(jiffies, timeout)) { 4108 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4109 break; 4110 } 4111 } 4112 } 4113 4114 pci_iounmap(dev, bar); 4115 4116 pcie_flr(dev); 4117 4118 return 0; 4119 } 4120 4121 /* 4122 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4123 * timeout waiting for ready status to change after NVMe enable if the driver 4124 * starts interacting with the device too soon after FLR. A 250ms delay after 4125 * FLR has heuristically proven to produce reliably working results for device 4126 * assignment cases. 4127 */ 4128 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4129 { 4130 if (probe) 4131 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4132 4133 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4134 4135 msleep(250); 4136 4137 return 0; 4138 } 4139 4140 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4141 #define HINIC_VF_FLR_TYPE 0x1000 4142 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4143 #define HINIC_VF_OP 0xE80 4144 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4145 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4146 4147 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4148 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4149 { 4150 unsigned long timeout; 4151 void __iomem *bar; 4152 u32 val; 4153 4154 if (probe) 4155 return 0; 4156 4157 bar = pci_iomap(pdev, 0, 0); 4158 if (!bar) 4159 return -ENOTTY; 4160 4161 /* Get and check firmware capabilities */ 4162 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4163 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4164 pci_iounmap(pdev, bar); 4165 return -ENOTTY; 4166 } 4167 4168 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4169 val = ioread32be(bar + HINIC_VF_OP); 4170 val = val | HINIC_VF_FLR_PROC_BIT; 4171 iowrite32be(val, bar + HINIC_VF_OP); 4172 4173 pcie_flr(pdev); 4174 4175 /* 4176 * The device must recapture its Bus and Device Numbers after FLR 4177 * in order generate Completions. Issue a config write to let the 4178 * device capture this information. 4179 */ 4180 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4181 4182 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4183 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4184 do { 4185 val = ioread32be(bar + HINIC_VF_OP); 4186 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4187 goto reset_complete; 4188 msleep(20); 4189 } while (time_before(jiffies, timeout)); 4190 4191 val = ioread32be(bar + HINIC_VF_OP); 4192 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4193 goto reset_complete; 4194 4195 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4196 4197 reset_complete: 4198 pci_iounmap(pdev, bar); 4199 4200 return 0; 4201 } 4202 4203 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4204 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4205 reset_intel_82599_sfp_virtfn }, 4206 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4207 reset_ivb_igd }, 4208 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4209 reset_ivb_igd }, 4210 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4211 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4212 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4213 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4214 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4215 reset_chelsio_generic_dev }, 4216 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4217 reset_hinic_vf_dev }, 4218 { 0 } 4219 }; 4220 4221 /* 4222 * These device-specific reset methods are here rather than in a driver 4223 * because when a host assigns a device to a guest VM, the host may need 4224 * to reset the device but probably doesn't have a driver for it. 4225 */ 4226 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4227 { 4228 const struct pci_dev_reset_methods *i; 4229 4230 for (i = pci_dev_reset_methods; i->reset; i++) { 4231 if ((i->vendor == dev->vendor || 4232 i->vendor == (u16)PCI_ANY_ID) && 4233 (i->device == dev->device || 4234 i->device == (u16)PCI_ANY_ID)) 4235 return i->reset(dev, probe); 4236 } 4237 4238 return -ENOTTY; 4239 } 4240 4241 static void quirk_dma_func0_alias(struct pci_dev *dev) 4242 { 4243 if (PCI_FUNC(dev->devfn) != 0) 4244 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4245 } 4246 4247 /* 4248 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4249 * 4250 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4251 */ 4252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4254 4255 static void quirk_dma_func1_alias(struct pci_dev *dev) 4256 { 4257 if (PCI_FUNC(dev->devfn) != 1) 4258 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4259 } 4260 4261 /* 4262 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4263 * SKUs function 1 is present and is a legacy IDE controller, in other 4264 * SKUs this function is not present, making this a ghost requester. 4265 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4266 */ 4267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4268 quirk_dma_func1_alias); 4269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4270 quirk_dma_func1_alias); 4271 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4273 quirk_dma_func1_alias); 4274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4275 quirk_dma_func1_alias); 4276 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4278 quirk_dma_func1_alias); 4279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4280 quirk_dma_func1_alias); 4281 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4283 quirk_dma_func1_alias); 4284 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4286 quirk_dma_func1_alias); 4287 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4289 quirk_dma_func1_alias); 4290 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4292 quirk_dma_func1_alias); 4293 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4295 quirk_dma_func1_alias); 4296 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4298 quirk_dma_func1_alias); 4299 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4301 quirk_dma_func1_alias); 4302 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4304 quirk_dma_func1_alias); 4305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4306 quirk_dma_func1_alias); 4307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4308 quirk_dma_func1_alias); 4309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4310 quirk_dma_func1_alias); 4311 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4313 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4314 quirk_dma_func1_alias); 4315 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4316 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4317 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4318 quirk_dma_func1_alias); 4319 4320 /* 4321 * Some devices DMA with the wrong devfn, not just the wrong function. 4322 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4323 * the alias is "fixed" and independent of the device devfn. 4324 * 4325 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4326 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4327 * single device on the secondary bus. In reality, the single exposed 4328 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4329 * that provides a bridge to the internal bus of the I/O processor. The 4330 * controller supports private devices, which can be hidden from PCI config 4331 * space. In the case of the Adaptec 3405, a private device at 01.0 4332 * appears to be the DMA engine, which therefore needs to become a DMA 4333 * alias for the device. 4334 */ 4335 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4336 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4337 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4338 .driver_data = PCI_DEVFN(1, 0) }, 4339 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4340 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4341 .driver_data = PCI_DEVFN(1, 0) }, 4342 { 0 } 4343 }; 4344 4345 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4346 { 4347 const struct pci_device_id *id; 4348 4349 id = pci_match_id(fixed_dma_alias_tbl, dev); 4350 if (id) 4351 pci_add_dma_alias(dev, id->driver_data, 1); 4352 } 4353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4354 4355 /* 4356 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4357 * using the wrong DMA alias for the device. Some of these devices can be 4358 * used as either forward or reverse bridges, so we need to test whether the 4359 * device is operating in the correct mode. We could probably apply this 4360 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4361 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4362 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4363 */ 4364 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4365 { 4366 if (!pci_is_root_bus(pdev->bus) && 4367 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4368 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4369 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4370 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4371 } 4372 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4374 quirk_use_pcie_bridge_dma_alias); 4375 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4376 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4377 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4378 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4379 /* ITE 8893 has the same problem as the 8892 */ 4380 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4381 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4382 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4383 4384 /* 4385 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4386 * be added as aliases to the DMA device in order to allow buffer access 4387 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4388 * programmed in the EEPROM. 4389 */ 4390 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4391 { 4392 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4393 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4394 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4395 } 4396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4398 4399 /* 4400 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4401 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4402 * 4403 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4404 * when IOMMU is enabled. These aliases allow computational unit access to 4405 * host memory. These aliases mark the whole VCA device as one IOMMU 4406 * group. 4407 * 4408 * All possible slot numbers (0x20) are used, since we are unable to tell 4409 * what slot is used on other side. This quirk is intended for both host 4410 * and computational unit sides. The VCA devices have up to five functions 4411 * (four for DMA channels and one additional). 4412 */ 4413 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4414 { 4415 const unsigned int num_pci_slots = 0x20; 4416 unsigned int slot; 4417 4418 for (slot = 0; slot < num_pci_slots; slot++) 4419 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4420 } 4421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4427 4428 /* 4429 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4430 * associated not at the root bus, but at a bridge below. This quirk avoids 4431 * generating invalid DMA aliases. 4432 */ 4433 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4434 { 4435 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4436 } 4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4438 quirk_bridge_cavm_thrx2_pcie_root); 4439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4440 quirk_bridge_cavm_thrx2_pcie_root); 4441 4442 /* 4443 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4444 * class code. Fix it. 4445 */ 4446 static void quirk_tw686x_class(struct pci_dev *pdev) 4447 { 4448 u32 class = pdev->class; 4449 4450 /* Use "Multimedia controller" class */ 4451 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4452 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4453 class, pdev->class); 4454 } 4455 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4456 quirk_tw686x_class); 4457 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4458 quirk_tw686x_class); 4459 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4460 quirk_tw686x_class); 4461 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4462 quirk_tw686x_class); 4463 4464 /* 4465 * Some devices have problems with Transaction Layer Packets with the Relaxed 4466 * Ordering Attribute set. Such devices should mark themselves and other 4467 * device drivers should check before sending TLPs with RO set. 4468 */ 4469 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4470 { 4471 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4472 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4473 } 4474 4475 /* 4476 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4477 * Complex have a Flow Control Credit issue which can cause performance 4478 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4479 */ 4480 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4481 quirk_relaxedordering_disable); 4482 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4483 quirk_relaxedordering_disable); 4484 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4485 quirk_relaxedordering_disable); 4486 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4487 quirk_relaxedordering_disable); 4488 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4489 quirk_relaxedordering_disable); 4490 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4491 quirk_relaxedordering_disable); 4492 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4493 quirk_relaxedordering_disable); 4494 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4495 quirk_relaxedordering_disable); 4496 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4497 quirk_relaxedordering_disable); 4498 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4499 quirk_relaxedordering_disable); 4500 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4501 quirk_relaxedordering_disable); 4502 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4503 quirk_relaxedordering_disable); 4504 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4505 quirk_relaxedordering_disable); 4506 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4507 quirk_relaxedordering_disable); 4508 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4509 quirk_relaxedordering_disable); 4510 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4511 quirk_relaxedordering_disable); 4512 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4513 quirk_relaxedordering_disable); 4514 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4515 quirk_relaxedordering_disable); 4516 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4517 quirk_relaxedordering_disable); 4518 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4519 quirk_relaxedordering_disable); 4520 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4521 quirk_relaxedordering_disable); 4522 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4523 quirk_relaxedordering_disable); 4524 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4525 quirk_relaxedordering_disable); 4526 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4527 quirk_relaxedordering_disable); 4528 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4529 quirk_relaxedordering_disable); 4530 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4531 quirk_relaxedordering_disable); 4532 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4533 quirk_relaxedordering_disable); 4534 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4535 quirk_relaxedordering_disable); 4536 4537 /* 4538 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4539 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4540 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4541 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4542 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4543 * November 10, 2010). As a result, on this platform we can't use Relaxed 4544 * Ordering for Upstream TLPs. 4545 */ 4546 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4547 quirk_relaxedordering_disable); 4548 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4549 quirk_relaxedordering_disable); 4550 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4551 quirk_relaxedordering_disable); 4552 4553 /* 4554 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4555 * values for the Attribute as were supplied in the header of the 4556 * corresponding Request, except as explicitly allowed when IDO is used." 4557 * 4558 * If a non-compliant device generates a completion with a different 4559 * attribute than the request, the receiver may accept it (which itself 4560 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4561 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4562 * device access timeout. 4563 * 4564 * If the non-compliant device generates completions with zero attributes 4565 * (instead of copying the attributes from the request), we can work around 4566 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4567 * upstream devices so they always generate requests with zero attributes. 4568 * 4569 * This affects other devices under the same Root Port, but since these 4570 * attributes are performance hints, there should be no functional problem. 4571 * 4572 * Note that Configuration Space accesses are never supposed to have TLP 4573 * Attributes, so we're safe waiting till after any Configuration Space 4574 * accesses to do the Root Port fixup. 4575 */ 4576 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4577 { 4578 struct pci_dev *root_port = pcie_find_root_port(pdev); 4579 4580 if (!root_port) { 4581 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4582 return; 4583 } 4584 4585 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4586 dev_name(&pdev->dev)); 4587 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4588 PCI_EXP_DEVCTL_RELAX_EN | 4589 PCI_EXP_DEVCTL_NOSNOOP_EN); 4590 } 4591 4592 /* 4593 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4594 * Completion it generates. 4595 */ 4596 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4597 { 4598 /* 4599 * This mask/compare operation selects for Physical Function 4 on a 4600 * T5. We only need to fix up the Root Port once for any of the 4601 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4602 * 0x54xx so we use that one. 4603 */ 4604 if ((pdev->device & 0xff00) == 0x5400) 4605 quirk_disable_root_port_attributes(pdev); 4606 } 4607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4608 quirk_chelsio_T5_disable_root_port_attributes); 4609 4610 /* 4611 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4612 * by a device 4613 * @acs_ctrl_req: Bitmask of desired ACS controls 4614 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4615 * the hardware design 4616 * 4617 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4618 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4619 * caller desires. Return 0 otherwise. 4620 */ 4621 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4622 { 4623 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4624 return 1; 4625 return 0; 4626 } 4627 4628 /* 4629 * AMD has indicated that the devices below do not support peer-to-peer 4630 * in any system where they are found in the southbridge with an AMD 4631 * IOMMU in the system. Multifunction devices that do not support 4632 * peer-to-peer between functions can claim to support a subset of ACS. 4633 * Such devices effectively enable request redirect (RR) and completion 4634 * redirect (CR) since all transactions are redirected to the upstream 4635 * root complex. 4636 * 4637 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4638 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4639 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4640 * 4641 * 1002:4385 SBx00 SMBus Controller 4642 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4643 * 1002:4383 SBx00 Azalia (Intel HDA) 4644 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4645 * 1002:4384 SBx00 PCI to PCI Bridge 4646 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4647 * 4648 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4649 * 4650 * 1022:780f [AMD] FCH PCI Bridge 4651 * 1022:7809 [AMD] FCH USB OHCI Controller 4652 */ 4653 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4654 { 4655 #ifdef CONFIG_ACPI 4656 struct acpi_table_header *header = NULL; 4657 acpi_status status; 4658 4659 /* Targeting multifunction devices on the SB (appears on root bus) */ 4660 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4661 return -ENODEV; 4662 4663 /* The IVRS table describes the AMD IOMMU */ 4664 status = acpi_get_table("IVRS", 0, &header); 4665 if (ACPI_FAILURE(status)) 4666 return -ENODEV; 4667 4668 acpi_put_table(header); 4669 4670 /* Filter out flags not applicable to multifunction */ 4671 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4672 4673 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4674 #else 4675 return -ENODEV; 4676 #endif 4677 } 4678 4679 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4680 { 4681 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4682 return false; 4683 4684 switch (dev->device) { 4685 /* 4686 * Effectively selects all downstream ports for whole ThunderX1 4687 * (which represents 8 SoCs). 4688 */ 4689 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4690 case 0xaf84: /* ThunderX2 */ 4691 case 0xb884: /* ThunderX3 */ 4692 return true; 4693 default: 4694 return false; 4695 } 4696 } 4697 4698 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4699 { 4700 if (!pci_quirk_cavium_acs_match(dev)) 4701 return -ENOTTY; 4702 4703 /* 4704 * Cavium Root Ports don't advertise an ACS capability. However, 4705 * the RTL internally implements similar protection as if ACS had 4706 * Source Validation, Request Redirection, Completion Redirection, 4707 * and Upstream Forwarding features enabled. Assert that the 4708 * hardware implements and enables equivalent ACS functionality for 4709 * these flags. 4710 */ 4711 return pci_acs_ctrl_enabled(acs_flags, 4712 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4713 } 4714 4715 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4716 { 4717 /* 4718 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4719 * transactions with others, allowing masking out these bits as if they 4720 * were unimplemented in the ACS capability. 4721 */ 4722 return pci_acs_ctrl_enabled(acs_flags, 4723 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4724 } 4725 4726 /* 4727 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4728 * But the implementation could block peer-to-peer transactions between them 4729 * and provide ACS-like functionality. 4730 */ 4731 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4732 { 4733 if (!pci_is_pcie(dev) || 4734 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4735 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4736 return -ENOTTY; 4737 4738 /* 4739 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4740 * implement ACS capability in accordance with the PCIe Spec. 4741 */ 4742 switch (dev->device) { 4743 case 0x0710 ... 0x071e: 4744 case 0x0721: 4745 case 0x0723 ... 0x0752: 4746 return pci_acs_ctrl_enabled(acs_flags, 4747 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4748 } 4749 4750 return false; 4751 } 4752 4753 /* 4754 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4755 * transactions and validate bus numbers in requests, but do not provide an 4756 * actual PCIe ACS capability. This is the list of device IDs known to fall 4757 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4758 */ 4759 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4760 /* Ibexpeak PCH */ 4761 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4762 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4763 /* Cougarpoint PCH */ 4764 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4765 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4766 /* Pantherpoint PCH */ 4767 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4768 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4769 /* Lynxpoint-H PCH */ 4770 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4771 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4772 /* Lynxpoint-LP PCH */ 4773 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4774 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4775 /* Wildcat PCH */ 4776 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4777 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4778 /* Patsburg (X79) PCH */ 4779 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4780 /* Wellsburg (X99) PCH */ 4781 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4782 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4783 /* Lynx Point (9 series) PCH */ 4784 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4785 }; 4786 4787 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4788 { 4789 int i; 4790 4791 /* Filter out a few obvious non-matches first */ 4792 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4793 return false; 4794 4795 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4796 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4797 return true; 4798 4799 return false; 4800 } 4801 4802 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4803 { 4804 if (!pci_quirk_intel_pch_acs_match(dev)) 4805 return -ENOTTY; 4806 4807 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4808 return pci_acs_ctrl_enabled(acs_flags, 4809 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4810 4811 return pci_acs_ctrl_enabled(acs_flags, 0); 4812 } 4813 4814 /* 4815 * These QCOM Root Ports do provide ACS-like features to disable peer 4816 * transactions and validate bus numbers in requests, but do not provide an 4817 * actual PCIe ACS capability. Hardware supports source validation but it 4818 * will report the issue as Completer Abort instead of ACS Violation. 4819 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4820 * Complex with unique segment numbers. It is not possible for one Root 4821 * Port to pass traffic to another Root Port. All PCIe transactions are 4822 * terminated inside the Root Port. 4823 */ 4824 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4825 { 4826 return pci_acs_ctrl_enabled(acs_flags, 4827 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4828 } 4829 4830 /* 4831 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4832 * number and does provide isolation features to disable peer transactions 4833 * and validate bus numbers in requests, but does not provide an ACS 4834 * capability. 4835 */ 4836 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4837 { 4838 return pci_acs_ctrl_enabled(acs_flags, 4839 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4840 } 4841 4842 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4843 { 4844 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4845 return -ENOTTY; 4846 4847 /* 4848 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4849 * but do include ACS-like functionality. The hardware doesn't support 4850 * peer-to-peer transactions via the root port and each has a unique 4851 * segment number. 4852 * 4853 * Additionally, the root ports cannot send traffic to each other. 4854 */ 4855 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4856 4857 return acs_flags ? 0 : 1; 4858 } 4859 4860 /* 4861 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4862 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4863 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4864 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4865 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4866 * control register is at offset 8 instead of 6 and we should probably use 4867 * dword accesses to them. This applies to the following PCI Device IDs, as 4868 * found in volume 1 of the datasheet[2]: 4869 * 4870 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4871 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4872 * 4873 * N.B. This doesn't fix what lspci shows. 4874 * 4875 * The 100 series chipset specification update includes this as errata #23[3]. 4876 * 4877 * The 200 series chipset (Union Point) has the same bug according to the 4878 * specification update (Intel 200 Series Chipset Family Platform Controller 4879 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4880 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4881 * chipset include: 4882 * 4883 * 0xa290-0xa29f PCI Express Root port #{0-16} 4884 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4885 * 4886 * Mobile chipsets are also affected, 7th & 8th Generation 4887 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4888 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4889 * Processor Family I/O for U Quad Core Platforms Specification Update, 4890 * August 2017, Revision 002, Document#: 334660-002)[6] 4891 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4892 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4893 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4894 * 4895 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4896 * 4897 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4898 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4899 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4900 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4901 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4902 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4903 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4904 */ 4905 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4906 { 4907 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4908 return false; 4909 4910 switch (dev->device) { 4911 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4912 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4913 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4914 return true; 4915 } 4916 4917 return false; 4918 } 4919 4920 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4921 4922 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4923 { 4924 int pos; 4925 u32 cap, ctrl; 4926 4927 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4928 return -ENOTTY; 4929 4930 pos = dev->acs_cap; 4931 if (!pos) 4932 return -ENOTTY; 4933 4934 /* see pci_acs_flags_enabled() */ 4935 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4936 acs_flags &= (cap | PCI_ACS_EC); 4937 4938 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4939 4940 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4941 } 4942 4943 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4944 { 4945 /* 4946 * SV, TB, and UF are not relevant to multifunction endpoints. 4947 * 4948 * Multifunction devices are only required to implement RR, CR, and DT 4949 * in their ACS capability if they support peer-to-peer transactions. 4950 * Devices matching this quirk have been verified by the vendor to not 4951 * perform peer-to-peer with other functions, allowing us to mask out 4952 * these bits as if they were unimplemented in the ACS capability. 4953 */ 4954 return pci_acs_ctrl_enabled(acs_flags, 4955 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4956 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4957 } 4958 4959 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4960 { 4961 /* 4962 * Intel RCiEP's are required to allow p2p only on translated 4963 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4964 * "Root-Complex Peer to Peer Considerations". 4965 */ 4966 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4967 return -ENOTTY; 4968 4969 return pci_acs_ctrl_enabled(acs_flags, 4970 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4971 } 4972 4973 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4974 { 4975 /* 4976 * iProc PAXB Root Ports don't advertise an ACS capability, but 4977 * they do not allow peer-to-peer transactions between Root Ports. 4978 * Allow each Root Port to be in a separate IOMMU group by masking 4979 * SV/RR/CR/UF bits. 4980 */ 4981 return pci_acs_ctrl_enabled(acs_flags, 4982 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4983 } 4984 4985 /* 4986 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function 4987 * devices, peer-to-peer transactions are not be used between the functions. 4988 * So add an ACS quirk for below devices to isolate functions. 4989 * SFxxx 1G NICs(em). 4990 * RP1000/RP2000 10G NICs(sp). 4991 */ 4992 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 4993 { 4994 switch (dev->device) { 4995 case 0x0100 ... 0x010F: 4996 case 0x1001: 4997 case 0x2001: 4998 return pci_acs_ctrl_enabled(acs_flags, 4999 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5000 } 5001 5002 return false; 5003 } 5004 5005 static const struct pci_dev_acs_enabled { 5006 u16 vendor; 5007 u16 device; 5008 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5009 } pci_dev_acs_enabled[] = { 5010 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5011 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5012 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5013 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5014 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5015 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5016 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5017 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5018 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5019 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5020 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5021 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5022 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5023 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5024 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5025 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5026 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5027 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5028 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5029 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5030 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5031 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5032 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5033 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5034 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5035 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5036 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5037 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5038 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5039 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5040 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5041 /* 82580 */ 5042 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5043 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5044 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5045 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5046 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5047 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5048 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5049 /* 82576 */ 5050 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5051 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5052 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5053 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5054 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5055 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5056 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5057 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5058 /* 82575 */ 5059 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5060 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5061 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5062 /* I350 */ 5063 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5064 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5065 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5066 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5067 /* 82571 (Quads omitted due to non-ACS switch) */ 5068 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5069 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5070 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5071 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5072 /* I219 */ 5073 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5074 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5075 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5076 /* QCOM QDF2xxx root ports */ 5077 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5078 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5079 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5080 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5081 /* Intel PCH root ports */ 5082 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5083 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5084 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5085 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5086 /* Cavium ThunderX */ 5087 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5088 /* Cavium multi-function devices */ 5089 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5090 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5091 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5092 /* APM X-Gene */ 5093 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5094 /* Ampere Computing */ 5095 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5096 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5097 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5098 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5099 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5100 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5101 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5102 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5103 /* Broadcom multi-function device */ 5104 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5105 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5106 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5107 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5109 /* Amazon Annapurna Labs */ 5110 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5111 /* Zhaoxin multi-function devices */ 5112 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5113 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5114 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5115 /* NXP root ports, xx=16, 12, or 08 cores */ 5116 /* LX2xx0A : without security features + CAN-FD */ 5117 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5118 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5119 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5120 /* LX2xx0C : security features + CAN-FD */ 5121 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5122 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5123 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5124 /* LX2xx0E : security features + CAN */ 5125 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5126 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5127 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5128 /* LX2xx0N : without security features + CAN */ 5129 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5130 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5131 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5132 /* LX2xx2A : without security features + CAN-FD */ 5133 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5134 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5135 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5136 /* LX2xx2C : security features + CAN-FD */ 5137 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5138 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5139 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5140 /* LX2xx2E : security features + CAN */ 5141 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5142 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5143 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5144 /* LX2xx2N : without security features + CAN */ 5145 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5146 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5147 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5148 /* Zhaoxin Root/Downstream Ports */ 5149 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5150 /* Wangxun nics */ 5151 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5152 { 0 } 5153 }; 5154 5155 /* 5156 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5157 * @dev: PCI device 5158 * @acs_flags: Bitmask of desired ACS controls 5159 * 5160 * Returns: 5161 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5162 * device provides the desired controls 5163 * 0: Device does not provide all the desired controls 5164 * >0: Device provides all the controls in @acs_flags 5165 */ 5166 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5167 { 5168 const struct pci_dev_acs_enabled *i; 5169 int ret; 5170 5171 /* 5172 * Allow devices that do not expose standard PCIe ACS capabilities 5173 * or control to indicate their support here. Multi-function express 5174 * devices which do not allow internal peer-to-peer between functions, 5175 * but do not implement PCIe ACS may wish to return true here. 5176 */ 5177 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5178 if ((i->vendor == dev->vendor || 5179 i->vendor == (u16)PCI_ANY_ID) && 5180 (i->device == dev->device || 5181 i->device == (u16)PCI_ANY_ID)) { 5182 ret = i->acs_enabled(dev, acs_flags); 5183 if (ret >= 0) 5184 return ret; 5185 } 5186 } 5187 5188 return -ENOTTY; 5189 } 5190 5191 /* Config space offset of Root Complex Base Address register */ 5192 #define INTEL_LPC_RCBA_REG 0xf0 5193 /* 31:14 RCBA address */ 5194 #define INTEL_LPC_RCBA_MASK 0xffffc000 5195 /* RCBA Enable */ 5196 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5197 5198 /* Backbone Scratch Pad Register */ 5199 #define INTEL_BSPR_REG 0x1104 5200 /* Backbone Peer Non-Posted Disable */ 5201 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5202 /* Backbone Peer Posted Disable */ 5203 #define INTEL_BSPR_REG_BPPD (1 << 9) 5204 5205 /* Upstream Peer Decode Configuration Register */ 5206 #define INTEL_UPDCR_REG 0x1014 5207 /* 5:0 Peer Decode Enable bits */ 5208 #define INTEL_UPDCR_REG_MASK 0x3f 5209 5210 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5211 { 5212 u32 rcba, bspr, updcr; 5213 void __iomem *rcba_mem; 5214 5215 /* 5216 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5217 * are D28:F* and therefore get probed before LPC, thus we can't 5218 * use pci_get_slot()/pci_read_config_dword() here. 5219 */ 5220 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5221 INTEL_LPC_RCBA_REG, &rcba); 5222 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5223 return -EINVAL; 5224 5225 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5226 PAGE_ALIGN(INTEL_UPDCR_REG)); 5227 if (!rcba_mem) 5228 return -ENOMEM; 5229 5230 /* 5231 * The BSPR can disallow peer cycles, but it's set by soft strap and 5232 * therefore read-only. If both posted and non-posted peer cycles are 5233 * disallowed, we're ok. If either are allowed, then we need to use 5234 * the UPDCR to disable peer decodes for each port. This provides the 5235 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5236 */ 5237 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5238 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5239 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5240 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5241 if (updcr & INTEL_UPDCR_REG_MASK) { 5242 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5243 updcr &= ~INTEL_UPDCR_REG_MASK; 5244 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5245 } 5246 } 5247 5248 iounmap(rcba_mem); 5249 return 0; 5250 } 5251 5252 /* Miscellaneous Port Configuration register */ 5253 #define INTEL_MPC_REG 0xd8 5254 /* MPC: Invalid Receive Bus Number Check Enable */ 5255 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5256 5257 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5258 { 5259 u32 mpc; 5260 5261 /* 5262 * When enabled, the IRBNCE bit of the MPC register enables the 5263 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5264 * ensures that requester IDs fall within the bus number range 5265 * of the bridge. Enable if not already. 5266 */ 5267 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5268 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5269 pci_info(dev, "Enabling MPC IRBNCE\n"); 5270 mpc |= INTEL_MPC_REG_IRBNCE; 5271 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5272 } 5273 } 5274 5275 /* 5276 * Currently this quirk does the equivalent of 5277 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5278 * 5279 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5280 * if dev->external_facing || dev->untrusted 5281 */ 5282 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5283 { 5284 if (!pci_quirk_intel_pch_acs_match(dev)) 5285 return -ENOTTY; 5286 5287 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5288 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5289 return 0; 5290 } 5291 5292 pci_quirk_enable_intel_rp_mpc_acs(dev); 5293 5294 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5295 5296 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5297 5298 return 0; 5299 } 5300 5301 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5302 { 5303 int pos; 5304 u32 cap, ctrl; 5305 5306 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5307 return -ENOTTY; 5308 5309 pos = dev->acs_cap; 5310 if (!pos) 5311 return -ENOTTY; 5312 5313 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5314 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5315 5316 ctrl |= (cap & PCI_ACS_SV); 5317 ctrl |= (cap & PCI_ACS_RR); 5318 ctrl |= (cap & PCI_ACS_CR); 5319 ctrl |= (cap & PCI_ACS_UF); 5320 5321 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5322 ctrl |= (cap & PCI_ACS_TB); 5323 5324 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5325 5326 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5327 5328 return 0; 5329 } 5330 5331 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5332 { 5333 int pos; 5334 u32 cap, ctrl; 5335 5336 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5337 return -ENOTTY; 5338 5339 pos = dev->acs_cap; 5340 if (!pos) 5341 return -ENOTTY; 5342 5343 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5344 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5345 5346 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5347 5348 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5349 5350 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5351 5352 return 0; 5353 } 5354 5355 static const struct pci_dev_acs_ops { 5356 u16 vendor; 5357 u16 device; 5358 int (*enable_acs)(struct pci_dev *dev); 5359 int (*disable_acs_redir)(struct pci_dev *dev); 5360 } pci_dev_acs_ops[] = { 5361 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5362 .enable_acs = pci_quirk_enable_intel_pch_acs, 5363 }, 5364 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5365 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5366 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5367 }, 5368 }; 5369 5370 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5371 { 5372 const struct pci_dev_acs_ops *p; 5373 int i, ret; 5374 5375 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5376 p = &pci_dev_acs_ops[i]; 5377 if ((p->vendor == dev->vendor || 5378 p->vendor == (u16)PCI_ANY_ID) && 5379 (p->device == dev->device || 5380 p->device == (u16)PCI_ANY_ID) && 5381 p->enable_acs) { 5382 ret = p->enable_acs(dev); 5383 if (ret >= 0) 5384 return ret; 5385 } 5386 } 5387 5388 return -ENOTTY; 5389 } 5390 5391 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5392 { 5393 const struct pci_dev_acs_ops *p; 5394 int i, ret; 5395 5396 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5397 p = &pci_dev_acs_ops[i]; 5398 if ((p->vendor == dev->vendor || 5399 p->vendor == (u16)PCI_ANY_ID) && 5400 (p->device == dev->device || 5401 p->device == (u16)PCI_ANY_ID) && 5402 p->disable_acs_redir) { 5403 ret = p->disable_acs_redir(dev); 5404 if (ret >= 0) 5405 return ret; 5406 } 5407 } 5408 5409 return -ENOTTY; 5410 } 5411 5412 /* 5413 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5414 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5415 * Next Capability pointer in the MSI Capability Structure should point to 5416 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5417 * the list. 5418 */ 5419 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5420 { 5421 int pos, i = 0, ret; 5422 u8 next_cap; 5423 u16 reg16, *cap; 5424 struct pci_cap_saved_state *state; 5425 5426 /* Bail if the hardware bug is fixed */ 5427 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5428 return; 5429 5430 /* Bail if MSI Capability Structure is not found for some reason */ 5431 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5432 if (!pos) 5433 return; 5434 5435 /* 5436 * Bail if Next Capability pointer in the MSI Capability Structure 5437 * is not the expected incorrect 0x00. 5438 */ 5439 pci_read_config_byte(pdev, pos + 1, &next_cap); 5440 if (next_cap) 5441 return; 5442 5443 /* 5444 * PCIe Capability Structure is expected to be at 0x50 and should 5445 * terminate the list (Next Capability pointer is 0x00). Verify 5446 * Capability Id and Next Capability pointer is as expected. 5447 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5448 * to correctly set kernel data structures which have already been 5449 * set incorrectly due to the hardware bug. 5450 */ 5451 pos = 0x50; 5452 pci_read_config_word(pdev, pos, ®16); 5453 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5454 u32 status; 5455 #ifndef PCI_EXP_SAVE_REGS 5456 #define PCI_EXP_SAVE_REGS 7 5457 #endif 5458 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5459 5460 pdev->pcie_cap = pos; 5461 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5462 pdev->pcie_flags_reg = reg16; 5463 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5464 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5465 5466 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5467 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5468 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5469 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5470 5471 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5472 return; 5473 5474 /* Save PCIe cap */ 5475 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5476 if (!state) 5477 return; 5478 5479 state->cap.cap_nr = PCI_CAP_ID_EXP; 5480 state->cap.cap_extended = 0; 5481 state->cap.size = size; 5482 cap = (u16 *)&state->cap.data[0]; 5483 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5484 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5485 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5486 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5487 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5488 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5489 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5490 hlist_add_head(&state->next, &pdev->saved_cap_space); 5491 } 5492 } 5493 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5494 5495 /* 5496 * FLR may cause the following to devices to hang: 5497 * 5498 * AMD Starship/Matisse HD Audio Controller 0x1487 5499 * AMD Starship USB 3.0 Host Controller 0x148c 5500 * AMD Matisse USB 3.0 Host Controller 0x149c 5501 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5502 * Intel 82579V Gigabit Ethernet Controller 0x1503 5503 * 5504 */ 5505 static void quirk_no_flr(struct pci_dev *dev) 5506 { 5507 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5508 } 5509 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5510 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5511 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5512 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5513 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5514 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5515 5516 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5517 static void quirk_no_flr_snet(struct pci_dev *dev) 5518 { 5519 if (dev->revision == 0x1) 5520 quirk_no_flr(dev); 5521 } 5522 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5523 5524 static void quirk_no_ext_tags(struct pci_dev *pdev) 5525 { 5526 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5527 5528 if (!bridge) 5529 return; 5530 5531 bridge->no_ext_tags = 1; 5532 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5533 5534 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5535 } 5536 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5537 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5538 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5539 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5540 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5541 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5542 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5544 5545 #ifdef CONFIG_PCI_ATS 5546 static void quirk_no_ats(struct pci_dev *pdev) 5547 { 5548 pci_info(pdev, "disabling ATS\n"); 5549 pdev->ats_cap = 0; 5550 } 5551 5552 /* 5553 * Some devices require additional driver setup to enable ATS. Don't use 5554 * ATS for those devices as ATS will be enabled before the driver has had a 5555 * chance to load and configure the device. 5556 */ 5557 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5558 { 5559 if (pdev->device == 0x15d8) { 5560 if (pdev->revision == 0xcf && 5561 pdev->subsystem_vendor == 0xea50 && 5562 (pdev->subsystem_device == 0xce19 || 5563 pdev->subsystem_device == 0xcc10 || 5564 pdev->subsystem_device == 0xcc08)) 5565 quirk_no_ats(pdev); 5566 } else { 5567 quirk_no_ats(pdev); 5568 } 5569 } 5570 5571 /* AMD Stoney platform GPU */ 5572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5573 /* AMD Iceland dGPU */ 5574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5575 /* AMD Navi10 dGPU */ 5576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5584 /* AMD Navi14 dGPU */ 5585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5589 /* AMD Raven platform iGPU */ 5590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5591 5592 /* 5593 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5594 * in ATS Invalidate Request message body. Disable ATS for those devices. 5595 */ 5596 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5597 { 5598 if (pdev->revision < 0x20) 5599 quirk_no_ats(pdev); 5600 } 5601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5610 #endif /* CONFIG_PCI_ATS */ 5611 5612 /* Freescale PCIe doesn't support MSI in RC mode */ 5613 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5614 { 5615 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5616 pdev->no_msi = 1; 5617 } 5618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5619 5620 /* 5621 * Although not allowed by the spec, some multi-function devices have 5622 * dependencies of one function (consumer) on another (supplier). For the 5623 * consumer to work in D0, the supplier must also be in D0. Create a 5624 * device link from the consumer to the supplier to enforce this 5625 * dependency. Runtime PM is allowed by default on the consumer to prevent 5626 * it from permanently keeping the supplier awake. 5627 */ 5628 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5629 unsigned int supplier, unsigned int class, 5630 unsigned int class_shift) 5631 { 5632 struct pci_dev *supplier_pdev; 5633 5634 if (PCI_FUNC(pdev->devfn) != consumer) 5635 return; 5636 5637 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5638 pdev->bus->number, 5639 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5640 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5641 pci_dev_put(supplier_pdev); 5642 return; 5643 } 5644 5645 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5646 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5647 pci_info(pdev, "D0 power state depends on %s\n", 5648 pci_name(supplier_pdev)); 5649 else 5650 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5651 pci_name(supplier_pdev)); 5652 5653 pm_runtime_allow(&pdev->dev); 5654 pci_dev_put(supplier_pdev); 5655 } 5656 5657 /* 5658 * Create device link for GPUs with integrated HDA controller for streaming 5659 * audio to attached displays. 5660 */ 5661 static void quirk_gpu_hda(struct pci_dev *hda) 5662 { 5663 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5664 } 5665 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5666 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5667 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5668 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5669 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5670 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5671 5672 /* 5673 * Create device link for GPUs with integrated USB xHCI Host 5674 * controller to VGA. 5675 */ 5676 static void quirk_gpu_usb(struct pci_dev *usb) 5677 { 5678 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5679 } 5680 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5681 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5682 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5683 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5684 5685 /* 5686 * Create device link for GPUs with integrated Type-C UCSI controller 5687 * to VGA. Currently there is no class code defined for UCSI device over PCI 5688 * so using UNKNOWN class for now and it will be updated when UCSI 5689 * over PCI gets a class code. 5690 */ 5691 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5692 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5693 { 5694 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5695 } 5696 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5697 PCI_CLASS_SERIAL_UNKNOWN, 8, 5698 quirk_gpu_usb_typec_ucsi); 5699 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5700 PCI_CLASS_SERIAL_UNKNOWN, 8, 5701 quirk_gpu_usb_typec_ucsi); 5702 5703 /* 5704 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5705 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5706 */ 5707 static void quirk_nvidia_hda(struct pci_dev *gpu) 5708 { 5709 u8 hdr_type; 5710 u32 val; 5711 5712 /* There was no integrated HDA controller before MCP89 */ 5713 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5714 return; 5715 5716 /* Bit 25 at offset 0x488 enables the HDA controller */ 5717 pci_read_config_dword(gpu, 0x488, &val); 5718 if (val & BIT(25)) 5719 return; 5720 5721 pci_info(gpu, "Enabling HDA controller\n"); 5722 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5723 5724 /* The GPU becomes a multi-function device when the HDA is enabled */ 5725 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5726 gpu->multifunction = !!(hdr_type & 0x80); 5727 } 5728 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5729 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5730 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5731 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5732 5733 /* 5734 * Some IDT switches incorrectly flag an ACS Source Validation error on 5735 * completions for config read requests even though PCIe r4.0, sec 5736 * 6.12.1.1, says that completions are never affected by ACS Source 5737 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5738 * 5739 * Item #36 - Downstream port applies ACS Source Validation to Completions 5740 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5741 * completions are never affected by ACS Source Validation. However, 5742 * completions received by a downstream port of the PCIe switch from a 5743 * device that has not yet captured a PCIe bus number are incorrectly 5744 * dropped by ACS Source Validation by the switch downstream port. 5745 * 5746 * The workaround suggested by IDT is to issue a config write to the 5747 * downstream device before issuing the first config read. This allows the 5748 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5749 * sec 2.2.9), thus avoiding the ACS error on the completion. 5750 * 5751 * However, we don't know when the device is ready to accept the config 5752 * write, so we do config reads until we receive a non-Config Request Retry 5753 * Status, then do the config write. 5754 * 5755 * To avoid hitting the erratum when doing the config reads, we disable ACS 5756 * SV around this process. 5757 */ 5758 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5759 { 5760 int pos; 5761 u16 ctrl = 0; 5762 bool found; 5763 struct pci_dev *bridge = bus->self; 5764 5765 pos = bridge->acs_cap; 5766 5767 /* Disable ACS SV before initial config reads */ 5768 if (pos) { 5769 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5770 if (ctrl & PCI_ACS_SV) 5771 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5772 ctrl & ~PCI_ACS_SV); 5773 } 5774 5775 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5776 5777 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5778 if (found) 5779 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5780 5781 /* Re-enable ACS_SV if it was previously enabled */ 5782 if (ctrl & PCI_ACS_SV) 5783 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5784 5785 return found; 5786 } 5787 5788 /* 5789 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5790 * NT endpoints via the internal switch fabric. These IDs replace the 5791 * originating Requester ID TLPs which access host memory on peer NTB 5792 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5793 * to permit access when the IOMMU is turned on. 5794 */ 5795 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5796 { 5797 void __iomem *mmio; 5798 struct ntb_info_regs __iomem *mmio_ntb; 5799 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5800 u64 partition_map; 5801 u8 partition; 5802 int pp; 5803 5804 if (pci_enable_device(pdev)) { 5805 pci_err(pdev, "Cannot enable Switchtec device\n"); 5806 return; 5807 } 5808 5809 mmio = pci_iomap(pdev, 0, 0); 5810 if (mmio == NULL) { 5811 pci_disable_device(pdev); 5812 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5813 return; 5814 } 5815 5816 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5817 5818 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5819 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5820 5821 partition = ioread8(&mmio_ntb->partition_id); 5822 5823 partition_map = ioread32(&mmio_ntb->ep_map); 5824 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5825 partition_map &= ~(1ULL << partition); 5826 5827 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5828 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5829 u32 table_sz = 0; 5830 int te; 5831 5832 if (!(partition_map & (1ULL << pp))) 5833 continue; 5834 5835 pci_dbg(pdev, "Processing partition %d\n", pp); 5836 5837 mmio_peer_ctrl = &mmio_ctrl[pp]; 5838 5839 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5840 if (!table_sz) { 5841 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5842 continue; 5843 } 5844 5845 if (table_sz > 512) { 5846 pci_warn(pdev, 5847 "Invalid Switchtec partition %d table_sz %d\n", 5848 pp, table_sz); 5849 continue; 5850 } 5851 5852 for (te = 0; te < table_sz; te++) { 5853 u32 rid_entry; 5854 u8 devfn; 5855 5856 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5857 devfn = (rid_entry >> 1) & 0xFF; 5858 pci_dbg(pdev, 5859 "Aliasing Partition %d Proxy ID %02x.%d\n", 5860 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5861 pci_add_dma_alias(pdev, devfn, 1); 5862 } 5863 } 5864 5865 pci_iounmap(pdev, mmio); 5866 pci_disable_device(pdev); 5867 } 5868 #define SWITCHTEC_QUIRK(vid) \ 5869 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5870 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5871 5872 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5873 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5874 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5875 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5876 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5877 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5878 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5879 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5880 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5881 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5882 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5883 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5884 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5885 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5886 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5887 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5888 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5889 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5890 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5891 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5892 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5893 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5894 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5895 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5896 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5897 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5898 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5899 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5900 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5901 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5902 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5903 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5904 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5905 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5906 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5907 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5908 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5909 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5910 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5911 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5912 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5913 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5914 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5915 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5916 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5917 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5918 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5919 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5920 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 5921 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 5922 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 5923 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 5924 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 5925 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 5926 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 5927 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 5928 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 5929 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 5930 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 5931 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 5932 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 5933 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 5934 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 5935 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 5936 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 5937 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 5938 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 5939 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 5940 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 5941 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 5942 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 5943 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 5944 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 5945 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 5946 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 5947 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 5948 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 5949 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 5950 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 5951 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 5952 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 5953 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 5954 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 5955 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 5956 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 5957 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 5958 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 5959 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 5960 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 5961 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 5962 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 5963 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 5964 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 5965 5966 /* 5967 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5968 * These IDs are used to forward responses to the originator on the other 5969 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5970 * the IOMMU is turned on. 5971 */ 5972 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5973 { 5974 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5975 /* PLX NTB may use all 256 devfns */ 5976 pci_add_dma_alias(pdev, 0, 256); 5977 } 5978 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 5979 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 5980 5981 /* 5982 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 5983 * not always reset the secondary Nvidia GPU between reboots if the system 5984 * is configured to use Hybrid Graphics mode. This results in the GPU 5985 * being left in whatever state it was in during the *previous* boot, which 5986 * causes spurious interrupts from the GPU, which in turn causes us to 5987 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 5988 * this also completely breaks nouveau. 5989 * 5990 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 5991 * clean state and fixes all these issues. 5992 * 5993 * When the machine is configured in Dedicated display mode, the issue 5994 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 5995 * mode, so we can detect that and avoid resetting it. 5996 */ 5997 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 5998 { 5999 void __iomem *map; 6000 int ret; 6001 6002 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6003 pdev->subsystem_device != 0x222e || 6004 !pci_reset_supported(pdev)) 6005 return; 6006 6007 if (pci_enable_device_mem(pdev)) 6008 return; 6009 6010 /* 6011 * Based on nvkm_device_ctor() in 6012 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6013 */ 6014 map = pci_iomap(pdev, 0, 0x23000); 6015 if (!map) { 6016 pci_err(pdev, "Can't map MMIO space\n"); 6017 goto out_disable; 6018 } 6019 6020 /* 6021 * Make sure the GPU looks like it's been POSTed before resetting 6022 * it. 6023 */ 6024 if (ioread32(map + 0x2240c) & 0x2) { 6025 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6026 ret = pci_reset_bus(pdev); 6027 if (ret < 0) 6028 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6029 } 6030 6031 iounmap(map); 6032 out_disable: 6033 pci_disable_device(pdev); 6034 } 6035 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6036 PCI_CLASS_DISPLAY_VGA, 8, 6037 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6038 6039 /* 6040 * Device [1b21:2142] 6041 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6042 */ 6043 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6044 { 6045 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6046 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6047 } 6048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6049 6050 /* 6051 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6052 * 6053 * These devices advertise PME# support in all power states but don't 6054 * reliably assert it. 6055 * 6056 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6057 * says "The MSI Function is not implemented on this device" in chapters 6058 * 7.3.27, 7.3.29-7.3.31. 6059 */ 6060 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6061 { 6062 #ifdef CONFIG_PCI_MSI 6063 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6064 dev->no_msi = 1; 6065 #endif 6066 pci_info(dev, "PME# is unreliable, disabling it\n"); 6067 dev->pme_support = 0; 6068 } 6069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6071 6072 static void apex_pci_fixup_class(struct pci_dev *pdev) 6073 { 6074 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6075 } 6076 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6077 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6078 6079 /* 6080 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6081 * ACS P2P Request Redirect is not functional 6082 * 6083 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6084 * between upstream and downstream ports, packets are queued in an internal 6085 * buffer until CPLD packet. The workaround is to use the switch in store and 6086 * forward mode. 6087 */ 6088 #define PI7C9X2Gxxx_MODE_REG 0x74 6089 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6090 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6091 { 6092 struct pci_dev *upstream; 6093 u16 val; 6094 6095 /* Downstream ports only */ 6096 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6097 return; 6098 6099 /* Check for ACS P2P Request Redirect use */ 6100 if (!pdev->acs_cap) 6101 return; 6102 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6103 if (!(val & PCI_ACS_RR)) 6104 return; 6105 6106 upstream = pci_upstream_bridge(pdev); 6107 if (!upstream) 6108 return; 6109 6110 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6111 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6112 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6113 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6114 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6115 } 6116 } 6117 /* 6118 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6119 * ACS configuration changes or switch mode is reset 6120 */ 6121 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6122 pci_fixup_pericom_acs_store_forward); 6123 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6124 pci_fixup_pericom_acs_store_forward); 6125 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6126 pci_fixup_pericom_acs_store_forward); 6127 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6128 pci_fixup_pericom_acs_store_forward); 6129 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6130 pci_fixup_pericom_acs_store_forward); 6131 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6132 pci_fixup_pericom_acs_store_forward); 6133 6134 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6135 { 6136 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6137 } 6138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6139 6140 static void rom_bar_overlap_defect(struct pci_dev *dev) 6141 { 6142 pci_info(dev, "working around ROM BAR overlap defect\n"); 6143 dev->rom_bar_overlap = 1; 6144 } 6145 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6146 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6147 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6148 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6149 6150 #ifdef CONFIG_PCIEASPM 6151 /* 6152 * Several Intel DG2 graphics devices advertise that they can only tolerate 6153 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6154 * from being enabled. But in fact these devices can tolerate unlimited 6155 * latency. Override their Device Capabilities value to allow ASPM L1 to 6156 * be enabled. 6157 */ 6158 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6159 { 6160 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6161 6162 if (l1_lat < 7) { 6163 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6164 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6165 l1_lat); 6166 } 6167 } 6168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6191 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6193 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6194 #endif 6195 6196 #ifdef CONFIG_PCIE_DPC 6197 /* 6198 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6199 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6200 * Ports. 6201 */ 6202 static void dpc_log_size(struct pci_dev *dev) 6203 { 6204 u16 dpc, val; 6205 6206 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6207 if (!dpc) 6208 return; 6209 6210 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6211 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6212 return; 6213 6214 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6215 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); 6216 dev->dpc_rp_log_size = 4; 6217 } 6218 } 6219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6237 #endif 6238 6239 /* 6240 * For a PCI device with multiple downstream devices, its driver may use 6241 * a flattened device tree to describe the downstream devices. 6242 * To overlay the flattened device tree, the PCI device and all its ancestor 6243 * devices need to have device tree nodes on system base device tree. Thus, 6244 * before driver probing, it might need to add a device tree node as the final 6245 * fixup. 6246 */ 6247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6250 6251 /* 6252 * Devices known to require a longer delay before first config space access 6253 * after reset recovery or resume from D3cold: 6254 * 6255 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6256 */ 6257 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6258 { 6259 pdev->d3cold_delay = 1000; 6260 } 6261 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6262