1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/acpi.h> 21 #include <linux/kallsyms.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <linux/platform_data/x86/apple.h> 29 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 30 #include "pci.h" 31 32 /* 33 * Decoding should be disabled for a PCI device during BAR sizing to avoid 34 * conflict. But doing so may cause problems on host bridge and perhaps other 35 * key system devices. For devices that need to have mmio decoding always-on, 36 * we need to set the dev->mmio_always_on bit. 37 */ 38 static void quirk_mmio_always_on(struct pci_dev *dev) 39 { 40 dev->mmio_always_on = 1; 41 } 42 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 43 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 44 45 /* The Mellanox Tavor device gives false positive parity errors 46 * Mark this device with a broken_parity_status, to allow 47 * PCI scanning code to "skip" this now blacklisted device. 48 */ 49 static void quirk_mellanox_tavor(struct pci_dev *dev) 50 { 51 dev->broken_parity_status = 1; /* This device gives false positives */ 52 } 53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 54 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 55 56 /* Deal with broken BIOSes that neglect to enable passive release, 57 which can cause problems in combination with the 82441FX/PPro MTRRs */ 58 static void quirk_passive_release(struct pci_dev *dev) 59 { 60 struct pci_dev *d = NULL; 61 unsigned char dlc; 62 63 /* We have to make sure a particular bit is set in the PIIX3 64 ISA bridge, so we have to go out and find it. */ 65 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 66 pci_read_config_byte(d, 0x82, &dlc); 67 if (!(dlc & 1<<1)) { 68 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 69 dlc |= 1<<1; 70 pci_write_config_byte(d, 0x82, dlc); 71 } 72 } 73 } 74 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 75 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 76 77 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 78 but VIA don't answer queries. If you happen to have good contacts at VIA 79 ask them for me please -- Alan 80 81 This appears to be BIOS not version dependent. So presumably there is a 82 chipset level fix */ 83 84 static void quirk_isa_dma_hangs(struct pci_dev *dev) 85 { 86 if (!isa_dma_bridge_buggy) { 87 isa_dma_bridge_buggy = 1; 88 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 89 } 90 } 91 /* 92 * Its not totally clear which chipsets are the problematic ones 93 * We know 82C586 and 82C596 variants are affected. 94 */ 95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 102 103 /* 104 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 105 * for some HT machines to use C4 w/o hanging. 106 */ 107 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 108 { 109 u32 pmbase; 110 u16 pm1a; 111 112 pci_read_config_dword(dev, 0x40, &pmbase); 113 pmbase = pmbase & 0xff80; 114 pm1a = inw(pmbase); 115 116 if (pm1a & 0x10) { 117 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 118 outw(0x10, pmbase); 119 } 120 } 121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 122 123 /* 124 * Chipsets where PCI->PCI transfers vanish or hang 125 */ 126 static void quirk_nopcipci(struct pci_dev *dev) 127 { 128 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 129 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 130 pci_pci_problems |= PCIPCI_FAIL; 131 } 132 } 133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 135 136 static void quirk_nopciamd(struct pci_dev *dev) 137 { 138 u8 rev; 139 pci_read_config_byte(dev, 0x08, &rev); 140 if (rev == 0x13) { 141 /* Erratum 24 */ 142 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 143 pci_pci_problems |= PCIAGP_FAIL; 144 } 145 } 146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 147 148 /* 149 * Triton requires workarounds to be used by the drivers 150 */ 151 static void quirk_triton(struct pci_dev *dev) 152 { 153 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 154 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 155 pci_pci_problems |= PCIPCI_TRITON; 156 } 157 } 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 162 163 /* 164 * VIA Apollo KT133 needs PCI latency patch 165 * Made according to a windows driver based patch by George E. Breese 166 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 168 * the info on which Mr Breese based his work. 169 * 170 * Updated based on further information from the site and also on 171 * information provided by VIA 172 */ 173 static void quirk_vialatency(struct pci_dev *dev) 174 { 175 struct pci_dev *p; 176 u8 busarb; 177 /* Ok we have a potential problem chipset here. Now see if we have 178 a buggy southbridge */ 179 180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 181 if (p != NULL) { 182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 183 /* Check for buggy part revisions */ 184 if (p->revision < 0x40 || p->revision > 0x42) 185 goto exit; 186 } else { 187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 188 if (p == NULL) /* No problem parts */ 189 goto exit; 190 /* Check for buggy part revisions */ 191 if (p->revision < 0x10 || p->revision > 0x12) 192 goto exit; 193 } 194 195 /* 196 * Ok we have the problem. Now set the PCI master grant to 197 * occur every master grant. The apparent bug is that under high 198 * PCI load (quite common in Linux of course) you can get data 199 * loss when the CPU is held off the bus for 3 bus master requests 200 * This happens to include the IDE controllers.... 201 * 202 * VIA only apply this fix when an SB Live! is present but under 203 * both Linux and Windows this isn't enough, and we have seen 204 * corruption without SB Live! but with things like 3 UDMA IDE 205 * controllers. So we ignore that bit of the VIA recommendation.. 206 */ 207 208 pci_read_config_byte(dev, 0x76, &busarb); 209 /* Set bit 4 and bi 5 of byte 76 to 0x01 210 "Master priority rotation on every PCI master grant */ 211 busarb &= ~(1<<5); 212 busarb |= (1<<4); 213 pci_write_config_byte(dev, 0x76, busarb); 214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 215 exit: 216 pci_dev_put(p); 217 } 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 221 /* Must restore this on a resume from RAM */ 222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 225 226 /* 227 * VIA Apollo VP3 needs ETBF on BT848/878 228 */ 229 static void quirk_viaetbf(struct pci_dev *dev) 230 { 231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 233 pci_pci_problems |= PCIPCI_VIAETBF; 234 } 235 } 236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 237 238 static void quirk_vsfx(struct pci_dev *dev) 239 { 240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 242 pci_pci_problems |= PCIPCI_VSFX; 243 } 244 } 245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 246 247 /* 248 * Ali Magik requires workarounds to be used by the drivers 249 * that DMA to AGP space. Latency must be set to 0xA and triton 250 * workaround applied too 251 * [Info kindly provided by ALi] 252 */ 253 static void quirk_alimagik(struct pci_dev *dev) 254 { 255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 258 } 259 } 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 262 263 /* 264 * Natoma has some interesting boundary conditions with Zoran stuff 265 * at least 266 */ 267 static void quirk_natoma(struct pci_dev *dev) 268 { 269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 271 pci_pci_problems |= PCIPCI_NATOMA; 272 } 273 } 274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 280 281 /* 282 * This chip can cause PCI parity errors if config register 0xA0 is read 283 * while DMAs are occurring. 284 */ 285 static void quirk_citrine(struct pci_dev *dev) 286 { 287 dev->cfg_size = 0xA0; 288 } 289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 290 291 /* 292 * This chip can cause bus lockups if config addresses above 0x600 293 * are read or written. 294 */ 295 static void quirk_nfp6000(struct pci_dev *dev) 296 { 297 dev->cfg_size = 0x600; 298 } 299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 302 303 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 304 static void quirk_extend_bar_to_page(struct pci_dev *dev) 305 { 306 int i; 307 308 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { 309 struct resource *r = &dev->resource[i]; 310 311 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 312 r->end = PAGE_SIZE - 1; 313 r->start = 0; 314 r->flags |= IORESOURCE_UNSET; 315 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 316 i, r); 317 } 318 } 319 } 320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 321 322 /* 323 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 324 * If it's needed, re-allocate the region. 325 */ 326 static void quirk_s3_64M(struct pci_dev *dev) 327 { 328 struct resource *r = &dev->resource[0]; 329 330 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 331 r->flags |= IORESOURCE_UNSET; 332 r->start = 0; 333 r->end = 0x3ffffff; 334 } 335 } 336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 338 339 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 340 const char *name) 341 { 342 u32 region; 343 struct pci_bus_region bus_region; 344 struct resource *res = dev->resource + pos; 345 346 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 347 348 if (!region) 349 return; 350 351 res->name = pci_name(dev); 352 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 353 res->flags |= 354 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 355 region &= ~(size - 1); 356 357 /* Convert from PCI bus to resource space */ 358 bus_region.start = region; 359 bus_region.end = region + size - 1; 360 pcibios_bus_to_resource(dev->bus, res, &bus_region); 361 362 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 363 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 364 } 365 366 /* 367 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 368 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 369 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 370 * (which conflicts w/ BAR1's memory range). 371 * 372 * CS553x's ISA PCI BARs may also be read-only (ref: 373 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 374 */ 375 static void quirk_cs5536_vsa(struct pci_dev *dev) 376 { 377 static char *name = "CS5536 ISA bridge"; 378 379 if (pci_resource_len(dev, 0) != 8) { 380 quirk_io(dev, 0, 8, name); /* SMB */ 381 quirk_io(dev, 1, 256, name); /* GPIO */ 382 quirk_io(dev, 2, 64, name); /* MFGPT */ 383 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 384 name); 385 } 386 } 387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 388 389 static void quirk_io_region(struct pci_dev *dev, int port, 390 unsigned size, int nr, const char *name) 391 { 392 u16 region; 393 struct pci_bus_region bus_region; 394 struct resource *res = dev->resource + nr; 395 396 pci_read_config_word(dev, port, ®ion); 397 region &= ~(size - 1); 398 399 if (!region) 400 return; 401 402 res->name = pci_name(dev); 403 res->flags = IORESOURCE_IO; 404 405 /* Convert from PCI bus to resource space */ 406 bus_region.start = region; 407 bus_region.end = region + size - 1; 408 pcibios_bus_to_resource(dev->bus, res, &bus_region); 409 410 if (!pci_claim_resource(dev, nr)) 411 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 412 } 413 414 /* 415 * ATI Northbridge setups MCE the processor if you even 416 * read somewhere between 0x3b0->0x3bb or read 0x3d3 417 */ 418 static void quirk_ati_exploding_mce(struct pci_dev *dev) 419 { 420 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 421 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 422 request_region(0x3b0, 0x0C, "RadeonIGP"); 423 request_region(0x3d3, 0x01, "RadeonIGP"); 424 } 425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 426 427 /* 428 * In the AMD NL platform, this device ([1022:7912]) has a class code of 429 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 430 * claim it. 431 * But the dwc3 driver is a more specific driver for this device, and we'd 432 * prefer to use it instead of xhci. To prevent xhci from claiming the 433 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 434 * defines as "USB device (not host controller)". The dwc3 driver can then 435 * claim it based on its Vendor and Device ID. 436 */ 437 static void quirk_amd_nl_class(struct pci_dev *pdev) 438 { 439 u32 class = pdev->class; 440 441 /* Use "USB Device (not host controller)" class */ 442 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 443 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 444 class, pdev->class); 445 } 446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 447 quirk_amd_nl_class); 448 449 /* 450 * Let's make the southbridge information explicit instead 451 * of having to worry about people probing the ACPI areas, 452 * for example.. (Yes, it happens, and if you read the wrong 453 * ACPI register it will put the machine to sleep with no 454 * way of waking it up again. Bummer). 455 * 456 * ALI M7101: Two IO regions pointed to by words at 457 * 0xE0 (64 bytes of ACPI registers) 458 * 0xE2 (32 bytes of SMB registers) 459 */ 460 static void quirk_ali7101_acpi(struct pci_dev *dev) 461 { 462 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 463 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 464 } 465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 466 467 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 468 { 469 u32 devres; 470 u32 mask, size, base; 471 472 pci_read_config_dword(dev, port, &devres); 473 if ((devres & enable) != enable) 474 return; 475 mask = (devres >> 16) & 15; 476 base = devres & 0xffff; 477 size = 16; 478 for (;;) { 479 unsigned bit = size >> 1; 480 if ((bit & mask) == bit) 481 break; 482 size = bit; 483 } 484 /* 485 * For now we only print it out. Eventually we'll want to 486 * reserve it (at least if it's in the 0x1000+ range), but 487 * let's get enough confirmation reports first. 488 */ 489 base &= -size; 490 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 491 base + size - 1); 492 } 493 494 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 495 { 496 u32 devres; 497 u32 mask, size, base; 498 499 pci_read_config_dword(dev, port, &devres); 500 if ((devres & enable) != enable) 501 return; 502 base = devres & 0xffff0000; 503 mask = (devres & 0x3f) << 16; 504 size = 128 << 16; 505 for (;;) { 506 unsigned bit = size >> 1; 507 if ((bit & mask) == bit) 508 break; 509 size = bit; 510 } 511 /* 512 * For now we only print it out. Eventually we'll want to 513 * reserve it, but let's get enough confirmation reports first. 514 */ 515 base &= -size; 516 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 517 base + size - 1); 518 } 519 520 /* 521 * PIIX4 ACPI: Two IO regions pointed to by longwords at 522 * 0x40 (64 bytes of ACPI registers) 523 * 0x90 (16 bytes of SMB registers) 524 * and a few strange programmable PIIX4 device resources. 525 */ 526 static void quirk_piix4_acpi(struct pci_dev *dev) 527 { 528 u32 res_a; 529 530 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 531 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 532 533 /* Device resource A has enables for some of the other ones */ 534 pci_read_config_dword(dev, 0x5c, &res_a); 535 536 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 537 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 538 539 /* Device resource D is just bitfields for static resources */ 540 541 /* Device 12 enabled? */ 542 if (res_a & (1 << 29)) { 543 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 544 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 545 } 546 /* Device 13 enabled? */ 547 if (res_a & (1 << 30)) { 548 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 549 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 550 } 551 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 552 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 553 } 554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 556 557 #define ICH_PMBASE 0x40 558 #define ICH_ACPI_CNTL 0x44 559 #define ICH4_ACPI_EN 0x10 560 #define ICH6_ACPI_EN 0x80 561 #define ICH4_GPIOBASE 0x58 562 #define ICH4_GPIO_CNTL 0x5c 563 #define ICH4_GPIO_EN 0x10 564 #define ICH6_GPIOBASE 0x48 565 #define ICH6_GPIO_CNTL 0x4c 566 #define ICH6_GPIO_EN 0x10 567 568 /* 569 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 570 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 571 * 0x58 (64 bytes of GPIO I/O space) 572 */ 573 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 574 { 575 u8 enable; 576 577 /* 578 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 579 * with low legacy (and fixed) ports. We don't know the decoding 580 * priority and can't tell whether the legacy device or the one created 581 * here is really at that address. This happens on boards with broken 582 * BIOSes. 583 */ 584 585 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 586 if (enable & ICH4_ACPI_EN) 587 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 588 "ICH4 ACPI/GPIO/TCO"); 589 590 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 591 if (enable & ICH4_GPIO_EN) 592 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 593 "ICH4 GPIO"); 594 } 595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 605 606 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 607 { 608 u8 enable; 609 610 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 611 if (enable & ICH6_ACPI_EN) 612 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 613 "ICH6 ACPI/GPIO/TCO"); 614 615 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 616 if (enable & ICH6_GPIO_EN) 617 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 618 "ICH6 GPIO"); 619 } 620 621 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 622 { 623 u32 val; 624 u32 size, base; 625 626 pci_read_config_dword(dev, reg, &val); 627 628 /* Enabled? */ 629 if (!(val & 1)) 630 return; 631 base = val & 0xfffc; 632 if (dynsize) { 633 /* 634 * This is not correct. It is 16, 32 or 64 bytes depending on 635 * register D31:F0:ADh bits 5:4. 636 * 637 * But this gets us at least _part_ of it. 638 */ 639 size = 16; 640 } else { 641 size = 128; 642 } 643 base &= ~(size-1); 644 645 /* Just print it out for now. We should reserve it after more debugging */ 646 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 647 } 648 649 static void quirk_ich6_lpc(struct pci_dev *dev) 650 { 651 /* Shared ACPI/GPIO decode with all ICH6+ */ 652 ich6_lpc_acpi_gpio(dev); 653 654 /* ICH6-specific generic IO decode */ 655 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 656 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 657 } 658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 660 661 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 662 { 663 u32 val; 664 u32 mask, base; 665 666 pci_read_config_dword(dev, reg, &val); 667 668 /* Enabled? */ 669 if (!(val & 1)) 670 return; 671 672 /* 673 * IO base in bits 15:2, mask in bits 23:18, both 674 * are dword-based 675 */ 676 base = val & 0xfffc; 677 mask = (val >> 16) & 0xfc; 678 mask |= 3; 679 680 /* Just print it out for now. We should reserve it after more debugging */ 681 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 682 } 683 684 /* ICH7-10 has the same common LPC generic IO decode registers */ 685 static void quirk_ich7_lpc(struct pci_dev *dev) 686 { 687 /* We share the common ACPI/GPIO decode with ICH6 */ 688 ich6_lpc_acpi_gpio(dev); 689 690 /* And have 4 ICH7+ generic decodes */ 691 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 692 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 693 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 694 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 695 } 696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 709 710 /* 711 * VIA ACPI: One IO region pointed to by longword at 712 * 0x48 or 0x20 (256 bytes of ACPI registers) 713 */ 714 static void quirk_vt82c586_acpi(struct pci_dev *dev) 715 { 716 if (dev->revision & 0x10) 717 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 718 "vt82c586 ACPI"); 719 } 720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 721 722 /* 723 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 724 * 0x48 (256 bytes of ACPI registers) 725 * 0x70 (128 bytes of hardware monitoring register) 726 * 0x90 (16 bytes of SMB registers) 727 */ 728 static void quirk_vt82c686_acpi(struct pci_dev *dev) 729 { 730 quirk_vt82c586_acpi(dev); 731 732 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 733 "vt82c686 HW-mon"); 734 735 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 736 } 737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 738 739 /* 740 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 741 * 0x88 (128 bytes of power management registers) 742 * 0xd0 (16 bytes of SMB registers) 743 */ 744 static void quirk_vt8235_acpi(struct pci_dev *dev) 745 { 746 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 747 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 748 } 749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 750 751 /* 752 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 753 * Disable fast back-to-back on the secondary bus segment 754 */ 755 static void quirk_xio2000a(struct pci_dev *dev) 756 { 757 struct pci_dev *pdev; 758 u16 command; 759 760 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 761 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 762 pci_read_config_word(pdev, PCI_COMMAND, &command); 763 if (command & PCI_COMMAND_FAST_BACK) 764 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 765 } 766 } 767 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 768 quirk_xio2000a); 769 770 #ifdef CONFIG_X86_IO_APIC 771 772 #include <asm/io_apic.h> 773 774 /* 775 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 776 * devices to the external APIC. 777 * 778 * TODO: When we have device-specific interrupt routers, 779 * this code will go away from quirks. 780 */ 781 static void quirk_via_ioapic(struct pci_dev *dev) 782 { 783 u8 tmp; 784 785 if (nr_ioapics < 1) 786 tmp = 0; /* nothing routed to external APIC */ 787 else 788 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 789 790 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 791 tmp == 0 ? "Disa" : "Ena"); 792 793 /* Offset 0x58: External APIC IRQ output control */ 794 pci_write_config_byte(dev, 0x58, tmp); 795 } 796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 797 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 798 799 /* 800 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 801 * This leads to doubled level interrupt rates. 802 * Set this bit to get rid of cycle wastage. 803 * Otherwise uncritical. 804 */ 805 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 806 { 807 u8 misc_control2; 808 #define BYPASS_APIC_DEASSERT 8 809 810 pci_read_config_byte(dev, 0x5B, &misc_control2); 811 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 812 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 813 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 814 } 815 } 816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 817 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 818 819 /* 820 * The AMD io apic can hang the box when an apic irq is masked. 821 * We check all revs >= B0 (yet not in the pre production!) as the bug 822 * is currently marked NoFix 823 * 824 * We have multiple reports of hangs with this chipset that went away with 825 * noapic specified. For the moment we assume it's the erratum. We may be wrong 826 * of course. However the advice is demonstrably good even if so.. 827 */ 828 static void quirk_amd_ioapic(struct pci_dev *dev) 829 { 830 if (dev->revision >= 0x02) { 831 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 832 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 833 } 834 } 835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 836 #endif /* CONFIG_X86_IO_APIC */ 837 838 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 839 840 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 841 { 842 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */ 843 if (dev->subsystem_device == 0xa118) 844 dev->sriov->link = dev->devfn; 845 } 846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 847 #endif 848 849 /* 850 * Some settings of MMRBC can lead to data corruption so block changes. 851 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 852 */ 853 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 854 { 855 if (dev->subordinate && dev->revision <= 0x12) { 856 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 857 dev->revision); 858 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 859 } 860 } 861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 862 863 /* 864 * FIXME: it is questionable that quirk_via_acpi 865 * is needed. It shows up as an ISA bridge, and does not 866 * support the PCI_INTERRUPT_LINE register at all. Therefore 867 * it seems like setting the pci_dev's 'irq' to the 868 * value of the ACPI SCI interrupt is only done for convenience. 869 * -jgarzik 870 */ 871 static void quirk_via_acpi(struct pci_dev *d) 872 { 873 /* 874 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 875 */ 876 u8 irq; 877 pci_read_config_byte(d, 0x42, &irq); 878 irq &= 0xf; 879 if (irq && (irq != 2)) 880 d->irq = irq; 881 } 882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 884 885 886 /* 887 * VIA bridges which have VLink 888 */ 889 890 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 891 892 static void quirk_via_bridge(struct pci_dev *dev) 893 { 894 /* See what bridge we have and find the device ranges */ 895 switch (dev->device) { 896 case PCI_DEVICE_ID_VIA_82C686: 897 /* The VT82C686 is special, it attaches to PCI and can have 898 any device number. All its subdevices are functions of 899 that single device. */ 900 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 901 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 902 break; 903 case PCI_DEVICE_ID_VIA_8237: 904 case PCI_DEVICE_ID_VIA_8237A: 905 via_vlink_dev_lo = 15; 906 break; 907 case PCI_DEVICE_ID_VIA_8235: 908 via_vlink_dev_lo = 16; 909 break; 910 case PCI_DEVICE_ID_VIA_8231: 911 case PCI_DEVICE_ID_VIA_8233_0: 912 case PCI_DEVICE_ID_VIA_8233A: 913 case PCI_DEVICE_ID_VIA_8233C_0: 914 via_vlink_dev_lo = 17; 915 break; 916 } 917 } 918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 926 927 /** 928 * quirk_via_vlink - VIA VLink IRQ number update 929 * @dev: PCI device 930 * 931 * If the device we are dealing with is on a PIC IRQ we need to 932 * ensure that the IRQ line register which usually is not relevant 933 * for PCI cards, is actually written so that interrupts get sent 934 * to the right place. 935 * We only do this on systems where a VIA south bridge was detected, 936 * and only for VIA devices on the motherboard (see quirk_via_bridge 937 * above). 938 */ 939 940 static void quirk_via_vlink(struct pci_dev *dev) 941 { 942 u8 irq, new_irq; 943 944 /* Check if we have VLink at all */ 945 if (via_vlink_dev_lo == -1) 946 return; 947 948 new_irq = dev->irq; 949 950 /* Don't quirk interrupts outside the legacy IRQ range */ 951 if (!new_irq || new_irq > 15) 952 return; 953 954 /* Internal device ? */ 955 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 956 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 957 return; 958 959 /* This is an internal VLink device on a PIC interrupt. The BIOS 960 ought to have set this but may not have, so we redo it */ 961 962 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 963 if (new_irq != irq) { 964 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 965 irq, new_irq); 966 udelay(15); /* unknown if delay really needed */ 967 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 968 } 969 } 970 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 971 972 /* 973 * VIA VT82C598 has its device ID settable and many BIOSes 974 * set it to the ID of VT82C597 for backward compatibility. 975 * We need to switch it off to be able to recognize the real 976 * type of the chip. 977 */ 978 static void quirk_vt82c598_id(struct pci_dev *dev) 979 { 980 pci_write_config_byte(dev, 0xfc, 0); 981 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 982 } 983 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 984 985 /* 986 * CardBus controllers have a legacy base address that enables them 987 * to respond as i82365 pcmcia controllers. We don't want them to 988 * do this even if the Linux CardBus driver is not loaded, because 989 * the Linux i82365 driver does not (and should not) handle CardBus. 990 */ 991 static void quirk_cardbus_legacy(struct pci_dev *dev) 992 { 993 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 994 } 995 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 996 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 997 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 998 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 999 1000 /* 1001 * Following the PCI ordering rules is optional on the AMD762. I'm not 1002 * sure what the designers were smoking but let's not inhale... 1003 * 1004 * To be fair to AMD, it follows the spec by default, its BIOS people 1005 * who turn it off! 1006 */ 1007 static void quirk_amd_ordering(struct pci_dev *dev) 1008 { 1009 u32 pcic; 1010 pci_read_config_dword(dev, 0x4C, &pcic); 1011 if ((pcic & 6) != 6) { 1012 pcic |= 6; 1013 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1014 pci_write_config_dword(dev, 0x4C, pcic); 1015 pci_read_config_dword(dev, 0x84, &pcic); 1016 pcic |= (1 << 23); /* Required in this mode */ 1017 pci_write_config_dword(dev, 0x84, pcic); 1018 } 1019 } 1020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1021 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1022 1023 /* 1024 * DreamWorks provided workaround for Dunord I-3000 problem 1025 * 1026 * This card decodes and responds to addresses not apparently 1027 * assigned to it. We force a larger allocation to ensure that 1028 * nothing gets put too close to it. 1029 */ 1030 static void quirk_dunord(struct pci_dev *dev) 1031 { 1032 struct resource *r = &dev->resource[1]; 1033 1034 r->flags |= IORESOURCE_UNSET; 1035 r->start = 0; 1036 r->end = 0xffffff; 1037 } 1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1039 1040 /* 1041 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1042 * is subtractive decoding (transparent), and does indicate this 1043 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1044 * instead of 0x01. 1045 */ 1046 static void quirk_transparent_bridge(struct pci_dev *dev) 1047 { 1048 dev->transparent = 1; 1049 } 1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1052 1053 /* 1054 * Common misconfiguration of the MediaGX/Geode PCI master that will 1055 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1056 * datasheets found at http://www.national.com/analog for info on what 1057 * these bits do. <christer@weinigel.se> 1058 */ 1059 static void quirk_mediagx_master(struct pci_dev *dev) 1060 { 1061 u8 reg; 1062 1063 pci_read_config_byte(dev, 0x41, ®); 1064 if (reg & 2) { 1065 reg &= ~2; 1066 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1067 reg); 1068 pci_write_config_byte(dev, 0x41, reg); 1069 } 1070 } 1071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1072 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1073 1074 /* 1075 * Ensure C0 rev restreaming is off. This is normally done by 1076 * the BIOS but in the odd case it is not the results are corruption 1077 * hence the presence of a Linux check 1078 */ 1079 static void quirk_disable_pxb(struct pci_dev *pdev) 1080 { 1081 u16 config; 1082 1083 if (pdev->revision != 0x04) /* Only C0 requires this */ 1084 return; 1085 pci_read_config_word(pdev, 0x40, &config); 1086 if (config & (1<<6)) { 1087 config &= ~(1<<6); 1088 pci_write_config_word(pdev, 0x40, config); 1089 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1090 } 1091 } 1092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1093 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1094 1095 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1096 { 1097 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1098 u8 tmp; 1099 1100 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1101 if (tmp == 0x01) { 1102 pci_read_config_byte(pdev, 0x40, &tmp); 1103 pci_write_config_byte(pdev, 0x40, tmp|1); 1104 pci_write_config_byte(pdev, 0x9, 1); 1105 pci_write_config_byte(pdev, 0xa, 6); 1106 pci_write_config_byte(pdev, 0x40, tmp); 1107 1108 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1109 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1110 } 1111 } 1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1113 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1117 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1119 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1120 1121 /* 1122 * Serverworks CSB5 IDE does not fully support native mode 1123 */ 1124 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1125 { 1126 u8 prog; 1127 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1128 if (prog & 5) { 1129 prog &= ~5; 1130 pdev->class &= ~5; 1131 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1132 /* PCI layer will sort out resources */ 1133 } 1134 } 1135 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1136 1137 /* 1138 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1139 */ 1140 static void quirk_ide_samemode(struct pci_dev *pdev) 1141 { 1142 u8 prog; 1143 1144 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1145 1146 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1147 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1148 prog &= ~5; 1149 pdev->class &= ~5; 1150 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1151 } 1152 } 1153 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1154 1155 /* 1156 * Some ATA devices break if put into D3 1157 */ 1158 1159 static void quirk_no_ata_d3(struct pci_dev *pdev) 1160 { 1161 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1162 } 1163 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1164 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1165 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1166 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1167 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1168 /* ALi loses some register settings that we cannot then restore */ 1169 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1170 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1171 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1172 occur when mode detecting */ 1173 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1174 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1175 1176 /* This was originally an Alpha specific thing, but it really fits here. 1177 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1178 */ 1179 static void quirk_eisa_bridge(struct pci_dev *dev) 1180 { 1181 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1182 } 1183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1184 1185 1186 /* 1187 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1188 * is not activated. The myth is that Asus said that they do not want the 1189 * users to be irritated by just another PCI Device in the Win98 device 1190 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1191 * package 2.7.0 for details) 1192 * 1193 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1194 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1195 * becomes necessary to do this tweak in two steps -- the chosen trigger 1196 * is either the Host bridge (preferred) or on-board VGA controller. 1197 * 1198 * Note that we used to unhide the SMBus that way on Toshiba laptops 1199 * (Satellite A40 and Tecra M2) but then found that the thermal management 1200 * was done by SMM code, which could cause unsynchronized concurrent 1201 * accesses to the SMBus registers, with potentially bad effects. Thus you 1202 * should be very careful when adding new entries: if SMM is accessing the 1203 * Intel SMBus, this is a very good reason to leave it hidden. 1204 * 1205 * Likewise, many recent laptops use ACPI for thermal management. If the 1206 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1207 * natively, and keeping the SMBus hidden is the right thing to do. If you 1208 * are about to add an entry in the table below, please first disassemble 1209 * the DSDT and double-check that there is no code accessing the SMBus. 1210 */ 1211 static int asus_hides_smbus; 1212 1213 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1214 { 1215 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1216 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1217 switch (dev->subsystem_device) { 1218 case 0x8025: /* P4B-LX */ 1219 case 0x8070: /* P4B */ 1220 case 0x8088: /* P4B533 */ 1221 case 0x1626: /* L3C notebook */ 1222 asus_hides_smbus = 1; 1223 } 1224 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1225 switch (dev->subsystem_device) { 1226 case 0x80b1: /* P4GE-V */ 1227 case 0x80b2: /* P4PE */ 1228 case 0x8093: /* P4B533-V */ 1229 asus_hides_smbus = 1; 1230 } 1231 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1232 switch (dev->subsystem_device) { 1233 case 0x8030: /* P4T533 */ 1234 asus_hides_smbus = 1; 1235 } 1236 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1237 switch (dev->subsystem_device) { 1238 case 0x8070: /* P4G8X Deluxe */ 1239 asus_hides_smbus = 1; 1240 } 1241 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1242 switch (dev->subsystem_device) { 1243 case 0x80c9: /* PU-DLS */ 1244 asus_hides_smbus = 1; 1245 } 1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1247 switch (dev->subsystem_device) { 1248 case 0x1751: /* M2N notebook */ 1249 case 0x1821: /* M5N notebook */ 1250 case 0x1897: /* A6L notebook */ 1251 asus_hides_smbus = 1; 1252 } 1253 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1254 switch (dev->subsystem_device) { 1255 case 0x184b: /* W1N notebook */ 1256 case 0x186a: /* M6Ne notebook */ 1257 asus_hides_smbus = 1; 1258 } 1259 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1260 switch (dev->subsystem_device) { 1261 case 0x80f2: /* P4P800-X */ 1262 asus_hides_smbus = 1; 1263 } 1264 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1265 switch (dev->subsystem_device) { 1266 case 0x1882: /* M6V notebook */ 1267 case 0x1977: /* A6VA notebook */ 1268 asus_hides_smbus = 1; 1269 } 1270 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1271 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1272 switch (dev->subsystem_device) { 1273 case 0x088C: /* HP Compaq nc8000 */ 1274 case 0x0890: /* HP Compaq nc6000 */ 1275 asus_hides_smbus = 1; 1276 } 1277 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1278 switch (dev->subsystem_device) { 1279 case 0x12bc: /* HP D330L */ 1280 case 0x12bd: /* HP D530 */ 1281 case 0x006a: /* HP Compaq nx9500 */ 1282 asus_hides_smbus = 1; 1283 } 1284 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1285 switch (dev->subsystem_device) { 1286 case 0x12bf: /* HP xw4100 */ 1287 asus_hides_smbus = 1; 1288 } 1289 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1290 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1291 switch (dev->subsystem_device) { 1292 case 0xC00C: /* Samsung P35 notebook */ 1293 asus_hides_smbus = 1; 1294 } 1295 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1296 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1297 switch (dev->subsystem_device) { 1298 case 0x0058: /* Compaq Evo N620c */ 1299 asus_hides_smbus = 1; 1300 } 1301 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1302 switch (dev->subsystem_device) { 1303 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1304 /* Motherboard doesn't have Host bridge 1305 * subvendor/subdevice IDs, therefore checking 1306 * its on-board VGA controller */ 1307 asus_hides_smbus = 1; 1308 } 1309 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1310 switch (dev->subsystem_device) { 1311 case 0x00b8: /* Compaq Evo D510 CMT */ 1312 case 0x00b9: /* Compaq Evo D510 SFF */ 1313 case 0x00ba: /* Compaq Evo D510 USDT */ 1314 /* Motherboard doesn't have Host bridge 1315 * subvendor/subdevice IDs and on-board VGA 1316 * controller is disabled if an AGP card is 1317 * inserted, therefore checking USB UHCI 1318 * Controller #1 */ 1319 asus_hides_smbus = 1; 1320 } 1321 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1322 switch (dev->subsystem_device) { 1323 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1324 /* Motherboard doesn't have host bridge 1325 * subvendor/subdevice IDs, therefore checking 1326 * its on-board VGA controller */ 1327 asus_hides_smbus = 1; 1328 } 1329 } 1330 } 1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1341 1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1345 1346 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1347 { 1348 u16 val; 1349 1350 if (likely(!asus_hides_smbus)) 1351 return; 1352 1353 pci_read_config_word(dev, 0xF2, &val); 1354 if (val & 0x8) { 1355 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1356 pci_read_config_word(dev, 0xF2, &val); 1357 if (val & 0x8) 1358 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1359 val); 1360 else 1361 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1362 } 1363 } 1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1377 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1378 1379 /* It appears we just have one such device. If not, we have a warning */ 1380 static void __iomem *asus_rcba_base; 1381 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1382 { 1383 u32 rcba; 1384 1385 if (likely(!asus_hides_smbus)) 1386 return; 1387 WARN_ON(asus_rcba_base); 1388 1389 pci_read_config_dword(dev, 0xF0, &rcba); 1390 /* use bits 31:14, 16 kB aligned */ 1391 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1392 if (asus_rcba_base == NULL) 1393 return; 1394 } 1395 1396 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1397 { 1398 u32 val; 1399 1400 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1401 return; 1402 /* read the Function Disable register, dword mode only */ 1403 val = readl(asus_rcba_base + 0x3418); 1404 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1405 } 1406 1407 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1408 { 1409 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1410 return; 1411 iounmap(asus_rcba_base); 1412 asus_rcba_base = NULL; 1413 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1414 } 1415 1416 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1417 { 1418 asus_hides_smbus_lpc_ich6_suspend(dev); 1419 asus_hides_smbus_lpc_ich6_resume_early(dev); 1420 asus_hides_smbus_lpc_ich6_resume(dev); 1421 } 1422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1423 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1424 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1425 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1426 1427 /* 1428 * SiS 96x south bridge: BIOS typically hides SMBus device... 1429 */ 1430 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1431 { 1432 u8 val = 0; 1433 pci_read_config_byte(dev, 0x77, &val); 1434 if (val & 0x10) { 1435 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1436 pci_write_config_byte(dev, 0x77, val & ~0x10); 1437 } 1438 } 1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1446 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1447 1448 /* 1449 * ... This is further complicated by the fact that some SiS96x south 1450 * bridges pretend to be 85C503/5513 instead. In that case see if we 1451 * spotted a compatible north bridge to make sure. 1452 * (pci_find_device doesn't work yet) 1453 * 1454 * We can also enable the sis96x bit in the discovery register.. 1455 */ 1456 #define SIS_DETECT_REGISTER 0x40 1457 1458 static void quirk_sis_503(struct pci_dev *dev) 1459 { 1460 u8 reg; 1461 u16 devid; 1462 1463 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1464 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1465 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1466 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1467 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1468 return; 1469 } 1470 1471 /* 1472 * Ok, it now shows up as a 96x.. run the 96x quirk by 1473 * hand in case it has already been processed. 1474 * (depends on link order, which is apparently not guaranteed) 1475 */ 1476 dev->device = devid; 1477 quirk_sis_96x_smbus(dev); 1478 } 1479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1480 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1481 1482 1483 /* 1484 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1485 * and MC97 modem controller are disabled when a second PCI soundcard is 1486 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1487 * -- bjd 1488 */ 1489 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1490 { 1491 u8 val; 1492 int asus_hides_ac97 = 0; 1493 1494 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1495 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1496 asus_hides_ac97 = 1; 1497 } 1498 1499 if (!asus_hides_ac97) 1500 return; 1501 1502 pci_read_config_byte(dev, 0x50, &val); 1503 if (val & 0xc0) { 1504 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1505 pci_read_config_byte(dev, 0x50, &val); 1506 if (val & 0xc0) 1507 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1508 val); 1509 else 1510 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1511 } 1512 } 1513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1514 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1515 1516 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1517 1518 /* 1519 * If we are using libata we can drive this chip properly but must 1520 * do this early on to make the additional device appear during 1521 * the PCI scanning. 1522 */ 1523 static void quirk_jmicron_ata(struct pci_dev *pdev) 1524 { 1525 u32 conf1, conf5, class; 1526 u8 hdr; 1527 1528 /* Only poke fn 0 */ 1529 if (PCI_FUNC(pdev->devfn)) 1530 return; 1531 1532 pci_read_config_dword(pdev, 0x40, &conf1); 1533 pci_read_config_dword(pdev, 0x80, &conf5); 1534 1535 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1536 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1537 1538 switch (pdev->device) { 1539 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1540 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1541 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1542 /* The controller should be in single function ahci mode */ 1543 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1544 break; 1545 1546 case PCI_DEVICE_ID_JMICRON_JMB365: 1547 case PCI_DEVICE_ID_JMICRON_JMB366: 1548 /* Redirect IDE second PATA port to the right spot */ 1549 conf5 |= (1 << 24); 1550 /* Fall through */ 1551 case PCI_DEVICE_ID_JMICRON_JMB361: 1552 case PCI_DEVICE_ID_JMICRON_JMB363: 1553 case PCI_DEVICE_ID_JMICRON_JMB369: 1554 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1555 /* Set the class codes correctly and then direct IDE 0 */ 1556 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1557 break; 1558 1559 case PCI_DEVICE_ID_JMICRON_JMB368: 1560 /* The controller should be in single function IDE mode */ 1561 conf1 |= 0x00C00000; /* Set 22, 23 */ 1562 break; 1563 } 1564 1565 pci_write_config_dword(pdev, 0x40, conf1); 1566 pci_write_config_dword(pdev, 0x80, conf5); 1567 1568 /* Update pdev accordingly */ 1569 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1570 pdev->hdr_type = hdr & 0x7f; 1571 pdev->multifunction = !!(hdr & 0x80); 1572 1573 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1574 pdev->class = class >> 8; 1575 } 1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1593 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1594 1595 #endif 1596 1597 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1598 { 1599 if (dev->multifunction) { 1600 device_disable_async_suspend(&dev->dev); 1601 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1602 } 1603 } 1604 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1605 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1608 1609 #ifdef CONFIG_X86_IO_APIC 1610 static void quirk_alder_ioapic(struct pci_dev *pdev) 1611 { 1612 int i; 1613 1614 if ((pdev->class >> 8) != 0xff00) 1615 return; 1616 1617 /* the first BAR is the location of the IO APIC...we must 1618 * not touch this (and it's already covered by the fixmap), so 1619 * forcibly insert it into the resource tree */ 1620 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1621 insert_resource(&iomem_resource, &pdev->resource[0]); 1622 1623 /* The next five BARs all seem to be rubbish, so just clean 1624 * them out */ 1625 for (i = 1; i < 6; i++) 1626 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1627 } 1628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1629 #endif 1630 1631 static void quirk_pcie_mch(struct pci_dev *pdev) 1632 { 1633 pdev->no_msi = 1; 1634 } 1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch); 1639 1640 1641 /* 1642 * It's possible for the MSI to get corrupted if shpc and acpi 1643 * are used together on certain PXH-based systems. 1644 */ 1645 static void quirk_pcie_pxh(struct pci_dev *dev) 1646 { 1647 dev->no_msi = 1; 1648 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1649 } 1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1654 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1655 1656 /* 1657 * Some Intel PCI Express chipsets have trouble with downstream 1658 * device power management. 1659 */ 1660 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1661 { 1662 pci_pm_d3_delay = 120; 1663 dev->no_d1d2 = 1; 1664 } 1665 1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1687 1688 static void quirk_radeon_pm(struct pci_dev *dev) 1689 { 1690 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1691 dev->subsystem_device == 0x00e2) { 1692 if (dev->d3_delay < 20) { 1693 dev->d3_delay = 20; 1694 dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n", 1695 dev->d3_delay); 1696 } 1697 } 1698 } 1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1700 1701 #ifdef CONFIG_X86_IO_APIC 1702 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1703 { 1704 noioapicreroute = 1; 1705 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1706 1707 return 0; 1708 } 1709 1710 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1711 /* 1712 * Systems to exclude from boot interrupt reroute quirks 1713 */ 1714 { 1715 .callback = dmi_disable_ioapicreroute, 1716 .ident = "ASUSTek Computer INC. M2N-LR", 1717 .matches = { 1718 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1719 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1720 }, 1721 }, 1722 {} 1723 }; 1724 1725 /* 1726 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1727 * remap the original interrupt in the linux kernel to the boot interrupt, so 1728 * that a PCI device's interrupt handler is installed on the boot interrupt 1729 * line instead. 1730 */ 1731 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1732 { 1733 dmi_check_system(boot_interrupt_dmi_table); 1734 if (noioapicquirk || noioapicreroute) 1735 return; 1736 1737 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1738 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1739 dev->vendor, dev->device); 1740 } 1741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1748 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1749 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1754 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1755 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1756 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1757 1758 /* 1759 * On some chipsets we can disable the generation of legacy INTx boot 1760 * interrupts. 1761 */ 1762 1763 /* 1764 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1765 * 300641-004US, section 5.7.3. 1766 */ 1767 #define INTEL_6300_IOAPIC_ABAR 0x40 1768 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1769 1770 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1771 { 1772 u16 pci_config_word; 1773 1774 if (noioapicquirk) 1775 return; 1776 1777 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1778 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1779 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1780 1781 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1782 dev->vendor, dev->device); 1783 } 1784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1785 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1786 1787 /* 1788 * disable boot interrupts on HT-1000 1789 */ 1790 #define BC_HT1000_FEATURE_REG 0x64 1791 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1792 #define BC_HT1000_MAP_IDX 0xC00 1793 #define BC_HT1000_MAP_DATA 0xC01 1794 1795 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1796 { 1797 u32 pci_config_dword; 1798 u8 irq; 1799 1800 if (noioapicquirk) 1801 return; 1802 1803 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1804 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1805 BC_HT1000_PIC_REGS_ENABLE); 1806 1807 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1808 outb(irq, BC_HT1000_MAP_IDX); 1809 outb(0x00, BC_HT1000_MAP_DATA); 1810 } 1811 1812 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1813 1814 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1815 dev->vendor, dev->device); 1816 } 1817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1818 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1819 1820 /* 1821 * disable boot interrupts on AMD and ATI chipsets 1822 */ 1823 /* 1824 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1825 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1826 * (due to an erratum). 1827 */ 1828 #define AMD_813X_MISC 0x40 1829 #define AMD_813X_NOIOAMODE (1<<0) 1830 #define AMD_813X_REV_B1 0x12 1831 #define AMD_813X_REV_B2 0x13 1832 1833 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1834 { 1835 u32 pci_config_dword; 1836 1837 if (noioapicquirk) 1838 return; 1839 if ((dev->revision == AMD_813X_REV_B1) || 1840 (dev->revision == AMD_813X_REV_B2)) 1841 return; 1842 1843 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1844 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1845 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1846 1847 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1848 dev->vendor, dev->device); 1849 } 1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1851 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1853 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1854 1855 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1856 1857 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1858 { 1859 u16 pci_config_word; 1860 1861 if (noioapicquirk) 1862 return; 1863 1864 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1865 if (!pci_config_word) { 1866 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1867 dev->vendor, dev->device); 1868 return; 1869 } 1870 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1871 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1872 dev->vendor, dev->device); 1873 } 1874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1875 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1876 #endif /* CONFIG_X86_IO_APIC */ 1877 1878 /* 1879 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1880 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1881 * Re-allocate the region if needed... 1882 */ 1883 static void quirk_tc86c001_ide(struct pci_dev *dev) 1884 { 1885 struct resource *r = &dev->resource[0]; 1886 1887 if (r->start & 0x8) { 1888 r->flags |= IORESOURCE_UNSET; 1889 r->start = 0; 1890 r->end = 0xf; 1891 } 1892 } 1893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1894 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1895 quirk_tc86c001_ide); 1896 1897 /* 1898 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1899 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1900 * being read correctly if bit 7 of the base address is set. 1901 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1902 * Re-allocate the regions to a 256-byte boundary if necessary. 1903 */ 1904 static void quirk_plx_pci9050(struct pci_dev *dev) 1905 { 1906 unsigned int bar; 1907 1908 /* Fixed in revision 2 (PCI 9052). */ 1909 if (dev->revision >= 2) 1910 return; 1911 for (bar = 0; bar <= 1; bar++) 1912 if (pci_resource_len(dev, bar) == 0x80 && 1913 (pci_resource_start(dev, bar) & 0x80)) { 1914 struct resource *r = &dev->resource[bar]; 1915 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1916 bar); 1917 r->flags |= IORESOURCE_UNSET; 1918 r->start = 0; 1919 r->end = 0xff; 1920 } 1921 } 1922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1923 quirk_plx_pci9050); 1924 /* 1925 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1926 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1927 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1928 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1929 * 1930 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1931 * driver. 1932 */ 1933 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1934 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1935 1936 static void quirk_netmos(struct pci_dev *dev) 1937 { 1938 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1939 unsigned int num_serial = dev->subsystem_device & 0xf; 1940 1941 /* 1942 * These Netmos parts are multiport serial devices with optional 1943 * parallel ports. Even when parallel ports are present, they 1944 * are identified as class SERIAL, which means the serial driver 1945 * will claim them. To prevent this, mark them as class OTHER. 1946 * These combo devices should be claimed by parport_serial. 1947 * 1948 * The subdevice ID is of the form 0x00PS, where <P> is the number 1949 * of parallel ports and <S> is the number of serial ports. 1950 */ 1951 switch (dev->device) { 1952 case PCI_DEVICE_ID_NETMOS_9835: 1953 /* Well, this rule doesn't hold for the following 9835 device */ 1954 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1955 dev->subsystem_device == 0x0299) 1956 return; 1957 case PCI_DEVICE_ID_NETMOS_9735: 1958 case PCI_DEVICE_ID_NETMOS_9745: 1959 case PCI_DEVICE_ID_NETMOS_9845: 1960 case PCI_DEVICE_ID_NETMOS_9855: 1961 if (num_parallel) { 1962 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1963 dev->device, num_parallel, num_serial); 1964 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1965 (dev->class & 0xff); 1966 } 1967 } 1968 } 1969 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1970 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1971 1972 /* 1973 * Quirk non-zero PCI functions to route VPD access through function 0 for 1974 * devices that share VPD resources between functions. The functions are 1975 * expected to be identical devices. 1976 */ 1977 static void quirk_f0_vpd_link(struct pci_dev *dev) 1978 { 1979 struct pci_dev *f0; 1980 1981 if (!PCI_FUNC(dev->devfn)) 1982 return; 1983 1984 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 1985 if (!f0) 1986 return; 1987 1988 if (f0->vpd && dev->class == f0->class && 1989 dev->vendor == f0->vendor && dev->device == f0->device) 1990 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; 1991 1992 pci_dev_put(f0); 1993 } 1994 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1995 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link); 1996 1997 static void quirk_e100_interrupt(struct pci_dev *dev) 1998 { 1999 u16 command, pmcsr; 2000 u8 __iomem *csr; 2001 u8 cmd_hi; 2002 2003 switch (dev->device) { 2004 /* PCI IDs taken from drivers/net/e100.c */ 2005 case 0x1029: 2006 case 0x1030 ... 0x1034: 2007 case 0x1038 ... 0x103E: 2008 case 0x1050 ... 0x1057: 2009 case 0x1059: 2010 case 0x1064 ... 0x106B: 2011 case 0x1091 ... 0x1095: 2012 case 0x1209: 2013 case 0x1229: 2014 case 0x2449: 2015 case 0x2459: 2016 case 0x245D: 2017 case 0x27DC: 2018 break; 2019 default: 2020 return; 2021 } 2022 2023 /* 2024 * Some firmware hands off the e100 with interrupts enabled, 2025 * which can cause a flood of interrupts if packets are 2026 * received before the driver attaches to the device. So 2027 * disable all e100 interrupts here. The driver will 2028 * re-enable them when it's ready. 2029 */ 2030 pci_read_config_word(dev, PCI_COMMAND, &command); 2031 2032 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2033 return; 2034 2035 /* 2036 * Check that the device is in the D0 power state. If it's not, 2037 * there is no point to look any further. 2038 */ 2039 if (dev->pm_cap) { 2040 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2041 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2042 return; 2043 } 2044 2045 /* Convert from PCI bus to resource space. */ 2046 csr = ioremap(pci_resource_start(dev, 0), 8); 2047 if (!csr) { 2048 dev_warn(&dev->dev, "Can't map e100 registers\n"); 2049 return; 2050 } 2051 2052 cmd_hi = readb(csr + 3); 2053 if (cmd_hi == 0) { 2054 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 2055 writeb(1, csr + 3); 2056 } 2057 2058 iounmap(csr); 2059 } 2060 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2061 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2062 2063 /* 2064 * The 82575 and 82598 may experience data corruption issues when transitioning 2065 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2066 */ 2067 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2068 { 2069 dev_info(&dev->dev, "Disabling L0s\n"); 2070 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2071 } 2072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2086 2087 static void fixup_rev1_53c810(struct pci_dev *dev) 2088 { 2089 u32 class = dev->class; 2090 2091 /* 2092 * rev 1 ncr53c810 chips don't set the class at all which means 2093 * they don't get their resources remapped. Fix that here. 2094 */ 2095 if (class) 2096 return; 2097 2098 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2099 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2100 class, dev->class); 2101 } 2102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2103 2104 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2105 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2106 { 2107 u16 en1k; 2108 2109 pci_read_config_word(dev, 0x40, &en1k); 2110 2111 if (en1k & 0x200) { 2112 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2113 dev->io_window_1k = 1; 2114 } 2115 } 2116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2117 2118 /* Under some circumstances, AER is not linked with extended capabilities. 2119 * Force it to be linked by setting the corresponding control bit in the 2120 * config space. 2121 */ 2122 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2123 { 2124 uint8_t b; 2125 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2126 if (!(b & 0x20)) { 2127 pci_write_config_byte(dev, 0xf41, b | 0x20); 2128 dev_info(&dev->dev, "Linking AER extended capability\n"); 2129 } 2130 } 2131 } 2132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2133 quirk_nvidia_ck804_pcie_aer_ext_cap); 2134 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2135 quirk_nvidia_ck804_pcie_aer_ext_cap); 2136 2137 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2138 { 2139 /* 2140 * Disable PCI Bus Parking and PCI Master read caching on CX700 2141 * which causes unspecified timing errors with a VT6212L on the PCI 2142 * bus leading to USB2.0 packet loss. 2143 * 2144 * This quirk is only enabled if a second (on the external PCI bus) 2145 * VT6212L is found -- the CX700 core itself also contains a USB 2146 * host controller with the same PCI ID as the VT6212L. 2147 */ 2148 2149 /* Count VT6212L instances */ 2150 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2151 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2152 uint8_t b; 2153 2154 /* p should contain the first (internal) VT6212L -- see if we have 2155 an external one by searching again */ 2156 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2157 if (!p) 2158 return; 2159 pci_dev_put(p); 2160 2161 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2162 if (b & 0x40) { 2163 /* Turn off PCI Bus Parking */ 2164 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2165 2166 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2167 } 2168 } 2169 2170 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2171 if (b != 0) { 2172 /* Turn off PCI Master read caching */ 2173 pci_write_config_byte(dev, 0x72, 0x0); 2174 2175 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2176 pci_write_config_byte(dev, 0x75, 0x1); 2177 2178 /* Disable "Read FIFO Timer" */ 2179 pci_write_config_byte(dev, 0x77, 0x0); 2180 2181 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2182 } 2183 } 2184 } 2185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2186 2187 /* 2188 * If a device follows the VPD format spec, the PCI core will not read or 2189 * write past the VPD End Tag. But some vendors do not follow the VPD 2190 * format spec, so we can't tell how much data is safe to access. Devices 2191 * may behave unpredictably if we access too much. Blacklist these devices 2192 * so we don't touch VPD at all. 2193 */ 2194 static void quirk_blacklist_vpd(struct pci_dev *dev) 2195 { 2196 if (dev->vpd) { 2197 dev->vpd->len = 0; 2198 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); 2199 } 2200 } 2201 2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd); 2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd); 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd); 2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd); 2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd); 2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd); 2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd); 2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd); 2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd); 2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd); 2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd); 2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, 2214 quirk_blacklist_vpd); 2215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd); 2216 2217 /* 2218 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2219 * VPD end tag will hang the device. This problem was initially 2220 * observed when a vpd entry was created in sysfs 2221 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2222 * will dump 32k of data. Reading a full 32k will cause an access 2223 * beyond the VPD end tag causing the device to hang. Once the device 2224 * is hung, the bnx2 driver will not be able to reset the device. 2225 * We believe that it is legal to read beyond the end tag and 2226 * therefore the solution is to limit the read/write length. 2227 */ 2228 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2229 { 2230 /* 2231 * Only disable the VPD capability for 5706, 5706S, 5708, 2232 * 5708S and 5709 rev. A 2233 */ 2234 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2235 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2236 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2237 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2238 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2239 (dev->revision & 0xf0) == 0x0)) { 2240 if (dev->vpd) 2241 dev->vpd->len = 0x80; 2242 } 2243 } 2244 2245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2246 PCI_DEVICE_ID_NX2_5706, 2247 quirk_brcm_570x_limit_vpd); 2248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2249 PCI_DEVICE_ID_NX2_5706S, 2250 quirk_brcm_570x_limit_vpd); 2251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2252 PCI_DEVICE_ID_NX2_5708, 2253 quirk_brcm_570x_limit_vpd); 2254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2255 PCI_DEVICE_ID_NX2_5708S, 2256 quirk_brcm_570x_limit_vpd); 2257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2258 PCI_DEVICE_ID_NX2_5709, 2259 quirk_brcm_570x_limit_vpd); 2260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2261 PCI_DEVICE_ID_NX2_5709S, 2262 quirk_brcm_570x_limit_vpd); 2263 2264 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2265 { 2266 u32 rev; 2267 2268 pci_read_config_dword(dev, 0xf4, &rev); 2269 2270 /* Only CAP the MRRS if the device is a 5719 A0 */ 2271 if (rev == 0x05719000) { 2272 int readrq = pcie_get_readrq(dev); 2273 if (readrq > 2048) 2274 pcie_set_readrq(dev, 2048); 2275 } 2276 } 2277 2278 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2279 PCI_DEVICE_ID_TIGON3_5719, 2280 quirk_brcm_5719_limit_mrrs); 2281 2282 #ifdef CONFIG_PCIE_IPROC_PLATFORM 2283 static void quirk_paxc_bridge(struct pci_dev *pdev) 2284 { 2285 /* The PCI config space is shared with the PAXC root port and the first 2286 * Ethernet device. So, we need to workaround this by telling the PCI 2287 * code that the bridge is not an Ethernet device. 2288 */ 2289 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2290 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2291 2292 /* MPSS is not being set properly (as it is currently 0). This is 2293 * because that area of the PCI config space is hard coded to zero, and 2294 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2295 * so that the MPS can be set to the real max value. 2296 */ 2297 pdev->pcie_mpss = 2; 2298 } 2299 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); 2300 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2301 #endif 2302 2303 /* Originally in EDAC sources for i82875P: 2304 * Intel tells BIOS developers to hide device 6 which 2305 * configures the overflow device access containing 2306 * the DRBs - this is where we expose device 6. 2307 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2308 */ 2309 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2310 { 2311 u8 reg; 2312 2313 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2314 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2315 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2316 } 2317 } 2318 2319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2320 quirk_unhide_mch_dev6); 2321 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2322 quirk_unhide_mch_dev6); 2323 2324 #ifdef CONFIG_TILEPRO 2325 /* 2326 * The Tilera TILEmpower tilepro platform needs to set the link speed 2327 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2328 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2329 * capability register of the PEX8624 PCIe switch. The switch 2330 * supports link speed auto negotiation, but falsely sets 2331 * the link speed to 5GT/s. 2332 */ 2333 static void quirk_tile_plx_gen1(struct pci_dev *dev) 2334 { 2335 if (tile_plx_gen1) { 2336 pci_write_config_dword(dev, 0x98, 0x1); 2337 mdelay(50); 2338 } 2339 } 2340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2341 #endif /* CONFIG_TILEPRO */ 2342 2343 #ifdef CONFIG_PCI_MSI 2344 /* Some chipsets do not support MSI. We cannot easily rely on setting 2345 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2346 * some other buses controlled by the chipset even if Linux is not 2347 * aware of it. Instead of setting the flag on all buses in the 2348 * machine, simply disable MSI globally. 2349 */ 2350 static void quirk_disable_all_msi(struct pci_dev *dev) 2351 { 2352 pci_no_msi(); 2353 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2354 } 2355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2363 2364 /* Disable MSI on chipsets that are known to not support it */ 2365 static void quirk_disable_msi(struct pci_dev *dev) 2366 { 2367 if (dev->subordinate) { 2368 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2369 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2370 } 2371 } 2372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2375 2376 /* 2377 * The APC bridge device in AMD 780 family northbridges has some random 2378 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2379 * we use the possible vendor/device IDs of the host bridge for the 2380 * declared quirk, and search for the APC bridge by slot number. 2381 */ 2382 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2383 { 2384 struct pci_dev *apc_bridge; 2385 2386 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2387 if (apc_bridge) { 2388 if (apc_bridge->device == 0x9602) 2389 quirk_disable_msi(apc_bridge); 2390 pci_dev_put(apc_bridge); 2391 } 2392 } 2393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2395 2396 /* Go through the list of Hypertransport capabilities and 2397 * return 1 if a HT MSI capability is found and enabled */ 2398 static int msi_ht_cap_enabled(struct pci_dev *dev) 2399 { 2400 int pos, ttl = PCI_FIND_CAP_TTL; 2401 2402 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2403 while (pos && ttl--) { 2404 u8 flags; 2405 2406 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2407 &flags) == 0) { 2408 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2409 flags & HT_MSI_FLAGS_ENABLE ? 2410 "enabled" : "disabled"); 2411 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2412 } 2413 2414 pos = pci_find_next_ht_capability(dev, pos, 2415 HT_CAPTYPE_MSI_MAPPING); 2416 } 2417 return 0; 2418 } 2419 2420 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2421 static void quirk_msi_ht_cap(struct pci_dev *dev) 2422 { 2423 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2424 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2425 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2426 } 2427 } 2428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2429 quirk_msi_ht_cap); 2430 2431 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2432 * MSI are supported if the MSI capability set in any of these mappings. 2433 */ 2434 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2435 { 2436 struct pci_dev *pdev; 2437 2438 if (!dev->subordinate) 2439 return; 2440 2441 /* check HT MSI cap on this chipset and the root one. 2442 * a single one having MSI is enough to be sure that MSI are supported. 2443 */ 2444 pdev = pci_get_slot(dev->bus, 0); 2445 if (!pdev) 2446 return; 2447 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2448 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2449 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2450 } 2451 pci_dev_put(pdev); 2452 } 2453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2454 quirk_nvidia_ck804_msi_ht_cap); 2455 2456 /* Force enable MSI mapping capability on HT bridges */ 2457 static void ht_enable_msi_mapping(struct pci_dev *dev) 2458 { 2459 int pos, ttl = PCI_FIND_CAP_TTL; 2460 2461 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2462 while (pos && ttl--) { 2463 u8 flags; 2464 2465 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2466 &flags) == 0) { 2467 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2468 2469 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2470 flags | HT_MSI_FLAGS_ENABLE); 2471 } 2472 pos = pci_find_next_ht_capability(dev, pos, 2473 HT_CAPTYPE_MSI_MAPPING); 2474 } 2475 } 2476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2477 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2478 ht_enable_msi_mapping); 2479 2480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2481 ht_enable_msi_mapping); 2482 2483 /* The P5N32-SLI motherboards from Asus have a problem with msi 2484 * for the MCP55 NIC. It is not yet determined whether the msi problem 2485 * also affects other devices. As for now, turn off msi for this device. 2486 */ 2487 static void nvenet_msi_disable(struct pci_dev *dev) 2488 { 2489 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2490 2491 if (board_name && 2492 (strstr(board_name, "P5N32-SLI PREMIUM") || 2493 strstr(board_name, "P5N32-E SLI"))) { 2494 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2495 dev->no_msi = 1; 2496 } 2497 } 2498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2499 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2500 nvenet_msi_disable); 2501 2502 /* 2503 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2504 * config register. This register controls the routing of legacy 2505 * interrupts from devices that route through the MCP55. If this register 2506 * is misprogrammed, interrupts are only sent to the BSP, unlike 2507 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2508 * having this register set properly prevents kdump from booting up 2509 * properly, so let's make sure that we have it set correctly. 2510 * Note that this is an undocumented register. 2511 */ 2512 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2513 { 2514 u32 cfg; 2515 2516 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2517 return; 2518 2519 pci_read_config_dword(dev, 0x74, &cfg); 2520 2521 if (cfg & ((1 << 2) | (1 << 15))) { 2522 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2523 cfg &= ~((1 << 2) | (1 << 15)); 2524 pci_write_config_dword(dev, 0x74, cfg); 2525 } 2526 } 2527 2528 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2529 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2530 nvbridge_check_legacy_irq_routing); 2531 2532 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2533 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2534 nvbridge_check_legacy_irq_routing); 2535 2536 static int ht_check_msi_mapping(struct pci_dev *dev) 2537 { 2538 int pos, ttl = PCI_FIND_CAP_TTL; 2539 int found = 0; 2540 2541 /* check if there is HT MSI cap or enabled on this device */ 2542 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2543 while (pos && ttl--) { 2544 u8 flags; 2545 2546 if (found < 1) 2547 found = 1; 2548 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2549 &flags) == 0) { 2550 if (flags & HT_MSI_FLAGS_ENABLE) { 2551 if (found < 2) { 2552 found = 2; 2553 break; 2554 } 2555 } 2556 } 2557 pos = pci_find_next_ht_capability(dev, pos, 2558 HT_CAPTYPE_MSI_MAPPING); 2559 } 2560 2561 return found; 2562 } 2563 2564 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2565 { 2566 struct pci_dev *dev; 2567 int pos; 2568 int i, dev_no; 2569 int found = 0; 2570 2571 dev_no = host_bridge->devfn >> 3; 2572 for (i = dev_no + 1; i < 0x20; i++) { 2573 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2574 if (!dev) 2575 continue; 2576 2577 /* found next host bridge ?*/ 2578 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2579 if (pos != 0) { 2580 pci_dev_put(dev); 2581 break; 2582 } 2583 2584 if (ht_check_msi_mapping(dev)) { 2585 found = 1; 2586 pci_dev_put(dev); 2587 break; 2588 } 2589 pci_dev_put(dev); 2590 } 2591 2592 return found; 2593 } 2594 2595 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2596 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2597 2598 static int is_end_of_ht_chain(struct pci_dev *dev) 2599 { 2600 int pos, ctrl_off; 2601 int end = 0; 2602 u16 flags, ctrl; 2603 2604 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2605 2606 if (!pos) 2607 goto out; 2608 2609 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2610 2611 ctrl_off = ((flags >> 10) & 1) ? 2612 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2613 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2614 2615 if (ctrl & (1 << 6)) 2616 end = 1; 2617 2618 out: 2619 return end; 2620 } 2621 2622 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2623 { 2624 struct pci_dev *host_bridge; 2625 int pos; 2626 int i, dev_no; 2627 int found = 0; 2628 2629 dev_no = dev->devfn >> 3; 2630 for (i = dev_no; i >= 0; i--) { 2631 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2632 if (!host_bridge) 2633 continue; 2634 2635 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2636 if (pos != 0) { 2637 found = 1; 2638 break; 2639 } 2640 pci_dev_put(host_bridge); 2641 } 2642 2643 if (!found) 2644 return; 2645 2646 /* don't enable end_device/host_bridge with leaf directly here */ 2647 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2648 host_bridge_with_leaf(host_bridge)) 2649 goto out; 2650 2651 /* root did that ! */ 2652 if (msi_ht_cap_enabled(host_bridge)) 2653 goto out; 2654 2655 ht_enable_msi_mapping(dev); 2656 2657 out: 2658 pci_dev_put(host_bridge); 2659 } 2660 2661 static void ht_disable_msi_mapping(struct pci_dev *dev) 2662 { 2663 int pos, ttl = PCI_FIND_CAP_TTL; 2664 2665 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2666 while (pos && ttl--) { 2667 u8 flags; 2668 2669 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2670 &flags) == 0) { 2671 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2672 2673 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2674 flags & ~HT_MSI_FLAGS_ENABLE); 2675 } 2676 pos = pci_find_next_ht_capability(dev, pos, 2677 HT_CAPTYPE_MSI_MAPPING); 2678 } 2679 } 2680 2681 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2682 { 2683 struct pci_dev *host_bridge; 2684 int pos; 2685 int found; 2686 2687 if (!pci_msi_enabled()) 2688 return; 2689 2690 /* check if there is HT MSI cap or enabled on this device */ 2691 found = ht_check_msi_mapping(dev); 2692 2693 /* no HT MSI CAP */ 2694 if (found == 0) 2695 return; 2696 2697 /* 2698 * HT MSI mapping should be disabled on devices that are below 2699 * a non-Hypertransport host bridge. Locate the host bridge... 2700 */ 2701 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2702 if (host_bridge == NULL) { 2703 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2704 return; 2705 } 2706 2707 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2708 if (pos != 0) { 2709 /* Host bridge is to HT */ 2710 if (found == 1) { 2711 /* it is not enabled, try to enable it */ 2712 if (all) 2713 ht_enable_msi_mapping(dev); 2714 else 2715 nv_ht_enable_msi_mapping(dev); 2716 } 2717 goto out; 2718 } 2719 2720 /* HT MSI is not enabled */ 2721 if (found == 1) 2722 goto out; 2723 2724 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2725 ht_disable_msi_mapping(dev); 2726 2727 out: 2728 pci_dev_put(host_bridge); 2729 } 2730 2731 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2732 { 2733 return __nv_msi_ht_cap_quirk(dev, 1); 2734 } 2735 2736 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2737 { 2738 return __nv_msi_ht_cap_quirk(dev, 0); 2739 } 2740 2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2742 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2743 2744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2745 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2746 2747 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2748 { 2749 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2750 } 2751 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2752 { 2753 struct pci_dev *p; 2754 2755 /* SB700 MSI issue will be fixed at HW level from revision A21, 2756 * we need check PCI REVISION ID of SMBus controller to get SB700 2757 * revision. 2758 */ 2759 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2760 NULL); 2761 if (!p) 2762 return; 2763 2764 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2765 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2766 pci_dev_put(p); 2767 } 2768 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2769 { 2770 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2771 if (dev->revision < 0x18) { 2772 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2773 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2774 } 2775 } 2776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2777 PCI_DEVICE_ID_TIGON3_5780, 2778 quirk_msi_intx_disable_bug); 2779 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2780 PCI_DEVICE_ID_TIGON3_5780S, 2781 quirk_msi_intx_disable_bug); 2782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2783 PCI_DEVICE_ID_TIGON3_5714, 2784 quirk_msi_intx_disable_bug); 2785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2786 PCI_DEVICE_ID_TIGON3_5714S, 2787 quirk_msi_intx_disable_bug); 2788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2789 PCI_DEVICE_ID_TIGON3_5715, 2790 quirk_msi_intx_disable_bug); 2791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2792 PCI_DEVICE_ID_TIGON3_5715S, 2793 quirk_msi_intx_disable_bug); 2794 2795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2796 quirk_msi_intx_disable_ati_bug); 2797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2798 quirk_msi_intx_disable_ati_bug); 2799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2800 quirk_msi_intx_disable_ati_bug); 2801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2802 quirk_msi_intx_disable_ati_bug); 2803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2804 quirk_msi_intx_disable_ati_bug); 2805 2806 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2807 quirk_msi_intx_disable_bug); 2808 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2809 quirk_msi_intx_disable_bug); 2810 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2811 quirk_msi_intx_disable_bug); 2812 2813 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2814 quirk_msi_intx_disable_bug); 2815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2816 quirk_msi_intx_disable_bug); 2817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2818 quirk_msi_intx_disable_bug); 2819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2820 quirk_msi_intx_disable_bug); 2821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2822 quirk_msi_intx_disable_bug); 2823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2824 quirk_msi_intx_disable_bug); 2825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2826 quirk_msi_intx_disable_qca_bug); 2827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2828 quirk_msi_intx_disable_qca_bug); 2829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2830 quirk_msi_intx_disable_qca_bug); 2831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2832 quirk_msi_intx_disable_qca_bug); 2833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2834 quirk_msi_intx_disable_qca_bug); 2835 #endif /* CONFIG_PCI_MSI */ 2836 2837 /* Allow manual resource allocation for PCI hotplug bridges 2838 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2839 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2840 * kernel fails to allocate resources when hotplug device is 2841 * inserted and PCI bus is rescanned. 2842 */ 2843 static void quirk_hotplug_bridge(struct pci_dev *dev) 2844 { 2845 dev->is_hotplug_bridge = 1; 2846 } 2847 2848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2849 2850 /* 2851 * This is a quirk for the Ricoh MMC controller found as a part of 2852 * some mulifunction chips. 2853 2854 * This is very similar and based on the ricoh_mmc driver written by 2855 * Philip Langdale. Thank you for these magic sequences. 2856 * 2857 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2858 * and one or both of cardbus or firewire. 2859 * 2860 * It happens that they implement SD and MMC 2861 * support as separate controllers (and PCI functions). The linux SDHCI 2862 * driver supports MMC cards but the chip detects MMC cards in hardware 2863 * and directs them to the MMC controller - so the SDHCI driver never sees 2864 * them. 2865 * 2866 * To get around this, we must disable the useless MMC controller. 2867 * At that point, the SDHCI controller will start seeing them 2868 * It seems to be the case that the relevant PCI registers to deactivate the 2869 * MMC controller live on PCI function 0, which might be the cardbus controller 2870 * or the firewire controller, depending on the particular chip in question 2871 * 2872 * This has to be done early, because as soon as we disable the MMC controller 2873 * other pci functions shift up one level, e.g. function #2 becomes function 2874 * #1, and this will confuse the pci core. 2875 */ 2876 2877 #ifdef CONFIG_MMC_RICOH_MMC 2878 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2879 { 2880 /* disable via cardbus interface */ 2881 u8 write_enable; 2882 u8 write_target; 2883 u8 disable; 2884 2885 /* disable must be done via function #0 */ 2886 if (PCI_FUNC(dev->devfn)) 2887 return; 2888 2889 pci_read_config_byte(dev, 0xB7, &disable); 2890 if (disable & 0x02) 2891 return; 2892 2893 pci_read_config_byte(dev, 0x8E, &write_enable); 2894 pci_write_config_byte(dev, 0x8E, 0xAA); 2895 pci_read_config_byte(dev, 0x8D, &write_target); 2896 pci_write_config_byte(dev, 0x8D, 0xB7); 2897 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2898 pci_write_config_byte(dev, 0x8E, write_enable); 2899 pci_write_config_byte(dev, 0x8D, write_target); 2900 2901 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2902 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2903 } 2904 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2905 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2906 2907 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2908 { 2909 /* disable via firewire interface */ 2910 u8 write_enable; 2911 u8 disable; 2912 2913 /* disable must be done via function #0 */ 2914 if (PCI_FUNC(dev->devfn)) 2915 return; 2916 /* 2917 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2918 * certain types of SD/MMC cards. Lowering the SD base 2919 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2920 * 2921 * 0x150 - SD2.0 mode enable for changing base clock 2922 * frequency to 50Mhz 2923 * 0xe1 - Base clock frequency 2924 * 0x32 - 50Mhz new clock frequency 2925 * 0xf9 - Key register for 0x150 2926 * 0xfc - key register for 0xe1 2927 */ 2928 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2929 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2930 pci_write_config_byte(dev, 0xf9, 0xfc); 2931 pci_write_config_byte(dev, 0x150, 0x10); 2932 pci_write_config_byte(dev, 0xf9, 0x00); 2933 pci_write_config_byte(dev, 0xfc, 0x01); 2934 pci_write_config_byte(dev, 0xe1, 0x32); 2935 pci_write_config_byte(dev, 0xfc, 0x00); 2936 2937 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2938 } 2939 2940 pci_read_config_byte(dev, 0xCB, &disable); 2941 2942 if (disable & 0x02) 2943 return; 2944 2945 pci_read_config_byte(dev, 0xCA, &write_enable); 2946 pci_write_config_byte(dev, 0xCA, 0x57); 2947 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2948 pci_write_config_byte(dev, 0xCA, write_enable); 2949 2950 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2951 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2952 2953 } 2954 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2955 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2956 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2957 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2958 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2959 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2960 #endif /*CONFIG_MMC_RICOH_MMC*/ 2961 2962 #ifdef CONFIG_DMAR_TABLE 2963 #define VTUNCERRMSK_REG 0x1ac 2964 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2965 /* 2966 * This is a quirk for masking vt-d spec defined errors to platform error 2967 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2968 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2969 * on the RAS config settings of the platform) when a vt-d fault happens. 2970 * The resulting SMI caused the system to hang. 2971 * 2972 * VT-d spec related errors are already handled by the VT-d OS code, so no 2973 * need to report the same error through other channels. 2974 */ 2975 static void vtd_mask_spec_errors(struct pci_dev *dev) 2976 { 2977 u32 word; 2978 2979 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2980 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2981 } 2982 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2983 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2984 #endif 2985 2986 static void fixup_ti816x_class(struct pci_dev *dev) 2987 { 2988 u32 class = dev->class; 2989 2990 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2991 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 2992 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", 2993 class, dev->class); 2994 } 2995 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2996 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 2997 2998 /* Some PCIe devices do not work reliably with the claimed maximum 2999 * payload size supported. 3000 */ 3001 static void fixup_mpss_256(struct pci_dev *dev) 3002 { 3003 dev->pcie_mpss = 1; /* 256 bytes */ 3004 } 3005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3006 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3008 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3010 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3011 3012 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 3013 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3014 * Since there is no way of knowing what the PCIE MPS on each fabric will be 3015 * until all of the devices are discovered and buses walked, read completion 3016 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3017 * it is possible to hotplug a device with MPS of 256B. 3018 */ 3019 static void quirk_intel_mc_errata(struct pci_dev *dev) 3020 { 3021 int err; 3022 u16 rcc; 3023 3024 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3025 pcie_bus_config == PCIE_BUS_DEFAULT) 3026 return; 3027 3028 /* Intel errata specifies bits to change but does not say what they are. 3029 * Keeping them magical until such time as the registers and values can 3030 * be explained. 3031 */ 3032 err = pci_read_config_word(dev, 0x48, &rcc); 3033 if (err) { 3034 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 3035 return; 3036 } 3037 3038 if (!(rcc & (1 << 10))) 3039 return; 3040 3041 rcc &= ~(1 << 10); 3042 3043 err = pci_write_config_word(dev, 0x48, rcc); 3044 if (err) { 3045 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 3046 return; 3047 } 3048 3049 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 3050 } 3051 /* Intel 5000 series memory controllers and ports 2-7 */ 3052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3066 /* Intel 5100 series memory controllers and ports 2-7 */ 3067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3078 3079 3080 /* 3081 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 3082 * work around this, query the size it should be configured to by the device and 3083 * modify the resource end to correspond to this new size. 3084 */ 3085 static void quirk_intel_ntb(struct pci_dev *dev) 3086 { 3087 int rc; 3088 u8 val; 3089 3090 rc = pci_read_config_byte(dev, 0x00D0, &val); 3091 if (rc) 3092 return; 3093 3094 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3095 3096 rc = pci_read_config_byte(dev, 0x00D1, &val); 3097 if (rc) 3098 return; 3099 3100 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3101 } 3102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3104 3105 static ktime_t fixup_debug_start(struct pci_dev *dev, 3106 void (*fn)(struct pci_dev *dev)) 3107 { 3108 ktime_t calltime = 0; 3109 3110 dev_dbg(&dev->dev, "calling %pF\n", fn); 3111 if (initcall_debug) { 3112 pr_debug("calling %pF @ %i for %s\n", 3113 fn, task_pid_nr(current), dev_name(&dev->dev)); 3114 calltime = ktime_get(); 3115 } 3116 3117 return calltime; 3118 } 3119 3120 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 3121 void (*fn)(struct pci_dev *dev)) 3122 { 3123 ktime_t delta, rettime; 3124 unsigned long long duration; 3125 3126 if (initcall_debug) { 3127 rettime = ktime_get(); 3128 delta = ktime_sub(rettime, calltime); 3129 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 3130 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 3131 fn, duration, dev_name(&dev->dev)); 3132 } 3133 } 3134 3135 /* 3136 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3137 * even though no one is handling them (f.e. i915 driver is never loaded). 3138 * Additionally the interrupt destination is not set up properly 3139 * and the interrupt ends up -somewhere-. 3140 * 3141 * These spurious interrupts are "sticky" and the kernel disables 3142 * the (shared) interrupt line after 100.000+ generated interrupts. 3143 * 3144 * Fix it by disabling the still enabled interrupts. 3145 * This resolves crashes often seen on monitor unplug. 3146 */ 3147 #define I915_DEIER_REG 0x4400c 3148 static void disable_igfx_irq(struct pci_dev *dev) 3149 { 3150 void __iomem *regs = pci_iomap(dev, 0, 0); 3151 if (regs == NULL) { 3152 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 3153 return; 3154 } 3155 3156 /* Check if any interrupt line is still enabled */ 3157 if (readl(regs + I915_DEIER_REG) != 0) { 3158 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3159 3160 writel(0, regs + I915_DEIER_REG); 3161 } 3162 3163 pci_iounmap(dev, regs); 3164 } 3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3168 3169 /* 3170 * PCI devices which are on Intel chips can skip the 10ms delay 3171 * before entering D3 mode. 3172 */ 3173 static void quirk_remove_d3_delay(struct pci_dev *dev) 3174 { 3175 dev->d3_delay = 0; 3176 } 3177 /* C600 Series devices do not need 10ms d3_delay */ 3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3181 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3193 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3203 3204 /* 3205 * Some devices may pass our check in pci_intx_mask_supported() if 3206 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3207 * support this feature. 3208 */ 3209 static void quirk_broken_intx_masking(struct pci_dev *dev) 3210 { 3211 dev->broken_intx_masking = 1; 3212 } 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3214 quirk_broken_intx_masking); 3215 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3216 quirk_broken_intx_masking); 3217 3218 /* 3219 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3220 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3221 * 3222 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3223 */ 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3225 quirk_broken_intx_masking); 3226 3227 /* 3228 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3229 * DisINTx can be set but the interrupt status bit is non-functional. 3230 */ 3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, 3232 quirk_broken_intx_masking); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, 3234 quirk_broken_intx_masking); 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, 3236 quirk_broken_intx_masking); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, 3238 quirk_broken_intx_masking); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, 3240 quirk_broken_intx_masking); 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, 3242 quirk_broken_intx_masking); 3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, 3244 quirk_broken_intx_masking); 3245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, 3246 quirk_broken_intx_masking); 3247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, 3248 quirk_broken_intx_masking); 3249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, 3250 quirk_broken_intx_masking); 3251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, 3252 quirk_broken_intx_masking); 3253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, 3254 quirk_broken_intx_masking); 3255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, 3256 quirk_broken_intx_masking); 3257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, 3258 quirk_broken_intx_masking); 3259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, 3260 quirk_broken_intx_masking); 3261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, 3262 quirk_broken_intx_masking); 3263 3264 static u16 mellanox_broken_intx_devs[] = { 3265 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3266 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3267 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3268 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3269 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3270 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3271 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3272 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3273 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3274 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3275 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3276 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3277 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3278 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3279 }; 3280 3281 #define CONNECTX_4_CURR_MAX_MINOR 99 3282 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3283 3284 /* 3285 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3286 * If so, don't mark it as broken. 3287 * FW minor > 99 means older FW version format and no INTx masking support. 3288 * FW minor < 14 means new FW version format and no INTx masking support. 3289 */ 3290 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3291 { 3292 __be32 __iomem *fw_ver; 3293 u16 fw_major; 3294 u16 fw_minor; 3295 u16 fw_subminor; 3296 u32 fw_maj_min; 3297 u32 fw_sub_min; 3298 int i; 3299 3300 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3301 if (pdev->device == mellanox_broken_intx_devs[i]) { 3302 pdev->broken_intx_masking = 1; 3303 return; 3304 } 3305 } 3306 3307 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx 3308 * support so shouldn't be checked further 3309 */ 3310 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3311 return; 3312 3313 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3314 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3315 return; 3316 3317 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3318 if (pci_enable_device_mem(pdev)) { 3319 dev_warn(&pdev->dev, "Can't enable device memory\n"); 3320 return; 3321 } 3322 3323 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3324 if (!fw_ver) { 3325 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n"); 3326 goto out; 3327 } 3328 3329 /* Reading from resource space should be 32b aligned */ 3330 fw_maj_min = ioread32be(fw_ver); 3331 fw_sub_min = ioread32be(fw_ver + 1); 3332 fw_major = fw_maj_min & 0xffff; 3333 fw_minor = fw_maj_min >> 16; 3334 fw_subminor = fw_sub_min & 0xffff; 3335 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3336 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3337 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3338 fw_major, fw_minor, fw_subminor, pdev->device == 3339 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3340 pdev->broken_intx_masking = 1; 3341 } 3342 3343 iounmap(fw_ver); 3344 3345 out: 3346 pci_disable_device(pdev); 3347 } 3348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3349 mellanox_check_broken_intx_masking); 3350 3351 static void quirk_no_bus_reset(struct pci_dev *dev) 3352 { 3353 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3354 } 3355 3356 /* 3357 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3358 * The device will throw a Link Down error on AER-capable systems and 3359 * regardless of AER, config space of the device is never accessible again 3360 * and typically causes the system to hang or reset when access is attempted. 3361 * http://www.spinics.net/lists/linux-pci/msg34797.html 3362 */ 3363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3367 3368 static void quirk_no_pm_reset(struct pci_dev *dev) 3369 { 3370 /* 3371 * We can't do a bus reset on root bus devices, but an ineffective 3372 * PM reset may be better than nothing. 3373 */ 3374 if (!pci_is_root_bus(dev->bus)) 3375 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3376 } 3377 3378 /* 3379 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3380 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3381 * to have no effect on the device: it retains the framebuffer contents and 3382 * monitor sync. Advertising this support makes other layers, like VFIO, 3383 * assume pci_reset_function() is viable for this device. Mark it as 3384 * unavailable to skip it when testing reset methods. 3385 */ 3386 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3387 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3388 3389 /* 3390 * Thunderbolt controllers with broken MSI hotplug signaling: 3391 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3392 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3393 */ 3394 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3395 { 3396 if (pdev->is_hotplug_bridge && 3397 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3398 pdev->revision <= 1)) 3399 pdev->no_msi = 1; 3400 } 3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3402 quirk_thunderbolt_hotplug_msi); 3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3404 quirk_thunderbolt_hotplug_msi); 3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3406 quirk_thunderbolt_hotplug_msi); 3407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3408 quirk_thunderbolt_hotplug_msi); 3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3410 quirk_thunderbolt_hotplug_msi); 3411 3412 static void quirk_chelsio_extend_vpd(struct pci_dev *dev) 3413 { 3414 pci_set_vpd_size(dev, 8192); 3415 } 3416 3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd); 3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd); 3419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd); 3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd); 3421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd); 3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd); 3423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd); 3424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd); 3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd); 3426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd); 3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd); 3428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd); 3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd); 3430 3431 #ifdef CONFIG_ACPI 3432 /* 3433 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3434 * 3435 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3436 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3437 * be present after resume if a device was plugged in before suspend. 3438 * 3439 * The thunderbolt controller consists of a pcie switch with downstream 3440 * bridges leading to the NHI and to the tunnel pci bridges. 3441 * 3442 * This quirk cuts power to the whole chip. Therefore we have to apply it 3443 * during suspend_noirq of the upstream bridge. 3444 * 3445 * Power is automagically restored before resume. No action is needed. 3446 */ 3447 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3448 { 3449 acpi_handle bridge, SXIO, SXFP, SXLV; 3450 3451 if (!x86_apple_machine) 3452 return; 3453 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3454 return; 3455 bridge = ACPI_HANDLE(&dev->dev); 3456 if (!bridge) 3457 return; 3458 /* 3459 * SXIO and SXLV are present only on machines requiring this quirk. 3460 * TB bridges in external devices might have the same device id as those 3461 * on the host, but they will not have the associated ACPI methods. This 3462 * implicitly checks that we are at the right bridge. 3463 */ 3464 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3465 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3466 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3467 return; 3468 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3469 3470 /* magic sequence */ 3471 acpi_execute_simple_method(SXIO, NULL, 1); 3472 acpi_execute_simple_method(SXFP, NULL, 0); 3473 msleep(300); 3474 acpi_execute_simple_method(SXLV, NULL, 0); 3475 acpi_execute_simple_method(SXIO, NULL, 0); 3476 acpi_execute_simple_method(SXLV, NULL, 0); 3477 } 3478 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3479 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3480 quirk_apple_poweroff_thunderbolt); 3481 3482 /* 3483 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3484 * 3485 * During suspend the thunderbolt controller is reset and all pci 3486 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3487 * during resume. We have to manually wait for the NHI since there is 3488 * no parent child relationship between the NHI and the tunneled 3489 * bridges. 3490 */ 3491 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3492 { 3493 struct pci_dev *sibling = NULL; 3494 struct pci_dev *nhi = NULL; 3495 3496 if (!x86_apple_machine) 3497 return; 3498 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3499 return; 3500 /* 3501 * Find the NHI and confirm that we are a bridge on the tb host 3502 * controller and not on a tb endpoint. 3503 */ 3504 sibling = pci_get_slot(dev->bus, 0x0); 3505 if (sibling == dev) 3506 goto out; /* we are the downstream bridge to the NHI */ 3507 if (!sibling || !sibling->subordinate) 3508 goto out; 3509 nhi = pci_get_slot(sibling->subordinate, 0x0); 3510 if (!nhi) 3511 goto out; 3512 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3513 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && 3514 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && 3515 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && 3516 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3517 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3518 goto out; 3519 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3520 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3521 out: 3522 pci_dev_put(nhi); 3523 pci_dev_put(sibling); 3524 } 3525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3526 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3527 quirk_apple_wait_for_thunderbolt); 3528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3529 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3530 quirk_apple_wait_for_thunderbolt); 3531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3532 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, 3533 quirk_apple_wait_for_thunderbolt); 3534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3535 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, 3536 quirk_apple_wait_for_thunderbolt); 3537 #endif 3538 3539 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3540 struct pci_fixup *end) 3541 { 3542 ktime_t calltime; 3543 3544 for (; f < end; f++) 3545 if ((f->class == (u32) (dev->class >> f->class_shift) || 3546 f->class == (u32) PCI_ANY_ID) && 3547 (f->vendor == dev->vendor || 3548 f->vendor == (u16) PCI_ANY_ID) && 3549 (f->device == dev->device || 3550 f->device == (u16) PCI_ANY_ID)) { 3551 calltime = fixup_debug_start(dev, f->hook); 3552 f->hook(dev); 3553 fixup_debug_report(dev, calltime, f->hook); 3554 } 3555 } 3556 3557 extern struct pci_fixup __start_pci_fixups_early[]; 3558 extern struct pci_fixup __end_pci_fixups_early[]; 3559 extern struct pci_fixup __start_pci_fixups_header[]; 3560 extern struct pci_fixup __end_pci_fixups_header[]; 3561 extern struct pci_fixup __start_pci_fixups_final[]; 3562 extern struct pci_fixup __end_pci_fixups_final[]; 3563 extern struct pci_fixup __start_pci_fixups_enable[]; 3564 extern struct pci_fixup __end_pci_fixups_enable[]; 3565 extern struct pci_fixup __start_pci_fixups_resume[]; 3566 extern struct pci_fixup __end_pci_fixups_resume[]; 3567 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3568 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3569 extern struct pci_fixup __start_pci_fixups_suspend[]; 3570 extern struct pci_fixup __end_pci_fixups_suspend[]; 3571 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3572 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3573 3574 static bool pci_apply_fixup_final_quirks; 3575 3576 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3577 { 3578 struct pci_fixup *start, *end; 3579 3580 switch (pass) { 3581 case pci_fixup_early: 3582 start = __start_pci_fixups_early; 3583 end = __end_pci_fixups_early; 3584 break; 3585 3586 case pci_fixup_header: 3587 start = __start_pci_fixups_header; 3588 end = __end_pci_fixups_header; 3589 break; 3590 3591 case pci_fixup_final: 3592 if (!pci_apply_fixup_final_quirks) 3593 return; 3594 start = __start_pci_fixups_final; 3595 end = __end_pci_fixups_final; 3596 break; 3597 3598 case pci_fixup_enable: 3599 start = __start_pci_fixups_enable; 3600 end = __end_pci_fixups_enable; 3601 break; 3602 3603 case pci_fixup_resume: 3604 start = __start_pci_fixups_resume; 3605 end = __end_pci_fixups_resume; 3606 break; 3607 3608 case pci_fixup_resume_early: 3609 start = __start_pci_fixups_resume_early; 3610 end = __end_pci_fixups_resume_early; 3611 break; 3612 3613 case pci_fixup_suspend: 3614 start = __start_pci_fixups_suspend; 3615 end = __end_pci_fixups_suspend; 3616 break; 3617 3618 case pci_fixup_suspend_late: 3619 start = __start_pci_fixups_suspend_late; 3620 end = __end_pci_fixups_suspend_late; 3621 break; 3622 3623 default: 3624 /* stupid compiler warning, you would think with an enum... */ 3625 return; 3626 } 3627 pci_do_fixups(dev, start, end); 3628 } 3629 EXPORT_SYMBOL(pci_fixup_device); 3630 3631 3632 static int __init pci_apply_final_quirks(void) 3633 { 3634 struct pci_dev *dev = NULL; 3635 u8 cls = 0; 3636 u8 tmp; 3637 3638 if (pci_cache_line_size) 3639 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3640 pci_cache_line_size << 2); 3641 3642 pci_apply_fixup_final_quirks = true; 3643 for_each_pci_dev(dev) { 3644 pci_fixup_device(pci_fixup_final, dev); 3645 /* 3646 * If arch hasn't set it explicitly yet, use the CLS 3647 * value shared by all PCI devices. If there's a 3648 * mismatch, fall back to the default value. 3649 */ 3650 if (!pci_cache_line_size) { 3651 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3652 if (!cls) 3653 cls = tmp; 3654 if (!tmp || cls == tmp) 3655 continue; 3656 3657 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3658 cls << 2, tmp << 2, 3659 pci_dfl_cache_line_size << 2); 3660 pci_cache_line_size = pci_dfl_cache_line_size; 3661 } 3662 } 3663 3664 if (!pci_cache_line_size) { 3665 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3666 cls << 2, pci_dfl_cache_line_size << 2); 3667 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3668 } 3669 3670 return 0; 3671 } 3672 3673 fs_initcall_sync(pci_apply_final_quirks); 3674 3675 /* 3676 * Following are device-specific reset methods which can be used to 3677 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3678 * not available. 3679 */ 3680 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3681 { 3682 /* 3683 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3684 * 3685 * The 82599 supports FLR on VFs, but FLR support is reported only 3686 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3687 * Thus we must call pcie_flr() directly without first checking if it is 3688 * supported. 3689 */ 3690 if (!probe) 3691 pcie_flr(dev); 3692 return 0; 3693 } 3694 3695 #define SOUTH_CHICKEN2 0xc2004 3696 #define PCH_PP_STATUS 0xc7200 3697 #define PCH_PP_CONTROL 0xc7204 3698 #define MSG_CTL 0x45010 3699 #define NSDE_PWR_STATE 0xd0100 3700 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3701 3702 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3703 { 3704 void __iomem *mmio_base; 3705 unsigned long timeout; 3706 u32 val; 3707 3708 if (probe) 3709 return 0; 3710 3711 mmio_base = pci_iomap(dev, 0, 0); 3712 if (!mmio_base) 3713 return -ENOMEM; 3714 3715 iowrite32(0x00000002, mmio_base + MSG_CTL); 3716 3717 /* 3718 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3719 * driver loaded sets the right bits. However, this's a reset and 3720 * the bits have been set by i915 previously, so we clobber 3721 * SOUTH_CHICKEN2 register directly here. 3722 */ 3723 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3724 3725 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3726 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3727 3728 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3729 do { 3730 val = ioread32(mmio_base + PCH_PP_STATUS); 3731 if ((val & 0xb0000000) == 0) 3732 goto reset_complete; 3733 msleep(10); 3734 } while (time_before(jiffies, timeout)); 3735 dev_warn(&dev->dev, "timeout during reset\n"); 3736 3737 reset_complete: 3738 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3739 3740 pci_iounmap(dev, mmio_base); 3741 return 0; 3742 } 3743 3744 /* 3745 * Device-specific reset method for Chelsio T4-based adapters. 3746 */ 3747 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3748 { 3749 u16 old_command; 3750 u16 msix_flags; 3751 3752 /* 3753 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3754 * that we have no device-specific reset method. 3755 */ 3756 if ((dev->device & 0xf000) != 0x4000) 3757 return -ENOTTY; 3758 3759 /* 3760 * If this is the "probe" phase, return 0 indicating that we can 3761 * reset this device. 3762 */ 3763 if (probe) 3764 return 0; 3765 3766 /* 3767 * T4 can wedge if there are DMAs in flight within the chip and Bus 3768 * Master has been disabled. We need to have it on till the Function 3769 * Level Reset completes. (BUS_MASTER is disabled in 3770 * pci_reset_function()). 3771 */ 3772 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3773 pci_write_config_word(dev, PCI_COMMAND, 3774 old_command | PCI_COMMAND_MASTER); 3775 3776 /* 3777 * Perform the actual device function reset, saving and restoring 3778 * configuration information around the reset. 3779 */ 3780 pci_save_state(dev); 3781 3782 /* 3783 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3784 * are disabled when an MSI-X interrupt message needs to be delivered. 3785 * So we briefly re-enable MSI-X interrupts for the duration of the 3786 * FLR. The pci_restore_state() below will restore the original 3787 * MSI-X state. 3788 */ 3789 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3790 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3791 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3792 msix_flags | 3793 PCI_MSIX_FLAGS_ENABLE | 3794 PCI_MSIX_FLAGS_MASKALL); 3795 3796 pcie_flr(dev); 3797 3798 /* 3799 * Restore the configuration information (BAR values, etc.) including 3800 * the original PCI Configuration Space Command word, and return 3801 * success. 3802 */ 3803 pci_restore_state(dev); 3804 pci_write_config_word(dev, PCI_COMMAND, old_command); 3805 return 0; 3806 } 3807 3808 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3809 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3810 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3811 3812 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3813 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3814 reset_intel_82599_sfp_virtfn }, 3815 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3816 reset_ivb_igd }, 3817 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3818 reset_ivb_igd }, 3819 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3820 reset_chelsio_generic_dev }, 3821 { 0 } 3822 }; 3823 3824 /* 3825 * These device-specific reset methods are here rather than in a driver 3826 * because when a host assigns a device to a guest VM, the host may need 3827 * to reset the device but probably doesn't have a driver for it. 3828 */ 3829 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3830 { 3831 const struct pci_dev_reset_methods *i; 3832 3833 for (i = pci_dev_reset_methods; i->reset; i++) { 3834 if ((i->vendor == dev->vendor || 3835 i->vendor == (u16)PCI_ANY_ID) && 3836 (i->device == dev->device || 3837 i->device == (u16)PCI_ANY_ID)) 3838 return i->reset(dev, probe); 3839 } 3840 3841 return -ENOTTY; 3842 } 3843 3844 static void quirk_dma_func0_alias(struct pci_dev *dev) 3845 { 3846 if (PCI_FUNC(dev->devfn) != 0) 3847 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3848 } 3849 3850 /* 3851 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3852 * 3853 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3854 */ 3855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3857 3858 static void quirk_dma_func1_alias(struct pci_dev *dev) 3859 { 3860 if (PCI_FUNC(dev->devfn) != 1) 3861 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); 3862 } 3863 3864 /* 3865 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3866 * SKUs function 1 is present and is a legacy IDE controller, in other 3867 * SKUs this function is not present, making this a ghost requester. 3868 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3869 */ 3870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3871 quirk_dma_func1_alias); 3872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3873 quirk_dma_func1_alias); 3874 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3876 quirk_dma_func1_alias); 3877 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3879 quirk_dma_func1_alias); 3880 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3882 quirk_dma_func1_alias); 3883 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3885 quirk_dma_func1_alias); 3886 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3888 quirk_dma_func1_alias); 3889 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3891 quirk_dma_func1_alias); 3892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3893 quirk_dma_func1_alias); 3894 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3896 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3897 quirk_dma_func1_alias); 3898 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 3899 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 3900 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 3901 quirk_dma_func1_alias); 3902 3903 /* 3904 * Some devices DMA with the wrong devfn, not just the wrong function. 3905 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3906 * the alias is "fixed" and independent of the device devfn. 3907 * 3908 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3909 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3910 * single device on the secondary bus. In reality, the single exposed 3911 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3912 * that provides a bridge to the internal bus of the I/O processor. The 3913 * controller supports private devices, which can be hidden from PCI config 3914 * space. In the case of the Adaptec 3405, a private device at 01.0 3915 * appears to be the DMA engine, which therefore needs to become a DMA 3916 * alias for the device. 3917 */ 3918 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3919 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3920 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3921 .driver_data = PCI_DEVFN(1, 0) }, 3922 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3923 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 3924 .driver_data = PCI_DEVFN(1, 0) }, 3925 { 0 } 3926 }; 3927 3928 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3929 { 3930 const struct pci_device_id *id; 3931 3932 id = pci_match_id(fixed_dma_alias_tbl, dev); 3933 if (id) 3934 pci_add_dma_alias(dev, id->driver_data); 3935 } 3936 3937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3938 3939 /* 3940 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3941 * using the wrong DMA alias for the device. Some of these devices can be 3942 * used as either forward or reverse bridges, so we need to test whether the 3943 * device is operating in the correct mode. We could probably apply this 3944 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3945 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3946 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3947 */ 3948 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3949 { 3950 if (!pci_is_root_bus(pdev->bus) && 3951 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3952 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3953 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3954 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3955 } 3956 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3957 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3958 quirk_use_pcie_bridge_dma_alias); 3959 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3960 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3961 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3962 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3963 /* ITE 8893 has the same problem as the 8892 */ 3964 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 3965 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3966 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3967 3968 /* 3969 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 3970 * be added as aliases to the DMA device in order to allow buffer access 3971 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 3972 * programmed in the EEPROM. 3973 */ 3974 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 3975 { 3976 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); 3977 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); 3978 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); 3979 } 3980 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 3981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 3982 3983 /* 3984 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 3985 * associated not at the root bus, but at a bridge below. This quirk avoids 3986 * generating invalid DMA aliases. 3987 */ 3988 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 3989 { 3990 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 3991 } 3992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 3993 quirk_bridge_cavm_thrx2_pcie_root); 3994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 3995 quirk_bridge_cavm_thrx2_pcie_root); 3996 3997 /* 3998 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 3999 * class code. Fix it. 4000 */ 4001 static void quirk_tw686x_class(struct pci_dev *pdev) 4002 { 4003 u32 class = pdev->class; 4004 4005 /* Use "Multimedia controller" class */ 4006 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4007 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4008 class, pdev->class); 4009 } 4010 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4011 quirk_tw686x_class); 4012 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4013 quirk_tw686x_class); 4014 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4015 quirk_tw686x_class); 4016 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4017 quirk_tw686x_class); 4018 4019 /* 4020 * Some devices have problems with Transaction Layer Packets with the Relaxed 4021 * Ordering Attribute set. Such devices should mark themselves and other 4022 * Device Drivers should check before sending TLPs with RO set. 4023 */ 4024 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4025 { 4026 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4027 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4028 } 4029 4030 /* 4031 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4032 * Complex has a Flow Control Credit issue which can cause performance 4033 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4034 */ 4035 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4036 quirk_relaxedordering_disable); 4037 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4038 quirk_relaxedordering_disable); 4039 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4040 quirk_relaxedordering_disable); 4041 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4042 quirk_relaxedordering_disable); 4043 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4044 quirk_relaxedordering_disable); 4045 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4046 quirk_relaxedordering_disable); 4047 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4048 quirk_relaxedordering_disable); 4049 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4050 quirk_relaxedordering_disable); 4051 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4052 quirk_relaxedordering_disable); 4053 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4054 quirk_relaxedordering_disable); 4055 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4056 quirk_relaxedordering_disable); 4057 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4058 quirk_relaxedordering_disable); 4059 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4060 quirk_relaxedordering_disable); 4061 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4062 quirk_relaxedordering_disable); 4063 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4064 quirk_relaxedordering_disable); 4065 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4066 quirk_relaxedordering_disable); 4067 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4068 quirk_relaxedordering_disable); 4069 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4070 quirk_relaxedordering_disable); 4071 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4072 quirk_relaxedordering_disable); 4073 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4074 quirk_relaxedordering_disable); 4075 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4076 quirk_relaxedordering_disable); 4077 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4078 quirk_relaxedordering_disable); 4079 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4080 quirk_relaxedordering_disable); 4081 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4082 quirk_relaxedordering_disable); 4083 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4084 quirk_relaxedordering_disable); 4085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4086 quirk_relaxedordering_disable); 4087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4088 quirk_relaxedordering_disable); 4089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4090 quirk_relaxedordering_disable); 4091 4092 /* 4093 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex 4094 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4095 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4096 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4097 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4098 * November 10, 2010). As a result, on this platform we can't use Relaxed 4099 * Ordering for Upstream TLPs. 4100 */ 4101 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4102 quirk_relaxedordering_disable); 4103 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4104 quirk_relaxedordering_disable); 4105 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4106 quirk_relaxedordering_disable); 4107 4108 /* 4109 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4110 * values for the Attribute as were supplied in the header of the 4111 * corresponding Request, except as explicitly allowed when IDO is used." 4112 * 4113 * If a non-compliant device generates a completion with a different 4114 * attribute than the request, the receiver may accept it (which itself 4115 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4116 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4117 * device access timeout. 4118 * 4119 * If the non-compliant device generates completions with zero attributes 4120 * (instead of copying the attributes from the request), we can work around 4121 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4122 * upstream devices so they always generate requests with zero attributes. 4123 * 4124 * This affects other devices under the same Root Port, but since these 4125 * attributes are performance hints, there should be no functional problem. 4126 * 4127 * Note that Configuration Space accesses are never supposed to have TLP 4128 * Attributes, so we're safe waiting till after any Configuration Space 4129 * accesses to do the Root Port fixup. 4130 */ 4131 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4132 { 4133 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 4134 4135 if (!root_port) { 4136 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n"); 4137 return; 4138 } 4139 4140 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4141 dev_name(&pdev->dev)); 4142 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4143 PCI_EXP_DEVCTL_RELAX_EN | 4144 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4145 } 4146 4147 /* 4148 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4149 * Completion it generates. 4150 */ 4151 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4152 { 4153 /* 4154 * This mask/compare operation selects for Physical Function 4 on a 4155 * T5. We only need to fix up the Root Port once for any of the 4156 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4157 * 0x54xx so we use that one, 4158 */ 4159 if ((pdev->device & 0xff00) == 0x5400) 4160 quirk_disable_root_port_attributes(pdev); 4161 } 4162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4163 quirk_chelsio_T5_disable_root_port_attributes); 4164 4165 /* 4166 * AMD has indicated that the devices below do not support peer-to-peer 4167 * in any system where they are found in the southbridge with an AMD 4168 * IOMMU in the system. Multifunction devices that do not support 4169 * peer-to-peer between functions can claim to support a subset of ACS. 4170 * Such devices effectively enable request redirect (RR) and completion 4171 * redirect (CR) since all transactions are redirected to the upstream 4172 * root complex. 4173 * 4174 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 4175 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 4176 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 4177 * 4178 * 1002:4385 SBx00 SMBus Controller 4179 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4180 * 1002:4383 SBx00 Azalia (Intel HDA) 4181 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4182 * 1002:4384 SBx00 PCI to PCI Bridge 4183 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4184 * 4185 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4186 * 4187 * 1022:780f [AMD] FCH PCI Bridge 4188 * 1022:7809 [AMD] FCH USB OHCI Controller 4189 */ 4190 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4191 { 4192 #ifdef CONFIG_ACPI 4193 struct acpi_table_header *header = NULL; 4194 acpi_status status; 4195 4196 /* Targeting multifunction devices on the SB (appears on root bus) */ 4197 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4198 return -ENODEV; 4199 4200 /* The IVRS table describes the AMD IOMMU */ 4201 status = acpi_get_table("IVRS", 0, &header); 4202 if (ACPI_FAILURE(status)) 4203 return -ENODEV; 4204 4205 /* Filter out flags not applicable to multifunction */ 4206 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4207 4208 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 4209 #else 4210 return -ENODEV; 4211 #endif 4212 } 4213 4214 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4215 { 4216 /* 4217 * Cavium devices matching this quirk do not perform peer-to-peer 4218 * with other functions, allowing masking out these bits as if they 4219 * were unimplemented in the ACS capability. 4220 */ 4221 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4222 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4223 4224 if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff))) 4225 return -ENOTTY; 4226 4227 return acs_flags ? 0 : 1; 4228 } 4229 4230 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4231 { 4232 /* 4233 * X-Gene root matching this quirk do not allow peer-to-peer 4234 * transactions with others, allowing masking out these bits as if they 4235 * were unimplemented in the ACS capability. 4236 */ 4237 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4238 4239 return acs_flags ? 0 : 1; 4240 } 4241 4242 /* 4243 * Many Intel PCH root ports do provide ACS-like features to disable peer 4244 * transactions and validate bus numbers in requests, but do not provide an 4245 * actual PCIe ACS capability. This is the list of device IDs known to fall 4246 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4247 */ 4248 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4249 /* Ibexpeak PCH */ 4250 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4251 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4252 /* Cougarpoint PCH */ 4253 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4254 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4255 /* Pantherpoint PCH */ 4256 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4257 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4258 /* Lynxpoint-H PCH */ 4259 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4260 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4261 /* Lynxpoint-LP PCH */ 4262 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4263 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4264 /* Wildcat PCH */ 4265 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4266 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4267 /* Patsburg (X79) PCH */ 4268 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4269 /* Wellsburg (X99) PCH */ 4270 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4271 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4272 /* Lynx Point (9 series) PCH */ 4273 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4274 }; 4275 4276 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4277 { 4278 int i; 4279 4280 /* Filter out a few obvious non-matches first */ 4281 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4282 return false; 4283 4284 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4285 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4286 return true; 4287 4288 return false; 4289 } 4290 4291 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 4292 4293 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4294 { 4295 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 4296 INTEL_PCH_ACS_FLAGS : 0; 4297 4298 if (!pci_quirk_intel_pch_acs_match(dev)) 4299 return -ENOTTY; 4300 4301 return acs_flags & ~flags ? 0 : 1; 4302 } 4303 4304 /* 4305 * These QCOM root ports do provide ACS-like features to disable peer 4306 * transactions and validate bus numbers in requests, but do not provide an 4307 * actual PCIe ACS capability. Hardware supports source validation but it 4308 * will report the issue as Completer Abort instead of ACS Violation. 4309 * Hardware doesn't support peer-to-peer and each root port is a root 4310 * complex with unique segment numbers. It is not possible for one root 4311 * port to pass traffic to another root port. All PCIe transactions are 4312 * terminated inside the root port. 4313 */ 4314 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4315 { 4316 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4317 int ret = acs_flags & ~flags ? 0 : 1; 4318 4319 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); 4320 4321 return ret; 4322 } 4323 4324 /* 4325 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4326 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4327 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4328 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4329 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4330 * control register is at offset 8 instead of 6 and we should probably use 4331 * dword accesses to them. This applies to the following PCI Device IDs, as 4332 * found in volume 1 of the datasheet[2]: 4333 * 4334 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4335 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4336 * 4337 * N.B. This doesn't fix what lspci shows. 4338 * 4339 * The 100 series chipset specification update includes this as errata #23[3]. 4340 * 4341 * The 200 series chipset (Union Point) has the same bug according to the 4342 * specification update (Intel 200 Series Chipset Family Platform Controller 4343 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4344 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4345 * chipset include: 4346 * 4347 * 0xa290-0xa29f PCI Express Root port #{0-16} 4348 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4349 * 4350 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4351 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4352 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4353 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4354 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4355 */ 4356 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4357 { 4358 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4359 return false; 4360 4361 switch (dev->device) { 4362 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4363 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4364 return true; 4365 } 4366 4367 return false; 4368 } 4369 4370 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4371 4372 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4373 { 4374 int pos; 4375 u32 cap, ctrl; 4376 4377 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4378 return -ENOTTY; 4379 4380 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4381 if (!pos) 4382 return -ENOTTY; 4383 4384 /* see pci_acs_flags_enabled() */ 4385 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4386 acs_flags &= (cap | PCI_ACS_EC); 4387 4388 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4389 4390 return acs_flags & ~ctrl ? 0 : 1; 4391 } 4392 4393 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4394 { 4395 /* 4396 * SV, TB, and UF are not relevant to multifunction endpoints. 4397 * 4398 * Multifunction devices are only required to implement RR, CR, and DT 4399 * in their ACS capability if they support peer-to-peer transactions. 4400 * Devices matching this quirk have been verified by the vendor to not 4401 * perform peer-to-peer with other functions, allowing us to mask out 4402 * these bits as if they were unimplemented in the ACS capability. 4403 */ 4404 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4405 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4406 4407 return acs_flags ? 0 : 1; 4408 } 4409 4410 static const struct pci_dev_acs_enabled { 4411 u16 vendor; 4412 u16 device; 4413 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4414 } pci_dev_acs_enabled[] = { 4415 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4416 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4417 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4418 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4419 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4420 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4421 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4422 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4423 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4424 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4425 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4426 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4427 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4428 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4429 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4430 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4431 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4432 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4433 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4434 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4435 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4436 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4437 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4438 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4439 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4440 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4441 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4442 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4443 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4444 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4445 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4446 /* 82580 */ 4447 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4448 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4449 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4450 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4451 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4452 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4453 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4454 /* 82576 */ 4455 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4456 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4457 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4458 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4459 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4460 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4461 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4462 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4463 /* 82575 */ 4464 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4465 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4466 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4467 /* I350 */ 4468 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4469 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4470 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4471 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4472 /* 82571 (Quads omitted due to non-ACS switch) */ 4473 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4474 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4475 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4476 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4477 /* I219 */ 4478 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4479 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4480 /* QCOM QDF2xxx root ports */ 4481 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs }, 4482 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs }, 4483 /* Intel PCH root ports */ 4484 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4485 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4486 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4487 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4488 /* Cavium ThunderX */ 4489 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4490 /* APM X-Gene */ 4491 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4492 { 0 } 4493 }; 4494 4495 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4496 { 4497 const struct pci_dev_acs_enabled *i; 4498 int ret; 4499 4500 /* 4501 * Allow devices that do not expose standard PCIe ACS capabilities 4502 * or control to indicate their support here. Multi-function express 4503 * devices which do not allow internal peer-to-peer between functions, 4504 * but do not implement PCIe ACS may wish to return true here. 4505 */ 4506 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4507 if ((i->vendor == dev->vendor || 4508 i->vendor == (u16)PCI_ANY_ID) && 4509 (i->device == dev->device || 4510 i->device == (u16)PCI_ANY_ID)) { 4511 ret = i->acs_enabled(dev, acs_flags); 4512 if (ret >= 0) 4513 return ret; 4514 } 4515 } 4516 4517 return -ENOTTY; 4518 } 4519 4520 /* Config space offset of Root Complex Base Address register */ 4521 #define INTEL_LPC_RCBA_REG 0xf0 4522 /* 31:14 RCBA address */ 4523 #define INTEL_LPC_RCBA_MASK 0xffffc000 4524 /* RCBA Enable */ 4525 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4526 4527 /* Backbone Scratch Pad Register */ 4528 #define INTEL_BSPR_REG 0x1104 4529 /* Backbone Peer Non-Posted Disable */ 4530 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4531 /* Backbone Peer Posted Disable */ 4532 #define INTEL_BSPR_REG_BPPD (1 << 9) 4533 4534 /* Upstream Peer Decode Configuration Register */ 4535 #define INTEL_UPDCR_REG 0x1114 4536 /* 5:0 Peer Decode Enable bits */ 4537 #define INTEL_UPDCR_REG_MASK 0x3f 4538 4539 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4540 { 4541 u32 rcba, bspr, updcr; 4542 void __iomem *rcba_mem; 4543 4544 /* 4545 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4546 * are D28:F* and therefore get probed before LPC, thus we can't 4547 * use pci_get_slot/pci_read_config_dword here. 4548 */ 4549 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4550 INTEL_LPC_RCBA_REG, &rcba); 4551 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4552 return -EINVAL; 4553 4554 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 4555 PAGE_ALIGN(INTEL_UPDCR_REG)); 4556 if (!rcba_mem) 4557 return -ENOMEM; 4558 4559 /* 4560 * The BSPR can disallow peer cycles, but it's set by soft strap and 4561 * therefore read-only. If both posted and non-posted peer cycles are 4562 * disallowed, we're ok. If either are allowed, then we need to use 4563 * the UPDCR to disable peer decodes for each port. This provides the 4564 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4565 */ 4566 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4567 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4568 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4569 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4570 if (updcr & INTEL_UPDCR_REG_MASK) { 4571 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 4572 updcr &= ~INTEL_UPDCR_REG_MASK; 4573 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4574 } 4575 } 4576 4577 iounmap(rcba_mem); 4578 return 0; 4579 } 4580 4581 /* Miscellaneous Port Configuration register */ 4582 #define INTEL_MPC_REG 0xd8 4583 /* MPC: Invalid Receive Bus Number Check Enable */ 4584 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4585 4586 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4587 { 4588 u32 mpc; 4589 4590 /* 4591 * When enabled, the IRBNCE bit of the MPC register enables the 4592 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4593 * ensures that requester IDs fall within the bus number range 4594 * of the bridge. Enable if not already. 4595 */ 4596 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4597 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4598 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 4599 mpc |= INTEL_MPC_REG_IRBNCE; 4600 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4601 } 4602 } 4603 4604 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4605 { 4606 if (!pci_quirk_intel_pch_acs_match(dev)) 4607 return -ENOTTY; 4608 4609 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4610 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 4611 return 0; 4612 } 4613 4614 pci_quirk_enable_intel_rp_mpc_acs(dev); 4615 4616 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4617 4618 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 4619 4620 return 0; 4621 } 4622 4623 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4624 { 4625 int pos; 4626 u32 cap, ctrl; 4627 4628 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4629 return -ENOTTY; 4630 4631 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4632 if (!pos) 4633 return -ENOTTY; 4634 4635 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4636 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4637 4638 ctrl |= (cap & PCI_ACS_SV); 4639 ctrl |= (cap & PCI_ACS_RR); 4640 ctrl |= (cap & PCI_ACS_CR); 4641 ctrl |= (cap & PCI_ACS_UF); 4642 4643 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4644 4645 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4646 4647 return 0; 4648 } 4649 4650 static const struct pci_dev_enable_acs { 4651 u16 vendor; 4652 u16 device; 4653 int (*enable_acs)(struct pci_dev *dev); 4654 } pci_dev_enable_acs[] = { 4655 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 4656 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs }, 4657 { 0 } 4658 }; 4659 4660 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4661 { 4662 const struct pci_dev_enable_acs *i; 4663 int ret; 4664 4665 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4666 if ((i->vendor == dev->vendor || 4667 i->vendor == (u16)PCI_ANY_ID) && 4668 (i->device == dev->device || 4669 i->device == (u16)PCI_ANY_ID)) { 4670 ret = i->enable_acs(dev); 4671 if (ret >= 0) 4672 return ret; 4673 } 4674 } 4675 4676 return -ENOTTY; 4677 } 4678 4679 /* 4680 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with 4681 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4682 * Next Capability pointer in the MSI Capability Structure should point to 4683 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4684 * the list. 4685 */ 4686 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4687 { 4688 int pos, i = 0; 4689 u8 next_cap; 4690 u16 reg16, *cap; 4691 struct pci_cap_saved_state *state; 4692 4693 /* Bail if the hardware bug is fixed */ 4694 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4695 return; 4696 4697 /* Bail if MSI Capability Structure is not found for some reason */ 4698 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4699 if (!pos) 4700 return; 4701 4702 /* 4703 * Bail if Next Capability pointer in the MSI Capability Structure 4704 * is not the expected incorrect 0x00. 4705 */ 4706 pci_read_config_byte(pdev, pos + 1, &next_cap); 4707 if (next_cap) 4708 return; 4709 4710 /* 4711 * PCIe Capability Structure is expected to be at 0x50 and should 4712 * terminate the list (Next Capability pointer is 0x00). Verify 4713 * Capability Id and Next Capability pointer is as expected. 4714 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4715 * to correctly set kernel data structures which have already been 4716 * set incorrectly due to the hardware bug. 4717 */ 4718 pos = 0x50; 4719 pci_read_config_word(pdev, pos, ®16); 4720 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4721 u32 status; 4722 #ifndef PCI_EXP_SAVE_REGS 4723 #define PCI_EXP_SAVE_REGS 7 4724 #endif 4725 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4726 4727 pdev->pcie_cap = pos; 4728 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4729 pdev->pcie_flags_reg = reg16; 4730 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4731 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4732 4733 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4734 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4735 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4736 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4737 4738 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4739 return; 4740 4741 /* 4742 * Save PCIE cap 4743 */ 4744 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4745 if (!state) 4746 return; 4747 4748 state->cap.cap_nr = PCI_CAP_ID_EXP; 4749 state->cap.cap_extended = 0; 4750 state->cap.size = size; 4751 cap = (u16 *)&state->cap.data[0]; 4752 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4753 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4754 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4755 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4756 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4757 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4758 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4759 hlist_add_head(&state->next, &pdev->saved_cap_space); 4760 } 4761 } 4762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4763 4764 /* FLR may cause some 82579 devices to hang. */ 4765 static void quirk_intel_no_flr(struct pci_dev *dev) 4766 { 4767 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4768 } 4769 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); 4770 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); 4771 4772 static void quirk_no_ext_tags(struct pci_dev *pdev) 4773 { 4774 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 4775 4776 if (!bridge) 4777 return; 4778 4779 bridge->no_ext_tags = 1; 4780 dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n"); 4781 4782 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 4783 } 4784 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 4785 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 4786 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 4787 4788 #ifdef CONFIG_PCI_ATS 4789 /* 4790 * Some devices have a broken ATS implementation causing IOMMU stalls. 4791 * Don't use ATS for those devices. 4792 */ 4793 static void quirk_no_ats(struct pci_dev *pdev) 4794 { 4795 dev_info(&pdev->dev, "disabling ATS (broken on this device)\n"); 4796 pdev->ats_cap = 0; 4797 } 4798 4799 /* AMD Stoney platform GPU */ 4800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); 4801 #endif /* CONFIG_PCI_ATS */ 4802