1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/pci.h> 20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 #include <linux/dmi.h> 25 #include <linux/ioport.h> 26 #include <linux/sched.h> 27 #include <linux/ktime.h> 28 #include <linux/mm.h> 29 #include <linux/nvme.h> 30 #include <linux/platform_data/x86/apple.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/suspend.h> 33 #include <linux/switchtec.h> 34 #include "pci.h" 35 36 /* 37 * Retrain the link of a downstream PCIe port by hand if necessary. 38 * 39 * This is needed at least where a downstream port of the ASMedia ASM2824 40 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 41 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 42 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 43 * board. 44 * 45 * In such a configuration the switches are supposed to negotiate the link 46 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 47 * continues switching between the two speeds indefinitely and the data 48 * link layer never reaches the active state, with link training reported 49 * repeatedly active ~84% of the time. Forcing the target link speed to 50 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 51 * each other correctly however. And more interestingly retraining with a 52 * higher target link speed afterwards lets the two successfully negotiate 53 * 5.0GT/s. 54 * 55 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 56 * Link Active status bit and in the failed link training scenario it will 57 * be off along with the Link Bandwidth Management Status indicating that 58 * hardware has changed the link speed or width in an attempt to correct 59 * unreliable link operation. For a port that has been left unconnected 60 * both bits will be clear. So use this information to detect the problem 61 * rather than polling the Link Training bit and watching out for flips or 62 * at least the active status. 63 * 64 * Since the exact nature of the problem isn't known and in principle this 65 * could trigger where an ASM2824 device is downstream rather upstream, 66 * apply this erratum workaround to any downstream ports as long as they 67 * support Link Active reporting and have the Link Control 2 register. 68 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 69 * request a retrain and wait 200ms for the data link to go up. 70 * 71 * If this turns out successful and we know by the Vendor:Device ID it is 72 * safe to do so, then lift the restriction, letting the devices negotiate 73 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 74 * firmware may have already arranged and lift it with ports that already 75 * report their data link being up. 76 * 77 * Return TRUE if the link has been successfully retrained, otherwise FALSE. 78 */ 79 bool pcie_failed_link_retrain(struct pci_dev *dev) 80 { 81 static const struct pci_device_id ids[] = { 82 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 83 {} 84 }; 85 u16 lnksta, lnkctl2; 86 87 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 88 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 89 return false; 90 91 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 92 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 93 if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) == 94 PCI_EXP_LNKSTA_LBMS) { 95 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 96 97 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 98 lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT; 99 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 100 101 if (pcie_retrain_link(dev, false)) { 102 pci_info(dev, "retraining failed\n"); 103 return false; 104 } 105 106 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 107 } 108 109 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 110 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 111 pci_match_id(ids, dev)) { 112 u32 lnkcap; 113 114 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 115 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 116 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 117 lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS; 118 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); 119 120 if (pcie_retrain_link(dev, false)) { 121 pci_info(dev, "retraining failed\n"); 122 return false; 123 } 124 } 125 126 return true; 127 } 128 129 static ktime_t fixup_debug_start(struct pci_dev *dev, 130 void (*fn)(struct pci_dev *dev)) 131 { 132 if (initcall_debug) 133 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 134 135 return ktime_get(); 136 } 137 138 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 139 void (*fn)(struct pci_dev *dev)) 140 { 141 ktime_t delta, rettime; 142 unsigned long long duration; 143 144 rettime = ktime_get(); 145 delta = ktime_sub(rettime, calltime); 146 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 147 if (initcall_debug || duration > 10000) 148 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 149 } 150 151 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 152 struct pci_fixup *end) 153 { 154 ktime_t calltime; 155 156 for (; f < end; f++) 157 if ((f->class == (u32) (dev->class >> f->class_shift) || 158 f->class == (u32) PCI_ANY_ID) && 159 (f->vendor == dev->vendor || 160 f->vendor == (u16) PCI_ANY_ID) && 161 (f->device == dev->device || 162 f->device == (u16) PCI_ANY_ID)) { 163 void (*hook)(struct pci_dev *dev); 164 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 165 hook = offset_to_ptr(&f->hook_offset); 166 #else 167 hook = f->hook; 168 #endif 169 calltime = fixup_debug_start(dev, hook); 170 hook(dev); 171 fixup_debug_report(dev, calltime, hook); 172 } 173 } 174 175 extern struct pci_fixup __start_pci_fixups_early[]; 176 extern struct pci_fixup __end_pci_fixups_early[]; 177 extern struct pci_fixup __start_pci_fixups_header[]; 178 extern struct pci_fixup __end_pci_fixups_header[]; 179 extern struct pci_fixup __start_pci_fixups_final[]; 180 extern struct pci_fixup __end_pci_fixups_final[]; 181 extern struct pci_fixup __start_pci_fixups_enable[]; 182 extern struct pci_fixup __end_pci_fixups_enable[]; 183 extern struct pci_fixup __start_pci_fixups_resume[]; 184 extern struct pci_fixup __end_pci_fixups_resume[]; 185 extern struct pci_fixup __start_pci_fixups_resume_early[]; 186 extern struct pci_fixup __end_pci_fixups_resume_early[]; 187 extern struct pci_fixup __start_pci_fixups_suspend[]; 188 extern struct pci_fixup __end_pci_fixups_suspend[]; 189 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 190 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 191 192 static bool pci_apply_fixup_final_quirks; 193 194 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 195 { 196 struct pci_fixup *start, *end; 197 198 switch (pass) { 199 case pci_fixup_early: 200 start = __start_pci_fixups_early; 201 end = __end_pci_fixups_early; 202 break; 203 204 case pci_fixup_header: 205 start = __start_pci_fixups_header; 206 end = __end_pci_fixups_header; 207 break; 208 209 case pci_fixup_final: 210 if (!pci_apply_fixup_final_quirks) 211 return; 212 start = __start_pci_fixups_final; 213 end = __end_pci_fixups_final; 214 break; 215 216 case pci_fixup_enable: 217 start = __start_pci_fixups_enable; 218 end = __end_pci_fixups_enable; 219 break; 220 221 case pci_fixup_resume: 222 start = __start_pci_fixups_resume; 223 end = __end_pci_fixups_resume; 224 break; 225 226 case pci_fixup_resume_early: 227 start = __start_pci_fixups_resume_early; 228 end = __end_pci_fixups_resume_early; 229 break; 230 231 case pci_fixup_suspend: 232 start = __start_pci_fixups_suspend; 233 end = __end_pci_fixups_suspend; 234 break; 235 236 case pci_fixup_suspend_late: 237 start = __start_pci_fixups_suspend_late; 238 end = __end_pci_fixups_suspend_late; 239 break; 240 241 default: 242 /* stupid compiler warning, you would think with an enum... */ 243 return; 244 } 245 pci_do_fixups(dev, start, end); 246 } 247 EXPORT_SYMBOL(pci_fixup_device); 248 249 static int __init pci_apply_final_quirks(void) 250 { 251 struct pci_dev *dev = NULL; 252 u8 cls = 0; 253 u8 tmp; 254 255 if (pci_cache_line_size) 256 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 257 258 pci_apply_fixup_final_quirks = true; 259 for_each_pci_dev(dev) { 260 pci_fixup_device(pci_fixup_final, dev); 261 /* 262 * If arch hasn't set it explicitly yet, use the CLS 263 * value shared by all PCI devices. If there's a 264 * mismatch, fall back to the default value. 265 */ 266 if (!pci_cache_line_size) { 267 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 268 if (!cls) 269 cls = tmp; 270 if (!tmp || cls == tmp) 271 continue; 272 273 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 274 cls << 2, tmp << 2, 275 pci_dfl_cache_line_size << 2); 276 pci_cache_line_size = pci_dfl_cache_line_size; 277 } 278 } 279 280 if (!pci_cache_line_size) { 281 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 282 pci_dfl_cache_line_size << 2); 283 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 284 } 285 286 return 0; 287 } 288 fs_initcall_sync(pci_apply_final_quirks); 289 290 /* 291 * Decoding should be disabled for a PCI device during BAR sizing to avoid 292 * conflict. But doing so may cause problems on host bridge and perhaps other 293 * key system devices. For devices that need to have mmio decoding always-on, 294 * we need to set the dev->mmio_always_on bit. 295 */ 296 static void quirk_mmio_always_on(struct pci_dev *dev) 297 { 298 dev->mmio_always_on = 1; 299 } 300 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 301 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 302 303 /* 304 * The Mellanox Tavor device gives false positive parity errors. Disable 305 * parity error reporting. 306 */ 307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 309 310 /* 311 * Deal with broken BIOSes that neglect to enable passive release, 312 * which can cause problems in combination with the 82441FX/PPro MTRRs 313 */ 314 static void quirk_passive_release(struct pci_dev *dev) 315 { 316 struct pci_dev *d = NULL; 317 unsigned char dlc; 318 319 /* 320 * We have to make sure a particular bit is set in the PIIX3 321 * ISA bridge, so we have to go out and find it. 322 */ 323 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 324 pci_read_config_byte(d, 0x82, &dlc); 325 if (!(dlc & 1<<1)) { 326 pci_info(d, "PIIX3: Enabling Passive Release\n"); 327 dlc |= 1<<1; 328 pci_write_config_byte(d, 0x82, dlc); 329 } 330 } 331 } 332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 333 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 334 335 #ifdef CONFIG_X86_32 336 /* 337 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 338 * workaround but VIA don't answer queries. If you happen to have good 339 * contacts at VIA ask them for me please -- Alan 340 * 341 * This appears to be BIOS not version dependent. So presumably there is a 342 * chipset level fix. 343 */ 344 static void quirk_isa_dma_hangs(struct pci_dev *dev) 345 { 346 if (!isa_dma_bridge_buggy) { 347 isa_dma_bridge_buggy = 1; 348 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 349 } 350 } 351 /* 352 * It's not totally clear which chipsets are the problematic ones. We know 353 * 82C586 and 82C596 variants are affected. 354 */ 355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 362 #endif 363 364 /* 365 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 366 * for some HT machines to use C4 w/o hanging. 367 */ 368 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 369 { 370 u32 pmbase; 371 u16 pm1a; 372 373 pci_read_config_dword(dev, 0x40, &pmbase); 374 pmbase = pmbase & 0xff80; 375 pm1a = inw(pmbase); 376 377 if (pm1a & 0x10) { 378 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 379 outw(0x10, pmbase); 380 } 381 } 382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 383 384 /* Chipsets where PCI->PCI transfers vanish or hang */ 385 static void quirk_nopcipci(struct pci_dev *dev) 386 { 387 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 388 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 389 pci_pci_problems |= PCIPCI_FAIL; 390 } 391 } 392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 394 395 static void quirk_nopciamd(struct pci_dev *dev) 396 { 397 u8 rev; 398 pci_read_config_byte(dev, 0x08, &rev); 399 if (rev == 0x13) { 400 /* Erratum 24 */ 401 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 402 pci_pci_problems |= PCIAGP_FAIL; 403 } 404 } 405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 406 407 /* Triton requires workarounds to be used by the drivers */ 408 static void quirk_triton(struct pci_dev *dev) 409 { 410 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 411 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 412 pci_pci_problems |= PCIPCI_TRITON; 413 } 414 } 415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 419 420 /* 421 * VIA Apollo KT133 needs PCI latency patch 422 * Made according to a Windows driver-based patch by George E. Breese; 423 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 424 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 425 * which Mr Breese based his work. 426 * 427 * Updated based on further information from the site and also on 428 * information provided by VIA 429 */ 430 static void quirk_vialatency(struct pci_dev *dev) 431 { 432 struct pci_dev *p; 433 u8 busarb; 434 435 /* 436 * Ok, we have a potential problem chipset here. Now see if we have 437 * a buggy southbridge. 438 */ 439 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 440 if (p != NULL) { 441 442 /* 443 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 444 * thanks Dan Hollis. 445 * Check for buggy part revisions 446 */ 447 if (p->revision < 0x40 || p->revision > 0x42) 448 goto exit; 449 } else { 450 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 451 if (p == NULL) /* No problem parts */ 452 goto exit; 453 454 /* Check for buggy part revisions */ 455 if (p->revision < 0x10 || p->revision > 0x12) 456 goto exit; 457 } 458 459 /* 460 * Ok we have the problem. Now set the PCI master grant to occur 461 * every master grant. The apparent bug is that under high PCI load 462 * (quite common in Linux of course) you can get data loss when the 463 * CPU is held off the bus for 3 bus master requests. This happens 464 * to include the IDE controllers.... 465 * 466 * VIA only apply this fix when an SB Live! is present but under 467 * both Linux and Windows this isn't enough, and we have seen 468 * corruption without SB Live! but with things like 3 UDMA IDE 469 * controllers. So we ignore that bit of the VIA recommendation.. 470 */ 471 pci_read_config_byte(dev, 0x76, &busarb); 472 473 /* 474 * Set bit 4 and bit 5 of byte 76 to 0x01 475 * "Master priority rotation on every PCI master grant" 476 */ 477 busarb &= ~(1<<5); 478 busarb |= (1<<4); 479 pci_write_config_byte(dev, 0x76, busarb); 480 pci_info(dev, "Applying VIA southbridge workaround\n"); 481 exit: 482 pci_dev_put(p); 483 } 484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 487 /* Must restore this on a resume from RAM */ 488 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 489 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 490 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 491 492 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 493 static void quirk_viaetbf(struct pci_dev *dev) 494 { 495 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 496 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 497 pci_pci_problems |= PCIPCI_VIAETBF; 498 } 499 } 500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 501 502 static void quirk_vsfx(struct pci_dev *dev) 503 { 504 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 505 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 506 pci_pci_problems |= PCIPCI_VSFX; 507 } 508 } 509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 510 511 /* 512 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 513 * space. Latency must be set to 0xA and Triton workaround applied too. 514 * [Info kindly provided by ALi] 515 */ 516 static void quirk_alimagik(struct pci_dev *dev) 517 { 518 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 519 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 520 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 521 } 522 } 523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 525 526 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 527 static void quirk_natoma(struct pci_dev *dev) 528 { 529 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 530 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 531 pci_pci_problems |= PCIPCI_NATOMA; 532 } 533 } 534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 540 541 /* 542 * This chip can cause PCI parity errors if config register 0xA0 is read 543 * while DMAs are occurring. 544 */ 545 static void quirk_citrine(struct pci_dev *dev) 546 { 547 dev->cfg_size = 0xA0; 548 } 549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 550 551 /* 552 * This chip can cause bus lockups if config addresses above 0x600 553 * are read or written. 554 */ 555 static void quirk_nfp6000(struct pci_dev *dev) 556 { 557 dev->cfg_size = 0x600; 558 } 559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 560 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 563 564 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 565 static void quirk_extend_bar_to_page(struct pci_dev *dev) 566 { 567 int i; 568 569 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 570 struct resource *r = &dev->resource[i]; 571 572 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 573 r->end = PAGE_SIZE - 1; 574 r->start = 0; 575 r->flags |= IORESOURCE_UNSET; 576 pci_info(dev, "expanded BAR %d to page size: %pR\n", 577 i, r); 578 } 579 } 580 } 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 582 583 /* 584 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 585 * If it's needed, re-allocate the region. 586 */ 587 static void quirk_s3_64M(struct pci_dev *dev) 588 { 589 struct resource *r = &dev->resource[0]; 590 591 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 592 r->flags |= IORESOURCE_UNSET; 593 r->start = 0; 594 r->end = 0x3ffffff; 595 } 596 } 597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 599 600 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 601 const char *name) 602 { 603 u32 region; 604 struct pci_bus_region bus_region; 605 struct resource *res = dev->resource + pos; 606 607 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 608 609 if (!region) 610 return; 611 612 res->name = pci_name(dev); 613 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 614 res->flags |= 615 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 616 region &= ~(size - 1); 617 618 /* Convert from PCI bus to resource space */ 619 bus_region.start = region; 620 bus_region.end = region + size - 1; 621 pcibios_bus_to_resource(dev->bus, res, &bus_region); 622 623 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 624 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 625 } 626 627 /* 628 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 629 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 630 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 631 * (which conflicts w/ BAR1's memory range). 632 * 633 * CS553x's ISA PCI BARs may also be read-only (ref: 634 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 635 */ 636 static void quirk_cs5536_vsa(struct pci_dev *dev) 637 { 638 static char *name = "CS5536 ISA bridge"; 639 640 if (pci_resource_len(dev, 0) != 8) { 641 quirk_io(dev, 0, 8, name); /* SMB */ 642 quirk_io(dev, 1, 256, name); /* GPIO */ 643 quirk_io(dev, 2, 64, name); /* MFGPT */ 644 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 645 name); 646 } 647 } 648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 649 650 static void quirk_io_region(struct pci_dev *dev, int port, 651 unsigned int size, int nr, const char *name) 652 { 653 u16 region; 654 struct pci_bus_region bus_region; 655 struct resource *res = dev->resource + nr; 656 657 pci_read_config_word(dev, port, ®ion); 658 region &= ~(size - 1); 659 660 if (!region) 661 return; 662 663 res->name = pci_name(dev); 664 res->flags = IORESOURCE_IO; 665 666 /* Convert from PCI bus to resource space */ 667 bus_region.start = region; 668 bus_region.end = region + size - 1; 669 pcibios_bus_to_resource(dev->bus, res, &bus_region); 670 671 if (!pci_claim_resource(dev, nr)) 672 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 673 } 674 675 /* 676 * ATI Northbridge setups MCE the processor if you even read somewhere 677 * between 0x3b0->0x3bb or read 0x3d3 678 */ 679 static void quirk_ati_exploding_mce(struct pci_dev *dev) 680 { 681 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 682 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 683 request_region(0x3b0, 0x0C, "RadeonIGP"); 684 request_region(0x3d3, 0x01, "RadeonIGP"); 685 } 686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 687 688 /* 689 * In the AMD NL platform, this device ([1022:7912]) has a class code of 690 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 691 * claim it. 692 * 693 * But the dwc3 driver is a more specific driver for this device, and we'd 694 * prefer to use it instead of xhci. To prevent xhci from claiming the 695 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 696 * defines as "USB device (not host controller)". The dwc3 driver can then 697 * claim it based on its Vendor and Device ID. 698 */ 699 static void quirk_amd_nl_class(struct pci_dev *pdev) 700 { 701 u32 class = pdev->class; 702 703 /* Use "USB Device (not host controller)" class */ 704 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 705 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 706 class, pdev->class); 707 } 708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 709 quirk_amd_nl_class); 710 711 /* 712 * Synopsys USB 3.x host HAPS platform has a class code of 713 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 714 * devices should use dwc3-haps driver. Change these devices' class code to 715 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 716 * them. 717 */ 718 static void quirk_synopsys_haps(struct pci_dev *pdev) 719 { 720 u32 class = pdev->class; 721 722 switch (pdev->device) { 723 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 724 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 725 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 726 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 727 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 728 class, pdev->class); 729 break; 730 } 731 } 732 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 733 PCI_CLASS_SERIAL_USB_XHCI, 0, 734 quirk_synopsys_haps); 735 736 /* 737 * Let's make the southbridge information explicit instead of having to 738 * worry about people probing the ACPI areas, for example.. (Yes, it 739 * happens, and if you read the wrong ACPI register it will put the machine 740 * to sleep with no way of waking it up again. Bummer). 741 * 742 * ALI M7101: Two IO regions pointed to by words at 743 * 0xE0 (64 bytes of ACPI registers) 744 * 0xE2 (32 bytes of SMB registers) 745 */ 746 static void quirk_ali7101_acpi(struct pci_dev *dev) 747 { 748 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 749 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 750 } 751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 752 753 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 754 { 755 u32 devres; 756 u32 mask, size, base; 757 758 pci_read_config_dword(dev, port, &devres); 759 if ((devres & enable) != enable) 760 return; 761 mask = (devres >> 16) & 15; 762 base = devres & 0xffff; 763 size = 16; 764 for (;;) { 765 unsigned int bit = size >> 1; 766 if ((bit & mask) == bit) 767 break; 768 size = bit; 769 } 770 /* 771 * For now we only print it out. Eventually we'll want to 772 * reserve it (at least if it's in the 0x1000+ range), but 773 * let's get enough confirmation reports first. 774 */ 775 base &= -size; 776 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 777 } 778 779 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 780 { 781 u32 devres; 782 u32 mask, size, base; 783 784 pci_read_config_dword(dev, port, &devres); 785 if ((devres & enable) != enable) 786 return; 787 base = devres & 0xffff0000; 788 mask = (devres & 0x3f) << 16; 789 size = 128 << 16; 790 for (;;) { 791 unsigned int bit = size >> 1; 792 if ((bit & mask) == bit) 793 break; 794 size = bit; 795 } 796 797 /* 798 * For now we only print it out. Eventually we'll want to 799 * reserve it, but let's get enough confirmation reports first. 800 */ 801 base &= -size; 802 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 803 } 804 805 /* 806 * PIIX4 ACPI: Two IO regions pointed to by longwords at 807 * 0x40 (64 bytes of ACPI registers) 808 * 0x90 (16 bytes of SMB registers) 809 * and a few strange programmable PIIX4 device resources. 810 */ 811 static void quirk_piix4_acpi(struct pci_dev *dev) 812 { 813 u32 res_a; 814 815 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 816 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 817 818 /* Device resource A has enables for some of the other ones */ 819 pci_read_config_dword(dev, 0x5c, &res_a); 820 821 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 822 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 823 824 /* Device resource D is just bitfields for static resources */ 825 826 /* Device 12 enabled? */ 827 if (res_a & (1 << 29)) { 828 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 829 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 830 } 831 /* Device 13 enabled? */ 832 if (res_a & (1 << 30)) { 833 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 834 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 835 } 836 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 837 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 838 } 839 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 841 842 #define ICH_PMBASE 0x40 843 #define ICH_ACPI_CNTL 0x44 844 #define ICH4_ACPI_EN 0x10 845 #define ICH6_ACPI_EN 0x80 846 #define ICH4_GPIOBASE 0x58 847 #define ICH4_GPIO_CNTL 0x5c 848 #define ICH4_GPIO_EN 0x10 849 #define ICH6_GPIOBASE 0x48 850 #define ICH6_GPIO_CNTL 0x4c 851 #define ICH6_GPIO_EN 0x10 852 853 /* 854 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 855 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 856 * 0x58 (64 bytes of GPIO I/O space) 857 */ 858 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 859 { 860 u8 enable; 861 862 /* 863 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 864 * with low legacy (and fixed) ports. We don't know the decoding 865 * priority and can't tell whether the legacy device or the one created 866 * here is really at that address. This happens on boards with broken 867 * BIOSes. 868 */ 869 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 870 if (enable & ICH4_ACPI_EN) 871 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 872 "ICH4 ACPI/GPIO/TCO"); 873 874 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 875 if (enable & ICH4_GPIO_EN) 876 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 877 "ICH4 GPIO"); 878 } 879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 889 890 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 891 { 892 u8 enable; 893 894 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 895 if (enable & ICH6_ACPI_EN) 896 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 897 "ICH6 ACPI/GPIO/TCO"); 898 899 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 900 if (enable & ICH6_GPIO_EN) 901 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 902 "ICH6 GPIO"); 903 } 904 905 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 906 const char *name, int dynsize) 907 { 908 u32 val; 909 u32 size, base; 910 911 pci_read_config_dword(dev, reg, &val); 912 913 /* Enabled? */ 914 if (!(val & 1)) 915 return; 916 base = val & 0xfffc; 917 if (dynsize) { 918 /* 919 * This is not correct. It is 16, 32 or 64 bytes depending on 920 * register D31:F0:ADh bits 5:4. 921 * 922 * But this gets us at least _part_ of it. 923 */ 924 size = 16; 925 } else { 926 size = 128; 927 } 928 base &= ~(size-1); 929 930 /* 931 * Just print it out for now. We should reserve it after more 932 * debugging. 933 */ 934 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 935 } 936 937 static void quirk_ich6_lpc(struct pci_dev *dev) 938 { 939 /* Shared ACPI/GPIO decode with all ICH6+ */ 940 ich6_lpc_acpi_gpio(dev); 941 942 /* ICH6-specific generic IO decode */ 943 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 944 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 945 } 946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 948 949 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 950 const char *name) 951 { 952 u32 val; 953 u32 mask, base; 954 955 pci_read_config_dword(dev, reg, &val); 956 957 /* Enabled? */ 958 if (!(val & 1)) 959 return; 960 961 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 962 base = val & 0xfffc; 963 mask = (val >> 16) & 0xfc; 964 mask |= 3; 965 966 /* 967 * Just print it out for now. We should reserve it after more 968 * debugging. 969 */ 970 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 971 } 972 973 /* ICH7-10 has the same common LPC generic IO decode registers */ 974 static void quirk_ich7_lpc(struct pci_dev *dev) 975 { 976 /* We share the common ACPI/GPIO decode with ICH6 */ 977 ich6_lpc_acpi_gpio(dev); 978 979 /* And have 4 ICH7+ generic decodes */ 980 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 981 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 982 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 983 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 984 } 985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 998 999 /* 1000 * VIA ACPI: One IO region pointed to by longword at 1001 * 0x48 or 0x20 (256 bytes of ACPI registers) 1002 */ 1003 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1004 { 1005 if (dev->revision & 0x10) 1006 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1007 "vt82c586 ACPI"); 1008 } 1009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1010 1011 /* 1012 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1013 * 0x48 (256 bytes of ACPI registers) 1014 * 0x70 (128 bytes of hardware monitoring register) 1015 * 0x90 (16 bytes of SMB registers) 1016 */ 1017 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1018 { 1019 quirk_vt82c586_acpi(dev); 1020 1021 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1022 "vt82c686 HW-mon"); 1023 1024 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1025 } 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1027 1028 /* 1029 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1030 * 0x88 (128 bytes of power management registers) 1031 * 0xd0 (16 bytes of SMB registers) 1032 */ 1033 static void quirk_vt8235_acpi(struct pci_dev *dev) 1034 { 1035 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1036 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1037 } 1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1039 1040 /* 1041 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1042 * back-to-back: Disable fast back-to-back on the secondary bus segment 1043 */ 1044 static void quirk_xio2000a(struct pci_dev *dev) 1045 { 1046 struct pci_dev *pdev; 1047 u16 command; 1048 1049 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1050 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1051 pci_read_config_word(pdev, PCI_COMMAND, &command); 1052 if (command & PCI_COMMAND_FAST_BACK) 1053 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1054 } 1055 } 1056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1057 quirk_xio2000a); 1058 1059 #ifdef CONFIG_X86_IO_APIC 1060 1061 #include <asm/io_apic.h> 1062 1063 /* 1064 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1065 * devices to the external APIC. 1066 * 1067 * TODO: When we have device-specific interrupt routers, this code will go 1068 * away from quirks. 1069 */ 1070 static void quirk_via_ioapic(struct pci_dev *dev) 1071 { 1072 u8 tmp; 1073 1074 if (nr_ioapics < 1) 1075 tmp = 0; /* nothing routed to external APIC */ 1076 else 1077 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1078 1079 pci_info(dev, "%s VIA external APIC routing\n", 1080 tmp ? "Enabling" : "Disabling"); 1081 1082 /* Offset 0x58: External APIC IRQ output control */ 1083 pci_write_config_byte(dev, 0x58, tmp); 1084 } 1085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1086 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1087 1088 /* 1089 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1090 * This leads to doubled level interrupt rates. 1091 * Set this bit to get rid of cycle wastage. 1092 * Otherwise uncritical. 1093 */ 1094 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1095 { 1096 u8 misc_control2; 1097 #define BYPASS_APIC_DEASSERT 8 1098 1099 pci_read_config_byte(dev, 0x5B, &misc_control2); 1100 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1101 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1102 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1103 } 1104 } 1105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1106 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1107 1108 /* 1109 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1110 * We check all revs >= B0 (yet not in the pre production!) as the bug 1111 * is currently marked NoFix 1112 * 1113 * We have multiple reports of hangs with this chipset that went away with 1114 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1115 * of course. However the advice is demonstrably good even if so. 1116 */ 1117 static void quirk_amd_ioapic(struct pci_dev *dev) 1118 { 1119 if (dev->revision >= 0x02) { 1120 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1121 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1122 } 1123 } 1124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1125 #endif /* CONFIG_X86_IO_APIC */ 1126 1127 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1128 1129 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1130 { 1131 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1132 if (dev->subsystem_device == 0xa118) 1133 dev->sriov->link = dev->devfn; 1134 } 1135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1136 #endif 1137 1138 /* 1139 * Some settings of MMRBC can lead to data corruption so block changes. 1140 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1141 */ 1142 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1143 { 1144 if (dev->subordinate && dev->revision <= 0x12) { 1145 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1146 dev->revision); 1147 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1148 } 1149 } 1150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1151 1152 /* 1153 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1154 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1155 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1156 * of the ACPI SCI interrupt is only done for convenience. 1157 * -jgarzik 1158 */ 1159 static void quirk_via_acpi(struct pci_dev *d) 1160 { 1161 u8 irq; 1162 1163 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1164 pci_read_config_byte(d, 0x42, &irq); 1165 irq &= 0xf; 1166 if (irq && (irq != 2)) 1167 d->irq = irq; 1168 } 1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1171 1172 /* VIA bridges which have VLink */ 1173 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1174 1175 static void quirk_via_bridge(struct pci_dev *dev) 1176 { 1177 /* See what bridge we have and find the device ranges */ 1178 switch (dev->device) { 1179 case PCI_DEVICE_ID_VIA_82C686: 1180 /* 1181 * The VT82C686 is special; it attaches to PCI and can have 1182 * any device number. All its subdevices are functions of 1183 * that single device. 1184 */ 1185 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1186 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1187 break; 1188 case PCI_DEVICE_ID_VIA_8237: 1189 case PCI_DEVICE_ID_VIA_8237A: 1190 via_vlink_dev_lo = 15; 1191 break; 1192 case PCI_DEVICE_ID_VIA_8235: 1193 via_vlink_dev_lo = 16; 1194 break; 1195 case PCI_DEVICE_ID_VIA_8231: 1196 case PCI_DEVICE_ID_VIA_8233_0: 1197 case PCI_DEVICE_ID_VIA_8233A: 1198 case PCI_DEVICE_ID_VIA_8233C_0: 1199 via_vlink_dev_lo = 17; 1200 break; 1201 } 1202 } 1203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1211 1212 /* 1213 * quirk_via_vlink - VIA VLink IRQ number update 1214 * @dev: PCI device 1215 * 1216 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1217 * the IRQ line register which usually is not relevant for PCI cards, is 1218 * actually written so that interrupts get sent to the right place. 1219 * 1220 * We only do this on systems where a VIA south bridge was detected, and 1221 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1222 */ 1223 static void quirk_via_vlink(struct pci_dev *dev) 1224 { 1225 u8 irq, new_irq; 1226 1227 /* Check if we have VLink at all */ 1228 if (via_vlink_dev_lo == -1) 1229 return; 1230 1231 new_irq = dev->irq; 1232 1233 /* Don't quirk interrupts outside the legacy IRQ range */ 1234 if (!new_irq || new_irq > 15) 1235 return; 1236 1237 /* Internal device ? */ 1238 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1239 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1240 return; 1241 1242 /* 1243 * This is an internal VLink device on a PIC interrupt. The BIOS 1244 * ought to have set this but may not have, so we redo it. 1245 */ 1246 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1247 if (new_irq != irq) { 1248 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1249 irq, new_irq); 1250 udelay(15); /* unknown if delay really needed */ 1251 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1252 } 1253 } 1254 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1255 1256 /* 1257 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1258 * of VT82C597 for backward compatibility. We need to switch it off to be 1259 * able to recognize the real type of the chip. 1260 */ 1261 static void quirk_vt82c598_id(struct pci_dev *dev) 1262 { 1263 pci_write_config_byte(dev, 0xfc, 0); 1264 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1265 } 1266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1267 1268 /* 1269 * CardBus controllers have a legacy base address that enables them to 1270 * respond as i82365 pcmcia controllers. We don't want them to do this 1271 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1272 * driver does not (and should not) handle CardBus. 1273 */ 1274 static void quirk_cardbus_legacy(struct pci_dev *dev) 1275 { 1276 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1277 } 1278 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1279 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1280 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1281 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1282 1283 /* 1284 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1285 * what the designers were smoking but let's not inhale... 1286 * 1287 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1288 * turn it off! 1289 */ 1290 static void quirk_amd_ordering(struct pci_dev *dev) 1291 { 1292 u32 pcic; 1293 pci_read_config_dword(dev, 0x4C, &pcic); 1294 if ((pcic & 6) != 6) { 1295 pcic |= 6; 1296 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1297 pci_write_config_dword(dev, 0x4C, pcic); 1298 pci_read_config_dword(dev, 0x84, &pcic); 1299 pcic |= (1 << 23); /* Required in this mode */ 1300 pci_write_config_dword(dev, 0x84, pcic); 1301 } 1302 } 1303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1304 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1305 1306 /* 1307 * DreamWorks-provided workaround for Dunord I-3000 problem 1308 * 1309 * This card decodes and responds to addresses not apparently assigned to 1310 * it. We force a larger allocation to ensure that nothing gets put too 1311 * close to it. 1312 */ 1313 static void quirk_dunord(struct pci_dev *dev) 1314 { 1315 struct resource *r = &dev->resource[1]; 1316 1317 r->flags |= IORESOURCE_UNSET; 1318 r->start = 0; 1319 r->end = 0xffffff; 1320 } 1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1322 1323 /* 1324 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1325 * decoding (transparent), and does indicate this in the ProgIf. 1326 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1327 */ 1328 static void quirk_transparent_bridge(struct pci_dev *dev) 1329 { 1330 dev->transparent = 1; 1331 } 1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1334 1335 /* 1336 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1337 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1338 * found at http://www.national.com/analog for info on what these bits do. 1339 * <christer@weinigel.se> 1340 */ 1341 static void quirk_mediagx_master(struct pci_dev *dev) 1342 { 1343 u8 reg; 1344 1345 pci_read_config_byte(dev, 0x41, ®); 1346 if (reg & 2) { 1347 reg &= ~2; 1348 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1349 reg); 1350 pci_write_config_byte(dev, 0x41, reg); 1351 } 1352 } 1353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1354 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1355 1356 /* 1357 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1358 * in the odd case it is not the results are corruption hence the presence 1359 * of a Linux check. 1360 */ 1361 static void quirk_disable_pxb(struct pci_dev *pdev) 1362 { 1363 u16 config; 1364 1365 if (pdev->revision != 0x04) /* Only C0 requires this */ 1366 return; 1367 pci_read_config_word(pdev, 0x40, &config); 1368 if (config & (1<<6)) { 1369 config &= ~(1<<6); 1370 pci_write_config_word(pdev, 0x40, config); 1371 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1372 } 1373 } 1374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1376 1377 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1378 { 1379 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1380 u8 tmp; 1381 1382 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1383 if (tmp == 0x01) { 1384 pci_read_config_byte(pdev, 0x40, &tmp); 1385 pci_write_config_byte(pdev, 0x40, tmp|1); 1386 pci_write_config_byte(pdev, 0x9, 1); 1387 pci_write_config_byte(pdev, 0xa, 6); 1388 pci_write_config_byte(pdev, 0x40, tmp); 1389 1390 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1391 pci_info(pdev, "set SATA to AHCI mode\n"); 1392 } 1393 } 1394 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1397 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1399 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1401 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1402 1403 /* Serverworks CSB5 IDE does not fully support native mode */ 1404 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1405 { 1406 u8 prog; 1407 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1408 if (prog & 5) { 1409 prog &= ~5; 1410 pdev->class &= ~5; 1411 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1412 /* PCI layer will sort out resources */ 1413 } 1414 } 1415 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1416 1417 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1418 static void quirk_ide_samemode(struct pci_dev *pdev) 1419 { 1420 u8 prog; 1421 1422 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1423 1424 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1425 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1426 prog &= ~5; 1427 pdev->class &= ~5; 1428 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1429 } 1430 } 1431 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1432 1433 /* Some ATA devices break if put into D3 */ 1434 static void quirk_no_ata_d3(struct pci_dev *pdev) 1435 { 1436 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1437 } 1438 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1439 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1440 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1441 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1442 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1443 /* ALi loses some register settings that we cannot then restore */ 1444 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1445 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1446 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1447 occur when mode detecting */ 1448 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1449 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1450 1451 /* 1452 * This was originally an Alpha-specific thing, but it really fits here. 1453 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1454 */ 1455 static void quirk_eisa_bridge(struct pci_dev *dev) 1456 { 1457 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1458 } 1459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1460 1461 /* 1462 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1463 * is not activated. The myth is that Asus said that they do not want the 1464 * users to be irritated by just another PCI Device in the Win98 device 1465 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1466 * package 2.7.0 for details) 1467 * 1468 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1469 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1470 * becomes necessary to do this tweak in two steps -- the chosen trigger 1471 * is either the Host bridge (preferred) or on-board VGA controller. 1472 * 1473 * Note that we used to unhide the SMBus that way on Toshiba laptops 1474 * (Satellite A40 and Tecra M2) but then found that the thermal management 1475 * was done by SMM code, which could cause unsynchronized concurrent 1476 * accesses to the SMBus registers, with potentially bad effects. Thus you 1477 * should be very careful when adding new entries: if SMM is accessing the 1478 * Intel SMBus, this is a very good reason to leave it hidden. 1479 * 1480 * Likewise, many recent laptops use ACPI for thermal management. If the 1481 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1482 * natively, and keeping the SMBus hidden is the right thing to do. If you 1483 * are about to add an entry in the table below, please first disassemble 1484 * the DSDT and double-check that there is no code accessing the SMBus. 1485 */ 1486 static int asus_hides_smbus; 1487 1488 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1489 { 1490 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1491 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1492 switch (dev->subsystem_device) { 1493 case 0x8025: /* P4B-LX */ 1494 case 0x8070: /* P4B */ 1495 case 0x8088: /* P4B533 */ 1496 case 0x1626: /* L3C notebook */ 1497 asus_hides_smbus = 1; 1498 } 1499 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1500 switch (dev->subsystem_device) { 1501 case 0x80b1: /* P4GE-V */ 1502 case 0x80b2: /* P4PE */ 1503 case 0x8093: /* P4B533-V */ 1504 asus_hides_smbus = 1; 1505 } 1506 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1507 switch (dev->subsystem_device) { 1508 case 0x8030: /* P4T533 */ 1509 asus_hides_smbus = 1; 1510 } 1511 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1512 switch (dev->subsystem_device) { 1513 case 0x8070: /* P4G8X Deluxe */ 1514 asus_hides_smbus = 1; 1515 } 1516 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1517 switch (dev->subsystem_device) { 1518 case 0x80c9: /* PU-DLS */ 1519 asus_hides_smbus = 1; 1520 } 1521 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1522 switch (dev->subsystem_device) { 1523 case 0x1751: /* M2N notebook */ 1524 case 0x1821: /* M5N notebook */ 1525 case 0x1897: /* A6L notebook */ 1526 asus_hides_smbus = 1; 1527 } 1528 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1529 switch (dev->subsystem_device) { 1530 case 0x184b: /* W1N notebook */ 1531 case 0x186a: /* M6Ne notebook */ 1532 asus_hides_smbus = 1; 1533 } 1534 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1535 switch (dev->subsystem_device) { 1536 case 0x80f2: /* P4P800-X */ 1537 asus_hides_smbus = 1; 1538 } 1539 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1540 switch (dev->subsystem_device) { 1541 case 0x1882: /* M6V notebook */ 1542 case 0x1977: /* A6VA notebook */ 1543 asus_hides_smbus = 1; 1544 } 1545 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1546 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1547 switch (dev->subsystem_device) { 1548 case 0x088C: /* HP Compaq nc8000 */ 1549 case 0x0890: /* HP Compaq nc6000 */ 1550 asus_hides_smbus = 1; 1551 } 1552 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1553 switch (dev->subsystem_device) { 1554 case 0x12bc: /* HP D330L */ 1555 case 0x12bd: /* HP D530 */ 1556 case 0x006a: /* HP Compaq nx9500 */ 1557 asus_hides_smbus = 1; 1558 } 1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1560 switch (dev->subsystem_device) { 1561 case 0x12bf: /* HP xw4100 */ 1562 asus_hides_smbus = 1; 1563 } 1564 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1565 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1566 switch (dev->subsystem_device) { 1567 case 0xC00C: /* Samsung P35 notebook */ 1568 asus_hides_smbus = 1; 1569 } 1570 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1571 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1572 switch (dev->subsystem_device) { 1573 case 0x0058: /* Compaq Evo N620c */ 1574 asus_hides_smbus = 1; 1575 } 1576 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1577 switch (dev->subsystem_device) { 1578 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1579 /* Motherboard doesn't have Host bridge 1580 * subvendor/subdevice IDs, therefore checking 1581 * its on-board VGA controller */ 1582 asus_hides_smbus = 1; 1583 } 1584 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1585 switch (dev->subsystem_device) { 1586 case 0x00b8: /* Compaq Evo D510 CMT */ 1587 case 0x00b9: /* Compaq Evo D510 SFF */ 1588 case 0x00ba: /* Compaq Evo D510 USDT */ 1589 /* Motherboard doesn't have Host bridge 1590 * subvendor/subdevice IDs and on-board VGA 1591 * controller is disabled if an AGP card is 1592 * inserted, therefore checking USB UHCI 1593 * Controller #1 */ 1594 asus_hides_smbus = 1; 1595 } 1596 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1597 switch (dev->subsystem_device) { 1598 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1599 /* Motherboard doesn't have host bridge 1600 * subvendor/subdevice IDs, therefore checking 1601 * its on-board VGA controller */ 1602 asus_hides_smbus = 1; 1603 } 1604 } 1605 } 1606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1616 1617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1620 1621 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1622 { 1623 u16 val; 1624 1625 if (likely(!asus_hides_smbus)) 1626 return; 1627 1628 pci_read_config_word(dev, 0xF2, &val); 1629 if (val & 0x8) { 1630 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1631 pci_read_config_word(dev, 0xF2, &val); 1632 if (val & 0x8) 1633 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1634 val); 1635 else 1636 pci_info(dev, "Enabled i801 SMBus device\n"); 1637 } 1638 } 1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1646 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1647 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1648 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1649 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1650 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1651 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1652 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1653 1654 /* It appears we just have one such device. If not, we have a warning */ 1655 static void __iomem *asus_rcba_base; 1656 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1657 { 1658 u32 rcba; 1659 1660 if (likely(!asus_hides_smbus)) 1661 return; 1662 WARN_ON(asus_rcba_base); 1663 1664 pci_read_config_dword(dev, 0xF0, &rcba); 1665 /* use bits 31:14, 16 kB aligned */ 1666 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1667 if (asus_rcba_base == NULL) 1668 return; 1669 } 1670 1671 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1672 { 1673 u32 val; 1674 1675 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1676 return; 1677 1678 /* read the Function Disable register, dword mode only */ 1679 val = readl(asus_rcba_base + 0x3418); 1680 1681 /* enable the SMBus device */ 1682 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1683 } 1684 1685 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1686 { 1687 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1688 return; 1689 1690 iounmap(asus_rcba_base); 1691 asus_rcba_base = NULL; 1692 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1693 } 1694 1695 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1696 { 1697 asus_hides_smbus_lpc_ich6_suspend(dev); 1698 asus_hides_smbus_lpc_ich6_resume_early(dev); 1699 asus_hides_smbus_lpc_ich6_resume(dev); 1700 } 1701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1702 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1703 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1704 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1705 1706 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1707 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1708 { 1709 u8 val = 0; 1710 pci_read_config_byte(dev, 0x77, &val); 1711 if (val & 0x10) { 1712 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1713 pci_write_config_byte(dev, 0x77, val & ~0x10); 1714 } 1715 } 1716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1720 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1721 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1722 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1723 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1724 1725 /* 1726 * ... This is further complicated by the fact that some SiS96x south 1727 * bridges pretend to be 85C503/5513 instead. In that case see if we 1728 * spotted a compatible north bridge to make sure. 1729 * (pci_find_device() doesn't work yet) 1730 * 1731 * We can also enable the sis96x bit in the discovery register.. 1732 */ 1733 #define SIS_DETECT_REGISTER 0x40 1734 1735 static void quirk_sis_503(struct pci_dev *dev) 1736 { 1737 u8 reg; 1738 u16 devid; 1739 1740 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1741 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1742 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1743 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1744 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1745 return; 1746 } 1747 1748 /* 1749 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1750 * it has already been processed. (Depends on link order, which is 1751 * apparently not guaranteed) 1752 */ 1753 dev->device = devid; 1754 quirk_sis_96x_smbus(dev); 1755 } 1756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1757 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1758 1759 /* 1760 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1761 * and MC97 modem controller are disabled when a second PCI soundcard is 1762 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1763 * -- bjd 1764 */ 1765 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1766 { 1767 u8 val; 1768 int asus_hides_ac97 = 0; 1769 1770 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1771 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1772 asus_hides_ac97 = 1; 1773 } 1774 1775 if (!asus_hides_ac97) 1776 return; 1777 1778 pci_read_config_byte(dev, 0x50, &val); 1779 if (val & 0xc0) { 1780 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1781 pci_read_config_byte(dev, 0x50, &val); 1782 if (val & 0xc0) 1783 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1784 val); 1785 else 1786 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1787 } 1788 } 1789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1790 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1791 1792 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1793 1794 /* 1795 * If we are using libata we can drive this chip properly but must do this 1796 * early on to make the additional device appear during the PCI scanning. 1797 */ 1798 static void quirk_jmicron_ata(struct pci_dev *pdev) 1799 { 1800 u32 conf1, conf5, class; 1801 u8 hdr; 1802 1803 /* Only poke fn 0 */ 1804 if (PCI_FUNC(pdev->devfn)) 1805 return; 1806 1807 pci_read_config_dword(pdev, 0x40, &conf1); 1808 pci_read_config_dword(pdev, 0x80, &conf5); 1809 1810 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1811 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1812 1813 switch (pdev->device) { 1814 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1815 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1816 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1817 /* The controller should be in single function ahci mode */ 1818 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1819 break; 1820 1821 case PCI_DEVICE_ID_JMICRON_JMB365: 1822 case PCI_DEVICE_ID_JMICRON_JMB366: 1823 /* Redirect IDE second PATA port to the right spot */ 1824 conf5 |= (1 << 24); 1825 fallthrough; 1826 case PCI_DEVICE_ID_JMICRON_JMB361: 1827 case PCI_DEVICE_ID_JMICRON_JMB363: 1828 case PCI_DEVICE_ID_JMICRON_JMB369: 1829 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1830 /* Set the class codes correctly and then direct IDE 0 */ 1831 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1832 break; 1833 1834 case PCI_DEVICE_ID_JMICRON_JMB368: 1835 /* The controller should be in single function IDE mode */ 1836 conf1 |= 0x00C00000; /* Set 22, 23 */ 1837 break; 1838 } 1839 1840 pci_write_config_dword(pdev, 0x40, conf1); 1841 pci_write_config_dword(pdev, 0x80, conf5); 1842 1843 /* Update pdev accordingly */ 1844 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1845 pdev->hdr_type = hdr & 0x7f; 1846 pdev->multifunction = !!(hdr & 0x80); 1847 1848 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1849 pdev->class = class >> 8; 1850 } 1851 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1852 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1853 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1854 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1855 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1858 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1860 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1861 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1862 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1863 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1864 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1865 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1866 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1867 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1868 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1869 1870 #endif 1871 1872 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1873 { 1874 if (dev->multifunction) { 1875 device_disable_async_suspend(&dev->dev); 1876 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1877 } 1878 } 1879 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1880 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1883 1884 #ifdef CONFIG_X86_IO_APIC 1885 static void quirk_alder_ioapic(struct pci_dev *pdev) 1886 { 1887 int i; 1888 1889 if ((pdev->class >> 8) != 0xff00) 1890 return; 1891 1892 /* 1893 * The first BAR is the location of the IO-APIC... we must 1894 * not touch this (and it's already covered by the fixmap), so 1895 * forcibly insert it into the resource tree. 1896 */ 1897 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1898 insert_resource(&iomem_resource, &pdev->resource[0]); 1899 1900 /* 1901 * The next five BARs all seem to be rubbish, so just clean 1902 * them out. 1903 */ 1904 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1905 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1906 } 1907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1908 #endif 1909 1910 static void quirk_no_msi(struct pci_dev *dev) 1911 { 1912 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1913 dev->no_msi = 1; 1914 } 1915 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1921 1922 static void quirk_pcie_mch(struct pci_dev *pdev) 1923 { 1924 pdev->no_msi = 1; 1925 } 1926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1928 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1929 1930 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1931 1932 /* 1933 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1934 * actually on the AMBA bus. These fake PCI devices can support SVA via 1935 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1936 * 1937 * Normally stalling must not be enabled for PCI devices, since it would 1938 * break the PCI requirement for free-flowing writes and may lead to 1939 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1940 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1941 * even when a "PCI" device turns out to be a regular old SoC device 1942 * dressed up as a RCiEP and normal rules don't apply. 1943 */ 1944 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1945 { 1946 struct property_entry properties[] = { 1947 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1948 {}, 1949 }; 1950 1951 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1952 return; 1953 1954 pdev->pasid_no_tlp = 1; 1955 1956 /* 1957 * Set the dma-can-stall property on ACPI platforms. Device tree 1958 * can set it directly. 1959 */ 1960 if (!pdev->dev.of_node && 1961 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1962 pci_warn(pdev, "could not add stall property"); 1963 } 1964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1967 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1970 1971 /* 1972 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1973 * together on certain PXH-based systems. 1974 */ 1975 static void quirk_pcie_pxh(struct pci_dev *dev) 1976 { 1977 dev->no_msi = 1; 1978 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1979 } 1980 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1981 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1982 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1983 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1984 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1985 1986 /* 1987 * Some Intel PCI Express chipsets have trouble with downstream device 1988 * power management. 1989 */ 1990 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1991 { 1992 pci_pm_d3hot_delay = 120; 1993 dev->no_d1d2 = 1; 1994 } 1995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1998 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2016 2017 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2018 { 2019 if (dev->d3hot_delay >= delay) 2020 return; 2021 2022 dev->d3hot_delay = delay; 2023 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2024 dev->d3hot_delay); 2025 } 2026 2027 static void quirk_radeon_pm(struct pci_dev *dev) 2028 { 2029 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2030 dev->subsystem_device == 0x00e2) 2031 quirk_d3hot_delay(dev, 20); 2032 } 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2034 2035 /* 2036 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2037 * reset is performed too soon after transition to D0, extend d3hot_delay 2038 * to previous effective default for all NVIDIA HDA controllers. 2039 */ 2040 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2041 { 2042 quirk_d3hot_delay(dev, 20); 2043 } 2044 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2045 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2046 quirk_nvidia_hda_pm); 2047 2048 /* 2049 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2050 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2051 * 2052 * The kernel attempts to transition these devices to D3cold, but that seems 2053 * to be ineffective on the platforms in question; the PCI device appears to 2054 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2055 * extended delay in order to succeed. 2056 */ 2057 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2058 { 2059 quirk_d3hot_delay(dev, 20); 2060 } 2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2064 2065 #ifdef CONFIG_X86_IO_APIC 2066 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2067 { 2068 noioapicreroute = 1; 2069 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2070 2071 return 0; 2072 } 2073 2074 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2075 /* 2076 * Systems to exclude from boot interrupt reroute quirks 2077 */ 2078 { 2079 .callback = dmi_disable_ioapicreroute, 2080 .ident = "ASUSTek Computer INC. M2N-LR", 2081 .matches = { 2082 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2083 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2084 }, 2085 }, 2086 {} 2087 }; 2088 2089 /* 2090 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2091 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2092 * that a PCI device's interrupt handler is installed on the boot interrupt 2093 * line instead. 2094 */ 2095 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2096 { 2097 dmi_check_system(boot_interrupt_dmi_table); 2098 if (noioapicquirk || noioapicreroute) 2099 return; 2100 2101 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2102 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2103 dev->vendor, dev->device); 2104 } 2105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2113 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2114 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2115 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2116 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2117 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2118 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2119 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2120 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2121 2122 /* 2123 * On some chipsets we can disable the generation of legacy INTx boot 2124 * interrupts. 2125 */ 2126 2127 /* 2128 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2129 * 300641-004US, section 5.7.3. 2130 * 2131 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2132 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2133 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2134 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2135 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2136 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2137 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2138 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2139 * Core IO on Xeon Scalable, see Intel order no 610950. 2140 */ 2141 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2142 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2143 2144 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2145 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2146 2147 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2148 { 2149 u16 pci_config_word; 2150 u32 pci_config_dword; 2151 2152 if (noioapicquirk) 2153 return; 2154 2155 switch (dev->device) { 2156 case PCI_DEVICE_ID_INTEL_ESB_10: 2157 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2158 &pci_config_word); 2159 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2160 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2161 pci_config_word); 2162 break; 2163 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2164 case 0x0e28: /* Xeon E5/E7 V2 */ 2165 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2166 case 0x6f28: /* Xeon D-1500 */ 2167 case 0x2034: /* Xeon Scalable Family */ 2168 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2169 &pci_config_dword); 2170 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2171 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2172 pci_config_dword); 2173 break; 2174 default: 2175 return; 2176 } 2177 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2178 dev->vendor, dev->device); 2179 } 2180 /* 2181 * Device 29 Func 5 Device IDs of IO-APIC 2182 * containing ABAR—APIC1 Alternate Base Address Register 2183 */ 2184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2185 quirk_disable_intel_boot_interrupt); 2186 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2187 quirk_disable_intel_boot_interrupt); 2188 2189 /* 2190 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2191 * containing Coherent Interface Protocol Interrupt Control 2192 * 2193 * Device IDs obtained from volume 2 datasheets of commented 2194 * families above. 2195 */ 2196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2197 quirk_disable_intel_boot_interrupt); 2198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2199 quirk_disable_intel_boot_interrupt); 2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2201 quirk_disable_intel_boot_interrupt); 2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2203 quirk_disable_intel_boot_interrupt); 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2205 quirk_disable_intel_boot_interrupt); 2206 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2207 quirk_disable_intel_boot_interrupt); 2208 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2209 quirk_disable_intel_boot_interrupt); 2210 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2211 quirk_disable_intel_boot_interrupt); 2212 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2213 quirk_disable_intel_boot_interrupt); 2214 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2215 quirk_disable_intel_boot_interrupt); 2216 2217 /* Disable boot interrupts on HT-1000 */ 2218 #define BC_HT1000_FEATURE_REG 0x64 2219 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2220 #define BC_HT1000_MAP_IDX 0xC00 2221 #define BC_HT1000_MAP_DATA 0xC01 2222 2223 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2224 { 2225 u32 pci_config_dword; 2226 u8 irq; 2227 2228 if (noioapicquirk) 2229 return; 2230 2231 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2232 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2233 BC_HT1000_PIC_REGS_ENABLE); 2234 2235 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2236 outb(irq, BC_HT1000_MAP_IDX); 2237 outb(0x00, BC_HT1000_MAP_DATA); 2238 } 2239 2240 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2241 2242 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2243 dev->vendor, dev->device); 2244 } 2245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2246 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2247 2248 /* Disable boot interrupts on AMD and ATI chipsets */ 2249 2250 /* 2251 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2252 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2253 * (due to an erratum). 2254 */ 2255 #define AMD_813X_MISC 0x40 2256 #define AMD_813X_NOIOAMODE (1<<0) 2257 #define AMD_813X_REV_B1 0x12 2258 #define AMD_813X_REV_B2 0x13 2259 2260 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2261 { 2262 u32 pci_config_dword; 2263 2264 if (noioapicquirk) 2265 return; 2266 if ((dev->revision == AMD_813X_REV_B1) || 2267 (dev->revision == AMD_813X_REV_B2)) 2268 return; 2269 2270 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2271 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2272 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2273 2274 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2275 dev->vendor, dev->device); 2276 } 2277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2278 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2280 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2281 2282 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2283 2284 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2285 { 2286 u16 pci_config_word; 2287 2288 if (noioapicquirk) 2289 return; 2290 2291 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2292 if (!pci_config_word) { 2293 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2294 dev->vendor, dev->device); 2295 return; 2296 } 2297 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2298 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2299 dev->vendor, dev->device); 2300 } 2301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2302 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2303 #endif /* CONFIG_X86_IO_APIC */ 2304 2305 /* 2306 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2307 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2308 * Re-allocate the region if needed... 2309 */ 2310 static void quirk_tc86c001_ide(struct pci_dev *dev) 2311 { 2312 struct resource *r = &dev->resource[0]; 2313 2314 if (r->start & 0x8) { 2315 r->flags |= IORESOURCE_UNSET; 2316 r->start = 0; 2317 r->end = 0xf; 2318 } 2319 } 2320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2321 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2322 quirk_tc86c001_ide); 2323 2324 /* 2325 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2326 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2327 * being read correctly if bit 7 of the base address is set. 2328 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2329 * Re-allocate the regions to a 256-byte boundary if necessary. 2330 */ 2331 static void quirk_plx_pci9050(struct pci_dev *dev) 2332 { 2333 unsigned int bar; 2334 2335 /* Fixed in revision 2 (PCI 9052). */ 2336 if (dev->revision >= 2) 2337 return; 2338 for (bar = 0; bar <= 1; bar++) 2339 if (pci_resource_len(dev, bar) == 0x80 && 2340 (pci_resource_start(dev, bar) & 0x80)) { 2341 struct resource *r = &dev->resource[bar]; 2342 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2343 bar); 2344 r->flags |= IORESOURCE_UNSET; 2345 r->start = 0; 2346 r->end = 0xff; 2347 } 2348 } 2349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2350 quirk_plx_pci9050); 2351 /* 2352 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2353 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2354 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2355 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2356 * 2357 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2358 * driver. 2359 */ 2360 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2361 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2362 2363 static void quirk_netmos(struct pci_dev *dev) 2364 { 2365 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2366 unsigned int num_serial = dev->subsystem_device & 0xf; 2367 2368 /* 2369 * These Netmos parts are multiport serial devices with optional 2370 * parallel ports. Even when parallel ports are present, they 2371 * are identified as class SERIAL, which means the serial driver 2372 * will claim them. To prevent this, mark them as class OTHER. 2373 * These combo devices should be claimed by parport_serial. 2374 * 2375 * The subdevice ID is of the form 0x00PS, where <P> is the number 2376 * of parallel ports and <S> is the number of serial ports. 2377 */ 2378 switch (dev->device) { 2379 case PCI_DEVICE_ID_NETMOS_9835: 2380 /* Well, this rule doesn't hold for the following 9835 device */ 2381 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2382 dev->subsystem_device == 0x0299) 2383 return; 2384 fallthrough; 2385 case PCI_DEVICE_ID_NETMOS_9735: 2386 case PCI_DEVICE_ID_NETMOS_9745: 2387 case PCI_DEVICE_ID_NETMOS_9845: 2388 case PCI_DEVICE_ID_NETMOS_9855: 2389 if (num_parallel) { 2390 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2391 dev->device, num_parallel, num_serial); 2392 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2393 (dev->class & 0xff); 2394 } 2395 } 2396 } 2397 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2398 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2399 2400 static void quirk_e100_interrupt(struct pci_dev *dev) 2401 { 2402 u16 command, pmcsr; 2403 u8 __iomem *csr; 2404 u8 cmd_hi; 2405 2406 switch (dev->device) { 2407 /* PCI IDs taken from drivers/net/e100.c */ 2408 case 0x1029: 2409 case 0x1030 ... 0x1034: 2410 case 0x1038 ... 0x103E: 2411 case 0x1050 ... 0x1057: 2412 case 0x1059: 2413 case 0x1064 ... 0x106B: 2414 case 0x1091 ... 0x1095: 2415 case 0x1209: 2416 case 0x1229: 2417 case 0x2449: 2418 case 0x2459: 2419 case 0x245D: 2420 case 0x27DC: 2421 break; 2422 default: 2423 return; 2424 } 2425 2426 /* 2427 * Some firmware hands off the e100 with interrupts enabled, 2428 * which can cause a flood of interrupts if packets are 2429 * received before the driver attaches to the device. So 2430 * disable all e100 interrupts here. The driver will 2431 * re-enable them when it's ready. 2432 */ 2433 pci_read_config_word(dev, PCI_COMMAND, &command); 2434 2435 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2436 return; 2437 2438 /* 2439 * Check that the device is in the D0 power state. If it's not, 2440 * there is no point to look any further. 2441 */ 2442 if (dev->pm_cap) { 2443 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2444 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2445 return; 2446 } 2447 2448 /* Convert from PCI bus to resource space. */ 2449 csr = ioremap(pci_resource_start(dev, 0), 8); 2450 if (!csr) { 2451 pci_warn(dev, "Can't map e100 registers\n"); 2452 return; 2453 } 2454 2455 cmd_hi = readb(csr + 3); 2456 if (cmd_hi == 0) { 2457 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2458 writeb(1, csr + 3); 2459 } 2460 2461 iounmap(csr); 2462 } 2463 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2464 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2465 2466 /* 2467 * The 82575 and 82598 may experience data corruption issues when transitioning 2468 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2469 */ 2470 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2471 { 2472 pci_info(dev, "Disabling L0s\n"); 2473 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2474 } 2475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2489 2490 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2491 { 2492 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2493 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2494 } 2495 2496 /* 2497 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2498 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2499 * disable both L0s and L1 for now to be safe. 2500 */ 2501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2502 2503 /* 2504 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2505 * Link bit cleared after starting the link retrain process to allow this 2506 * process to finish. 2507 * 2508 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2509 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2510 */ 2511 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2512 { 2513 dev->clear_retrain_link = 1; 2514 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2515 } 2516 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2517 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2518 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2519 2520 static void fixup_rev1_53c810(struct pci_dev *dev) 2521 { 2522 u32 class = dev->class; 2523 2524 /* 2525 * rev 1 ncr53c810 chips don't set the class at all which means 2526 * they don't get their resources remapped. Fix that here. 2527 */ 2528 if (class) 2529 return; 2530 2531 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2532 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2533 class, dev->class); 2534 } 2535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2536 2537 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2538 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2539 { 2540 u16 en1k; 2541 2542 pci_read_config_word(dev, 0x40, &en1k); 2543 2544 if (en1k & 0x200) { 2545 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2546 dev->io_window_1k = 1; 2547 } 2548 } 2549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2550 2551 /* 2552 * Under some circumstances, AER is not linked with extended capabilities. 2553 * Force it to be linked by setting the corresponding control bit in the 2554 * config space. 2555 */ 2556 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2557 { 2558 uint8_t b; 2559 2560 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2561 if (!(b & 0x20)) { 2562 pci_write_config_byte(dev, 0xf41, b | 0x20); 2563 pci_info(dev, "Linking AER extended capability\n"); 2564 } 2565 } 2566 } 2567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2568 quirk_nvidia_ck804_pcie_aer_ext_cap); 2569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2570 quirk_nvidia_ck804_pcie_aer_ext_cap); 2571 2572 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2573 { 2574 /* 2575 * Disable PCI Bus Parking and PCI Master read caching on CX700 2576 * which causes unspecified timing errors with a VT6212L on the PCI 2577 * bus leading to USB2.0 packet loss. 2578 * 2579 * This quirk is only enabled if a second (on the external PCI bus) 2580 * VT6212L is found -- the CX700 core itself also contains a USB 2581 * host controller with the same PCI ID as the VT6212L. 2582 */ 2583 2584 /* Count VT6212L instances */ 2585 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2586 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2587 uint8_t b; 2588 2589 /* 2590 * p should contain the first (internal) VT6212L -- see if we have 2591 * an external one by searching again. 2592 */ 2593 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2594 if (!p) 2595 return; 2596 pci_dev_put(p); 2597 2598 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2599 if (b & 0x40) { 2600 /* Turn off PCI Bus Parking */ 2601 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2602 2603 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2604 } 2605 } 2606 2607 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2608 if (b != 0) { 2609 /* Turn off PCI Master read caching */ 2610 pci_write_config_byte(dev, 0x72, 0x0); 2611 2612 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2613 pci_write_config_byte(dev, 0x75, 0x1); 2614 2615 /* Disable "Read FIFO Timer" */ 2616 pci_write_config_byte(dev, 0x77, 0x0); 2617 2618 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2619 } 2620 } 2621 } 2622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2623 2624 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2625 { 2626 u32 rev; 2627 2628 pci_read_config_dword(dev, 0xf4, &rev); 2629 2630 /* Only CAP the MRRS if the device is a 5719 A0 */ 2631 if (rev == 0x05719000) { 2632 int readrq = pcie_get_readrq(dev); 2633 if (readrq > 2048) 2634 pcie_set_readrq(dev, 2048); 2635 } 2636 } 2637 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2638 PCI_DEVICE_ID_TIGON3_5719, 2639 quirk_brcm_5719_limit_mrrs); 2640 2641 /* 2642 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2643 * hide device 6 which configures the overflow device access containing the 2644 * DRBs - this is where we expose device 6. 2645 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2646 */ 2647 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2648 { 2649 u8 reg; 2650 2651 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2652 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2653 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2654 } 2655 } 2656 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2657 quirk_unhide_mch_dev6); 2658 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2659 quirk_unhide_mch_dev6); 2660 2661 #ifdef CONFIG_PCI_MSI 2662 /* 2663 * Some chipsets do not support MSI. We cannot easily rely on setting 2664 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2665 * other buses controlled by the chipset even if Linux is not aware of it. 2666 * Instead of setting the flag on all buses in the machine, simply disable 2667 * MSI globally. 2668 */ 2669 static void quirk_disable_all_msi(struct pci_dev *dev) 2670 { 2671 pci_no_msi(); 2672 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2673 } 2674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2683 2684 /* Disable MSI on chipsets that are known to not support it */ 2685 static void quirk_disable_msi(struct pci_dev *dev) 2686 { 2687 if (dev->subordinate) { 2688 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2689 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2690 } 2691 } 2692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2695 2696 /* 2697 * The APC bridge device in AMD 780 family northbridges has some random 2698 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2699 * we use the possible vendor/device IDs of the host bridge for the 2700 * declared quirk, and search for the APC bridge by slot number. 2701 */ 2702 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2703 { 2704 struct pci_dev *apc_bridge; 2705 2706 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2707 if (apc_bridge) { 2708 if (apc_bridge->device == 0x9602) 2709 quirk_disable_msi(apc_bridge); 2710 pci_dev_put(apc_bridge); 2711 } 2712 } 2713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2715 2716 /* 2717 * Go through the list of HyperTransport capabilities and return 1 if a HT 2718 * MSI capability is found and enabled. 2719 */ 2720 static int msi_ht_cap_enabled(struct pci_dev *dev) 2721 { 2722 int pos, ttl = PCI_FIND_CAP_TTL; 2723 2724 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2725 while (pos && ttl--) { 2726 u8 flags; 2727 2728 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2729 &flags) == 0) { 2730 pci_info(dev, "Found %s HT MSI Mapping\n", 2731 flags & HT_MSI_FLAGS_ENABLE ? 2732 "enabled" : "disabled"); 2733 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2734 } 2735 2736 pos = pci_find_next_ht_capability(dev, pos, 2737 HT_CAPTYPE_MSI_MAPPING); 2738 } 2739 return 0; 2740 } 2741 2742 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2743 static void quirk_msi_ht_cap(struct pci_dev *dev) 2744 { 2745 if (!msi_ht_cap_enabled(dev)) 2746 quirk_disable_msi(dev); 2747 } 2748 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2749 quirk_msi_ht_cap); 2750 2751 /* 2752 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2753 * if the MSI capability is set in any of these mappings. 2754 */ 2755 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2756 { 2757 struct pci_dev *pdev; 2758 2759 /* 2760 * Check HT MSI cap on this chipset and the root one. A single one 2761 * having MSI is enough to be sure that MSI is supported. 2762 */ 2763 pdev = pci_get_slot(dev->bus, 0); 2764 if (!pdev) 2765 return; 2766 if (!msi_ht_cap_enabled(pdev)) 2767 quirk_msi_ht_cap(dev); 2768 pci_dev_put(pdev); 2769 } 2770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2771 quirk_nvidia_ck804_msi_ht_cap); 2772 2773 /* Force enable MSI mapping capability on HT bridges */ 2774 static void ht_enable_msi_mapping(struct pci_dev *dev) 2775 { 2776 int pos, ttl = PCI_FIND_CAP_TTL; 2777 2778 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2779 while (pos && ttl--) { 2780 u8 flags; 2781 2782 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2783 &flags) == 0) { 2784 pci_info(dev, "Enabling HT MSI Mapping\n"); 2785 2786 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2787 flags | HT_MSI_FLAGS_ENABLE); 2788 } 2789 pos = pci_find_next_ht_capability(dev, pos, 2790 HT_CAPTYPE_MSI_MAPPING); 2791 } 2792 } 2793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2794 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2795 ht_enable_msi_mapping); 2796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2797 ht_enable_msi_mapping); 2798 2799 /* 2800 * The P5N32-SLI motherboards from Asus have a problem with MSI 2801 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2802 * also affects other devices. As for now, turn off MSI for this device. 2803 */ 2804 static void nvenet_msi_disable(struct pci_dev *dev) 2805 { 2806 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2807 2808 if (board_name && 2809 (strstr(board_name, "P5N32-SLI PREMIUM") || 2810 strstr(board_name, "P5N32-E SLI"))) { 2811 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2812 dev->no_msi = 1; 2813 } 2814 } 2815 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2816 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2817 nvenet_msi_disable); 2818 2819 /* 2820 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2821 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2822 * interrupts for PME and AER events; instead only INTx interrupts are 2823 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2824 * for other events, since PCIe specification doesn't support using a mix of 2825 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2826 * service drivers registering their respective ISRs for MSIs. 2827 */ 2828 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2829 { 2830 dev->no_msi = 1; 2831 } 2832 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2833 PCI_CLASS_BRIDGE_PCI, 8, 2834 pci_quirk_nvidia_tegra_disable_rp_msi); 2835 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2836 PCI_CLASS_BRIDGE_PCI, 8, 2837 pci_quirk_nvidia_tegra_disable_rp_msi); 2838 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2839 PCI_CLASS_BRIDGE_PCI, 8, 2840 pci_quirk_nvidia_tegra_disable_rp_msi); 2841 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2842 PCI_CLASS_BRIDGE_PCI, 8, 2843 pci_quirk_nvidia_tegra_disable_rp_msi); 2844 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2845 PCI_CLASS_BRIDGE_PCI, 8, 2846 pci_quirk_nvidia_tegra_disable_rp_msi); 2847 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2848 PCI_CLASS_BRIDGE_PCI, 8, 2849 pci_quirk_nvidia_tegra_disable_rp_msi); 2850 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2851 PCI_CLASS_BRIDGE_PCI, 8, 2852 pci_quirk_nvidia_tegra_disable_rp_msi); 2853 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2854 PCI_CLASS_BRIDGE_PCI, 8, 2855 pci_quirk_nvidia_tegra_disable_rp_msi); 2856 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2857 PCI_CLASS_BRIDGE_PCI, 8, 2858 pci_quirk_nvidia_tegra_disable_rp_msi); 2859 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2860 PCI_CLASS_BRIDGE_PCI, 8, 2861 pci_quirk_nvidia_tegra_disable_rp_msi); 2862 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2863 PCI_CLASS_BRIDGE_PCI, 8, 2864 pci_quirk_nvidia_tegra_disable_rp_msi); 2865 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2866 PCI_CLASS_BRIDGE_PCI, 8, 2867 pci_quirk_nvidia_tegra_disable_rp_msi); 2868 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2869 PCI_CLASS_BRIDGE_PCI, 8, 2870 pci_quirk_nvidia_tegra_disable_rp_msi); 2871 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2872 PCI_CLASS_BRIDGE_PCI, 8, 2873 pci_quirk_nvidia_tegra_disable_rp_msi); 2874 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2875 PCI_CLASS_BRIDGE_PCI, 8, 2876 pci_quirk_nvidia_tegra_disable_rp_msi); 2877 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2878 PCI_CLASS_BRIDGE_PCI, 8, 2879 pci_quirk_nvidia_tegra_disable_rp_msi); 2880 2881 /* 2882 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2883 * config register. This register controls the routing of legacy 2884 * interrupts from devices that route through the MCP55. If this register 2885 * is misprogrammed, interrupts are only sent to the BSP, unlike 2886 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2887 * having this register set properly prevents kdump from booting up 2888 * properly, so let's make sure that we have it set correctly. 2889 * Note that this is an undocumented register. 2890 */ 2891 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2892 { 2893 u32 cfg; 2894 2895 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2896 return; 2897 2898 pci_read_config_dword(dev, 0x74, &cfg); 2899 2900 if (cfg & ((1 << 2) | (1 << 15))) { 2901 pr_info("Rewriting IRQ routing register on MCP55\n"); 2902 cfg &= ~((1 << 2) | (1 << 15)); 2903 pci_write_config_dword(dev, 0x74, cfg); 2904 } 2905 } 2906 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2907 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2908 nvbridge_check_legacy_irq_routing); 2909 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2910 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2911 nvbridge_check_legacy_irq_routing); 2912 2913 static int ht_check_msi_mapping(struct pci_dev *dev) 2914 { 2915 int pos, ttl = PCI_FIND_CAP_TTL; 2916 int found = 0; 2917 2918 /* Check if there is HT MSI cap or enabled on this device */ 2919 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2920 while (pos && ttl--) { 2921 u8 flags; 2922 2923 if (found < 1) 2924 found = 1; 2925 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2926 &flags) == 0) { 2927 if (flags & HT_MSI_FLAGS_ENABLE) { 2928 if (found < 2) { 2929 found = 2; 2930 break; 2931 } 2932 } 2933 } 2934 pos = pci_find_next_ht_capability(dev, pos, 2935 HT_CAPTYPE_MSI_MAPPING); 2936 } 2937 2938 return found; 2939 } 2940 2941 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2942 { 2943 struct pci_dev *dev; 2944 int pos; 2945 int i, dev_no; 2946 int found = 0; 2947 2948 dev_no = host_bridge->devfn >> 3; 2949 for (i = dev_no + 1; i < 0x20; i++) { 2950 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2951 if (!dev) 2952 continue; 2953 2954 /* found next host bridge? */ 2955 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2956 if (pos != 0) { 2957 pci_dev_put(dev); 2958 break; 2959 } 2960 2961 if (ht_check_msi_mapping(dev)) { 2962 found = 1; 2963 pci_dev_put(dev); 2964 break; 2965 } 2966 pci_dev_put(dev); 2967 } 2968 2969 return found; 2970 } 2971 2972 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2973 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2974 2975 static int is_end_of_ht_chain(struct pci_dev *dev) 2976 { 2977 int pos, ctrl_off; 2978 int end = 0; 2979 u16 flags, ctrl; 2980 2981 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2982 2983 if (!pos) 2984 goto out; 2985 2986 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2987 2988 ctrl_off = ((flags >> 10) & 1) ? 2989 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2990 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2991 2992 if (ctrl & (1 << 6)) 2993 end = 1; 2994 2995 out: 2996 return end; 2997 } 2998 2999 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3000 { 3001 struct pci_dev *host_bridge; 3002 int pos; 3003 int i, dev_no; 3004 int found = 0; 3005 3006 dev_no = dev->devfn >> 3; 3007 for (i = dev_no; i >= 0; i--) { 3008 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3009 if (!host_bridge) 3010 continue; 3011 3012 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3013 if (pos != 0) { 3014 found = 1; 3015 break; 3016 } 3017 pci_dev_put(host_bridge); 3018 } 3019 3020 if (!found) 3021 return; 3022 3023 /* don't enable end_device/host_bridge with leaf directly here */ 3024 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3025 host_bridge_with_leaf(host_bridge)) 3026 goto out; 3027 3028 /* root did that ! */ 3029 if (msi_ht_cap_enabled(host_bridge)) 3030 goto out; 3031 3032 ht_enable_msi_mapping(dev); 3033 3034 out: 3035 pci_dev_put(host_bridge); 3036 } 3037 3038 static void ht_disable_msi_mapping(struct pci_dev *dev) 3039 { 3040 int pos, ttl = PCI_FIND_CAP_TTL; 3041 3042 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3043 while (pos && ttl--) { 3044 u8 flags; 3045 3046 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3047 &flags) == 0) { 3048 pci_info(dev, "Disabling HT MSI Mapping\n"); 3049 3050 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3051 flags & ~HT_MSI_FLAGS_ENABLE); 3052 } 3053 pos = pci_find_next_ht_capability(dev, pos, 3054 HT_CAPTYPE_MSI_MAPPING); 3055 } 3056 } 3057 3058 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3059 { 3060 struct pci_dev *host_bridge; 3061 int pos; 3062 int found; 3063 3064 if (!pci_msi_enabled()) 3065 return; 3066 3067 /* check if there is HT MSI cap or enabled on this device */ 3068 found = ht_check_msi_mapping(dev); 3069 3070 /* no HT MSI CAP */ 3071 if (found == 0) 3072 return; 3073 3074 /* 3075 * HT MSI mapping should be disabled on devices that are below 3076 * a non-Hypertransport host bridge. Locate the host bridge... 3077 */ 3078 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3079 PCI_DEVFN(0, 0)); 3080 if (host_bridge == NULL) { 3081 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3082 return; 3083 } 3084 3085 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3086 if (pos != 0) { 3087 /* Host bridge is to HT */ 3088 if (found == 1) { 3089 /* it is not enabled, try to enable it */ 3090 if (all) 3091 ht_enable_msi_mapping(dev); 3092 else 3093 nv_ht_enable_msi_mapping(dev); 3094 } 3095 goto out; 3096 } 3097 3098 /* HT MSI is not enabled */ 3099 if (found == 1) 3100 goto out; 3101 3102 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3103 ht_disable_msi_mapping(dev); 3104 3105 out: 3106 pci_dev_put(host_bridge); 3107 } 3108 3109 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3110 { 3111 return __nv_msi_ht_cap_quirk(dev, 1); 3112 } 3113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3115 3116 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3117 { 3118 return __nv_msi_ht_cap_quirk(dev, 0); 3119 } 3120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3121 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3122 3123 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3124 { 3125 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3126 } 3127 3128 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3129 { 3130 struct pci_dev *p; 3131 3132 /* 3133 * SB700 MSI issue will be fixed at HW level from revision A21; 3134 * we need check PCI REVISION ID of SMBus controller to get SB700 3135 * revision. 3136 */ 3137 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3138 NULL); 3139 if (!p) 3140 return; 3141 3142 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3143 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3144 pci_dev_put(p); 3145 } 3146 3147 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3148 { 3149 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3150 if (dev->revision < 0x18) { 3151 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3152 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3153 } 3154 } 3155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3156 PCI_DEVICE_ID_TIGON3_5780, 3157 quirk_msi_intx_disable_bug); 3158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3159 PCI_DEVICE_ID_TIGON3_5780S, 3160 quirk_msi_intx_disable_bug); 3161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3162 PCI_DEVICE_ID_TIGON3_5714, 3163 quirk_msi_intx_disable_bug); 3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3165 PCI_DEVICE_ID_TIGON3_5714S, 3166 quirk_msi_intx_disable_bug); 3167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3168 PCI_DEVICE_ID_TIGON3_5715, 3169 quirk_msi_intx_disable_bug); 3170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3171 PCI_DEVICE_ID_TIGON3_5715S, 3172 quirk_msi_intx_disable_bug); 3173 3174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3175 quirk_msi_intx_disable_ati_bug); 3176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3177 quirk_msi_intx_disable_ati_bug); 3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3179 quirk_msi_intx_disable_ati_bug); 3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3181 quirk_msi_intx_disable_ati_bug); 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3183 quirk_msi_intx_disable_ati_bug); 3184 3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3186 quirk_msi_intx_disable_bug); 3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3188 quirk_msi_intx_disable_bug); 3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3190 quirk_msi_intx_disable_bug); 3191 3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3193 quirk_msi_intx_disable_bug); 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3195 quirk_msi_intx_disable_bug); 3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3197 quirk_msi_intx_disable_bug); 3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3199 quirk_msi_intx_disable_bug); 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3201 quirk_msi_intx_disable_bug); 3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3203 quirk_msi_intx_disable_bug); 3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3205 quirk_msi_intx_disable_qca_bug); 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3207 quirk_msi_intx_disable_qca_bug); 3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3209 quirk_msi_intx_disable_qca_bug); 3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3211 quirk_msi_intx_disable_qca_bug); 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3213 quirk_msi_intx_disable_qca_bug); 3214 3215 /* 3216 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3217 * should be disabled on platforms where the device (mistakenly) advertises it. 3218 * 3219 * Notice that this quirk also disables MSI (which may work, but hasn't been 3220 * tested), since currently there is no standard way to disable only MSI-X. 3221 * 3222 * The 0031 device id is reused for other non Root Port device types, 3223 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3224 */ 3225 static void quirk_al_msi_disable(struct pci_dev *dev) 3226 { 3227 dev->no_msi = 1; 3228 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3229 } 3230 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3231 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3232 #endif /* CONFIG_PCI_MSI */ 3233 3234 /* 3235 * Allow manual resource allocation for PCI hotplug bridges via 3236 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3237 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3238 * allocate resources when hotplug device is inserted and PCI bus is 3239 * rescanned. 3240 */ 3241 static void quirk_hotplug_bridge(struct pci_dev *dev) 3242 { 3243 dev->is_hotplug_bridge = 1; 3244 } 3245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3246 3247 /* 3248 * This is a quirk for the Ricoh MMC controller found as a part of some 3249 * multifunction chips. 3250 * 3251 * This is very similar and based on the ricoh_mmc driver written by 3252 * Philip Langdale. Thank you for these magic sequences. 3253 * 3254 * These chips implement the four main memory card controllers (SD, MMC, 3255 * MS, xD) and one or both of CardBus or FireWire. 3256 * 3257 * It happens that they implement SD and MMC support as separate 3258 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3259 * cards but the chip detects MMC cards in hardware and directs them to the 3260 * MMC controller - so the SDHCI driver never sees them. 3261 * 3262 * To get around this, we must disable the useless MMC controller. At that 3263 * point, the SDHCI controller will start seeing them. It seems to be the 3264 * case that the relevant PCI registers to deactivate the MMC controller 3265 * live on PCI function 0, which might be the CardBus controller or the 3266 * FireWire controller, depending on the particular chip in question 3267 * 3268 * This has to be done early, because as soon as we disable the MMC controller 3269 * other PCI functions shift up one level, e.g. function #2 becomes function 3270 * #1, and this will confuse the PCI core. 3271 */ 3272 #ifdef CONFIG_MMC_RICOH_MMC 3273 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3274 { 3275 u8 write_enable; 3276 u8 write_target; 3277 u8 disable; 3278 3279 /* 3280 * Disable via CardBus interface 3281 * 3282 * This must be done via function #0 3283 */ 3284 if (PCI_FUNC(dev->devfn)) 3285 return; 3286 3287 pci_read_config_byte(dev, 0xB7, &disable); 3288 if (disable & 0x02) 3289 return; 3290 3291 pci_read_config_byte(dev, 0x8E, &write_enable); 3292 pci_write_config_byte(dev, 0x8E, 0xAA); 3293 pci_read_config_byte(dev, 0x8D, &write_target); 3294 pci_write_config_byte(dev, 0x8D, 0xB7); 3295 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3296 pci_write_config_byte(dev, 0x8E, write_enable); 3297 pci_write_config_byte(dev, 0x8D, write_target); 3298 3299 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3300 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3301 } 3302 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3304 3305 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3306 { 3307 u8 write_enable; 3308 u8 disable; 3309 3310 /* 3311 * Disable via FireWire interface 3312 * 3313 * This must be done via function #0 3314 */ 3315 if (PCI_FUNC(dev->devfn)) 3316 return; 3317 /* 3318 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3319 * certain types of SD/MMC cards. Lowering the SD base clock 3320 * frequency from 200Mhz to 50Mhz fixes this issue. 3321 * 3322 * 0x150 - SD2.0 mode enable for changing base clock 3323 * frequency to 50Mhz 3324 * 0xe1 - Base clock frequency 3325 * 0x32 - 50Mhz new clock frequency 3326 * 0xf9 - Key register for 0x150 3327 * 0xfc - key register for 0xe1 3328 */ 3329 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3330 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3331 pci_write_config_byte(dev, 0xf9, 0xfc); 3332 pci_write_config_byte(dev, 0x150, 0x10); 3333 pci_write_config_byte(dev, 0xf9, 0x00); 3334 pci_write_config_byte(dev, 0xfc, 0x01); 3335 pci_write_config_byte(dev, 0xe1, 0x32); 3336 pci_write_config_byte(dev, 0xfc, 0x00); 3337 3338 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3339 } 3340 3341 pci_read_config_byte(dev, 0xCB, &disable); 3342 3343 if (disable & 0x02) 3344 return; 3345 3346 pci_read_config_byte(dev, 0xCA, &write_enable); 3347 pci_write_config_byte(dev, 0xCA, 0x57); 3348 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3349 pci_write_config_byte(dev, 0xCA, write_enable); 3350 3351 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3352 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3353 3354 } 3355 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3356 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3357 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3358 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3359 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3360 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3361 #endif /*CONFIG_MMC_RICOH_MMC*/ 3362 3363 #ifdef CONFIG_DMAR_TABLE 3364 #define VTUNCERRMSK_REG 0x1ac 3365 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3366 /* 3367 * This is a quirk for masking VT-d spec-defined errors to platform error 3368 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3369 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3370 * on the RAS config settings of the platform) when a VT-d fault happens. 3371 * The resulting SMI caused the system to hang. 3372 * 3373 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3374 * need to report the same error through other channels. 3375 */ 3376 static void vtd_mask_spec_errors(struct pci_dev *dev) 3377 { 3378 u32 word; 3379 3380 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3381 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3382 } 3383 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3384 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3385 #endif 3386 3387 static void fixup_ti816x_class(struct pci_dev *dev) 3388 { 3389 u32 class = dev->class; 3390 3391 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3392 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3393 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3394 class, dev->class); 3395 } 3396 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3397 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3398 3399 /* 3400 * Some PCIe devices do not work reliably with the claimed maximum 3401 * payload size supported. 3402 */ 3403 static void fixup_mpss_256(struct pci_dev *dev) 3404 { 3405 dev->pcie_mpss = 1; /* 256 bytes */ 3406 } 3407 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3408 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3409 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3410 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3412 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3413 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3414 3415 /* 3416 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3417 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3418 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3419 * until all of the devices are discovered and buses walked, read completion 3420 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3421 * it is possible to hotplug a device with MPS of 256B. 3422 */ 3423 static void quirk_intel_mc_errata(struct pci_dev *dev) 3424 { 3425 int err; 3426 u16 rcc; 3427 3428 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3429 pcie_bus_config == PCIE_BUS_DEFAULT) 3430 return; 3431 3432 /* 3433 * Intel erratum specifies bits to change but does not say what 3434 * they are. Keeping them magical until such time as the registers 3435 * and values can be explained. 3436 */ 3437 err = pci_read_config_word(dev, 0x48, &rcc); 3438 if (err) { 3439 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3440 return; 3441 } 3442 3443 if (!(rcc & (1 << 10))) 3444 return; 3445 3446 rcc &= ~(1 << 10); 3447 3448 err = pci_write_config_word(dev, 0x48, rcc); 3449 if (err) { 3450 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3451 return; 3452 } 3453 3454 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3455 } 3456 /* Intel 5000 series memory controllers and ports 2-7 */ 3457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3471 /* Intel 5100 series memory controllers and ports 2-7 */ 3472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3483 3484 /* 3485 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3486 * To work around this, query the size it should be configured to by the 3487 * device and modify the resource end to correspond to this new size. 3488 */ 3489 static void quirk_intel_ntb(struct pci_dev *dev) 3490 { 3491 int rc; 3492 u8 val; 3493 3494 rc = pci_read_config_byte(dev, 0x00D0, &val); 3495 if (rc) 3496 return; 3497 3498 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3499 3500 rc = pci_read_config_byte(dev, 0x00D1, &val); 3501 if (rc) 3502 return; 3503 3504 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3505 } 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3508 3509 /* 3510 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3511 * though no one is handling them (e.g., if the i915 driver is never 3512 * loaded). Additionally the interrupt destination is not set up properly 3513 * and the interrupt ends up -somewhere-. 3514 * 3515 * These spurious interrupts are "sticky" and the kernel disables the 3516 * (shared) interrupt line after 100,000+ generated interrupts. 3517 * 3518 * Fix it by disabling the still enabled interrupts. This resolves crashes 3519 * often seen on monitor unplug. 3520 */ 3521 #define I915_DEIER_REG 0x4400c 3522 static void disable_igfx_irq(struct pci_dev *dev) 3523 { 3524 void __iomem *regs = pci_iomap(dev, 0, 0); 3525 if (regs == NULL) { 3526 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3527 return; 3528 } 3529 3530 /* Check if any interrupt line is still enabled */ 3531 if (readl(regs + I915_DEIER_REG) != 0) { 3532 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3533 3534 writel(0, regs + I915_DEIER_REG); 3535 } 3536 3537 pci_iounmap(dev, regs); 3538 } 3539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3546 3547 /* 3548 * PCI devices which are on Intel chips can skip the 10ms delay 3549 * before entering D3 mode. 3550 */ 3551 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3552 { 3553 dev->d3hot_delay = 0; 3554 } 3555 /* C600 Series devices do not need 10ms d3hot_delay */ 3556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3559 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3571 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3581 3582 /* 3583 * Some devices may pass our check in pci_intx_mask_supported() if 3584 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3585 * support this feature. 3586 */ 3587 static void quirk_broken_intx_masking(struct pci_dev *dev) 3588 { 3589 dev->broken_intx_masking = 1; 3590 } 3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3592 quirk_broken_intx_masking); 3593 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3594 quirk_broken_intx_masking); 3595 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3596 quirk_broken_intx_masking); 3597 3598 /* 3599 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3600 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3601 * 3602 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3603 */ 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3605 quirk_broken_intx_masking); 3606 3607 /* 3608 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3609 * DisINTx can be set but the interrupt status bit is non-functional. 3610 */ 3611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3627 3628 static u16 mellanox_broken_intx_devs[] = { 3629 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3630 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3631 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3632 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3633 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3634 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3635 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3636 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3637 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3638 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3639 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3640 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3641 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3642 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3643 }; 3644 3645 #define CONNECTX_4_CURR_MAX_MINOR 99 3646 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3647 3648 /* 3649 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3650 * If so, don't mark it as broken. 3651 * FW minor > 99 means older FW version format and no INTx masking support. 3652 * FW minor < 14 means new FW version format and no INTx masking support. 3653 */ 3654 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3655 { 3656 __be32 __iomem *fw_ver; 3657 u16 fw_major; 3658 u16 fw_minor; 3659 u16 fw_subminor; 3660 u32 fw_maj_min; 3661 u32 fw_sub_min; 3662 int i; 3663 3664 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3665 if (pdev->device == mellanox_broken_intx_devs[i]) { 3666 pdev->broken_intx_masking = 1; 3667 return; 3668 } 3669 } 3670 3671 /* 3672 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3673 * support so shouldn't be checked further 3674 */ 3675 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3676 return; 3677 3678 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3679 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3680 return; 3681 3682 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3683 if (pci_enable_device_mem(pdev)) { 3684 pci_warn(pdev, "Can't enable device memory\n"); 3685 return; 3686 } 3687 3688 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3689 if (!fw_ver) { 3690 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3691 goto out; 3692 } 3693 3694 /* Reading from resource space should be 32b aligned */ 3695 fw_maj_min = ioread32be(fw_ver); 3696 fw_sub_min = ioread32be(fw_ver + 1); 3697 fw_major = fw_maj_min & 0xffff; 3698 fw_minor = fw_maj_min >> 16; 3699 fw_subminor = fw_sub_min & 0xffff; 3700 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3701 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3702 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3703 fw_major, fw_minor, fw_subminor, pdev->device == 3704 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3705 pdev->broken_intx_masking = 1; 3706 } 3707 3708 iounmap(fw_ver); 3709 3710 out: 3711 pci_disable_device(pdev); 3712 } 3713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3714 mellanox_check_broken_intx_masking); 3715 3716 static void quirk_no_bus_reset(struct pci_dev *dev) 3717 { 3718 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3719 } 3720 3721 /* 3722 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3723 * prevented for those affected devices. 3724 */ 3725 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3726 { 3727 if ((dev->device & 0xffc0) == 0x2340) 3728 quirk_no_bus_reset(dev); 3729 } 3730 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3731 quirk_nvidia_no_bus_reset); 3732 3733 /* 3734 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3735 * The device will throw a Link Down error on AER-capable systems and 3736 * regardless of AER, config space of the device is never accessible again 3737 * and typically causes the system to hang or reset when access is attempted. 3738 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3739 */ 3740 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3741 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3742 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3743 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3746 3747 /* 3748 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3749 * reset when used with certain child devices. After the reset, config 3750 * accesses to the child may fail. 3751 */ 3752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3753 3754 /* 3755 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3756 * automatically disables LTSSM when Secondary Bus Reset is received and 3757 * the device stops working. Prevent bus reset for these devices. With 3758 * this change, the device can be assigned to VMs with VFIO, but it will 3759 * leak state between VMs. Reference 3760 * https://e2e.ti.com/support/processors/f/791/t/954382 3761 */ 3762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3763 3764 static void quirk_no_pm_reset(struct pci_dev *dev) 3765 { 3766 /* 3767 * We can't do a bus reset on root bus devices, but an ineffective 3768 * PM reset may be better than nothing. 3769 */ 3770 if (!pci_is_root_bus(dev->bus)) 3771 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3772 } 3773 3774 /* 3775 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3776 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3777 * to have no effect on the device: it retains the framebuffer contents and 3778 * monitor sync. Advertising this support makes other layers, like VFIO, 3779 * assume pci_reset_function() is viable for this device. Mark it as 3780 * unavailable to skip it when testing reset methods. 3781 */ 3782 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3783 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3784 3785 /* 3786 * Thunderbolt controllers with broken MSI hotplug signaling: 3787 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3788 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3789 */ 3790 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3791 { 3792 if (pdev->is_hotplug_bridge && 3793 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3794 pdev->revision <= 1)) 3795 pdev->no_msi = 1; 3796 } 3797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3798 quirk_thunderbolt_hotplug_msi); 3799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3800 quirk_thunderbolt_hotplug_msi); 3801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3802 quirk_thunderbolt_hotplug_msi); 3803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3804 quirk_thunderbolt_hotplug_msi); 3805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3806 quirk_thunderbolt_hotplug_msi); 3807 3808 #ifdef CONFIG_ACPI 3809 /* 3810 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3811 * 3812 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3813 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3814 * be present after resume if a device was plugged in before suspend. 3815 * 3816 * The Thunderbolt controller consists of a PCIe switch with downstream 3817 * bridges leading to the NHI and to the tunnel PCI bridges. 3818 * 3819 * This quirk cuts power to the whole chip. Therefore we have to apply it 3820 * during suspend_noirq of the upstream bridge. 3821 * 3822 * Power is automagically restored before resume. No action is needed. 3823 */ 3824 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3825 { 3826 acpi_handle bridge, SXIO, SXFP, SXLV; 3827 3828 if (!x86_apple_machine) 3829 return; 3830 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3831 return; 3832 3833 /* 3834 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3835 * We don't know how to turn it back on again, but firmware does, 3836 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3837 * firmware. 3838 */ 3839 if (!pm_suspend_via_firmware()) 3840 return; 3841 3842 bridge = ACPI_HANDLE(&dev->dev); 3843 if (!bridge) 3844 return; 3845 3846 /* 3847 * SXIO and SXLV are present only on machines requiring this quirk. 3848 * Thunderbolt bridges in external devices might have the same 3849 * device ID as those on the host, but they will not have the 3850 * associated ACPI methods. This implicitly checks that we are at 3851 * the right bridge. 3852 */ 3853 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3854 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3855 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3856 return; 3857 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3858 3859 /* magic sequence */ 3860 acpi_execute_simple_method(SXIO, NULL, 1); 3861 acpi_execute_simple_method(SXFP, NULL, 0); 3862 msleep(300); 3863 acpi_execute_simple_method(SXLV, NULL, 0); 3864 acpi_execute_simple_method(SXIO, NULL, 0); 3865 acpi_execute_simple_method(SXLV, NULL, 0); 3866 } 3867 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3868 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3869 quirk_apple_poweroff_thunderbolt); 3870 #endif 3871 3872 /* 3873 * Following are device-specific reset methods which can be used to 3874 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3875 * not available. 3876 */ 3877 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3878 { 3879 /* 3880 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3881 * 3882 * The 82599 supports FLR on VFs, but FLR support is reported only 3883 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3884 * Thus we must call pcie_flr() directly without first checking if it is 3885 * supported. 3886 */ 3887 if (!probe) 3888 pcie_flr(dev); 3889 return 0; 3890 } 3891 3892 #define SOUTH_CHICKEN2 0xc2004 3893 #define PCH_PP_STATUS 0xc7200 3894 #define PCH_PP_CONTROL 0xc7204 3895 #define MSG_CTL 0x45010 3896 #define NSDE_PWR_STATE 0xd0100 3897 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3898 3899 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3900 { 3901 void __iomem *mmio_base; 3902 unsigned long timeout; 3903 u32 val; 3904 3905 if (probe) 3906 return 0; 3907 3908 mmio_base = pci_iomap(dev, 0, 0); 3909 if (!mmio_base) 3910 return -ENOMEM; 3911 3912 iowrite32(0x00000002, mmio_base + MSG_CTL); 3913 3914 /* 3915 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3916 * driver loaded sets the right bits. However, this's a reset and 3917 * the bits have been set by i915 previously, so we clobber 3918 * SOUTH_CHICKEN2 register directly here. 3919 */ 3920 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3921 3922 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3923 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3924 3925 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3926 do { 3927 val = ioread32(mmio_base + PCH_PP_STATUS); 3928 if ((val & 0xb0000000) == 0) 3929 goto reset_complete; 3930 msleep(10); 3931 } while (time_before(jiffies, timeout)); 3932 pci_warn(dev, "timeout during reset\n"); 3933 3934 reset_complete: 3935 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3936 3937 pci_iounmap(dev, mmio_base); 3938 return 0; 3939 } 3940 3941 /* Device-specific reset method for Chelsio T4-based adapters */ 3942 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3943 { 3944 u16 old_command; 3945 u16 msix_flags; 3946 3947 /* 3948 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3949 * that we have no device-specific reset method. 3950 */ 3951 if ((dev->device & 0xf000) != 0x4000) 3952 return -ENOTTY; 3953 3954 /* 3955 * If this is the "probe" phase, return 0 indicating that we can 3956 * reset this device. 3957 */ 3958 if (probe) 3959 return 0; 3960 3961 /* 3962 * T4 can wedge if there are DMAs in flight within the chip and Bus 3963 * Master has been disabled. We need to have it on till the Function 3964 * Level Reset completes. (BUS_MASTER is disabled in 3965 * pci_reset_function()). 3966 */ 3967 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3968 pci_write_config_word(dev, PCI_COMMAND, 3969 old_command | PCI_COMMAND_MASTER); 3970 3971 /* 3972 * Perform the actual device function reset, saving and restoring 3973 * configuration information around the reset. 3974 */ 3975 pci_save_state(dev); 3976 3977 /* 3978 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3979 * are disabled when an MSI-X interrupt message needs to be delivered. 3980 * So we briefly re-enable MSI-X interrupts for the duration of the 3981 * FLR. The pci_restore_state() below will restore the original 3982 * MSI-X state. 3983 */ 3984 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3985 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3986 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3987 msix_flags | 3988 PCI_MSIX_FLAGS_ENABLE | 3989 PCI_MSIX_FLAGS_MASKALL); 3990 3991 pcie_flr(dev); 3992 3993 /* 3994 * Restore the configuration information (BAR values, etc.) including 3995 * the original PCI Configuration Space Command word, and return 3996 * success. 3997 */ 3998 pci_restore_state(dev); 3999 pci_write_config_word(dev, PCI_COMMAND, old_command); 4000 return 0; 4001 } 4002 4003 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4004 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4005 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4006 4007 /* 4008 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4009 * FLR where config space reads from the device return -1. We seem to be 4010 * able to avoid this condition if we disable the NVMe controller prior to 4011 * FLR. This quirk is generic for any NVMe class device requiring similar 4012 * assistance to quiesce the device prior to FLR. 4013 * 4014 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4015 * Revision 1.0e: 4016 * Chapter 2: Required and optional PCI config registers 4017 * Chapter 3: NVMe control registers 4018 * Chapter 7.3: Reset behavior 4019 */ 4020 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4021 { 4022 void __iomem *bar; 4023 u16 cmd; 4024 u32 cfg; 4025 4026 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4027 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4028 return -ENOTTY; 4029 4030 if (probe) 4031 return 0; 4032 4033 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4034 if (!bar) 4035 return -ENOTTY; 4036 4037 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4038 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4039 4040 cfg = readl(bar + NVME_REG_CC); 4041 4042 /* Disable controller if enabled */ 4043 if (cfg & NVME_CC_ENABLE) { 4044 u32 cap = readl(bar + NVME_REG_CAP); 4045 unsigned long timeout; 4046 4047 /* 4048 * Per nvme_disable_ctrl() skip shutdown notification as it 4049 * could complete commands to the admin queue. We only intend 4050 * to quiesce the device before reset. 4051 */ 4052 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4053 4054 writel(cfg, bar + NVME_REG_CC); 4055 4056 /* 4057 * Some controllers require an additional delay here, see 4058 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4059 * supported by this quirk. 4060 */ 4061 4062 /* Cap register provides max timeout in 500ms increments */ 4063 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4064 4065 for (;;) { 4066 u32 status = readl(bar + NVME_REG_CSTS); 4067 4068 /* Ready status becomes zero on disable complete */ 4069 if (!(status & NVME_CSTS_RDY)) 4070 break; 4071 4072 msleep(100); 4073 4074 if (time_after(jiffies, timeout)) { 4075 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4076 break; 4077 } 4078 } 4079 } 4080 4081 pci_iounmap(dev, bar); 4082 4083 pcie_flr(dev); 4084 4085 return 0; 4086 } 4087 4088 /* 4089 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4090 * timeout waiting for ready status to change after NVMe enable if the driver 4091 * starts interacting with the device too soon after FLR. A 250ms delay after 4092 * FLR has heuristically proven to produce reliably working results for device 4093 * assignment cases. 4094 */ 4095 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4096 { 4097 if (probe) 4098 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4099 4100 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4101 4102 msleep(250); 4103 4104 return 0; 4105 } 4106 4107 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4108 #define HINIC_VF_FLR_TYPE 0x1000 4109 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4110 #define HINIC_VF_OP 0xE80 4111 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4112 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4113 4114 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4115 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4116 { 4117 unsigned long timeout; 4118 void __iomem *bar; 4119 u32 val; 4120 4121 if (probe) 4122 return 0; 4123 4124 bar = pci_iomap(pdev, 0, 0); 4125 if (!bar) 4126 return -ENOTTY; 4127 4128 /* Get and check firmware capabilities */ 4129 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4130 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4131 pci_iounmap(pdev, bar); 4132 return -ENOTTY; 4133 } 4134 4135 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4136 val = ioread32be(bar + HINIC_VF_OP); 4137 val = val | HINIC_VF_FLR_PROC_BIT; 4138 iowrite32be(val, bar + HINIC_VF_OP); 4139 4140 pcie_flr(pdev); 4141 4142 /* 4143 * The device must recapture its Bus and Device Numbers after FLR 4144 * in order generate Completions. Issue a config write to let the 4145 * device capture this information. 4146 */ 4147 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4148 4149 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4150 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4151 do { 4152 val = ioread32be(bar + HINIC_VF_OP); 4153 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4154 goto reset_complete; 4155 msleep(20); 4156 } while (time_before(jiffies, timeout)); 4157 4158 val = ioread32be(bar + HINIC_VF_OP); 4159 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4160 goto reset_complete; 4161 4162 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4163 4164 reset_complete: 4165 pci_iounmap(pdev, bar); 4166 4167 return 0; 4168 } 4169 4170 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4171 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4172 reset_intel_82599_sfp_virtfn }, 4173 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4174 reset_ivb_igd }, 4175 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4176 reset_ivb_igd }, 4177 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4178 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4179 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4180 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4181 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4182 reset_chelsio_generic_dev }, 4183 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4184 reset_hinic_vf_dev }, 4185 { 0 } 4186 }; 4187 4188 /* 4189 * These device-specific reset methods are here rather than in a driver 4190 * because when a host assigns a device to a guest VM, the host may need 4191 * to reset the device but probably doesn't have a driver for it. 4192 */ 4193 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4194 { 4195 const struct pci_dev_reset_methods *i; 4196 4197 for (i = pci_dev_reset_methods; i->reset; i++) { 4198 if ((i->vendor == dev->vendor || 4199 i->vendor == (u16)PCI_ANY_ID) && 4200 (i->device == dev->device || 4201 i->device == (u16)PCI_ANY_ID)) 4202 return i->reset(dev, probe); 4203 } 4204 4205 return -ENOTTY; 4206 } 4207 4208 static void quirk_dma_func0_alias(struct pci_dev *dev) 4209 { 4210 if (PCI_FUNC(dev->devfn) != 0) 4211 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4212 } 4213 4214 /* 4215 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4216 * 4217 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4218 */ 4219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4221 4222 static void quirk_dma_func1_alias(struct pci_dev *dev) 4223 { 4224 if (PCI_FUNC(dev->devfn) != 1) 4225 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4226 } 4227 4228 /* 4229 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4230 * SKUs function 1 is present and is a legacy IDE controller, in other 4231 * SKUs this function is not present, making this a ghost requester. 4232 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4233 */ 4234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4235 quirk_dma_func1_alias); 4236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4237 quirk_dma_func1_alias); 4238 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4240 quirk_dma_func1_alias); 4241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4242 quirk_dma_func1_alias); 4243 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4245 quirk_dma_func1_alias); 4246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4247 quirk_dma_func1_alias); 4248 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4250 quirk_dma_func1_alias); 4251 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4253 quirk_dma_func1_alias); 4254 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4256 quirk_dma_func1_alias); 4257 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4259 quirk_dma_func1_alias); 4260 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4262 quirk_dma_func1_alias); 4263 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4265 quirk_dma_func1_alias); 4266 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4268 quirk_dma_func1_alias); 4269 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4271 quirk_dma_func1_alias); 4272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4273 quirk_dma_func1_alias); 4274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4275 quirk_dma_func1_alias); 4276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4277 quirk_dma_func1_alias); 4278 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4280 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4281 quirk_dma_func1_alias); 4282 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4283 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4284 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4285 quirk_dma_func1_alias); 4286 4287 /* 4288 * Some devices DMA with the wrong devfn, not just the wrong function. 4289 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4290 * the alias is "fixed" and independent of the device devfn. 4291 * 4292 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4293 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4294 * single device on the secondary bus. In reality, the single exposed 4295 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4296 * that provides a bridge to the internal bus of the I/O processor. The 4297 * controller supports private devices, which can be hidden from PCI config 4298 * space. In the case of the Adaptec 3405, a private device at 01.0 4299 * appears to be the DMA engine, which therefore needs to become a DMA 4300 * alias for the device. 4301 */ 4302 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4303 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4304 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4305 .driver_data = PCI_DEVFN(1, 0) }, 4306 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4307 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4308 .driver_data = PCI_DEVFN(1, 0) }, 4309 { 0 } 4310 }; 4311 4312 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4313 { 4314 const struct pci_device_id *id; 4315 4316 id = pci_match_id(fixed_dma_alias_tbl, dev); 4317 if (id) 4318 pci_add_dma_alias(dev, id->driver_data, 1); 4319 } 4320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4321 4322 /* 4323 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4324 * using the wrong DMA alias for the device. Some of these devices can be 4325 * used as either forward or reverse bridges, so we need to test whether the 4326 * device is operating in the correct mode. We could probably apply this 4327 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4328 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4329 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4330 */ 4331 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4332 { 4333 if (!pci_is_root_bus(pdev->bus) && 4334 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4335 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4336 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4337 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4338 } 4339 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4341 quirk_use_pcie_bridge_dma_alias); 4342 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4343 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4344 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4345 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4346 /* ITE 8893 has the same problem as the 8892 */ 4347 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4348 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4349 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4350 4351 /* 4352 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4353 * be added as aliases to the DMA device in order to allow buffer access 4354 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4355 * programmed in the EEPROM. 4356 */ 4357 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4358 { 4359 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4360 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4361 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4362 } 4363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4365 4366 /* 4367 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4368 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4369 * 4370 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4371 * when IOMMU is enabled. These aliases allow computational unit access to 4372 * host memory. These aliases mark the whole VCA device as one IOMMU 4373 * group. 4374 * 4375 * All possible slot numbers (0x20) are used, since we are unable to tell 4376 * what slot is used on other side. This quirk is intended for both host 4377 * and computational unit sides. The VCA devices have up to five functions 4378 * (four for DMA channels and one additional). 4379 */ 4380 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4381 { 4382 const unsigned int num_pci_slots = 0x20; 4383 unsigned int slot; 4384 4385 for (slot = 0; slot < num_pci_slots; slot++) 4386 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4387 } 4388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4390 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4391 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4393 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4394 4395 /* 4396 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4397 * associated not at the root bus, but at a bridge below. This quirk avoids 4398 * generating invalid DMA aliases. 4399 */ 4400 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4401 { 4402 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4403 } 4404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4405 quirk_bridge_cavm_thrx2_pcie_root); 4406 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4407 quirk_bridge_cavm_thrx2_pcie_root); 4408 4409 /* 4410 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4411 * class code. Fix it. 4412 */ 4413 static void quirk_tw686x_class(struct pci_dev *pdev) 4414 { 4415 u32 class = pdev->class; 4416 4417 /* Use "Multimedia controller" class */ 4418 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4419 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4420 class, pdev->class); 4421 } 4422 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4423 quirk_tw686x_class); 4424 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4425 quirk_tw686x_class); 4426 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4427 quirk_tw686x_class); 4428 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4429 quirk_tw686x_class); 4430 4431 /* 4432 * Some devices have problems with Transaction Layer Packets with the Relaxed 4433 * Ordering Attribute set. Such devices should mark themselves and other 4434 * device drivers should check before sending TLPs with RO set. 4435 */ 4436 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4437 { 4438 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4439 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4440 } 4441 4442 /* 4443 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4444 * Complex have a Flow Control Credit issue which can cause performance 4445 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4446 */ 4447 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4448 quirk_relaxedordering_disable); 4449 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4450 quirk_relaxedordering_disable); 4451 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4452 quirk_relaxedordering_disable); 4453 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4454 quirk_relaxedordering_disable); 4455 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4456 quirk_relaxedordering_disable); 4457 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4458 quirk_relaxedordering_disable); 4459 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4460 quirk_relaxedordering_disable); 4461 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4462 quirk_relaxedordering_disable); 4463 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4464 quirk_relaxedordering_disable); 4465 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4466 quirk_relaxedordering_disable); 4467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4468 quirk_relaxedordering_disable); 4469 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4470 quirk_relaxedordering_disable); 4471 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4472 quirk_relaxedordering_disable); 4473 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4474 quirk_relaxedordering_disable); 4475 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4476 quirk_relaxedordering_disable); 4477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4478 quirk_relaxedordering_disable); 4479 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4480 quirk_relaxedordering_disable); 4481 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4482 quirk_relaxedordering_disable); 4483 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4484 quirk_relaxedordering_disable); 4485 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4486 quirk_relaxedordering_disable); 4487 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4488 quirk_relaxedordering_disable); 4489 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4490 quirk_relaxedordering_disable); 4491 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4492 quirk_relaxedordering_disable); 4493 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4494 quirk_relaxedordering_disable); 4495 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4496 quirk_relaxedordering_disable); 4497 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4498 quirk_relaxedordering_disable); 4499 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4500 quirk_relaxedordering_disable); 4501 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4502 quirk_relaxedordering_disable); 4503 4504 /* 4505 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4506 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4507 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4508 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4509 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4510 * November 10, 2010). As a result, on this platform we can't use Relaxed 4511 * Ordering for Upstream TLPs. 4512 */ 4513 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4514 quirk_relaxedordering_disable); 4515 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4516 quirk_relaxedordering_disable); 4517 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4518 quirk_relaxedordering_disable); 4519 4520 /* 4521 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4522 * values for the Attribute as were supplied in the header of the 4523 * corresponding Request, except as explicitly allowed when IDO is used." 4524 * 4525 * If a non-compliant device generates a completion with a different 4526 * attribute than the request, the receiver may accept it (which itself 4527 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4528 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4529 * device access timeout. 4530 * 4531 * If the non-compliant device generates completions with zero attributes 4532 * (instead of copying the attributes from the request), we can work around 4533 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4534 * upstream devices so they always generate requests with zero attributes. 4535 * 4536 * This affects other devices under the same Root Port, but since these 4537 * attributes are performance hints, there should be no functional problem. 4538 * 4539 * Note that Configuration Space accesses are never supposed to have TLP 4540 * Attributes, so we're safe waiting till after any Configuration Space 4541 * accesses to do the Root Port fixup. 4542 */ 4543 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4544 { 4545 struct pci_dev *root_port = pcie_find_root_port(pdev); 4546 4547 if (!root_port) { 4548 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4549 return; 4550 } 4551 4552 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4553 dev_name(&pdev->dev)); 4554 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4555 PCI_EXP_DEVCTL_RELAX_EN | 4556 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4557 } 4558 4559 /* 4560 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4561 * Completion it generates. 4562 */ 4563 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4564 { 4565 /* 4566 * This mask/compare operation selects for Physical Function 4 on a 4567 * T5. We only need to fix up the Root Port once for any of the 4568 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4569 * 0x54xx so we use that one. 4570 */ 4571 if ((pdev->device & 0xff00) == 0x5400) 4572 quirk_disable_root_port_attributes(pdev); 4573 } 4574 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4575 quirk_chelsio_T5_disable_root_port_attributes); 4576 4577 /* 4578 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4579 * by a device 4580 * @acs_ctrl_req: Bitmask of desired ACS controls 4581 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4582 * the hardware design 4583 * 4584 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4585 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4586 * caller desires. Return 0 otherwise. 4587 */ 4588 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4589 { 4590 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4591 return 1; 4592 return 0; 4593 } 4594 4595 /* 4596 * AMD has indicated that the devices below do not support peer-to-peer 4597 * in any system where they are found in the southbridge with an AMD 4598 * IOMMU in the system. Multifunction devices that do not support 4599 * peer-to-peer between functions can claim to support a subset of ACS. 4600 * Such devices effectively enable request redirect (RR) and completion 4601 * redirect (CR) since all transactions are redirected to the upstream 4602 * root complex. 4603 * 4604 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4605 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4606 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4607 * 4608 * 1002:4385 SBx00 SMBus Controller 4609 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4610 * 1002:4383 SBx00 Azalia (Intel HDA) 4611 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4612 * 1002:4384 SBx00 PCI to PCI Bridge 4613 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4614 * 4615 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4616 * 4617 * 1022:780f [AMD] FCH PCI Bridge 4618 * 1022:7809 [AMD] FCH USB OHCI Controller 4619 */ 4620 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4621 { 4622 #ifdef CONFIG_ACPI 4623 struct acpi_table_header *header = NULL; 4624 acpi_status status; 4625 4626 /* Targeting multifunction devices on the SB (appears on root bus) */ 4627 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4628 return -ENODEV; 4629 4630 /* The IVRS table describes the AMD IOMMU */ 4631 status = acpi_get_table("IVRS", 0, &header); 4632 if (ACPI_FAILURE(status)) 4633 return -ENODEV; 4634 4635 acpi_put_table(header); 4636 4637 /* Filter out flags not applicable to multifunction */ 4638 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4639 4640 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4641 #else 4642 return -ENODEV; 4643 #endif 4644 } 4645 4646 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4647 { 4648 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4649 return false; 4650 4651 switch (dev->device) { 4652 /* 4653 * Effectively selects all downstream ports for whole ThunderX1 4654 * (which represents 8 SoCs). 4655 */ 4656 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4657 case 0xaf84: /* ThunderX2 */ 4658 case 0xb884: /* ThunderX3 */ 4659 return true; 4660 default: 4661 return false; 4662 } 4663 } 4664 4665 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4666 { 4667 if (!pci_quirk_cavium_acs_match(dev)) 4668 return -ENOTTY; 4669 4670 /* 4671 * Cavium Root Ports don't advertise an ACS capability. However, 4672 * the RTL internally implements similar protection as if ACS had 4673 * Source Validation, Request Redirection, Completion Redirection, 4674 * and Upstream Forwarding features enabled. Assert that the 4675 * hardware implements and enables equivalent ACS functionality for 4676 * these flags. 4677 */ 4678 return pci_acs_ctrl_enabled(acs_flags, 4679 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4680 } 4681 4682 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4683 { 4684 /* 4685 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4686 * transactions with others, allowing masking out these bits as if they 4687 * were unimplemented in the ACS capability. 4688 */ 4689 return pci_acs_ctrl_enabled(acs_flags, 4690 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4691 } 4692 4693 /* 4694 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4695 * But the implementation could block peer-to-peer transactions between them 4696 * and provide ACS-like functionality. 4697 */ 4698 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4699 { 4700 if (!pci_is_pcie(dev) || 4701 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4702 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4703 return -ENOTTY; 4704 4705 switch (dev->device) { 4706 case 0x0710 ... 0x071e: 4707 case 0x0721: 4708 case 0x0723 ... 0x0732: 4709 return pci_acs_ctrl_enabled(acs_flags, 4710 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4711 } 4712 4713 return false; 4714 } 4715 4716 /* 4717 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4718 * transactions and validate bus numbers in requests, but do not provide an 4719 * actual PCIe ACS capability. This is the list of device IDs known to fall 4720 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4721 */ 4722 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4723 /* Ibexpeak PCH */ 4724 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4725 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4726 /* Cougarpoint PCH */ 4727 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4728 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4729 /* Pantherpoint PCH */ 4730 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4731 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4732 /* Lynxpoint-H PCH */ 4733 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4734 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4735 /* Lynxpoint-LP PCH */ 4736 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4737 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4738 /* Wildcat PCH */ 4739 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4740 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4741 /* Patsburg (X79) PCH */ 4742 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4743 /* Wellsburg (X99) PCH */ 4744 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4745 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4746 /* Lynx Point (9 series) PCH */ 4747 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4748 }; 4749 4750 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4751 { 4752 int i; 4753 4754 /* Filter out a few obvious non-matches first */ 4755 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4756 return false; 4757 4758 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4759 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4760 return true; 4761 4762 return false; 4763 } 4764 4765 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4766 { 4767 if (!pci_quirk_intel_pch_acs_match(dev)) 4768 return -ENOTTY; 4769 4770 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4771 return pci_acs_ctrl_enabled(acs_flags, 4772 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4773 4774 return pci_acs_ctrl_enabled(acs_flags, 0); 4775 } 4776 4777 /* 4778 * These QCOM Root Ports do provide ACS-like features to disable peer 4779 * transactions and validate bus numbers in requests, but do not provide an 4780 * actual PCIe ACS capability. Hardware supports source validation but it 4781 * will report the issue as Completer Abort instead of ACS Violation. 4782 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4783 * Complex with unique segment numbers. It is not possible for one Root 4784 * Port to pass traffic to another Root Port. All PCIe transactions are 4785 * terminated inside the Root Port. 4786 */ 4787 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4788 { 4789 return pci_acs_ctrl_enabled(acs_flags, 4790 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4791 } 4792 4793 /* 4794 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4795 * number and does provide isolation features to disable peer transactions 4796 * and validate bus numbers in requests, but does not provide an ACS 4797 * capability. 4798 */ 4799 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4800 { 4801 return pci_acs_ctrl_enabled(acs_flags, 4802 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4803 } 4804 4805 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4806 { 4807 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4808 return -ENOTTY; 4809 4810 /* 4811 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4812 * but do include ACS-like functionality. The hardware doesn't support 4813 * peer-to-peer transactions via the root port and each has a unique 4814 * segment number. 4815 * 4816 * Additionally, the root ports cannot send traffic to each other. 4817 */ 4818 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4819 4820 return acs_flags ? 0 : 1; 4821 } 4822 4823 /* 4824 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4825 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4826 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4827 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4828 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4829 * control register is at offset 8 instead of 6 and we should probably use 4830 * dword accesses to them. This applies to the following PCI Device IDs, as 4831 * found in volume 1 of the datasheet[2]: 4832 * 4833 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4834 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4835 * 4836 * N.B. This doesn't fix what lspci shows. 4837 * 4838 * The 100 series chipset specification update includes this as errata #23[3]. 4839 * 4840 * The 200 series chipset (Union Point) has the same bug according to the 4841 * specification update (Intel 200 Series Chipset Family Platform Controller 4842 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4843 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4844 * chipset include: 4845 * 4846 * 0xa290-0xa29f PCI Express Root port #{0-16} 4847 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4848 * 4849 * Mobile chipsets are also affected, 7th & 8th Generation 4850 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4851 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4852 * Processor Family I/O for U Quad Core Platforms Specification Update, 4853 * August 2017, Revision 002, Document#: 334660-002)[6] 4854 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4855 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4856 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4857 * 4858 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4859 * 4860 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4861 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4862 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4863 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4864 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4865 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4866 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4867 */ 4868 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4869 { 4870 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4871 return false; 4872 4873 switch (dev->device) { 4874 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4875 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4876 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4877 return true; 4878 } 4879 4880 return false; 4881 } 4882 4883 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4884 4885 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4886 { 4887 int pos; 4888 u32 cap, ctrl; 4889 4890 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4891 return -ENOTTY; 4892 4893 pos = dev->acs_cap; 4894 if (!pos) 4895 return -ENOTTY; 4896 4897 /* see pci_acs_flags_enabled() */ 4898 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4899 acs_flags &= (cap | PCI_ACS_EC); 4900 4901 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4902 4903 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4904 } 4905 4906 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4907 { 4908 /* 4909 * SV, TB, and UF are not relevant to multifunction endpoints. 4910 * 4911 * Multifunction devices are only required to implement RR, CR, and DT 4912 * in their ACS capability if they support peer-to-peer transactions. 4913 * Devices matching this quirk have been verified by the vendor to not 4914 * perform peer-to-peer with other functions, allowing us to mask out 4915 * these bits as if they were unimplemented in the ACS capability. 4916 */ 4917 return pci_acs_ctrl_enabled(acs_flags, 4918 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4919 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4920 } 4921 4922 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4923 { 4924 /* 4925 * Intel RCiEP's are required to allow p2p only on translated 4926 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4927 * "Root-Complex Peer to Peer Considerations". 4928 */ 4929 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4930 return -ENOTTY; 4931 4932 return pci_acs_ctrl_enabled(acs_flags, 4933 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4934 } 4935 4936 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4937 { 4938 /* 4939 * iProc PAXB Root Ports don't advertise an ACS capability, but 4940 * they do not allow peer-to-peer transactions between Root Ports. 4941 * Allow each Root Port to be in a separate IOMMU group by masking 4942 * SV/RR/CR/UF bits. 4943 */ 4944 return pci_acs_ctrl_enabled(acs_flags, 4945 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4946 } 4947 4948 /* 4949 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function 4950 * devices, peer-to-peer transactions are not be used between the functions. 4951 * So add an ACS quirk for below devices to isolate functions. 4952 * SFxxx 1G NICs(em). 4953 * RP1000/RP2000 10G NICs(sp). 4954 */ 4955 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 4956 { 4957 switch (dev->device) { 4958 case 0x0100 ... 0x010F: 4959 case 0x1001: 4960 case 0x2001: 4961 return pci_acs_ctrl_enabled(acs_flags, 4962 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4963 } 4964 4965 return false; 4966 } 4967 4968 static const struct pci_dev_acs_enabled { 4969 u16 vendor; 4970 u16 device; 4971 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4972 } pci_dev_acs_enabled[] = { 4973 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4974 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4975 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4976 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4977 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4978 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4979 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4980 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4981 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4982 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4983 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4984 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4985 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4986 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4987 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4988 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4989 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4990 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4991 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4992 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4993 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4994 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4995 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4996 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4997 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4998 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4999 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5000 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5001 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5002 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5003 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5004 /* 82580 */ 5005 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5006 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5007 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5008 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5009 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5010 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5011 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5012 /* 82576 */ 5013 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5014 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5015 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5016 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5017 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5018 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5019 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5020 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5021 /* 82575 */ 5022 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5023 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5024 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5025 /* I350 */ 5026 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5027 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5028 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5029 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5030 /* 82571 (Quads omitted due to non-ACS switch) */ 5031 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5032 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5033 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5034 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5035 /* I219 */ 5036 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5037 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5038 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5039 /* QCOM QDF2xxx root ports */ 5040 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5041 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5042 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5043 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5044 /* Intel PCH root ports */ 5045 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5046 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5047 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5048 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5049 /* Cavium ThunderX */ 5050 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5051 /* Cavium multi-function devices */ 5052 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5053 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5054 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5055 /* APM X-Gene */ 5056 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5057 /* Ampere Computing */ 5058 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5059 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5060 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5061 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5062 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5063 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5064 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5065 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5066 /* Broadcom multi-function device */ 5067 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5068 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5069 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5070 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5071 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5072 /* Amazon Annapurna Labs */ 5073 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5074 /* Zhaoxin multi-function devices */ 5075 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5076 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5077 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5078 /* NXP root ports, xx=16, 12, or 08 cores */ 5079 /* LX2xx0A : without security features + CAN-FD */ 5080 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5081 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5082 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5083 /* LX2xx0C : security features + CAN-FD */ 5084 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5085 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5086 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5087 /* LX2xx0E : security features + CAN */ 5088 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5089 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5090 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5091 /* LX2xx0N : without security features + CAN */ 5092 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5093 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5094 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5095 /* LX2xx2A : without security features + CAN-FD */ 5096 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5097 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5098 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5099 /* LX2xx2C : security features + CAN-FD */ 5100 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5101 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5102 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5103 /* LX2xx2E : security features + CAN */ 5104 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5105 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5106 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5107 /* LX2xx2N : without security features + CAN */ 5108 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5109 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5110 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5111 /* Zhaoxin Root/Downstream Ports */ 5112 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5113 /* Wangxun nics */ 5114 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5115 { 0 } 5116 }; 5117 5118 /* 5119 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5120 * @dev: PCI device 5121 * @acs_flags: Bitmask of desired ACS controls 5122 * 5123 * Returns: 5124 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5125 * device provides the desired controls 5126 * 0: Device does not provide all the desired controls 5127 * >0: Device provides all the controls in @acs_flags 5128 */ 5129 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5130 { 5131 const struct pci_dev_acs_enabled *i; 5132 int ret; 5133 5134 /* 5135 * Allow devices that do not expose standard PCIe ACS capabilities 5136 * or control to indicate their support here. Multi-function express 5137 * devices which do not allow internal peer-to-peer between functions, 5138 * but do not implement PCIe ACS may wish to return true here. 5139 */ 5140 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5141 if ((i->vendor == dev->vendor || 5142 i->vendor == (u16)PCI_ANY_ID) && 5143 (i->device == dev->device || 5144 i->device == (u16)PCI_ANY_ID)) { 5145 ret = i->acs_enabled(dev, acs_flags); 5146 if (ret >= 0) 5147 return ret; 5148 } 5149 } 5150 5151 return -ENOTTY; 5152 } 5153 5154 /* Config space offset of Root Complex Base Address register */ 5155 #define INTEL_LPC_RCBA_REG 0xf0 5156 /* 31:14 RCBA address */ 5157 #define INTEL_LPC_RCBA_MASK 0xffffc000 5158 /* RCBA Enable */ 5159 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5160 5161 /* Backbone Scratch Pad Register */ 5162 #define INTEL_BSPR_REG 0x1104 5163 /* Backbone Peer Non-Posted Disable */ 5164 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5165 /* Backbone Peer Posted Disable */ 5166 #define INTEL_BSPR_REG_BPPD (1 << 9) 5167 5168 /* Upstream Peer Decode Configuration Register */ 5169 #define INTEL_UPDCR_REG 0x1014 5170 /* 5:0 Peer Decode Enable bits */ 5171 #define INTEL_UPDCR_REG_MASK 0x3f 5172 5173 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5174 { 5175 u32 rcba, bspr, updcr; 5176 void __iomem *rcba_mem; 5177 5178 /* 5179 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5180 * are D28:F* and therefore get probed before LPC, thus we can't 5181 * use pci_get_slot()/pci_read_config_dword() here. 5182 */ 5183 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5184 INTEL_LPC_RCBA_REG, &rcba); 5185 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5186 return -EINVAL; 5187 5188 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5189 PAGE_ALIGN(INTEL_UPDCR_REG)); 5190 if (!rcba_mem) 5191 return -ENOMEM; 5192 5193 /* 5194 * The BSPR can disallow peer cycles, but it's set by soft strap and 5195 * therefore read-only. If both posted and non-posted peer cycles are 5196 * disallowed, we're ok. If either are allowed, then we need to use 5197 * the UPDCR to disable peer decodes for each port. This provides the 5198 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5199 */ 5200 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5201 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5202 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5203 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5204 if (updcr & INTEL_UPDCR_REG_MASK) { 5205 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5206 updcr &= ~INTEL_UPDCR_REG_MASK; 5207 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5208 } 5209 } 5210 5211 iounmap(rcba_mem); 5212 return 0; 5213 } 5214 5215 /* Miscellaneous Port Configuration register */ 5216 #define INTEL_MPC_REG 0xd8 5217 /* MPC: Invalid Receive Bus Number Check Enable */ 5218 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5219 5220 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5221 { 5222 u32 mpc; 5223 5224 /* 5225 * When enabled, the IRBNCE bit of the MPC register enables the 5226 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5227 * ensures that requester IDs fall within the bus number range 5228 * of the bridge. Enable if not already. 5229 */ 5230 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5231 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5232 pci_info(dev, "Enabling MPC IRBNCE\n"); 5233 mpc |= INTEL_MPC_REG_IRBNCE; 5234 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5235 } 5236 } 5237 5238 /* 5239 * Currently this quirk does the equivalent of 5240 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5241 * 5242 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5243 * if dev->external_facing || dev->untrusted 5244 */ 5245 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5246 { 5247 if (!pci_quirk_intel_pch_acs_match(dev)) 5248 return -ENOTTY; 5249 5250 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5251 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5252 return 0; 5253 } 5254 5255 pci_quirk_enable_intel_rp_mpc_acs(dev); 5256 5257 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5258 5259 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5260 5261 return 0; 5262 } 5263 5264 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5265 { 5266 int pos; 5267 u32 cap, ctrl; 5268 5269 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5270 return -ENOTTY; 5271 5272 pos = dev->acs_cap; 5273 if (!pos) 5274 return -ENOTTY; 5275 5276 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5277 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5278 5279 ctrl |= (cap & PCI_ACS_SV); 5280 ctrl |= (cap & PCI_ACS_RR); 5281 ctrl |= (cap & PCI_ACS_CR); 5282 ctrl |= (cap & PCI_ACS_UF); 5283 5284 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5285 ctrl |= (cap & PCI_ACS_TB); 5286 5287 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5288 5289 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5290 5291 return 0; 5292 } 5293 5294 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5295 { 5296 int pos; 5297 u32 cap, ctrl; 5298 5299 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5300 return -ENOTTY; 5301 5302 pos = dev->acs_cap; 5303 if (!pos) 5304 return -ENOTTY; 5305 5306 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5307 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5308 5309 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5310 5311 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5312 5313 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5314 5315 return 0; 5316 } 5317 5318 static const struct pci_dev_acs_ops { 5319 u16 vendor; 5320 u16 device; 5321 int (*enable_acs)(struct pci_dev *dev); 5322 int (*disable_acs_redir)(struct pci_dev *dev); 5323 } pci_dev_acs_ops[] = { 5324 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5325 .enable_acs = pci_quirk_enable_intel_pch_acs, 5326 }, 5327 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5328 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5329 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5330 }, 5331 }; 5332 5333 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5334 { 5335 const struct pci_dev_acs_ops *p; 5336 int i, ret; 5337 5338 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5339 p = &pci_dev_acs_ops[i]; 5340 if ((p->vendor == dev->vendor || 5341 p->vendor == (u16)PCI_ANY_ID) && 5342 (p->device == dev->device || 5343 p->device == (u16)PCI_ANY_ID) && 5344 p->enable_acs) { 5345 ret = p->enable_acs(dev); 5346 if (ret >= 0) 5347 return ret; 5348 } 5349 } 5350 5351 return -ENOTTY; 5352 } 5353 5354 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5355 { 5356 const struct pci_dev_acs_ops *p; 5357 int i, ret; 5358 5359 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5360 p = &pci_dev_acs_ops[i]; 5361 if ((p->vendor == dev->vendor || 5362 p->vendor == (u16)PCI_ANY_ID) && 5363 (p->device == dev->device || 5364 p->device == (u16)PCI_ANY_ID) && 5365 p->disable_acs_redir) { 5366 ret = p->disable_acs_redir(dev); 5367 if (ret >= 0) 5368 return ret; 5369 } 5370 } 5371 5372 return -ENOTTY; 5373 } 5374 5375 /* 5376 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5377 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5378 * Next Capability pointer in the MSI Capability Structure should point to 5379 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5380 * the list. 5381 */ 5382 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5383 { 5384 int pos, i = 0; 5385 u8 next_cap; 5386 u16 reg16, *cap; 5387 struct pci_cap_saved_state *state; 5388 5389 /* Bail if the hardware bug is fixed */ 5390 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5391 return; 5392 5393 /* Bail if MSI Capability Structure is not found for some reason */ 5394 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5395 if (!pos) 5396 return; 5397 5398 /* 5399 * Bail if Next Capability pointer in the MSI Capability Structure 5400 * is not the expected incorrect 0x00. 5401 */ 5402 pci_read_config_byte(pdev, pos + 1, &next_cap); 5403 if (next_cap) 5404 return; 5405 5406 /* 5407 * PCIe Capability Structure is expected to be at 0x50 and should 5408 * terminate the list (Next Capability pointer is 0x00). Verify 5409 * Capability Id and Next Capability pointer is as expected. 5410 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5411 * to correctly set kernel data structures which have already been 5412 * set incorrectly due to the hardware bug. 5413 */ 5414 pos = 0x50; 5415 pci_read_config_word(pdev, pos, ®16); 5416 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5417 u32 status; 5418 #ifndef PCI_EXP_SAVE_REGS 5419 #define PCI_EXP_SAVE_REGS 7 5420 #endif 5421 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5422 5423 pdev->pcie_cap = pos; 5424 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5425 pdev->pcie_flags_reg = reg16; 5426 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5427 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5428 5429 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5430 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 5431 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 5432 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5433 5434 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5435 return; 5436 5437 /* Save PCIe cap */ 5438 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5439 if (!state) 5440 return; 5441 5442 state->cap.cap_nr = PCI_CAP_ID_EXP; 5443 state->cap.cap_extended = 0; 5444 state->cap.size = size; 5445 cap = (u16 *)&state->cap.data[0]; 5446 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5447 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5448 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5449 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5450 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5451 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5452 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5453 hlist_add_head(&state->next, &pdev->saved_cap_space); 5454 } 5455 } 5456 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5457 5458 /* 5459 * FLR may cause the following to devices to hang: 5460 * 5461 * AMD Starship/Matisse HD Audio Controller 0x1487 5462 * AMD Starship USB 3.0 Host Controller 0x148c 5463 * AMD Matisse USB 3.0 Host Controller 0x149c 5464 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5465 * Intel 82579V Gigabit Ethernet Controller 0x1503 5466 * 5467 */ 5468 static void quirk_no_flr(struct pci_dev *dev) 5469 { 5470 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5471 } 5472 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5473 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5474 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5475 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5476 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5477 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5478 5479 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5480 static void quirk_no_flr_snet(struct pci_dev *dev) 5481 { 5482 if (dev->revision == 0x1) 5483 quirk_no_flr(dev); 5484 } 5485 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5486 5487 static void quirk_no_ext_tags(struct pci_dev *pdev) 5488 { 5489 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5490 5491 if (!bridge) 5492 return; 5493 5494 bridge->no_ext_tags = 1; 5495 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5496 5497 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5498 } 5499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5500 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5502 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5503 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5504 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5505 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5506 5507 #ifdef CONFIG_PCI_ATS 5508 /* 5509 * Some devices require additional driver setup to enable ATS. Don't use 5510 * ATS for those devices as ATS will be enabled before the driver has had a 5511 * chance to load and configure the device. 5512 */ 5513 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5514 { 5515 if (pdev->device == 0x15d8) { 5516 if (pdev->revision == 0xcf && 5517 pdev->subsystem_vendor == 0xea50 && 5518 (pdev->subsystem_device == 0xce19 || 5519 pdev->subsystem_device == 0xcc10 || 5520 pdev->subsystem_device == 0xcc08)) 5521 goto no_ats; 5522 else 5523 return; 5524 } 5525 5526 no_ats: 5527 pci_info(pdev, "disabling ATS\n"); 5528 pdev->ats_cap = 0; 5529 } 5530 5531 /* AMD Stoney platform GPU */ 5532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5533 /* AMD Iceland dGPU */ 5534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5535 /* AMD Navi10 dGPU */ 5536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5544 /* AMD Navi14 dGPU */ 5545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5549 /* AMD Raven platform iGPU */ 5550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5551 #endif /* CONFIG_PCI_ATS */ 5552 5553 /* Freescale PCIe doesn't support MSI in RC mode */ 5554 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5555 { 5556 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5557 pdev->no_msi = 1; 5558 } 5559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5560 5561 /* 5562 * Although not allowed by the spec, some multi-function devices have 5563 * dependencies of one function (consumer) on another (supplier). For the 5564 * consumer to work in D0, the supplier must also be in D0. Create a 5565 * device link from the consumer to the supplier to enforce this 5566 * dependency. Runtime PM is allowed by default on the consumer to prevent 5567 * it from permanently keeping the supplier awake. 5568 */ 5569 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5570 unsigned int supplier, unsigned int class, 5571 unsigned int class_shift) 5572 { 5573 struct pci_dev *supplier_pdev; 5574 5575 if (PCI_FUNC(pdev->devfn) != consumer) 5576 return; 5577 5578 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5579 pdev->bus->number, 5580 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5581 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5582 pci_dev_put(supplier_pdev); 5583 return; 5584 } 5585 5586 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5587 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5588 pci_info(pdev, "D0 power state depends on %s\n", 5589 pci_name(supplier_pdev)); 5590 else 5591 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5592 pci_name(supplier_pdev)); 5593 5594 pm_runtime_allow(&pdev->dev); 5595 pci_dev_put(supplier_pdev); 5596 } 5597 5598 /* 5599 * Create device link for GPUs with integrated HDA controller for streaming 5600 * audio to attached displays. 5601 */ 5602 static void quirk_gpu_hda(struct pci_dev *hda) 5603 { 5604 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5605 } 5606 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5607 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5608 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5609 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5610 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5611 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5612 5613 /* 5614 * Create device link for GPUs with integrated USB xHCI Host 5615 * controller to VGA. 5616 */ 5617 static void quirk_gpu_usb(struct pci_dev *usb) 5618 { 5619 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5620 } 5621 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5622 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5623 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5624 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5625 5626 /* 5627 * Create device link for GPUs with integrated Type-C UCSI controller 5628 * to VGA. Currently there is no class code defined for UCSI device over PCI 5629 * so using UNKNOWN class for now and it will be updated when UCSI 5630 * over PCI gets a class code. 5631 */ 5632 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5633 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5634 { 5635 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5636 } 5637 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5638 PCI_CLASS_SERIAL_UNKNOWN, 8, 5639 quirk_gpu_usb_typec_ucsi); 5640 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5641 PCI_CLASS_SERIAL_UNKNOWN, 8, 5642 quirk_gpu_usb_typec_ucsi); 5643 5644 /* 5645 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5646 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5647 */ 5648 static void quirk_nvidia_hda(struct pci_dev *gpu) 5649 { 5650 u8 hdr_type; 5651 u32 val; 5652 5653 /* There was no integrated HDA controller before MCP89 */ 5654 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5655 return; 5656 5657 /* Bit 25 at offset 0x488 enables the HDA controller */ 5658 pci_read_config_dword(gpu, 0x488, &val); 5659 if (val & BIT(25)) 5660 return; 5661 5662 pci_info(gpu, "Enabling HDA controller\n"); 5663 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5664 5665 /* The GPU becomes a multi-function device when the HDA is enabled */ 5666 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5667 gpu->multifunction = !!(hdr_type & 0x80); 5668 } 5669 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5670 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5671 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5672 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5673 5674 /* 5675 * Some IDT switches incorrectly flag an ACS Source Validation error on 5676 * completions for config read requests even though PCIe r4.0, sec 5677 * 6.12.1.1, says that completions are never affected by ACS Source 5678 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5679 * 5680 * Item #36 - Downstream port applies ACS Source Validation to Completions 5681 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5682 * completions are never affected by ACS Source Validation. However, 5683 * completions received by a downstream port of the PCIe switch from a 5684 * device that has not yet captured a PCIe bus number are incorrectly 5685 * dropped by ACS Source Validation by the switch downstream port. 5686 * 5687 * The workaround suggested by IDT is to issue a config write to the 5688 * downstream device before issuing the first config read. This allows the 5689 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5690 * sec 2.2.9), thus avoiding the ACS error on the completion. 5691 * 5692 * However, we don't know when the device is ready to accept the config 5693 * write, so we do config reads until we receive a non-Config Request Retry 5694 * Status, then do the config write. 5695 * 5696 * To avoid hitting the erratum when doing the config reads, we disable ACS 5697 * SV around this process. 5698 */ 5699 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5700 { 5701 int pos; 5702 u16 ctrl = 0; 5703 bool found; 5704 struct pci_dev *bridge = bus->self; 5705 5706 pos = bridge->acs_cap; 5707 5708 /* Disable ACS SV before initial config reads */ 5709 if (pos) { 5710 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5711 if (ctrl & PCI_ACS_SV) 5712 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5713 ctrl & ~PCI_ACS_SV); 5714 } 5715 5716 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5717 5718 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5719 if (found) 5720 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5721 5722 /* Re-enable ACS_SV if it was previously enabled */ 5723 if (ctrl & PCI_ACS_SV) 5724 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5725 5726 return found; 5727 } 5728 5729 /* 5730 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5731 * NT endpoints via the internal switch fabric. These IDs replace the 5732 * originating requestor ID TLPs which access host memory on peer NTB 5733 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5734 * to permit access when the IOMMU is turned on. 5735 */ 5736 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5737 { 5738 void __iomem *mmio; 5739 struct ntb_info_regs __iomem *mmio_ntb; 5740 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5741 u64 partition_map; 5742 u8 partition; 5743 int pp; 5744 5745 if (pci_enable_device(pdev)) { 5746 pci_err(pdev, "Cannot enable Switchtec device\n"); 5747 return; 5748 } 5749 5750 mmio = pci_iomap(pdev, 0, 0); 5751 if (mmio == NULL) { 5752 pci_disable_device(pdev); 5753 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5754 return; 5755 } 5756 5757 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5758 5759 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5760 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5761 5762 partition = ioread8(&mmio_ntb->partition_id); 5763 5764 partition_map = ioread32(&mmio_ntb->ep_map); 5765 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5766 partition_map &= ~(1ULL << partition); 5767 5768 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5769 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5770 u32 table_sz = 0; 5771 int te; 5772 5773 if (!(partition_map & (1ULL << pp))) 5774 continue; 5775 5776 pci_dbg(pdev, "Processing partition %d\n", pp); 5777 5778 mmio_peer_ctrl = &mmio_ctrl[pp]; 5779 5780 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5781 if (!table_sz) { 5782 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5783 continue; 5784 } 5785 5786 if (table_sz > 512) { 5787 pci_warn(pdev, 5788 "Invalid Switchtec partition %d table_sz %d\n", 5789 pp, table_sz); 5790 continue; 5791 } 5792 5793 for (te = 0; te < table_sz; te++) { 5794 u32 rid_entry; 5795 u8 devfn; 5796 5797 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5798 devfn = (rid_entry >> 1) & 0xFF; 5799 pci_dbg(pdev, 5800 "Aliasing Partition %d Proxy ID %02x.%d\n", 5801 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5802 pci_add_dma_alias(pdev, devfn, 1); 5803 } 5804 } 5805 5806 pci_iounmap(pdev, mmio); 5807 pci_disable_device(pdev); 5808 } 5809 #define SWITCHTEC_QUIRK(vid) \ 5810 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5811 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5812 5813 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5814 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5815 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5816 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5817 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5818 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5819 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5820 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5821 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5822 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5823 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5824 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5825 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5826 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5827 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5828 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5829 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5830 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5831 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5832 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5833 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5834 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5835 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5836 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5837 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5838 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5839 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5840 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5841 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5842 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5843 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5844 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5845 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5846 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5847 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5848 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5849 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5850 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5851 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5852 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5853 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5854 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5855 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5856 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5857 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5858 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5859 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5860 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5861 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 5862 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 5863 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 5864 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 5865 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 5866 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 5867 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 5868 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 5869 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 5870 5871 /* 5872 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5873 * These IDs are used to forward responses to the originator on the other 5874 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5875 * the IOMMU is turned on. 5876 */ 5877 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5878 { 5879 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5880 /* PLX NTB may use all 256 devfns */ 5881 pci_add_dma_alias(pdev, 0, 256); 5882 } 5883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 5884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 5885 5886 /* 5887 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 5888 * not always reset the secondary Nvidia GPU between reboots if the system 5889 * is configured to use Hybrid Graphics mode. This results in the GPU 5890 * being left in whatever state it was in during the *previous* boot, which 5891 * causes spurious interrupts from the GPU, which in turn causes us to 5892 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 5893 * this also completely breaks nouveau. 5894 * 5895 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 5896 * clean state and fixes all these issues. 5897 * 5898 * When the machine is configured in Dedicated display mode, the issue 5899 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 5900 * mode, so we can detect that and avoid resetting it. 5901 */ 5902 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 5903 { 5904 void __iomem *map; 5905 int ret; 5906 5907 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 5908 pdev->subsystem_device != 0x222e || 5909 !pci_reset_supported(pdev)) 5910 return; 5911 5912 if (pci_enable_device_mem(pdev)) 5913 return; 5914 5915 /* 5916 * Based on nvkm_device_ctor() in 5917 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 5918 */ 5919 map = pci_iomap(pdev, 0, 0x23000); 5920 if (!map) { 5921 pci_err(pdev, "Can't map MMIO space\n"); 5922 goto out_disable; 5923 } 5924 5925 /* 5926 * Make sure the GPU looks like it's been POSTed before resetting 5927 * it. 5928 */ 5929 if (ioread32(map + 0x2240c) & 0x2) { 5930 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 5931 ret = pci_reset_bus(pdev); 5932 if (ret < 0) 5933 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 5934 } 5935 5936 iounmap(map); 5937 out_disable: 5938 pci_disable_device(pdev); 5939 } 5940 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 5941 PCI_CLASS_DISPLAY_VGA, 8, 5942 quirk_reset_lenovo_thinkpad_p50_nvgpu); 5943 5944 /* 5945 * Device [1b21:2142] 5946 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 5947 */ 5948 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 5949 { 5950 pci_info(dev, "PME# does not work under D0, disabling it\n"); 5951 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 5952 } 5953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 5954 5955 /* 5956 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 5957 * 5958 * These devices advertise PME# support in all power states but don't 5959 * reliably assert it. 5960 * 5961 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 5962 * says "The MSI Function is not implemented on this device" in chapters 5963 * 7.3.27, 7.3.29-7.3.31. 5964 */ 5965 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 5966 { 5967 #ifdef CONFIG_PCI_MSI 5968 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 5969 dev->no_msi = 1; 5970 #endif 5971 pci_info(dev, "PME# is unreliable, disabling it\n"); 5972 dev->pme_support = 0; 5973 } 5974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 5975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 5976 5977 static void apex_pci_fixup_class(struct pci_dev *pdev) 5978 { 5979 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 5980 } 5981 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 5982 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 5983 5984 /* 5985 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 5986 * ACS P2P Request Redirect is not functional 5987 * 5988 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 5989 * between upstream and downstream ports, packets are queued in an internal 5990 * buffer until CPLD packet. The workaround is to use the switch in store and 5991 * forward mode. 5992 */ 5993 #define PI7C9X2Gxxx_MODE_REG 0x74 5994 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 5995 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 5996 { 5997 struct pci_dev *upstream; 5998 u16 val; 5999 6000 /* Downstream ports only */ 6001 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6002 return; 6003 6004 /* Check for ACS P2P Request Redirect use */ 6005 if (!pdev->acs_cap) 6006 return; 6007 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6008 if (!(val & PCI_ACS_RR)) 6009 return; 6010 6011 upstream = pci_upstream_bridge(pdev); 6012 if (!upstream) 6013 return; 6014 6015 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6016 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6017 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6018 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6019 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6020 } 6021 } 6022 /* 6023 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6024 * ACS configuration changes or switch mode is reset 6025 */ 6026 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6027 pci_fixup_pericom_acs_store_forward); 6028 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6029 pci_fixup_pericom_acs_store_forward); 6030 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6031 pci_fixup_pericom_acs_store_forward); 6032 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6033 pci_fixup_pericom_acs_store_forward); 6034 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6035 pci_fixup_pericom_acs_store_forward); 6036 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6037 pci_fixup_pericom_acs_store_forward); 6038 6039 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6040 { 6041 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6042 } 6043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6044 6045 static void rom_bar_overlap_defect(struct pci_dev *dev) 6046 { 6047 pci_info(dev, "working around ROM BAR overlap defect\n"); 6048 dev->rom_bar_overlap = 1; 6049 } 6050 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6051 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6052 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6053 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6054 6055 #ifdef CONFIG_PCIEASPM 6056 /* 6057 * Several Intel DG2 graphics devices advertise that they can only tolerate 6058 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6059 * from being enabled. But in fact these devices can tolerate unlimited 6060 * latency. Override their Device Capabilities value to allow ASPM L1 to 6061 * be enabled. 6062 */ 6063 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6064 { 6065 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6066 6067 if (l1_lat < 7) { 6068 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6069 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6070 l1_lat); 6071 } 6072 } 6073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6099 #endif 6100 6101 #ifdef CONFIG_PCIE_DPC 6102 /* 6103 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6104 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6105 * Ports. 6106 */ 6107 static void dpc_log_size(struct pci_dev *dev) 6108 { 6109 u16 dpc, val; 6110 6111 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6112 if (!dpc) 6113 return; 6114 6115 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6116 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6117 return; 6118 6119 if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) { 6120 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); 6121 dev->dpc_rp_log_size = 4; 6122 } 6123 } 6124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6140 #endif 6141