1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <linux/ioport.h> 24 #include <linux/sched.h> 25 #include <linux/ktime.h> 26 #include <linux/mm.h> 27 #include <linux/nvme.h> 28 #include <linux/platform_data/x86/apple.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/suspend.h> 31 #include <linux/switchtec.h> 32 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 33 #include "pci.h" 34 35 static ktime_t fixup_debug_start(struct pci_dev *dev, 36 void (*fn)(struct pci_dev *dev)) 37 { 38 if (initcall_debug) 39 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 40 41 return ktime_get(); 42 } 43 44 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 45 void (*fn)(struct pci_dev *dev)) 46 { 47 ktime_t delta, rettime; 48 unsigned long long duration; 49 50 rettime = ktime_get(); 51 delta = ktime_sub(rettime, calltime); 52 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 53 if (initcall_debug || duration > 10000) 54 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 55 } 56 57 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 58 struct pci_fixup *end) 59 { 60 ktime_t calltime; 61 62 for (; f < end; f++) 63 if ((f->class == (u32) (dev->class >> f->class_shift) || 64 f->class == (u32) PCI_ANY_ID) && 65 (f->vendor == dev->vendor || 66 f->vendor == (u16) PCI_ANY_ID) && 67 (f->device == dev->device || 68 f->device == (u16) PCI_ANY_ID)) { 69 void (*hook)(struct pci_dev *dev); 70 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 71 hook = offset_to_ptr(&f->hook_offset); 72 #else 73 hook = f->hook; 74 #endif 75 calltime = fixup_debug_start(dev, hook); 76 hook(dev); 77 fixup_debug_report(dev, calltime, hook); 78 } 79 } 80 81 extern struct pci_fixup __start_pci_fixups_early[]; 82 extern struct pci_fixup __end_pci_fixups_early[]; 83 extern struct pci_fixup __start_pci_fixups_header[]; 84 extern struct pci_fixup __end_pci_fixups_header[]; 85 extern struct pci_fixup __start_pci_fixups_final[]; 86 extern struct pci_fixup __end_pci_fixups_final[]; 87 extern struct pci_fixup __start_pci_fixups_enable[]; 88 extern struct pci_fixup __end_pci_fixups_enable[]; 89 extern struct pci_fixup __start_pci_fixups_resume[]; 90 extern struct pci_fixup __end_pci_fixups_resume[]; 91 extern struct pci_fixup __start_pci_fixups_resume_early[]; 92 extern struct pci_fixup __end_pci_fixups_resume_early[]; 93 extern struct pci_fixup __start_pci_fixups_suspend[]; 94 extern struct pci_fixup __end_pci_fixups_suspend[]; 95 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 96 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 97 98 static bool pci_apply_fixup_final_quirks; 99 100 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 101 { 102 struct pci_fixup *start, *end; 103 104 switch (pass) { 105 case pci_fixup_early: 106 start = __start_pci_fixups_early; 107 end = __end_pci_fixups_early; 108 break; 109 110 case pci_fixup_header: 111 start = __start_pci_fixups_header; 112 end = __end_pci_fixups_header; 113 break; 114 115 case pci_fixup_final: 116 if (!pci_apply_fixup_final_quirks) 117 return; 118 start = __start_pci_fixups_final; 119 end = __end_pci_fixups_final; 120 break; 121 122 case pci_fixup_enable: 123 start = __start_pci_fixups_enable; 124 end = __end_pci_fixups_enable; 125 break; 126 127 case pci_fixup_resume: 128 start = __start_pci_fixups_resume; 129 end = __end_pci_fixups_resume; 130 break; 131 132 case pci_fixup_resume_early: 133 start = __start_pci_fixups_resume_early; 134 end = __end_pci_fixups_resume_early; 135 break; 136 137 case pci_fixup_suspend: 138 start = __start_pci_fixups_suspend; 139 end = __end_pci_fixups_suspend; 140 break; 141 142 case pci_fixup_suspend_late: 143 start = __start_pci_fixups_suspend_late; 144 end = __end_pci_fixups_suspend_late; 145 break; 146 147 default: 148 /* stupid compiler warning, you would think with an enum... */ 149 return; 150 } 151 pci_do_fixups(dev, start, end); 152 } 153 EXPORT_SYMBOL(pci_fixup_device); 154 155 static int __init pci_apply_final_quirks(void) 156 { 157 struct pci_dev *dev = NULL; 158 u8 cls = 0; 159 u8 tmp; 160 161 if (pci_cache_line_size) 162 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 163 164 pci_apply_fixup_final_quirks = true; 165 for_each_pci_dev(dev) { 166 pci_fixup_device(pci_fixup_final, dev); 167 /* 168 * If arch hasn't set it explicitly yet, use the CLS 169 * value shared by all PCI devices. If there's a 170 * mismatch, fall back to the default value. 171 */ 172 if (!pci_cache_line_size) { 173 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 174 if (!cls) 175 cls = tmp; 176 if (!tmp || cls == tmp) 177 continue; 178 179 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 180 cls << 2, tmp << 2, 181 pci_dfl_cache_line_size << 2); 182 pci_cache_line_size = pci_dfl_cache_line_size; 183 } 184 } 185 186 if (!pci_cache_line_size) { 187 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 188 pci_dfl_cache_line_size << 2); 189 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 190 } 191 192 return 0; 193 } 194 fs_initcall_sync(pci_apply_final_quirks); 195 196 /* 197 * Decoding should be disabled for a PCI device during BAR sizing to avoid 198 * conflict. But doing so may cause problems on host bridge and perhaps other 199 * key system devices. For devices that need to have mmio decoding always-on, 200 * we need to set the dev->mmio_always_on bit. 201 */ 202 static void quirk_mmio_always_on(struct pci_dev *dev) 203 { 204 dev->mmio_always_on = 1; 205 } 206 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 207 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 208 209 /* 210 * The Mellanox Tavor device gives false positive parity errors. Disable 211 * parity error reporting. 212 */ 213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 215 216 /* 217 * Deal with broken BIOSes that neglect to enable passive release, 218 * which can cause problems in combination with the 82441FX/PPro MTRRs 219 */ 220 static void quirk_passive_release(struct pci_dev *dev) 221 { 222 struct pci_dev *d = NULL; 223 unsigned char dlc; 224 225 /* 226 * We have to make sure a particular bit is set in the PIIX3 227 * ISA bridge, so we have to go out and find it. 228 */ 229 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 230 pci_read_config_byte(d, 0x82, &dlc); 231 if (!(dlc & 1<<1)) { 232 pci_info(d, "PIIX3: Enabling Passive Release\n"); 233 dlc |= 1<<1; 234 pci_write_config_byte(d, 0x82, dlc); 235 } 236 } 237 } 238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 240 241 /* 242 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 243 * workaround but VIA don't answer queries. If you happen to have good 244 * contacts at VIA ask them for me please -- Alan 245 * 246 * This appears to be BIOS not version dependent. So presumably there is a 247 * chipset level fix. 248 */ 249 static void quirk_isa_dma_hangs(struct pci_dev *dev) 250 { 251 if (!isa_dma_bridge_buggy) { 252 isa_dma_bridge_buggy = 1; 253 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 254 } 255 } 256 /* 257 * It's not totally clear which chipsets are the problematic ones. We know 258 * 82C586 and 82C596 variants are affected. 259 */ 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 267 268 /* 269 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 270 * for some HT machines to use C4 w/o hanging. 271 */ 272 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 273 { 274 u32 pmbase; 275 u16 pm1a; 276 277 pci_read_config_dword(dev, 0x40, &pmbase); 278 pmbase = pmbase & 0xff80; 279 pm1a = inw(pmbase); 280 281 if (pm1a & 0x10) { 282 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 283 outw(0x10, pmbase); 284 } 285 } 286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 287 288 /* Chipsets where PCI->PCI transfers vanish or hang */ 289 static void quirk_nopcipci(struct pci_dev *dev) 290 { 291 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 292 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 293 pci_pci_problems |= PCIPCI_FAIL; 294 } 295 } 296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 298 299 static void quirk_nopciamd(struct pci_dev *dev) 300 { 301 u8 rev; 302 pci_read_config_byte(dev, 0x08, &rev); 303 if (rev == 0x13) { 304 /* Erratum 24 */ 305 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 306 pci_pci_problems |= PCIAGP_FAIL; 307 } 308 } 309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 310 311 /* Triton requires workarounds to be used by the drivers */ 312 static void quirk_triton(struct pci_dev *dev) 313 { 314 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 315 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 316 pci_pci_problems |= PCIPCI_TRITON; 317 } 318 } 319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 323 324 /* 325 * VIA Apollo KT133 needs PCI latency patch 326 * Made according to a Windows driver-based patch by George E. Breese; 327 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 328 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 329 * which Mr Breese based his work. 330 * 331 * Updated based on further information from the site and also on 332 * information provided by VIA 333 */ 334 static void quirk_vialatency(struct pci_dev *dev) 335 { 336 struct pci_dev *p; 337 u8 busarb; 338 339 /* 340 * Ok, we have a potential problem chipset here. Now see if we have 341 * a buggy southbridge. 342 */ 343 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 344 if (p != NULL) { 345 346 /* 347 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 348 * thanks Dan Hollis. 349 * Check for buggy part revisions 350 */ 351 if (p->revision < 0x40 || p->revision > 0x42) 352 goto exit; 353 } else { 354 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 355 if (p == NULL) /* No problem parts */ 356 goto exit; 357 358 /* Check for buggy part revisions */ 359 if (p->revision < 0x10 || p->revision > 0x12) 360 goto exit; 361 } 362 363 /* 364 * Ok we have the problem. Now set the PCI master grant to occur 365 * every master grant. The apparent bug is that under high PCI load 366 * (quite common in Linux of course) you can get data loss when the 367 * CPU is held off the bus for 3 bus master requests. This happens 368 * to include the IDE controllers.... 369 * 370 * VIA only apply this fix when an SB Live! is present but under 371 * both Linux and Windows this isn't enough, and we have seen 372 * corruption without SB Live! but with things like 3 UDMA IDE 373 * controllers. So we ignore that bit of the VIA recommendation.. 374 */ 375 pci_read_config_byte(dev, 0x76, &busarb); 376 377 /* 378 * Set bit 4 and bit 5 of byte 76 to 0x01 379 * "Master priority rotation on every PCI master grant" 380 */ 381 busarb &= ~(1<<5); 382 busarb |= (1<<4); 383 pci_write_config_byte(dev, 0x76, busarb); 384 pci_info(dev, "Applying VIA southbridge workaround\n"); 385 exit: 386 pci_dev_put(p); 387 } 388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 391 /* Must restore this on a resume from RAM */ 392 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 393 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 394 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 395 396 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 397 static void quirk_viaetbf(struct pci_dev *dev) 398 { 399 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 400 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 401 pci_pci_problems |= PCIPCI_VIAETBF; 402 } 403 } 404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 405 406 static void quirk_vsfx(struct pci_dev *dev) 407 { 408 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 409 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 410 pci_pci_problems |= PCIPCI_VSFX; 411 } 412 } 413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 414 415 /* 416 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 417 * space. Latency must be set to 0xA and Triton workaround applied too. 418 * [Info kindly provided by ALi] 419 */ 420 static void quirk_alimagik(struct pci_dev *dev) 421 { 422 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 423 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 424 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 425 } 426 } 427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 429 430 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 431 static void quirk_natoma(struct pci_dev *dev) 432 { 433 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 434 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 435 pci_pci_problems |= PCIPCI_NATOMA; 436 } 437 } 438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 444 445 /* 446 * This chip can cause PCI parity errors if config register 0xA0 is read 447 * while DMAs are occurring. 448 */ 449 static void quirk_citrine(struct pci_dev *dev) 450 { 451 dev->cfg_size = 0xA0; 452 } 453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 454 455 /* 456 * This chip can cause bus lockups if config addresses above 0x600 457 * are read or written. 458 */ 459 static void quirk_nfp6000(struct pci_dev *dev) 460 { 461 dev->cfg_size = 0x600; 462 } 463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 467 468 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 469 static void quirk_extend_bar_to_page(struct pci_dev *dev) 470 { 471 int i; 472 473 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 474 struct resource *r = &dev->resource[i]; 475 476 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 477 r->end = PAGE_SIZE - 1; 478 r->start = 0; 479 r->flags |= IORESOURCE_UNSET; 480 pci_info(dev, "expanded BAR %d to page size: %pR\n", 481 i, r); 482 } 483 } 484 } 485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 486 487 /* 488 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 489 * If it's needed, re-allocate the region. 490 */ 491 static void quirk_s3_64M(struct pci_dev *dev) 492 { 493 struct resource *r = &dev->resource[0]; 494 495 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 496 r->flags |= IORESOURCE_UNSET; 497 r->start = 0; 498 r->end = 0x3ffffff; 499 } 500 } 501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 503 504 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 505 const char *name) 506 { 507 u32 region; 508 struct pci_bus_region bus_region; 509 struct resource *res = dev->resource + pos; 510 511 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 512 513 if (!region) 514 return; 515 516 res->name = pci_name(dev); 517 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 518 res->flags |= 519 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 520 region &= ~(size - 1); 521 522 /* Convert from PCI bus to resource space */ 523 bus_region.start = region; 524 bus_region.end = region + size - 1; 525 pcibios_bus_to_resource(dev->bus, res, &bus_region); 526 527 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 528 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 529 } 530 531 /* 532 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 533 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 534 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 535 * (which conflicts w/ BAR1's memory range). 536 * 537 * CS553x's ISA PCI BARs may also be read-only (ref: 538 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 539 */ 540 static void quirk_cs5536_vsa(struct pci_dev *dev) 541 { 542 static char *name = "CS5536 ISA bridge"; 543 544 if (pci_resource_len(dev, 0) != 8) { 545 quirk_io(dev, 0, 8, name); /* SMB */ 546 quirk_io(dev, 1, 256, name); /* GPIO */ 547 quirk_io(dev, 2, 64, name); /* MFGPT */ 548 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 549 name); 550 } 551 } 552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 553 554 static void quirk_io_region(struct pci_dev *dev, int port, 555 unsigned int size, int nr, const char *name) 556 { 557 u16 region; 558 struct pci_bus_region bus_region; 559 struct resource *res = dev->resource + nr; 560 561 pci_read_config_word(dev, port, ®ion); 562 region &= ~(size - 1); 563 564 if (!region) 565 return; 566 567 res->name = pci_name(dev); 568 res->flags = IORESOURCE_IO; 569 570 /* Convert from PCI bus to resource space */ 571 bus_region.start = region; 572 bus_region.end = region + size - 1; 573 pcibios_bus_to_resource(dev->bus, res, &bus_region); 574 575 if (!pci_claim_resource(dev, nr)) 576 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 577 } 578 579 /* 580 * ATI Northbridge setups MCE the processor if you even read somewhere 581 * between 0x3b0->0x3bb or read 0x3d3 582 */ 583 static void quirk_ati_exploding_mce(struct pci_dev *dev) 584 { 585 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 586 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 587 request_region(0x3b0, 0x0C, "RadeonIGP"); 588 request_region(0x3d3, 0x01, "RadeonIGP"); 589 } 590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 591 592 /* 593 * In the AMD NL platform, this device ([1022:7912]) has a class code of 594 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 595 * claim it. 596 * 597 * But the dwc3 driver is a more specific driver for this device, and we'd 598 * prefer to use it instead of xhci. To prevent xhci from claiming the 599 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 600 * defines as "USB device (not host controller)". The dwc3 driver can then 601 * claim it based on its Vendor and Device ID. 602 */ 603 static void quirk_amd_nl_class(struct pci_dev *pdev) 604 { 605 u32 class = pdev->class; 606 607 /* Use "USB Device (not host controller)" class */ 608 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 609 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 610 class, pdev->class); 611 } 612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 613 quirk_amd_nl_class); 614 615 /* 616 * Synopsys USB 3.x host HAPS platform has a class code of 617 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 618 * devices should use dwc3-haps driver. Change these devices' class code to 619 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 620 * them. 621 */ 622 static void quirk_synopsys_haps(struct pci_dev *pdev) 623 { 624 u32 class = pdev->class; 625 626 switch (pdev->device) { 627 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 628 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 629 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 630 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 631 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 632 class, pdev->class); 633 break; 634 } 635 } 636 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 637 PCI_CLASS_SERIAL_USB_XHCI, 0, 638 quirk_synopsys_haps); 639 640 /* 641 * Let's make the southbridge information explicit instead of having to 642 * worry about people probing the ACPI areas, for example.. (Yes, it 643 * happens, and if you read the wrong ACPI register it will put the machine 644 * to sleep with no way of waking it up again. Bummer). 645 * 646 * ALI M7101: Two IO regions pointed to by words at 647 * 0xE0 (64 bytes of ACPI registers) 648 * 0xE2 (32 bytes of SMB registers) 649 */ 650 static void quirk_ali7101_acpi(struct pci_dev *dev) 651 { 652 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 653 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 654 } 655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 656 657 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 658 { 659 u32 devres; 660 u32 mask, size, base; 661 662 pci_read_config_dword(dev, port, &devres); 663 if ((devres & enable) != enable) 664 return; 665 mask = (devres >> 16) & 15; 666 base = devres & 0xffff; 667 size = 16; 668 for (;;) { 669 unsigned int bit = size >> 1; 670 if ((bit & mask) == bit) 671 break; 672 size = bit; 673 } 674 /* 675 * For now we only print it out. Eventually we'll want to 676 * reserve it (at least if it's in the 0x1000+ range), but 677 * let's get enough confirmation reports first. 678 */ 679 base &= -size; 680 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 681 } 682 683 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 684 { 685 u32 devres; 686 u32 mask, size, base; 687 688 pci_read_config_dword(dev, port, &devres); 689 if ((devres & enable) != enable) 690 return; 691 base = devres & 0xffff0000; 692 mask = (devres & 0x3f) << 16; 693 size = 128 << 16; 694 for (;;) { 695 unsigned int bit = size >> 1; 696 if ((bit & mask) == bit) 697 break; 698 size = bit; 699 } 700 701 /* 702 * For now we only print it out. Eventually we'll want to 703 * reserve it, but let's get enough confirmation reports first. 704 */ 705 base &= -size; 706 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 707 } 708 709 /* 710 * PIIX4 ACPI: Two IO regions pointed to by longwords at 711 * 0x40 (64 bytes of ACPI registers) 712 * 0x90 (16 bytes of SMB registers) 713 * and a few strange programmable PIIX4 device resources. 714 */ 715 static void quirk_piix4_acpi(struct pci_dev *dev) 716 { 717 u32 res_a; 718 719 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 720 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 721 722 /* Device resource A has enables for some of the other ones */ 723 pci_read_config_dword(dev, 0x5c, &res_a); 724 725 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 726 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 727 728 /* Device resource D is just bitfields for static resources */ 729 730 /* Device 12 enabled? */ 731 if (res_a & (1 << 29)) { 732 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 733 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 734 } 735 /* Device 13 enabled? */ 736 if (res_a & (1 << 30)) { 737 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 738 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 739 } 740 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 741 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 742 } 743 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 745 746 #define ICH_PMBASE 0x40 747 #define ICH_ACPI_CNTL 0x44 748 #define ICH4_ACPI_EN 0x10 749 #define ICH6_ACPI_EN 0x80 750 #define ICH4_GPIOBASE 0x58 751 #define ICH4_GPIO_CNTL 0x5c 752 #define ICH4_GPIO_EN 0x10 753 #define ICH6_GPIOBASE 0x48 754 #define ICH6_GPIO_CNTL 0x4c 755 #define ICH6_GPIO_EN 0x10 756 757 /* 758 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 759 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 760 * 0x58 (64 bytes of GPIO I/O space) 761 */ 762 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 763 { 764 u8 enable; 765 766 /* 767 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 768 * with low legacy (and fixed) ports. We don't know the decoding 769 * priority and can't tell whether the legacy device or the one created 770 * here is really at that address. This happens on boards with broken 771 * BIOSes. 772 */ 773 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 774 if (enable & ICH4_ACPI_EN) 775 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 776 "ICH4 ACPI/GPIO/TCO"); 777 778 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 779 if (enable & ICH4_GPIO_EN) 780 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 781 "ICH4 GPIO"); 782 } 783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 784 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 786 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 793 794 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 795 { 796 u8 enable; 797 798 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 799 if (enable & ICH6_ACPI_EN) 800 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 801 "ICH6 ACPI/GPIO/TCO"); 802 803 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 804 if (enable & ICH6_GPIO_EN) 805 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 806 "ICH6 GPIO"); 807 } 808 809 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 810 const char *name, int dynsize) 811 { 812 u32 val; 813 u32 size, base; 814 815 pci_read_config_dword(dev, reg, &val); 816 817 /* Enabled? */ 818 if (!(val & 1)) 819 return; 820 base = val & 0xfffc; 821 if (dynsize) { 822 /* 823 * This is not correct. It is 16, 32 or 64 bytes depending on 824 * register D31:F0:ADh bits 5:4. 825 * 826 * But this gets us at least _part_ of it. 827 */ 828 size = 16; 829 } else { 830 size = 128; 831 } 832 base &= ~(size-1); 833 834 /* 835 * Just print it out for now. We should reserve it after more 836 * debugging. 837 */ 838 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 839 } 840 841 static void quirk_ich6_lpc(struct pci_dev *dev) 842 { 843 /* Shared ACPI/GPIO decode with all ICH6+ */ 844 ich6_lpc_acpi_gpio(dev); 845 846 /* ICH6-specific generic IO decode */ 847 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 848 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 849 } 850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 852 853 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 854 const char *name) 855 { 856 u32 val; 857 u32 mask, base; 858 859 pci_read_config_dword(dev, reg, &val); 860 861 /* Enabled? */ 862 if (!(val & 1)) 863 return; 864 865 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 866 base = val & 0xfffc; 867 mask = (val >> 16) & 0xfc; 868 mask |= 3; 869 870 /* 871 * Just print it out for now. We should reserve it after more 872 * debugging. 873 */ 874 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 875 } 876 877 /* ICH7-10 has the same common LPC generic IO decode registers */ 878 static void quirk_ich7_lpc(struct pci_dev *dev) 879 { 880 /* We share the common ACPI/GPIO decode with ICH6 */ 881 ich6_lpc_acpi_gpio(dev); 882 883 /* And have 4 ICH7+ generic decodes */ 884 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 885 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 886 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 887 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 888 } 889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 902 903 /* 904 * VIA ACPI: One IO region pointed to by longword at 905 * 0x48 or 0x20 (256 bytes of ACPI registers) 906 */ 907 static void quirk_vt82c586_acpi(struct pci_dev *dev) 908 { 909 if (dev->revision & 0x10) 910 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 911 "vt82c586 ACPI"); 912 } 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 914 915 /* 916 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 917 * 0x48 (256 bytes of ACPI registers) 918 * 0x70 (128 bytes of hardware monitoring register) 919 * 0x90 (16 bytes of SMB registers) 920 */ 921 static void quirk_vt82c686_acpi(struct pci_dev *dev) 922 { 923 quirk_vt82c586_acpi(dev); 924 925 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 926 "vt82c686 HW-mon"); 927 928 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 929 } 930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 931 932 /* 933 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 934 * 0x88 (128 bytes of power management registers) 935 * 0xd0 (16 bytes of SMB registers) 936 */ 937 static void quirk_vt8235_acpi(struct pci_dev *dev) 938 { 939 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 940 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 941 } 942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 943 944 /* 945 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 946 * back-to-back: Disable fast back-to-back on the secondary bus segment 947 */ 948 static void quirk_xio2000a(struct pci_dev *dev) 949 { 950 struct pci_dev *pdev; 951 u16 command; 952 953 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 954 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 955 pci_read_config_word(pdev, PCI_COMMAND, &command); 956 if (command & PCI_COMMAND_FAST_BACK) 957 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 958 } 959 } 960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 961 quirk_xio2000a); 962 963 #ifdef CONFIG_X86_IO_APIC 964 965 #include <asm/io_apic.h> 966 967 /* 968 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 969 * devices to the external APIC. 970 * 971 * TODO: When we have device-specific interrupt routers, this code will go 972 * away from quirks. 973 */ 974 static void quirk_via_ioapic(struct pci_dev *dev) 975 { 976 u8 tmp; 977 978 if (nr_ioapics < 1) 979 tmp = 0; /* nothing routed to external APIC */ 980 else 981 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 982 983 pci_info(dev, "%sbling VIA external APIC routing\n", 984 tmp == 0 ? "Disa" : "Ena"); 985 986 /* Offset 0x58: External APIC IRQ output control */ 987 pci_write_config_byte(dev, 0x58, tmp); 988 } 989 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 990 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 991 992 /* 993 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 994 * This leads to doubled level interrupt rates. 995 * Set this bit to get rid of cycle wastage. 996 * Otherwise uncritical. 997 */ 998 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 999 { 1000 u8 misc_control2; 1001 #define BYPASS_APIC_DEASSERT 8 1002 1003 pci_read_config_byte(dev, 0x5B, &misc_control2); 1004 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1005 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1006 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1007 } 1008 } 1009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1010 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1011 1012 /* 1013 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1014 * We check all revs >= B0 (yet not in the pre production!) as the bug 1015 * is currently marked NoFix 1016 * 1017 * We have multiple reports of hangs with this chipset that went away with 1018 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1019 * of course. However the advice is demonstrably good even if so. 1020 */ 1021 static void quirk_amd_ioapic(struct pci_dev *dev) 1022 { 1023 if (dev->revision >= 0x02) { 1024 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1025 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1026 } 1027 } 1028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1029 #endif /* CONFIG_X86_IO_APIC */ 1030 1031 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1032 1033 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1034 { 1035 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1036 if (dev->subsystem_device == 0xa118) 1037 dev->sriov->link = dev->devfn; 1038 } 1039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1040 #endif 1041 1042 /* 1043 * Some settings of MMRBC can lead to data corruption so block changes. 1044 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1045 */ 1046 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1047 { 1048 if (dev->subordinate && dev->revision <= 0x12) { 1049 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1050 dev->revision); 1051 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1052 } 1053 } 1054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1055 1056 /* 1057 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1058 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1059 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1060 * of the ACPI SCI interrupt is only done for convenience. 1061 * -jgarzik 1062 */ 1063 static void quirk_via_acpi(struct pci_dev *d) 1064 { 1065 u8 irq; 1066 1067 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1068 pci_read_config_byte(d, 0x42, &irq); 1069 irq &= 0xf; 1070 if (irq && (irq != 2)) 1071 d->irq = irq; 1072 } 1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1075 1076 /* VIA bridges which have VLink */ 1077 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1078 1079 static void quirk_via_bridge(struct pci_dev *dev) 1080 { 1081 /* See what bridge we have and find the device ranges */ 1082 switch (dev->device) { 1083 case PCI_DEVICE_ID_VIA_82C686: 1084 /* 1085 * The VT82C686 is special; it attaches to PCI and can have 1086 * any device number. All its subdevices are functions of 1087 * that single device. 1088 */ 1089 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1090 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1091 break; 1092 case PCI_DEVICE_ID_VIA_8237: 1093 case PCI_DEVICE_ID_VIA_8237A: 1094 via_vlink_dev_lo = 15; 1095 break; 1096 case PCI_DEVICE_ID_VIA_8235: 1097 via_vlink_dev_lo = 16; 1098 break; 1099 case PCI_DEVICE_ID_VIA_8231: 1100 case PCI_DEVICE_ID_VIA_8233_0: 1101 case PCI_DEVICE_ID_VIA_8233A: 1102 case PCI_DEVICE_ID_VIA_8233C_0: 1103 via_vlink_dev_lo = 17; 1104 break; 1105 } 1106 } 1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1115 1116 /* 1117 * quirk_via_vlink - VIA VLink IRQ number update 1118 * @dev: PCI device 1119 * 1120 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1121 * the IRQ line register which usually is not relevant for PCI cards, is 1122 * actually written so that interrupts get sent to the right place. 1123 * 1124 * We only do this on systems where a VIA south bridge was detected, and 1125 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1126 */ 1127 static void quirk_via_vlink(struct pci_dev *dev) 1128 { 1129 u8 irq, new_irq; 1130 1131 /* Check if we have VLink at all */ 1132 if (via_vlink_dev_lo == -1) 1133 return; 1134 1135 new_irq = dev->irq; 1136 1137 /* Don't quirk interrupts outside the legacy IRQ range */ 1138 if (!new_irq || new_irq > 15) 1139 return; 1140 1141 /* Internal device ? */ 1142 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1143 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1144 return; 1145 1146 /* 1147 * This is an internal VLink device on a PIC interrupt. The BIOS 1148 * ought to have set this but may not have, so we redo it. 1149 */ 1150 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1151 if (new_irq != irq) { 1152 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1153 irq, new_irq); 1154 udelay(15); /* unknown if delay really needed */ 1155 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1156 } 1157 } 1158 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1159 1160 /* 1161 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1162 * of VT82C597 for backward compatibility. We need to switch it off to be 1163 * able to recognize the real type of the chip. 1164 */ 1165 static void quirk_vt82c598_id(struct pci_dev *dev) 1166 { 1167 pci_write_config_byte(dev, 0xfc, 0); 1168 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1169 } 1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1171 1172 /* 1173 * CardBus controllers have a legacy base address that enables them to 1174 * respond as i82365 pcmcia controllers. We don't want them to do this 1175 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1176 * driver does not (and should not) handle CardBus. 1177 */ 1178 static void quirk_cardbus_legacy(struct pci_dev *dev) 1179 { 1180 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1181 } 1182 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1183 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1184 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1185 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1186 1187 /* 1188 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1189 * what the designers were smoking but let's not inhale... 1190 * 1191 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1192 * turn it off! 1193 */ 1194 static void quirk_amd_ordering(struct pci_dev *dev) 1195 { 1196 u32 pcic; 1197 pci_read_config_dword(dev, 0x4C, &pcic); 1198 if ((pcic & 6) != 6) { 1199 pcic |= 6; 1200 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1201 pci_write_config_dword(dev, 0x4C, pcic); 1202 pci_read_config_dword(dev, 0x84, &pcic); 1203 pcic |= (1 << 23); /* Required in this mode */ 1204 pci_write_config_dword(dev, 0x84, pcic); 1205 } 1206 } 1207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1208 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1209 1210 /* 1211 * DreamWorks-provided workaround for Dunord I-3000 problem 1212 * 1213 * This card decodes and responds to addresses not apparently assigned to 1214 * it. We force a larger allocation to ensure that nothing gets put too 1215 * close to it. 1216 */ 1217 static void quirk_dunord(struct pci_dev *dev) 1218 { 1219 struct resource *r = &dev->resource[1]; 1220 1221 r->flags |= IORESOURCE_UNSET; 1222 r->start = 0; 1223 r->end = 0xffffff; 1224 } 1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1226 1227 /* 1228 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1229 * decoding (transparent), and does indicate this in the ProgIf. 1230 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1231 */ 1232 static void quirk_transparent_bridge(struct pci_dev *dev) 1233 { 1234 dev->transparent = 1; 1235 } 1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1238 1239 /* 1240 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1241 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1242 * found at http://www.national.com/analog for info on what these bits do. 1243 * <christer@weinigel.se> 1244 */ 1245 static void quirk_mediagx_master(struct pci_dev *dev) 1246 { 1247 u8 reg; 1248 1249 pci_read_config_byte(dev, 0x41, ®); 1250 if (reg & 2) { 1251 reg &= ~2; 1252 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1253 reg); 1254 pci_write_config_byte(dev, 0x41, reg); 1255 } 1256 } 1257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1258 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1259 1260 /* 1261 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1262 * in the odd case it is not the results are corruption hence the presence 1263 * of a Linux check. 1264 */ 1265 static void quirk_disable_pxb(struct pci_dev *pdev) 1266 { 1267 u16 config; 1268 1269 if (pdev->revision != 0x04) /* Only C0 requires this */ 1270 return; 1271 pci_read_config_word(pdev, 0x40, &config); 1272 if (config & (1<<6)) { 1273 config &= ~(1<<6); 1274 pci_write_config_word(pdev, 0x40, config); 1275 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1276 } 1277 } 1278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1279 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1280 1281 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1282 { 1283 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1284 u8 tmp; 1285 1286 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1287 if (tmp == 0x01) { 1288 pci_read_config_byte(pdev, 0x40, &tmp); 1289 pci_write_config_byte(pdev, 0x40, tmp|1); 1290 pci_write_config_byte(pdev, 0x9, 1); 1291 pci_write_config_byte(pdev, 0xa, 6); 1292 pci_write_config_byte(pdev, 0x40, tmp); 1293 1294 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1295 pci_info(pdev, "set SATA to AHCI mode\n"); 1296 } 1297 } 1298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1301 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1305 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1306 1307 /* Serverworks CSB5 IDE does not fully support native mode */ 1308 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1309 { 1310 u8 prog; 1311 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1312 if (prog & 5) { 1313 prog &= ~5; 1314 pdev->class &= ~5; 1315 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1316 /* PCI layer will sort out resources */ 1317 } 1318 } 1319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1320 1321 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1322 static void quirk_ide_samemode(struct pci_dev *pdev) 1323 { 1324 u8 prog; 1325 1326 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1327 1328 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1329 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1330 prog &= ~5; 1331 pdev->class &= ~5; 1332 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1333 } 1334 } 1335 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1336 1337 /* Some ATA devices break if put into D3 */ 1338 static void quirk_no_ata_d3(struct pci_dev *pdev) 1339 { 1340 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1341 } 1342 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1343 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1344 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1345 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1346 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1347 /* ALi loses some register settings that we cannot then restore */ 1348 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1349 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1350 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1351 occur when mode detecting */ 1352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1353 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1354 1355 /* 1356 * This was originally an Alpha-specific thing, but it really fits here. 1357 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1358 */ 1359 static void quirk_eisa_bridge(struct pci_dev *dev) 1360 { 1361 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1362 } 1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1364 1365 /* 1366 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1367 * is not activated. The myth is that Asus said that they do not want the 1368 * users to be irritated by just another PCI Device in the Win98 device 1369 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1370 * package 2.7.0 for details) 1371 * 1372 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1373 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1374 * becomes necessary to do this tweak in two steps -- the chosen trigger 1375 * is either the Host bridge (preferred) or on-board VGA controller. 1376 * 1377 * Note that we used to unhide the SMBus that way on Toshiba laptops 1378 * (Satellite A40 and Tecra M2) but then found that the thermal management 1379 * was done by SMM code, which could cause unsynchronized concurrent 1380 * accesses to the SMBus registers, with potentially bad effects. Thus you 1381 * should be very careful when adding new entries: if SMM is accessing the 1382 * Intel SMBus, this is a very good reason to leave it hidden. 1383 * 1384 * Likewise, many recent laptops use ACPI for thermal management. If the 1385 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1386 * natively, and keeping the SMBus hidden is the right thing to do. If you 1387 * are about to add an entry in the table below, please first disassemble 1388 * the DSDT and double-check that there is no code accessing the SMBus. 1389 */ 1390 static int asus_hides_smbus; 1391 1392 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1393 { 1394 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1395 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1396 switch (dev->subsystem_device) { 1397 case 0x8025: /* P4B-LX */ 1398 case 0x8070: /* P4B */ 1399 case 0x8088: /* P4B533 */ 1400 case 0x1626: /* L3C notebook */ 1401 asus_hides_smbus = 1; 1402 } 1403 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1404 switch (dev->subsystem_device) { 1405 case 0x80b1: /* P4GE-V */ 1406 case 0x80b2: /* P4PE */ 1407 case 0x8093: /* P4B533-V */ 1408 asus_hides_smbus = 1; 1409 } 1410 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1411 switch (dev->subsystem_device) { 1412 case 0x8030: /* P4T533 */ 1413 asus_hides_smbus = 1; 1414 } 1415 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1416 switch (dev->subsystem_device) { 1417 case 0x8070: /* P4G8X Deluxe */ 1418 asus_hides_smbus = 1; 1419 } 1420 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1421 switch (dev->subsystem_device) { 1422 case 0x80c9: /* PU-DLS */ 1423 asus_hides_smbus = 1; 1424 } 1425 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1426 switch (dev->subsystem_device) { 1427 case 0x1751: /* M2N notebook */ 1428 case 0x1821: /* M5N notebook */ 1429 case 0x1897: /* A6L notebook */ 1430 asus_hides_smbus = 1; 1431 } 1432 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1433 switch (dev->subsystem_device) { 1434 case 0x184b: /* W1N notebook */ 1435 case 0x186a: /* M6Ne notebook */ 1436 asus_hides_smbus = 1; 1437 } 1438 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1439 switch (dev->subsystem_device) { 1440 case 0x80f2: /* P4P800-X */ 1441 asus_hides_smbus = 1; 1442 } 1443 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1444 switch (dev->subsystem_device) { 1445 case 0x1882: /* M6V notebook */ 1446 case 0x1977: /* A6VA notebook */ 1447 asus_hides_smbus = 1; 1448 } 1449 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1450 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1451 switch (dev->subsystem_device) { 1452 case 0x088C: /* HP Compaq nc8000 */ 1453 case 0x0890: /* HP Compaq nc6000 */ 1454 asus_hides_smbus = 1; 1455 } 1456 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1457 switch (dev->subsystem_device) { 1458 case 0x12bc: /* HP D330L */ 1459 case 0x12bd: /* HP D530 */ 1460 case 0x006a: /* HP Compaq nx9500 */ 1461 asus_hides_smbus = 1; 1462 } 1463 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1464 switch (dev->subsystem_device) { 1465 case 0x12bf: /* HP xw4100 */ 1466 asus_hides_smbus = 1; 1467 } 1468 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1469 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1470 switch (dev->subsystem_device) { 1471 case 0xC00C: /* Samsung P35 notebook */ 1472 asus_hides_smbus = 1; 1473 } 1474 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1475 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1476 switch (dev->subsystem_device) { 1477 case 0x0058: /* Compaq Evo N620c */ 1478 asus_hides_smbus = 1; 1479 } 1480 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1481 switch (dev->subsystem_device) { 1482 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1483 /* Motherboard doesn't have Host bridge 1484 * subvendor/subdevice IDs, therefore checking 1485 * its on-board VGA controller */ 1486 asus_hides_smbus = 1; 1487 } 1488 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1489 switch (dev->subsystem_device) { 1490 case 0x00b8: /* Compaq Evo D510 CMT */ 1491 case 0x00b9: /* Compaq Evo D510 SFF */ 1492 case 0x00ba: /* Compaq Evo D510 USDT */ 1493 /* Motherboard doesn't have Host bridge 1494 * subvendor/subdevice IDs and on-board VGA 1495 * controller is disabled if an AGP card is 1496 * inserted, therefore checking USB UHCI 1497 * Controller #1 */ 1498 asus_hides_smbus = 1; 1499 } 1500 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1501 switch (dev->subsystem_device) { 1502 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1503 /* Motherboard doesn't have host bridge 1504 * subvendor/subdevice IDs, therefore checking 1505 * its on-board VGA controller */ 1506 asus_hides_smbus = 1; 1507 } 1508 } 1509 } 1510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1520 1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1524 1525 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1526 { 1527 u16 val; 1528 1529 if (likely(!asus_hides_smbus)) 1530 return; 1531 1532 pci_read_config_word(dev, 0xF2, &val); 1533 if (val & 0x8) { 1534 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1535 pci_read_config_word(dev, 0xF2, &val); 1536 if (val & 0x8) 1537 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1538 val); 1539 else 1540 pci_info(dev, "Enabled i801 SMBus device\n"); 1541 } 1542 } 1543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1550 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1551 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1552 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1553 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1557 1558 /* It appears we just have one such device. If not, we have a warning */ 1559 static void __iomem *asus_rcba_base; 1560 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1561 { 1562 u32 rcba; 1563 1564 if (likely(!asus_hides_smbus)) 1565 return; 1566 WARN_ON(asus_rcba_base); 1567 1568 pci_read_config_dword(dev, 0xF0, &rcba); 1569 /* use bits 31:14, 16 kB aligned */ 1570 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1571 if (asus_rcba_base == NULL) 1572 return; 1573 } 1574 1575 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1576 { 1577 u32 val; 1578 1579 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1580 return; 1581 1582 /* read the Function Disable register, dword mode only */ 1583 val = readl(asus_rcba_base + 0x3418); 1584 1585 /* enable the SMBus device */ 1586 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1587 } 1588 1589 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1590 { 1591 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1592 return; 1593 1594 iounmap(asus_rcba_base); 1595 asus_rcba_base = NULL; 1596 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1597 } 1598 1599 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1600 { 1601 asus_hides_smbus_lpc_ich6_suspend(dev); 1602 asus_hides_smbus_lpc_ich6_resume_early(dev); 1603 asus_hides_smbus_lpc_ich6_resume(dev); 1604 } 1605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1606 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1607 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1609 1610 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1611 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1612 { 1613 u8 val = 0; 1614 pci_read_config_byte(dev, 0x77, &val); 1615 if (val & 0x10) { 1616 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1617 pci_write_config_byte(dev, 0x77, val & ~0x10); 1618 } 1619 } 1620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1624 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1625 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1626 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1627 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1628 1629 /* 1630 * ... This is further complicated by the fact that some SiS96x south 1631 * bridges pretend to be 85C503/5513 instead. In that case see if we 1632 * spotted a compatible north bridge to make sure. 1633 * (pci_find_device() doesn't work yet) 1634 * 1635 * We can also enable the sis96x bit in the discovery register.. 1636 */ 1637 #define SIS_DETECT_REGISTER 0x40 1638 1639 static void quirk_sis_503(struct pci_dev *dev) 1640 { 1641 u8 reg; 1642 u16 devid; 1643 1644 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1645 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1646 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1647 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1648 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1649 return; 1650 } 1651 1652 /* 1653 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1654 * it has already been processed. (Depends on link order, which is 1655 * apparently not guaranteed) 1656 */ 1657 dev->device = devid; 1658 quirk_sis_96x_smbus(dev); 1659 } 1660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1661 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1662 1663 /* 1664 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1665 * and MC97 modem controller are disabled when a second PCI soundcard is 1666 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1667 * -- bjd 1668 */ 1669 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1670 { 1671 u8 val; 1672 int asus_hides_ac97 = 0; 1673 1674 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1675 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1676 asus_hides_ac97 = 1; 1677 } 1678 1679 if (!asus_hides_ac97) 1680 return; 1681 1682 pci_read_config_byte(dev, 0x50, &val); 1683 if (val & 0xc0) { 1684 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1685 pci_read_config_byte(dev, 0x50, &val); 1686 if (val & 0xc0) 1687 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1688 val); 1689 else 1690 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1691 } 1692 } 1693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1694 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1695 1696 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1697 1698 /* 1699 * If we are using libata we can drive this chip properly but must do this 1700 * early on to make the additional device appear during the PCI scanning. 1701 */ 1702 static void quirk_jmicron_ata(struct pci_dev *pdev) 1703 { 1704 u32 conf1, conf5, class; 1705 u8 hdr; 1706 1707 /* Only poke fn 0 */ 1708 if (PCI_FUNC(pdev->devfn)) 1709 return; 1710 1711 pci_read_config_dword(pdev, 0x40, &conf1); 1712 pci_read_config_dword(pdev, 0x80, &conf5); 1713 1714 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1715 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1716 1717 switch (pdev->device) { 1718 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1719 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1720 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1721 /* The controller should be in single function ahci mode */ 1722 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1723 break; 1724 1725 case PCI_DEVICE_ID_JMICRON_JMB365: 1726 case PCI_DEVICE_ID_JMICRON_JMB366: 1727 /* Redirect IDE second PATA port to the right spot */ 1728 conf5 |= (1 << 24); 1729 fallthrough; 1730 case PCI_DEVICE_ID_JMICRON_JMB361: 1731 case PCI_DEVICE_ID_JMICRON_JMB363: 1732 case PCI_DEVICE_ID_JMICRON_JMB369: 1733 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1734 /* Set the class codes correctly and then direct IDE 0 */ 1735 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1736 break; 1737 1738 case PCI_DEVICE_ID_JMICRON_JMB368: 1739 /* The controller should be in single function IDE mode */ 1740 conf1 |= 0x00C00000; /* Set 22, 23 */ 1741 break; 1742 } 1743 1744 pci_write_config_dword(pdev, 0x40, conf1); 1745 pci_write_config_dword(pdev, 0x80, conf5); 1746 1747 /* Update pdev accordingly */ 1748 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1749 pdev->hdr_type = hdr & 0x7f; 1750 pdev->multifunction = !!(hdr & 0x80); 1751 1752 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1753 pdev->class = class >> 8; 1754 } 1755 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1756 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1757 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1758 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1764 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1765 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1766 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1767 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1773 1774 #endif 1775 1776 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1777 { 1778 if (dev->multifunction) { 1779 device_disable_async_suspend(&dev->dev); 1780 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1781 } 1782 } 1783 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1784 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1787 1788 #ifdef CONFIG_X86_IO_APIC 1789 static void quirk_alder_ioapic(struct pci_dev *pdev) 1790 { 1791 int i; 1792 1793 if ((pdev->class >> 8) != 0xff00) 1794 return; 1795 1796 /* 1797 * The first BAR is the location of the IO-APIC... we must 1798 * not touch this (and it's already covered by the fixmap), so 1799 * forcibly insert it into the resource tree. 1800 */ 1801 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1802 insert_resource(&iomem_resource, &pdev->resource[0]); 1803 1804 /* 1805 * The next five BARs all seem to be rubbish, so just clean 1806 * them out. 1807 */ 1808 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1809 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1810 } 1811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1812 #endif 1813 1814 static void quirk_pcie_mch(struct pci_dev *pdev) 1815 { 1816 pdev->no_msi = 1; 1817 } 1818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1821 1822 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1823 1824 /* 1825 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1826 * actually on the AMBA bus. These fake PCI devices can support SVA via 1827 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1828 * 1829 * Normally stalling must not be enabled for PCI devices, since it would 1830 * break the PCI requirement for free-flowing writes and may lead to 1831 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1832 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1833 * even when a "PCI" device turns out to be a regular old SoC device 1834 * dressed up as a RCiEP and normal rules don't apply. 1835 */ 1836 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1837 { 1838 struct property_entry properties[] = { 1839 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1840 {}, 1841 }; 1842 1843 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1844 return; 1845 1846 pdev->pasid_no_tlp = 1; 1847 1848 /* 1849 * Set the dma-can-stall property on ACPI platforms. Device tree 1850 * can set it directly. 1851 */ 1852 if (!pdev->dev.of_node && 1853 device_add_properties(&pdev->dev, properties)) 1854 pci_warn(pdev, "could not add stall property"); 1855 } 1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1862 1863 /* 1864 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1865 * together on certain PXH-based systems. 1866 */ 1867 static void quirk_pcie_pxh(struct pci_dev *dev) 1868 { 1869 dev->no_msi = 1; 1870 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1871 } 1872 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1873 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1874 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1875 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1876 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1877 1878 /* 1879 * Some Intel PCI Express chipsets have trouble with downstream device 1880 * power management. 1881 */ 1882 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1883 { 1884 pci_pm_d3hot_delay = 120; 1885 dev->no_d1d2 = 1; 1886 } 1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1891 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1892 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1893 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1894 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1895 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1896 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1897 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1898 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1899 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1908 1909 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 1910 { 1911 if (dev->d3hot_delay >= delay) 1912 return; 1913 1914 dev->d3hot_delay = delay; 1915 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 1916 dev->d3hot_delay); 1917 } 1918 1919 static void quirk_radeon_pm(struct pci_dev *dev) 1920 { 1921 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1922 dev->subsystem_device == 0x00e2) 1923 quirk_d3hot_delay(dev, 20); 1924 } 1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1926 1927 /* 1928 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 1929 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 1930 * 1931 * The kernel attempts to transition these devices to D3cold, but that seems 1932 * to be ineffective on the platforms in question; the PCI device appears to 1933 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 1934 * extended delay in order to succeed. 1935 */ 1936 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 1937 { 1938 quirk_d3hot_delay(dev, 20); 1939 } 1940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 1941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 1943 1944 #ifdef CONFIG_X86_IO_APIC 1945 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1946 { 1947 noioapicreroute = 1; 1948 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1949 1950 return 0; 1951 } 1952 1953 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1954 /* 1955 * Systems to exclude from boot interrupt reroute quirks 1956 */ 1957 { 1958 .callback = dmi_disable_ioapicreroute, 1959 .ident = "ASUSTek Computer INC. M2N-LR", 1960 .matches = { 1961 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1962 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1963 }, 1964 }, 1965 {} 1966 }; 1967 1968 /* 1969 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1970 * remap the original interrupt in the Linux kernel to the boot interrupt, so 1971 * that a PCI device's interrupt handler is installed on the boot interrupt 1972 * line instead. 1973 */ 1974 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1975 { 1976 dmi_check_system(boot_interrupt_dmi_table); 1977 if (noioapicquirk || noioapicreroute) 1978 return; 1979 1980 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1981 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 1982 dev->vendor, dev->device); 1983 } 1984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1987 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1989 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1990 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1992 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1993 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1994 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1995 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1996 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1997 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1998 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1999 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2000 2001 /* 2002 * On some chipsets we can disable the generation of legacy INTx boot 2003 * interrupts. 2004 */ 2005 2006 /* 2007 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2008 * 300641-004US, section 5.7.3. 2009 * 2010 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2011 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2012 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2013 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2014 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2015 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2016 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2017 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2018 * Core IO on Xeon Scalable, see Intel order no 610950. 2019 */ 2020 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2021 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2022 2023 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2024 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2025 2026 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2027 { 2028 u16 pci_config_word; 2029 u32 pci_config_dword; 2030 2031 if (noioapicquirk) 2032 return; 2033 2034 switch (dev->device) { 2035 case PCI_DEVICE_ID_INTEL_ESB_10: 2036 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2037 &pci_config_word); 2038 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2039 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2040 pci_config_word); 2041 break; 2042 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2043 case 0x0e28: /* Xeon E5/E7 V2 */ 2044 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2045 case 0x6f28: /* Xeon D-1500 */ 2046 case 0x2034: /* Xeon Scalable Family */ 2047 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2048 &pci_config_dword); 2049 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2050 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2051 pci_config_dword); 2052 break; 2053 default: 2054 return; 2055 } 2056 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2057 dev->vendor, dev->device); 2058 } 2059 /* 2060 * Device 29 Func 5 Device IDs of IO-APIC 2061 * containing ABAR—APIC1 Alternate Base Address Register 2062 */ 2063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2064 quirk_disable_intel_boot_interrupt); 2065 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2066 quirk_disable_intel_boot_interrupt); 2067 2068 /* 2069 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2070 * containing Coherent Interface Protocol Interrupt Control 2071 * 2072 * Device IDs obtained from volume 2 datasheets of commented 2073 * families above. 2074 */ 2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2076 quirk_disable_intel_boot_interrupt); 2077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2078 quirk_disable_intel_boot_interrupt); 2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2080 quirk_disable_intel_boot_interrupt); 2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2082 quirk_disable_intel_boot_interrupt); 2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2084 quirk_disable_intel_boot_interrupt); 2085 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2086 quirk_disable_intel_boot_interrupt); 2087 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2088 quirk_disable_intel_boot_interrupt); 2089 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2090 quirk_disable_intel_boot_interrupt); 2091 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2092 quirk_disable_intel_boot_interrupt); 2093 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2094 quirk_disable_intel_boot_interrupt); 2095 2096 /* Disable boot interrupts on HT-1000 */ 2097 #define BC_HT1000_FEATURE_REG 0x64 2098 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2099 #define BC_HT1000_MAP_IDX 0xC00 2100 #define BC_HT1000_MAP_DATA 0xC01 2101 2102 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2103 { 2104 u32 pci_config_dword; 2105 u8 irq; 2106 2107 if (noioapicquirk) 2108 return; 2109 2110 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2111 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2112 BC_HT1000_PIC_REGS_ENABLE); 2113 2114 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2115 outb(irq, BC_HT1000_MAP_IDX); 2116 outb(0x00, BC_HT1000_MAP_DATA); 2117 } 2118 2119 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2120 2121 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2122 dev->vendor, dev->device); 2123 } 2124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2125 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2126 2127 /* Disable boot interrupts on AMD and ATI chipsets */ 2128 2129 /* 2130 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2131 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2132 * (due to an erratum). 2133 */ 2134 #define AMD_813X_MISC 0x40 2135 #define AMD_813X_NOIOAMODE (1<<0) 2136 #define AMD_813X_REV_B1 0x12 2137 #define AMD_813X_REV_B2 0x13 2138 2139 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2140 { 2141 u32 pci_config_dword; 2142 2143 if (noioapicquirk) 2144 return; 2145 if ((dev->revision == AMD_813X_REV_B1) || 2146 (dev->revision == AMD_813X_REV_B2)) 2147 return; 2148 2149 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2150 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2151 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2152 2153 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2154 dev->vendor, dev->device); 2155 } 2156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2157 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2159 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2160 2161 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2162 2163 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2164 { 2165 u16 pci_config_word; 2166 2167 if (noioapicquirk) 2168 return; 2169 2170 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2171 if (!pci_config_word) { 2172 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2173 dev->vendor, dev->device); 2174 return; 2175 } 2176 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2177 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2178 dev->vendor, dev->device); 2179 } 2180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2181 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2182 #endif /* CONFIG_X86_IO_APIC */ 2183 2184 /* 2185 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2186 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2187 * Re-allocate the region if needed... 2188 */ 2189 static void quirk_tc86c001_ide(struct pci_dev *dev) 2190 { 2191 struct resource *r = &dev->resource[0]; 2192 2193 if (r->start & 0x8) { 2194 r->flags |= IORESOURCE_UNSET; 2195 r->start = 0; 2196 r->end = 0xf; 2197 } 2198 } 2199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2200 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2201 quirk_tc86c001_ide); 2202 2203 /* 2204 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2205 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2206 * being read correctly if bit 7 of the base address is set. 2207 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2208 * Re-allocate the regions to a 256-byte boundary if necessary. 2209 */ 2210 static void quirk_plx_pci9050(struct pci_dev *dev) 2211 { 2212 unsigned int bar; 2213 2214 /* Fixed in revision 2 (PCI 9052). */ 2215 if (dev->revision >= 2) 2216 return; 2217 for (bar = 0; bar <= 1; bar++) 2218 if (pci_resource_len(dev, bar) == 0x80 && 2219 (pci_resource_start(dev, bar) & 0x80)) { 2220 struct resource *r = &dev->resource[bar]; 2221 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2222 bar); 2223 r->flags |= IORESOURCE_UNSET; 2224 r->start = 0; 2225 r->end = 0xff; 2226 } 2227 } 2228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2229 quirk_plx_pci9050); 2230 /* 2231 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2232 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2233 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2234 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2235 * 2236 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2237 * driver. 2238 */ 2239 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2240 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2241 2242 static void quirk_netmos(struct pci_dev *dev) 2243 { 2244 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2245 unsigned int num_serial = dev->subsystem_device & 0xf; 2246 2247 /* 2248 * These Netmos parts are multiport serial devices with optional 2249 * parallel ports. Even when parallel ports are present, they 2250 * are identified as class SERIAL, which means the serial driver 2251 * will claim them. To prevent this, mark them as class OTHER. 2252 * These combo devices should be claimed by parport_serial. 2253 * 2254 * The subdevice ID is of the form 0x00PS, where <P> is the number 2255 * of parallel ports and <S> is the number of serial ports. 2256 */ 2257 switch (dev->device) { 2258 case PCI_DEVICE_ID_NETMOS_9835: 2259 /* Well, this rule doesn't hold for the following 9835 device */ 2260 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2261 dev->subsystem_device == 0x0299) 2262 return; 2263 fallthrough; 2264 case PCI_DEVICE_ID_NETMOS_9735: 2265 case PCI_DEVICE_ID_NETMOS_9745: 2266 case PCI_DEVICE_ID_NETMOS_9845: 2267 case PCI_DEVICE_ID_NETMOS_9855: 2268 if (num_parallel) { 2269 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2270 dev->device, num_parallel, num_serial); 2271 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2272 (dev->class & 0xff); 2273 } 2274 } 2275 } 2276 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2277 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2278 2279 static void quirk_e100_interrupt(struct pci_dev *dev) 2280 { 2281 u16 command, pmcsr; 2282 u8 __iomem *csr; 2283 u8 cmd_hi; 2284 2285 switch (dev->device) { 2286 /* PCI IDs taken from drivers/net/e100.c */ 2287 case 0x1029: 2288 case 0x1030 ... 0x1034: 2289 case 0x1038 ... 0x103E: 2290 case 0x1050 ... 0x1057: 2291 case 0x1059: 2292 case 0x1064 ... 0x106B: 2293 case 0x1091 ... 0x1095: 2294 case 0x1209: 2295 case 0x1229: 2296 case 0x2449: 2297 case 0x2459: 2298 case 0x245D: 2299 case 0x27DC: 2300 break; 2301 default: 2302 return; 2303 } 2304 2305 /* 2306 * Some firmware hands off the e100 with interrupts enabled, 2307 * which can cause a flood of interrupts if packets are 2308 * received before the driver attaches to the device. So 2309 * disable all e100 interrupts here. The driver will 2310 * re-enable them when it's ready. 2311 */ 2312 pci_read_config_word(dev, PCI_COMMAND, &command); 2313 2314 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2315 return; 2316 2317 /* 2318 * Check that the device is in the D0 power state. If it's not, 2319 * there is no point to look any further. 2320 */ 2321 if (dev->pm_cap) { 2322 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2323 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2324 return; 2325 } 2326 2327 /* Convert from PCI bus to resource space. */ 2328 csr = ioremap(pci_resource_start(dev, 0), 8); 2329 if (!csr) { 2330 pci_warn(dev, "Can't map e100 registers\n"); 2331 return; 2332 } 2333 2334 cmd_hi = readb(csr + 3); 2335 if (cmd_hi == 0) { 2336 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2337 writeb(1, csr + 3); 2338 } 2339 2340 iounmap(csr); 2341 } 2342 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2343 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2344 2345 /* 2346 * The 82575 and 82598 may experience data corruption issues when transitioning 2347 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2348 */ 2349 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2350 { 2351 pci_info(dev, "Disabling L0s\n"); 2352 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2353 } 2354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2364 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2366 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2368 2369 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2370 { 2371 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2372 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2373 } 2374 2375 /* 2376 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2377 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2378 * disable both L0s and L1 for now to be safe. 2379 */ 2380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2381 2382 /* 2383 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2384 * Link bit cleared after starting the link retrain process to allow this 2385 * process to finish. 2386 * 2387 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2388 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2389 */ 2390 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2391 { 2392 dev->clear_retrain_link = 1; 2393 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2394 } 2395 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2398 2399 static void fixup_rev1_53c810(struct pci_dev *dev) 2400 { 2401 u32 class = dev->class; 2402 2403 /* 2404 * rev 1 ncr53c810 chips don't set the class at all which means 2405 * they don't get their resources remapped. Fix that here. 2406 */ 2407 if (class) 2408 return; 2409 2410 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2411 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2412 class, dev->class); 2413 } 2414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2415 2416 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2417 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2418 { 2419 u16 en1k; 2420 2421 pci_read_config_word(dev, 0x40, &en1k); 2422 2423 if (en1k & 0x200) { 2424 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2425 dev->io_window_1k = 1; 2426 } 2427 } 2428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2429 2430 /* 2431 * Under some circumstances, AER is not linked with extended capabilities. 2432 * Force it to be linked by setting the corresponding control bit in the 2433 * config space. 2434 */ 2435 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2436 { 2437 uint8_t b; 2438 2439 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2440 if (!(b & 0x20)) { 2441 pci_write_config_byte(dev, 0xf41, b | 0x20); 2442 pci_info(dev, "Linking AER extended capability\n"); 2443 } 2444 } 2445 } 2446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2447 quirk_nvidia_ck804_pcie_aer_ext_cap); 2448 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2449 quirk_nvidia_ck804_pcie_aer_ext_cap); 2450 2451 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2452 { 2453 /* 2454 * Disable PCI Bus Parking and PCI Master read caching on CX700 2455 * which causes unspecified timing errors with a VT6212L on the PCI 2456 * bus leading to USB2.0 packet loss. 2457 * 2458 * This quirk is only enabled if a second (on the external PCI bus) 2459 * VT6212L is found -- the CX700 core itself also contains a USB 2460 * host controller with the same PCI ID as the VT6212L. 2461 */ 2462 2463 /* Count VT6212L instances */ 2464 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2465 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2466 uint8_t b; 2467 2468 /* 2469 * p should contain the first (internal) VT6212L -- see if we have 2470 * an external one by searching again. 2471 */ 2472 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2473 if (!p) 2474 return; 2475 pci_dev_put(p); 2476 2477 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2478 if (b & 0x40) { 2479 /* Turn off PCI Bus Parking */ 2480 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2481 2482 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2483 } 2484 } 2485 2486 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2487 if (b != 0) { 2488 /* Turn off PCI Master read caching */ 2489 pci_write_config_byte(dev, 0x72, 0x0); 2490 2491 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2492 pci_write_config_byte(dev, 0x75, 0x1); 2493 2494 /* Disable "Read FIFO Timer" */ 2495 pci_write_config_byte(dev, 0x77, 0x0); 2496 2497 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2498 } 2499 } 2500 } 2501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2502 2503 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2504 { 2505 u32 rev; 2506 2507 pci_read_config_dword(dev, 0xf4, &rev); 2508 2509 /* Only CAP the MRRS if the device is a 5719 A0 */ 2510 if (rev == 0x05719000) { 2511 int readrq = pcie_get_readrq(dev); 2512 if (readrq > 2048) 2513 pcie_set_readrq(dev, 2048); 2514 } 2515 } 2516 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2517 PCI_DEVICE_ID_TIGON3_5719, 2518 quirk_brcm_5719_limit_mrrs); 2519 2520 /* 2521 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2522 * hide device 6 which configures the overflow device access containing the 2523 * DRBs - this is where we expose device 6. 2524 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2525 */ 2526 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2527 { 2528 u8 reg; 2529 2530 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2531 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2532 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2533 } 2534 } 2535 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2536 quirk_unhide_mch_dev6); 2537 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2538 quirk_unhide_mch_dev6); 2539 2540 #ifdef CONFIG_PCI_MSI 2541 /* 2542 * Some chipsets do not support MSI. We cannot easily rely on setting 2543 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2544 * other buses controlled by the chipset even if Linux is not aware of it. 2545 * Instead of setting the flag on all buses in the machine, simply disable 2546 * MSI globally. 2547 */ 2548 static void quirk_disable_all_msi(struct pci_dev *dev) 2549 { 2550 pci_no_msi(); 2551 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2552 } 2553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2562 2563 /* Disable MSI on chipsets that are known to not support it */ 2564 static void quirk_disable_msi(struct pci_dev *dev) 2565 { 2566 if (dev->subordinate) { 2567 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2568 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2569 } 2570 } 2571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2574 2575 /* 2576 * The APC bridge device in AMD 780 family northbridges has some random 2577 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2578 * we use the possible vendor/device IDs of the host bridge for the 2579 * declared quirk, and search for the APC bridge by slot number. 2580 */ 2581 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2582 { 2583 struct pci_dev *apc_bridge; 2584 2585 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2586 if (apc_bridge) { 2587 if (apc_bridge->device == 0x9602) 2588 quirk_disable_msi(apc_bridge); 2589 pci_dev_put(apc_bridge); 2590 } 2591 } 2592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2594 2595 /* 2596 * Go through the list of HyperTransport capabilities and return 1 if a HT 2597 * MSI capability is found and enabled. 2598 */ 2599 static int msi_ht_cap_enabled(struct pci_dev *dev) 2600 { 2601 int pos, ttl = PCI_FIND_CAP_TTL; 2602 2603 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2604 while (pos && ttl--) { 2605 u8 flags; 2606 2607 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2608 &flags) == 0) { 2609 pci_info(dev, "Found %s HT MSI Mapping\n", 2610 flags & HT_MSI_FLAGS_ENABLE ? 2611 "enabled" : "disabled"); 2612 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2613 } 2614 2615 pos = pci_find_next_ht_capability(dev, pos, 2616 HT_CAPTYPE_MSI_MAPPING); 2617 } 2618 return 0; 2619 } 2620 2621 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2622 static void quirk_msi_ht_cap(struct pci_dev *dev) 2623 { 2624 if (!msi_ht_cap_enabled(dev)) 2625 quirk_disable_msi(dev); 2626 } 2627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2628 quirk_msi_ht_cap); 2629 2630 /* 2631 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2632 * if the MSI capability is set in any of these mappings. 2633 */ 2634 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2635 { 2636 struct pci_dev *pdev; 2637 2638 /* 2639 * Check HT MSI cap on this chipset and the root one. A single one 2640 * having MSI is enough to be sure that MSI is supported. 2641 */ 2642 pdev = pci_get_slot(dev->bus, 0); 2643 if (!pdev) 2644 return; 2645 if (!msi_ht_cap_enabled(pdev)) 2646 quirk_msi_ht_cap(dev); 2647 pci_dev_put(pdev); 2648 } 2649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2650 quirk_nvidia_ck804_msi_ht_cap); 2651 2652 /* Force enable MSI mapping capability on HT bridges */ 2653 static void ht_enable_msi_mapping(struct pci_dev *dev) 2654 { 2655 int pos, ttl = PCI_FIND_CAP_TTL; 2656 2657 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2658 while (pos && ttl--) { 2659 u8 flags; 2660 2661 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2662 &flags) == 0) { 2663 pci_info(dev, "Enabling HT MSI Mapping\n"); 2664 2665 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2666 flags | HT_MSI_FLAGS_ENABLE); 2667 } 2668 pos = pci_find_next_ht_capability(dev, pos, 2669 HT_CAPTYPE_MSI_MAPPING); 2670 } 2671 } 2672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2673 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2674 ht_enable_msi_mapping); 2675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2676 ht_enable_msi_mapping); 2677 2678 /* 2679 * The P5N32-SLI motherboards from Asus have a problem with MSI 2680 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2681 * also affects other devices. As for now, turn off MSI for this device. 2682 */ 2683 static void nvenet_msi_disable(struct pci_dev *dev) 2684 { 2685 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2686 2687 if (board_name && 2688 (strstr(board_name, "P5N32-SLI PREMIUM") || 2689 strstr(board_name, "P5N32-E SLI"))) { 2690 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2691 dev->no_msi = 1; 2692 } 2693 } 2694 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2695 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2696 nvenet_msi_disable); 2697 2698 /* 2699 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled, 2700 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't 2701 * generate MSI interrupts for PME and AER events instead only INTx interrupts 2702 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts 2703 * for other events, since PCIe specification doesn't support using a mix of 2704 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2705 * service drivers registering their respective ISRs for MSIs. 2706 */ 2707 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2708 { 2709 dev->no_msi = 1; 2710 } 2711 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2712 PCI_CLASS_BRIDGE_PCI, 8, 2713 pci_quirk_nvidia_tegra_disable_rp_msi); 2714 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2715 PCI_CLASS_BRIDGE_PCI, 8, 2716 pci_quirk_nvidia_tegra_disable_rp_msi); 2717 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2718 PCI_CLASS_BRIDGE_PCI, 8, 2719 pci_quirk_nvidia_tegra_disable_rp_msi); 2720 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2721 PCI_CLASS_BRIDGE_PCI, 8, 2722 pci_quirk_nvidia_tegra_disable_rp_msi); 2723 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2724 PCI_CLASS_BRIDGE_PCI, 8, 2725 pci_quirk_nvidia_tegra_disable_rp_msi); 2726 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2727 PCI_CLASS_BRIDGE_PCI, 8, 2728 pci_quirk_nvidia_tegra_disable_rp_msi); 2729 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2730 PCI_CLASS_BRIDGE_PCI, 8, 2731 pci_quirk_nvidia_tegra_disable_rp_msi); 2732 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2733 PCI_CLASS_BRIDGE_PCI, 8, 2734 pci_quirk_nvidia_tegra_disable_rp_msi); 2735 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2736 PCI_CLASS_BRIDGE_PCI, 8, 2737 pci_quirk_nvidia_tegra_disable_rp_msi); 2738 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2739 PCI_CLASS_BRIDGE_PCI, 8, 2740 pci_quirk_nvidia_tegra_disable_rp_msi); 2741 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2742 PCI_CLASS_BRIDGE_PCI, 8, 2743 pci_quirk_nvidia_tegra_disable_rp_msi); 2744 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2745 PCI_CLASS_BRIDGE_PCI, 8, 2746 pci_quirk_nvidia_tegra_disable_rp_msi); 2747 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2748 PCI_CLASS_BRIDGE_PCI, 8, 2749 pci_quirk_nvidia_tegra_disable_rp_msi); 2750 2751 /* 2752 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2753 * config register. This register controls the routing of legacy 2754 * interrupts from devices that route through the MCP55. If this register 2755 * is misprogrammed, interrupts are only sent to the BSP, unlike 2756 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2757 * having this register set properly prevents kdump from booting up 2758 * properly, so let's make sure that we have it set correctly. 2759 * Note that this is an undocumented register. 2760 */ 2761 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2762 { 2763 u32 cfg; 2764 2765 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2766 return; 2767 2768 pci_read_config_dword(dev, 0x74, &cfg); 2769 2770 if (cfg & ((1 << 2) | (1 << 15))) { 2771 pr_info("Rewriting IRQ routing register on MCP55\n"); 2772 cfg &= ~((1 << 2) | (1 << 15)); 2773 pci_write_config_dword(dev, 0x74, cfg); 2774 } 2775 } 2776 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2777 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2778 nvbridge_check_legacy_irq_routing); 2779 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2780 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2781 nvbridge_check_legacy_irq_routing); 2782 2783 static int ht_check_msi_mapping(struct pci_dev *dev) 2784 { 2785 int pos, ttl = PCI_FIND_CAP_TTL; 2786 int found = 0; 2787 2788 /* Check if there is HT MSI cap or enabled on this device */ 2789 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2790 while (pos && ttl--) { 2791 u8 flags; 2792 2793 if (found < 1) 2794 found = 1; 2795 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2796 &flags) == 0) { 2797 if (flags & HT_MSI_FLAGS_ENABLE) { 2798 if (found < 2) { 2799 found = 2; 2800 break; 2801 } 2802 } 2803 } 2804 pos = pci_find_next_ht_capability(dev, pos, 2805 HT_CAPTYPE_MSI_MAPPING); 2806 } 2807 2808 return found; 2809 } 2810 2811 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2812 { 2813 struct pci_dev *dev; 2814 int pos; 2815 int i, dev_no; 2816 int found = 0; 2817 2818 dev_no = host_bridge->devfn >> 3; 2819 for (i = dev_no + 1; i < 0x20; i++) { 2820 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2821 if (!dev) 2822 continue; 2823 2824 /* found next host bridge? */ 2825 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2826 if (pos != 0) { 2827 pci_dev_put(dev); 2828 break; 2829 } 2830 2831 if (ht_check_msi_mapping(dev)) { 2832 found = 1; 2833 pci_dev_put(dev); 2834 break; 2835 } 2836 pci_dev_put(dev); 2837 } 2838 2839 return found; 2840 } 2841 2842 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2843 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2844 2845 static int is_end_of_ht_chain(struct pci_dev *dev) 2846 { 2847 int pos, ctrl_off; 2848 int end = 0; 2849 u16 flags, ctrl; 2850 2851 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2852 2853 if (!pos) 2854 goto out; 2855 2856 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2857 2858 ctrl_off = ((flags >> 10) & 1) ? 2859 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2860 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2861 2862 if (ctrl & (1 << 6)) 2863 end = 1; 2864 2865 out: 2866 return end; 2867 } 2868 2869 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2870 { 2871 struct pci_dev *host_bridge; 2872 int pos; 2873 int i, dev_no; 2874 int found = 0; 2875 2876 dev_no = dev->devfn >> 3; 2877 for (i = dev_no; i >= 0; i--) { 2878 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2879 if (!host_bridge) 2880 continue; 2881 2882 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2883 if (pos != 0) { 2884 found = 1; 2885 break; 2886 } 2887 pci_dev_put(host_bridge); 2888 } 2889 2890 if (!found) 2891 return; 2892 2893 /* don't enable end_device/host_bridge with leaf directly here */ 2894 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2895 host_bridge_with_leaf(host_bridge)) 2896 goto out; 2897 2898 /* root did that ! */ 2899 if (msi_ht_cap_enabled(host_bridge)) 2900 goto out; 2901 2902 ht_enable_msi_mapping(dev); 2903 2904 out: 2905 pci_dev_put(host_bridge); 2906 } 2907 2908 static void ht_disable_msi_mapping(struct pci_dev *dev) 2909 { 2910 int pos, ttl = PCI_FIND_CAP_TTL; 2911 2912 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2913 while (pos && ttl--) { 2914 u8 flags; 2915 2916 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2917 &flags) == 0) { 2918 pci_info(dev, "Disabling HT MSI Mapping\n"); 2919 2920 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2921 flags & ~HT_MSI_FLAGS_ENABLE); 2922 } 2923 pos = pci_find_next_ht_capability(dev, pos, 2924 HT_CAPTYPE_MSI_MAPPING); 2925 } 2926 } 2927 2928 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2929 { 2930 struct pci_dev *host_bridge; 2931 int pos; 2932 int found; 2933 2934 if (!pci_msi_enabled()) 2935 return; 2936 2937 /* check if there is HT MSI cap or enabled on this device */ 2938 found = ht_check_msi_mapping(dev); 2939 2940 /* no HT MSI CAP */ 2941 if (found == 0) 2942 return; 2943 2944 /* 2945 * HT MSI mapping should be disabled on devices that are below 2946 * a non-Hypertransport host bridge. Locate the host bridge... 2947 */ 2948 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2949 PCI_DEVFN(0, 0)); 2950 if (host_bridge == NULL) { 2951 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2952 return; 2953 } 2954 2955 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2956 if (pos != 0) { 2957 /* Host bridge is to HT */ 2958 if (found == 1) { 2959 /* it is not enabled, try to enable it */ 2960 if (all) 2961 ht_enable_msi_mapping(dev); 2962 else 2963 nv_ht_enable_msi_mapping(dev); 2964 } 2965 goto out; 2966 } 2967 2968 /* HT MSI is not enabled */ 2969 if (found == 1) 2970 goto out; 2971 2972 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2973 ht_disable_msi_mapping(dev); 2974 2975 out: 2976 pci_dev_put(host_bridge); 2977 } 2978 2979 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2980 { 2981 return __nv_msi_ht_cap_quirk(dev, 1); 2982 } 2983 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2984 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2985 2986 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2987 { 2988 return __nv_msi_ht_cap_quirk(dev, 0); 2989 } 2990 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2991 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2992 2993 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2994 { 2995 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2996 } 2997 2998 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2999 { 3000 struct pci_dev *p; 3001 3002 /* 3003 * SB700 MSI issue will be fixed at HW level from revision A21; 3004 * we need check PCI REVISION ID of SMBus controller to get SB700 3005 * revision. 3006 */ 3007 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3008 NULL); 3009 if (!p) 3010 return; 3011 3012 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3013 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3014 pci_dev_put(p); 3015 } 3016 3017 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3018 { 3019 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3020 if (dev->revision < 0x18) { 3021 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3022 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3023 } 3024 } 3025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3026 PCI_DEVICE_ID_TIGON3_5780, 3027 quirk_msi_intx_disable_bug); 3028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3029 PCI_DEVICE_ID_TIGON3_5780S, 3030 quirk_msi_intx_disable_bug); 3031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3032 PCI_DEVICE_ID_TIGON3_5714, 3033 quirk_msi_intx_disable_bug); 3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3035 PCI_DEVICE_ID_TIGON3_5714S, 3036 quirk_msi_intx_disable_bug); 3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3038 PCI_DEVICE_ID_TIGON3_5715, 3039 quirk_msi_intx_disable_bug); 3040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3041 PCI_DEVICE_ID_TIGON3_5715S, 3042 quirk_msi_intx_disable_bug); 3043 3044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3045 quirk_msi_intx_disable_ati_bug); 3046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3047 quirk_msi_intx_disable_ati_bug); 3048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3049 quirk_msi_intx_disable_ati_bug); 3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3051 quirk_msi_intx_disable_ati_bug); 3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3053 quirk_msi_intx_disable_ati_bug); 3054 3055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3056 quirk_msi_intx_disable_bug); 3057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3058 quirk_msi_intx_disable_bug); 3059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3060 quirk_msi_intx_disable_bug); 3061 3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3063 quirk_msi_intx_disable_bug); 3064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3065 quirk_msi_intx_disable_bug); 3066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3067 quirk_msi_intx_disable_bug); 3068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3069 quirk_msi_intx_disable_bug); 3070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3071 quirk_msi_intx_disable_bug); 3072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3073 quirk_msi_intx_disable_bug); 3074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3075 quirk_msi_intx_disable_qca_bug); 3076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3077 quirk_msi_intx_disable_qca_bug); 3078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3079 quirk_msi_intx_disable_qca_bug); 3080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3081 quirk_msi_intx_disable_qca_bug); 3082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3083 quirk_msi_intx_disable_qca_bug); 3084 3085 /* 3086 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3087 * should be disabled on platforms where the device (mistakenly) advertises it. 3088 * 3089 * Notice that this quirk also disables MSI (which may work, but hasn't been 3090 * tested), since currently there is no standard way to disable only MSI-X. 3091 * 3092 * The 0031 device id is reused for other non Root Port device types, 3093 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3094 */ 3095 static void quirk_al_msi_disable(struct pci_dev *dev) 3096 { 3097 dev->no_msi = 1; 3098 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3099 } 3100 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3101 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3102 #endif /* CONFIG_PCI_MSI */ 3103 3104 /* 3105 * Allow manual resource allocation for PCI hotplug bridges via 3106 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3107 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3108 * allocate resources when hotplug device is inserted and PCI bus is 3109 * rescanned. 3110 */ 3111 static void quirk_hotplug_bridge(struct pci_dev *dev) 3112 { 3113 dev->is_hotplug_bridge = 1; 3114 } 3115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3116 3117 /* 3118 * This is a quirk for the Ricoh MMC controller found as a part of some 3119 * multifunction chips. 3120 * 3121 * This is very similar and based on the ricoh_mmc driver written by 3122 * Philip Langdale. Thank you for these magic sequences. 3123 * 3124 * These chips implement the four main memory card controllers (SD, MMC, 3125 * MS, xD) and one or both of CardBus or FireWire. 3126 * 3127 * It happens that they implement SD and MMC support as separate 3128 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3129 * cards but the chip detects MMC cards in hardware and directs them to the 3130 * MMC controller - so the SDHCI driver never sees them. 3131 * 3132 * To get around this, we must disable the useless MMC controller. At that 3133 * point, the SDHCI controller will start seeing them. It seems to be the 3134 * case that the relevant PCI registers to deactivate the MMC controller 3135 * live on PCI function 0, which might be the CardBus controller or the 3136 * FireWire controller, depending on the particular chip in question 3137 * 3138 * This has to be done early, because as soon as we disable the MMC controller 3139 * other PCI functions shift up one level, e.g. function #2 becomes function 3140 * #1, and this will confuse the PCI core. 3141 */ 3142 #ifdef CONFIG_MMC_RICOH_MMC 3143 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3144 { 3145 u8 write_enable; 3146 u8 write_target; 3147 u8 disable; 3148 3149 /* 3150 * Disable via CardBus interface 3151 * 3152 * This must be done via function #0 3153 */ 3154 if (PCI_FUNC(dev->devfn)) 3155 return; 3156 3157 pci_read_config_byte(dev, 0xB7, &disable); 3158 if (disable & 0x02) 3159 return; 3160 3161 pci_read_config_byte(dev, 0x8E, &write_enable); 3162 pci_write_config_byte(dev, 0x8E, 0xAA); 3163 pci_read_config_byte(dev, 0x8D, &write_target); 3164 pci_write_config_byte(dev, 0x8D, 0xB7); 3165 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3166 pci_write_config_byte(dev, 0x8E, write_enable); 3167 pci_write_config_byte(dev, 0x8D, write_target); 3168 3169 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3170 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3171 } 3172 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3173 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3174 3175 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3176 { 3177 u8 write_enable; 3178 u8 disable; 3179 3180 /* 3181 * Disable via FireWire interface 3182 * 3183 * This must be done via function #0 3184 */ 3185 if (PCI_FUNC(dev->devfn)) 3186 return; 3187 /* 3188 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3189 * certain types of SD/MMC cards. Lowering the SD base clock 3190 * frequency from 200Mhz to 50Mhz fixes this issue. 3191 * 3192 * 0x150 - SD2.0 mode enable for changing base clock 3193 * frequency to 50Mhz 3194 * 0xe1 - Base clock frequency 3195 * 0x32 - 50Mhz new clock frequency 3196 * 0xf9 - Key register for 0x150 3197 * 0xfc - key register for 0xe1 3198 */ 3199 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3200 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3201 pci_write_config_byte(dev, 0xf9, 0xfc); 3202 pci_write_config_byte(dev, 0x150, 0x10); 3203 pci_write_config_byte(dev, 0xf9, 0x00); 3204 pci_write_config_byte(dev, 0xfc, 0x01); 3205 pci_write_config_byte(dev, 0xe1, 0x32); 3206 pci_write_config_byte(dev, 0xfc, 0x00); 3207 3208 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3209 } 3210 3211 pci_read_config_byte(dev, 0xCB, &disable); 3212 3213 if (disable & 0x02) 3214 return; 3215 3216 pci_read_config_byte(dev, 0xCA, &write_enable); 3217 pci_write_config_byte(dev, 0xCA, 0x57); 3218 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3219 pci_write_config_byte(dev, 0xCA, write_enable); 3220 3221 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3222 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3223 3224 } 3225 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3226 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3227 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3228 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3229 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3230 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3231 #endif /*CONFIG_MMC_RICOH_MMC*/ 3232 3233 #ifdef CONFIG_DMAR_TABLE 3234 #define VTUNCERRMSK_REG 0x1ac 3235 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3236 /* 3237 * This is a quirk for masking VT-d spec-defined errors to platform error 3238 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3239 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3240 * on the RAS config settings of the platform) when a VT-d fault happens. 3241 * The resulting SMI caused the system to hang. 3242 * 3243 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3244 * need to report the same error through other channels. 3245 */ 3246 static void vtd_mask_spec_errors(struct pci_dev *dev) 3247 { 3248 u32 word; 3249 3250 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3251 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3252 } 3253 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3254 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3255 #endif 3256 3257 static void fixup_ti816x_class(struct pci_dev *dev) 3258 { 3259 u32 class = dev->class; 3260 3261 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3262 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3263 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3264 class, dev->class); 3265 } 3266 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3267 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3268 3269 /* 3270 * Some PCIe devices do not work reliably with the claimed maximum 3271 * payload size supported. 3272 */ 3273 static void fixup_mpss_256(struct pci_dev *dev) 3274 { 3275 dev->pcie_mpss = 1; /* 256 bytes */ 3276 } 3277 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3278 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3279 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3280 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3281 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3282 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3283 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3284 3285 /* 3286 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3287 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3288 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3289 * until all of the devices are discovered and buses walked, read completion 3290 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3291 * it is possible to hotplug a device with MPS of 256B. 3292 */ 3293 static void quirk_intel_mc_errata(struct pci_dev *dev) 3294 { 3295 int err; 3296 u16 rcc; 3297 3298 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3299 pcie_bus_config == PCIE_BUS_DEFAULT) 3300 return; 3301 3302 /* 3303 * Intel erratum specifies bits to change but does not say what 3304 * they are. Keeping them magical until such time as the registers 3305 * and values can be explained. 3306 */ 3307 err = pci_read_config_word(dev, 0x48, &rcc); 3308 if (err) { 3309 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3310 return; 3311 } 3312 3313 if (!(rcc & (1 << 10))) 3314 return; 3315 3316 rcc &= ~(1 << 10); 3317 3318 err = pci_write_config_word(dev, 0x48, rcc); 3319 if (err) { 3320 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3321 return; 3322 } 3323 3324 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3325 } 3326 /* Intel 5000 series memory controllers and ports 2-7 */ 3327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3341 /* Intel 5100 series memory controllers and ports 2-7 */ 3342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3353 3354 /* 3355 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3356 * To work around this, query the size it should be configured to by the 3357 * device and modify the resource end to correspond to this new size. 3358 */ 3359 static void quirk_intel_ntb(struct pci_dev *dev) 3360 { 3361 int rc; 3362 u8 val; 3363 3364 rc = pci_read_config_byte(dev, 0x00D0, &val); 3365 if (rc) 3366 return; 3367 3368 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3369 3370 rc = pci_read_config_byte(dev, 0x00D1, &val); 3371 if (rc) 3372 return; 3373 3374 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3375 } 3376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3378 3379 /* 3380 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3381 * though no one is handling them (e.g., if the i915 driver is never 3382 * loaded). Additionally the interrupt destination is not set up properly 3383 * and the interrupt ends up -somewhere-. 3384 * 3385 * These spurious interrupts are "sticky" and the kernel disables the 3386 * (shared) interrupt line after 100,000+ generated interrupts. 3387 * 3388 * Fix it by disabling the still enabled interrupts. This resolves crashes 3389 * often seen on monitor unplug. 3390 */ 3391 #define I915_DEIER_REG 0x4400c 3392 static void disable_igfx_irq(struct pci_dev *dev) 3393 { 3394 void __iomem *regs = pci_iomap(dev, 0, 0); 3395 if (regs == NULL) { 3396 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3397 return; 3398 } 3399 3400 /* Check if any interrupt line is still enabled */ 3401 if (readl(regs + I915_DEIER_REG) != 0) { 3402 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3403 3404 writel(0, regs + I915_DEIER_REG); 3405 } 3406 3407 pci_iounmap(dev, regs); 3408 } 3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3416 3417 /* 3418 * PCI devices which are on Intel chips can skip the 10ms delay 3419 * before entering D3 mode. 3420 */ 3421 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3422 { 3423 dev->d3hot_delay = 0; 3424 } 3425 /* C600 Series devices do not need 10ms d3hot_delay */ 3426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3429 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3441 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3451 3452 /* 3453 * Some devices may pass our check in pci_intx_mask_supported() if 3454 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3455 * support this feature. 3456 */ 3457 static void quirk_broken_intx_masking(struct pci_dev *dev) 3458 { 3459 dev->broken_intx_masking = 1; 3460 } 3461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3462 quirk_broken_intx_masking); 3463 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3464 quirk_broken_intx_masking); 3465 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3466 quirk_broken_intx_masking); 3467 3468 /* 3469 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3470 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3471 * 3472 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3473 */ 3474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3475 quirk_broken_intx_masking); 3476 3477 /* 3478 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3479 * DisINTx can be set but the interrupt status bit is non-functional. 3480 */ 3481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3489 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3493 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3497 3498 static u16 mellanox_broken_intx_devs[] = { 3499 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3500 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3501 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3502 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3503 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3504 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3505 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3506 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3507 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3508 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3509 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3510 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3511 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3512 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3513 }; 3514 3515 #define CONNECTX_4_CURR_MAX_MINOR 99 3516 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3517 3518 /* 3519 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3520 * If so, don't mark it as broken. 3521 * FW minor > 99 means older FW version format and no INTx masking support. 3522 * FW minor < 14 means new FW version format and no INTx masking support. 3523 */ 3524 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3525 { 3526 __be32 __iomem *fw_ver; 3527 u16 fw_major; 3528 u16 fw_minor; 3529 u16 fw_subminor; 3530 u32 fw_maj_min; 3531 u32 fw_sub_min; 3532 int i; 3533 3534 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3535 if (pdev->device == mellanox_broken_intx_devs[i]) { 3536 pdev->broken_intx_masking = 1; 3537 return; 3538 } 3539 } 3540 3541 /* 3542 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3543 * support so shouldn't be checked further 3544 */ 3545 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3546 return; 3547 3548 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3549 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3550 return; 3551 3552 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3553 if (pci_enable_device_mem(pdev)) { 3554 pci_warn(pdev, "Can't enable device memory\n"); 3555 return; 3556 } 3557 3558 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3559 if (!fw_ver) { 3560 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3561 goto out; 3562 } 3563 3564 /* Reading from resource space should be 32b aligned */ 3565 fw_maj_min = ioread32be(fw_ver); 3566 fw_sub_min = ioread32be(fw_ver + 1); 3567 fw_major = fw_maj_min & 0xffff; 3568 fw_minor = fw_maj_min >> 16; 3569 fw_subminor = fw_sub_min & 0xffff; 3570 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3571 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3572 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3573 fw_major, fw_minor, fw_subminor, pdev->device == 3574 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3575 pdev->broken_intx_masking = 1; 3576 } 3577 3578 iounmap(fw_ver); 3579 3580 out: 3581 pci_disable_device(pdev); 3582 } 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3584 mellanox_check_broken_intx_masking); 3585 3586 static void quirk_no_bus_reset(struct pci_dev *dev) 3587 { 3588 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3589 } 3590 3591 /* 3592 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3593 * prevented for those affected devices. 3594 */ 3595 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3596 { 3597 if ((dev->device & 0xffc0) == 0x2340) 3598 quirk_no_bus_reset(dev); 3599 } 3600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3601 quirk_nvidia_no_bus_reset); 3602 3603 /* 3604 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3605 * The device will throw a Link Down error on AER-capable systems and 3606 * regardless of AER, config space of the device is never accessible again 3607 * and typically causes the system to hang or reset when access is attempted. 3608 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3609 */ 3610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3616 3617 /* 3618 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3619 * reset when used with certain child devices. After the reset, config 3620 * accesses to the child may fail. 3621 */ 3622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3623 3624 /* 3625 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3626 * automatically disables LTSSM when Secondary Bus Reset is received and 3627 * the device stops working. Prevent bus reset for these devices. With 3628 * this change, the device can be assigned to VMs with VFIO, but it will 3629 * leak state between VMs. Reference 3630 * https://e2e.ti.com/support/processors/f/791/t/954382 3631 */ 3632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3633 3634 static void quirk_no_pm_reset(struct pci_dev *dev) 3635 { 3636 /* 3637 * We can't do a bus reset on root bus devices, but an ineffective 3638 * PM reset may be better than nothing. 3639 */ 3640 if (!pci_is_root_bus(dev->bus)) 3641 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3642 } 3643 3644 /* 3645 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3646 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3647 * to have no effect on the device: it retains the framebuffer contents and 3648 * monitor sync. Advertising this support makes other layers, like VFIO, 3649 * assume pci_reset_function() is viable for this device. Mark it as 3650 * unavailable to skip it when testing reset methods. 3651 */ 3652 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3653 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3654 3655 /* 3656 * Thunderbolt controllers with broken MSI hotplug signaling: 3657 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3658 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3659 */ 3660 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3661 { 3662 if (pdev->is_hotplug_bridge && 3663 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3664 pdev->revision <= 1)) 3665 pdev->no_msi = 1; 3666 } 3667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3668 quirk_thunderbolt_hotplug_msi); 3669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3670 quirk_thunderbolt_hotplug_msi); 3671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3672 quirk_thunderbolt_hotplug_msi); 3673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3674 quirk_thunderbolt_hotplug_msi); 3675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3676 quirk_thunderbolt_hotplug_msi); 3677 3678 #ifdef CONFIG_ACPI 3679 /* 3680 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3681 * 3682 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3683 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3684 * be present after resume if a device was plugged in before suspend. 3685 * 3686 * The Thunderbolt controller consists of a PCIe switch with downstream 3687 * bridges leading to the NHI and to the tunnel PCI bridges. 3688 * 3689 * This quirk cuts power to the whole chip. Therefore we have to apply it 3690 * during suspend_noirq of the upstream bridge. 3691 * 3692 * Power is automagically restored before resume. No action is needed. 3693 */ 3694 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3695 { 3696 acpi_handle bridge, SXIO, SXFP, SXLV; 3697 3698 if (!x86_apple_machine) 3699 return; 3700 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3701 return; 3702 3703 /* 3704 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3705 * We don't know how to turn it back on again, but firmware does, 3706 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3707 * firmware. 3708 */ 3709 if (!pm_suspend_via_firmware()) 3710 return; 3711 3712 bridge = ACPI_HANDLE(&dev->dev); 3713 if (!bridge) 3714 return; 3715 3716 /* 3717 * SXIO and SXLV are present only on machines requiring this quirk. 3718 * Thunderbolt bridges in external devices might have the same 3719 * device ID as those on the host, but they will not have the 3720 * associated ACPI methods. This implicitly checks that we are at 3721 * the right bridge. 3722 */ 3723 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3724 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3725 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3726 return; 3727 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3728 3729 /* magic sequence */ 3730 acpi_execute_simple_method(SXIO, NULL, 1); 3731 acpi_execute_simple_method(SXFP, NULL, 0); 3732 msleep(300); 3733 acpi_execute_simple_method(SXLV, NULL, 0); 3734 acpi_execute_simple_method(SXIO, NULL, 0); 3735 acpi_execute_simple_method(SXLV, NULL, 0); 3736 } 3737 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3738 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3739 quirk_apple_poweroff_thunderbolt); 3740 #endif 3741 3742 /* 3743 * Following are device-specific reset methods which can be used to 3744 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3745 * not available. 3746 */ 3747 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3748 { 3749 /* 3750 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3751 * 3752 * The 82599 supports FLR on VFs, but FLR support is reported only 3753 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3754 * Thus we must call pcie_flr() directly without first checking if it is 3755 * supported. 3756 */ 3757 if (!probe) 3758 pcie_flr(dev); 3759 return 0; 3760 } 3761 3762 #define SOUTH_CHICKEN2 0xc2004 3763 #define PCH_PP_STATUS 0xc7200 3764 #define PCH_PP_CONTROL 0xc7204 3765 #define MSG_CTL 0x45010 3766 #define NSDE_PWR_STATE 0xd0100 3767 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3768 3769 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3770 { 3771 void __iomem *mmio_base; 3772 unsigned long timeout; 3773 u32 val; 3774 3775 if (probe) 3776 return 0; 3777 3778 mmio_base = pci_iomap(dev, 0, 0); 3779 if (!mmio_base) 3780 return -ENOMEM; 3781 3782 iowrite32(0x00000002, mmio_base + MSG_CTL); 3783 3784 /* 3785 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3786 * driver loaded sets the right bits. However, this's a reset and 3787 * the bits have been set by i915 previously, so we clobber 3788 * SOUTH_CHICKEN2 register directly here. 3789 */ 3790 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3791 3792 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3793 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3794 3795 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3796 do { 3797 val = ioread32(mmio_base + PCH_PP_STATUS); 3798 if ((val & 0xb0000000) == 0) 3799 goto reset_complete; 3800 msleep(10); 3801 } while (time_before(jiffies, timeout)); 3802 pci_warn(dev, "timeout during reset\n"); 3803 3804 reset_complete: 3805 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3806 3807 pci_iounmap(dev, mmio_base); 3808 return 0; 3809 } 3810 3811 /* Device-specific reset method for Chelsio T4-based adapters */ 3812 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3813 { 3814 u16 old_command; 3815 u16 msix_flags; 3816 3817 /* 3818 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3819 * that we have no device-specific reset method. 3820 */ 3821 if ((dev->device & 0xf000) != 0x4000) 3822 return -ENOTTY; 3823 3824 /* 3825 * If this is the "probe" phase, return 0 indicating that we can 3826 * reset this device. 3827 */ 3828 if (probe) 3829 return 0; 3830 3831 /* 3832 * T4 can wedge if there are DMAs in flight within the chip and Bus 3833 * Master has been disabled. We need to have it on till the Function 3834 * Level Reset completes. (BUS_MASTER is disabled in 3835 * pci_reset_function()). 3836 */ 3837 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3838 pci_write_config_word(dev, PCI_COMMAND, 3839 old_command | PCI_COMMAND_MASTER); 3840 3841 /* 3842 * Perform the actual device function reset, saving and restoring 3843 * configuration information around the reset. 3844 */ 3845 pci_save_state(dev); 3846 3847 /* 3848 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3849 * are disabled when an MSI-X interrupt message needs to be delivered. 3850 * So we briefly re-enable MSI-X interrupts for the duration of the 3851 * FLR. The pci_restore_state() below will restore the original 3852 * MSI-X state. 3853 */ 3854 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3855 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3856 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3857 msix_flags | 3858 PCI_MSIX_FLAGS_ENABLE | 3859 PCI_MSIX_FLAGS_MASKALL); 3860 3861 pcie_flr(dev); 3862 3863 /* 3864 * Restore the configuration information (BAR values, etc.) including 3865 * the original PCI Configuration Space Command word, and return 3866 * success. 3867 */ 3868 pci_restore_state(dev); 3869 pci_write_config_word(dev, PCI_COMMAND, old_command); 3870 return 0; 3871 } 3872 3873 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3874 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3875 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3876 3877 /* 3878 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 3879 * FLR where config space reads from the device return -1. We seem to be 3880 * able to avoid this condition if we disable the NVMe controller prior to 3881 * FLR. This quirk is generic for any NVMe class device requiring similar 3882 * assistance to quiesce the device prior to FLR. 3883 * 3884 * NVMe specification: https://nvmexpress.org/resources/specifications/ 3885 * Revision 1.0e: 3886 * Chapter 2: Required and optional PCI config registers 3887 * Chapter 3: NVMe control registers 3888 * Chapter 7.3: Reset behavior 3889 */ 3890 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 3891 { 3892 void __iomem *bar; 3893 u16 cmd; 3894 u32 cfg; 3895 3896 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 3897 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 3898 return -ENOTTY; 3899 3900 if (probe) 3901 return 0; 3902 3903 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 3904 if (!bar) 3905 return -ENOTTY; 3906 3907 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3908 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 3909 3910 cfg = readl(bar + NVME_REG_CC); 3911 3912 /* Disable controller if enabled */ 3913 if (cfg & NVME_CC_ENABLE) { 3914 u32 cap = readl(bar + NVME_REG_CAP); 3915 unsigned long timeout; 3916 3917 /* 3918 * Per nvme_disable_ctrl() skip shutdown notification as it 3919 * could complete commands to the admin queue. We only intend 3920 * to quiesce the device before reset. 3921 */ 3922 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 3923 3924 writel(cfg, bar + NVME_REG_CC); 3925 3926 /* 3927 * Some controllers require an additional delay here, see 3928 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 3929 * supported by this quirk. 3930 */ 3931 3932 /* Cap register provides max timeout in 500ms increments */ 3933 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 3934 3935 for (;;) { 3936 u32 status = readl(bar + NVME_REG_CSTS); 3937 3938 /* Ready status becomes zero on disable complete */ 3939 if (!(status & NVME_CSTS_RDY)) 3940 break; 3941 3942 msleep(100); 3943 3944 if (time_after(jiffies, timeout)) { 3945 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 3946 break; 3947 } 3948 } 3949 } 3950 3951 pci_iounmap(dev, bar); 3952 3953 pcie_flr(dev); 3954 3955 return 0; 3956 } 3957 3958 /* 3959 * Intel DC P3700 NVMe controller will timeout waiting for ready status 3960 * to change after NVMe enable if the driver starts interacting with the 3961 * device too soon after FLR. A 250ms delay after FLR has heuristically 3962 * proven to produce reliably working results for device assignment cases. 3963 */ 3964 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 3965 { 3966 if (probe) 3967 return pcie_reset_flr(dev, PCI_RESET_PROBE); 3968 3969 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 3970 3971 msleep(250); 3972 3973 return 0; 3974 } 3975 3976 #define PCI_DEVICE_ID_HINIC_VF 0x375E 3977 #define HINIC_VF_FLR_TYPE 0x1000 3978 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 3979 #define HINIC_VF_OP 0xE80 3980 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 3981 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 3982 3983 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 3984 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 3985 { 3986 unsigned long timeout; 3987 void __iomem *bar; 3988 u32 val; 3989 3990 if (probe) 3991 return 0; 3992 3993 bar = pci_iomap(pdev, 0, 0); 3994 if (!bar) 3995 return -ENOTTY; 3996 3997 /* Get and check firmware capabilities */ 3998 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 3999 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4000 pci_iounmap(pdev, bar); 4001 return -ENOTTY; 4002 } 4003 4004 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4005 val = ioread32be(bar + HINIC_VF_OP); 4006 val = val | HINIC_VF_FLR_PROC_BIT; 4007 iowrite32be(val, bar + HINIC_VF_OP); 4008 4009 pcie_flr(pdev); 4010 4011 /* 4012 * The device must recapture its Bus and Device Numbers after FLR 4013 * in order generate Completions. Issue a config write to let the 4014 * device capture this information. 4015 */ 4016 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4017 4018 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4019 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4020 do { 4021 val = ioread32be(bar + HINIC_VF_OP); 4022 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4023 goto reset_complete; 4024 msleep(20); 4025 } while (time_before(jiffies, timeout)); 4026 4027 val = ioread32be(bar + HINIC_VF_OP); 4028 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4029 goto reset_complete; 4030 4031 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4032 4033 reset_complete: 4034 pci_iounmap(pdev, bar); 4035 4036 return 0; 4037 } 4038 4039 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4040 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4041 reset_intel_82599_sfp_virtfn }, 4042 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4043 reset_ivb_igd }, 4044 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4045 reset_ivb_igd }, 4046 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4047 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4048 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4049 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4050 reset_chelsio_generic_dev }, 4051 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4052 reset_hinic_vf_dev }, 4053 { 0 } 4054 }; 4055 4056 /* 4057 * These device-specific reset methods are here rather than in a driver 4058 * because when a host assigns a device to a guest VM, the host may need 4059 * to reset the device but probably doesn't have a driver for it. 4060 */ 4061 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4062 { 4063 const struct pci_dev_reset_methods *i; 4064 4065 for (i = pci_dev_reset_methods; i->reset; i++) { 4066 if ((i->vendor == dev->vendor || 4067 i->vendor == (u16)PCI_ANY_ID) && 4068 (i->device == dev->device || 4069 i->device == (u16)PCI_ANY_ID)) 4070 return i->reset(dev, probe); 4071 } 4072 4073 return -ENOTTY; 4074 } 4075 4076 static void quirk_dma_func0_alias(struct pci_dev *dev) 4077 { 4078 if (PCI_FUNC(dev->devfn) != 0) 4079 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4080 } 4081 4082 /* 4083 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4084 * 4085 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4086 */ 4087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4089 4090 static void quirk_dma_func1_alias(struct pci_dev *dev) 4091 { 4092 if (PCI_FUNC(dev->devfn) != 1) 4093 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4094 } 4095 4096 /* 4097 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4098 * SKUs function 1 is present and is a legacy IDE controller, in other 4099 * SKUs this function is not present, making this a ghost requester. 4100 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4101 */ 4102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4103 quirk_dma_func1_alias); 4104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4105 quirk_dma_func1_alias); 4106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4107 quirk_dma_func1_alias); 4108 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4110 quirk_dma_func1_alias); 4111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4112 quirk_dma_func1_alias); 4113 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4115 quirk_dma_func1_alias); 4116 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4118 quirk_dma_func1_alias); 4119 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4121 quirk_dma_func1_alias); 4122 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4124 quirk_dma_func1_alias); 4125 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4127 quirk_dma_func1_alias); 4128 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4130 quirk_dma_func1_alias); 4131 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4133 quirk_dma_func1_alias); 4134 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4136 quirk_dma_func1_alias); 4137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4138 quirk_dma_func1_alias); 4139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4140 quirk_dma_func1_alias); 4141 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4143 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4144 quirk_dma_func1_alias); 4145 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4146 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4147 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4148 quirk_dma_func1_alias); 4149 4150 /* 4151 * Some devices DMA with the wrong devfn, not just the wrong function. 4152 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4153 * the alias is "fixed" and independent of the device devfn. 4154 * 4155 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4156 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4157 * single device on the secondary bus. In reality, the single exposed 4158 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4159 * that provides a bridge to the internal bus of the I/O processor. The 4160 * controller supports private devices, which can be hidden from PCI config 4161 * space. In the case of the Adaptec 3405, a private device at 01.0 4162 * appears to be the DMA engine, which therefore needs to become a DMA 4163 * alias for the device. 4164 */ 4165 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4166 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4167 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4168 .driver_data = PCI_DEVFN(1, 0) }, 4169 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4170 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4171 .driver_data = PCI_DEVFN(1, 0) }, 4172 { 0 } 4173 }; 4174 4175 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4176 { 4177 const struct pci_device_id *id; 4178 4179 id = pci_match_id(fixed_dma_alias_tbl, dev); 4180 if (id) 4181 pci_add_dma_alias(dev, id->driver_data, 1); 4182 } 4183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4184 4185 /* 4186 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4187 * using the wrong DMA alias for the device. Some of these devices can be 4188 * used as either forward or reverse bridges, so we need to test whether the 4189 * device is operating in the correct mode. We could probably apply this 4190 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4191 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4192 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4193 */ 4194 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4195 { 4196 if (!pci_is_root_bus(pdev->bus) && 4197 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4198 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4199 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4200 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4201 } 4202 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4204 quirk_use_pcie_bridge_dma_alias); 4205 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4206 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4207 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4208 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4209 /* ITE 8893 has the same problem as the 8892 */ 4210 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4211 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4212 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4213 4214 /* 4215 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4216 * be added as aliases to the DMA device in order to allow buffer access 4217 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4218 * programmed in the EEPROM. 4219 */ 4220 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4221 { 4222 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4223 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4224 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4225 } 4226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4228 4229 /* 4230 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4231 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4232 * 4233 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4234 * when IOMMU is enabled. These aliases allow computational unit access to 4235 * host memory. These aliases mark the whole VCA device as one IOMMU 4236 * group. 4237 * 4238 * All possible slot numbers (0x20) are used, since we are unable to tell 4239 * what slot is used on other side. This quirk is intended for both host 4240 * and computational unit sides. The VCA devices have up to five functions 4241 * (four for DMA channels and one additional). 4242 */ 4243 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4244 { 4245 const unsigned int num_pci_slots = 0x20; 4246 unsigned int slot; 4247 4248 for (slot = 0; slot < num_pci_slots; slot++) 4249 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4250 } 4251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4257 4258 /* 4259 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4260 * associated not at the root bus, but at a bridge below. This quirk avoids 4261 * generating invalid DMA aliases. 4262 */ 4263 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4264 { 4265 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4266 } 4267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4268 quirk_bridge_cavm_thrx2_pcie_root); 4269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4270 quirk_bridge_cavm_thrx2_pcie_root); 4271 4272 /* 4273 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4274 * class code. Fix it. 4275 */ 4276 static void quirk_tw686x_class(struct pci_dev *pdev) 4277 { 4278 u32 class = pdev->class; 4279 4280 /* Use "Multimedia controller" class */ 4281 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4282 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4283 class, pdev->class); 4284 } 4285 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4286 quirk_tw686x_class); 4287 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4288 quirk_tw686x_class); 4289 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4290 quirk_tw686x_class); 4291 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4292 quirk_tw686x_class); 4293 4294 /* 4295 * Some devices have problems with Transaction Layer Packets with the Relaxed 4296 * Ordering Attribute set. Such devices should mark themselves and other 4297 * device drivers should check before sending TLPs with RO set. 4298 */ 4299 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4300 { 4301 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4302 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4303 } 4304 4305 /* 4306 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4307 * Complex have a Flow Control Credit issue which can cause performance 4308 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4309 */ 4310 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4311 quirk_relaxedordering_disable); 4312 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4313 quirk_relaxedordering_disable); 4314 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4315 quirk_relaxedordering_disable); 4316 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4317 quirk_relaxedordering_disable); 4318 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4319 quirk_relaxedordering_disable); 4320 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4321 quirk_relaxedordering_disable); 4322 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4323 quirk_relaxedordering_disable); 4324 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4325 quirk_relaxedordering_disable); 4326 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4327 quirk_relaxedordering_disable); 4328 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4329 quirk_relaxedordering_disable); 4330 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4331 quirk_relaxedordering_disable); 4332 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4333 quirk_relaxedordering_disable); 4334 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4335 quirk_relaxedordering_disable); 4336 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4337 quirk_relaxedordering_disable); 4338 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4339 quirk_relaxedordering_disable); 4340 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4341 quirk_relaxedordering_disable); 4342 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4343 quirk_relaxedordering_disable); 4344 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4345 quirk_relaxedordering_disable); 4346 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4347 quirk_relaxedordering_disable); 4348 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4349 quirk_relaxedordering_disable); 4350 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4351 quirk_relaxedordering_disable); 4352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4353 quirk_relaxedordering_disable); 4354 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4355 quirk_relaxedordering_disable); 4356 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4357 quirk_relaxedordering_disable); 4358 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4359 quirk_relaxedordering_disable); 4360 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4361 quirk_relaxedordering_disable); 4362 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4363 quirk_relaxedordering_disable); 4364 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4365 quirk_relaxedordering_disable); 4366 4367 /* 4368 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4369 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4370 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4371 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4372 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4373 * November 10, 2010). As a result, on this platform we can't use Relaxed 4374 * Ordering for Upstream TLPs. 4375 */ 4376 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4377 quirk_relaxedordering_disable); 4378 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4379 quirk_relaxedordering_disable); 4380 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4381 quirk_relaxedordering_disable); 4382 4383 /* 4384 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4385 * values for the Attribute as were supplied in the header of the 4386 * corresponding Request, except as explicitly allowed when IDO is used." 4387 * 4388 * If a non-compliant device generates a completion with a different 4389 * attribute than the request, the receiver may accept it (which itself 4390 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4391 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4392 * device access timeout. 4393 * 4394 * If the non-compliant device generates completions with zero attributes 4395 * (instead of copying the attributes from the request), we can work around 4396 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4397 * upstream devices so they always generate requests with zero attributes. 4398 * 4399 * This affects other devices under the same Root Port, but since these 4400 * attributes are performance hints, there should be no functional problem. 4401 * 4402 * Note that Configuration Space accesses are never supposed to have TLP 4403 * Attributes, so we're safe waiting till after any Configuration Space 4404 * accesses to do the Root Port fixup. 4405 */ 4406 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4407 { 4408 struct pci_dev *root_port = pcie_find_root_port(pdev); 4409 4410 if (!root_port) { 4411 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4412 return; 4413 } 4414 4415 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4416 dev_name(&pdev->dev)); 4417 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4418 PCI_EXP_DEVCTL_RELAX_EN | 4419 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4420 } 4421 4422 /* 4423 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4424 * Completion it generates. 4425 */ 4426 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4427 { 4428 /* 4429 * This mask/compare operation selects for Physical Function 4 on a 4430 * T5. We only need to fix up the Root Port once for any of the 4431 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4432 * 0x54xx so we use that one. 4433 */ 4434 if ((pdev->device & 0xff00) == 0x5400) 4435 quirk_disable_root_port_attributes(pdev); 4436 } 4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4438 quirk_chelsio_T5_disable_root_port_attributes); 4439 4440 /* 4441 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4442 * by a device 4443 * @acs_ctrl_req: Bitmask of desired ACS controls 4444 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4445 * the hardware design 4446 * 4447 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4448 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4449 * caller desires. Return 0 otherwise. 4450 */ 4451 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4452 { 4453 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4454 return 1; 4455 return 0; 4456 } 4457 4458 /* 4459 * AMD has indicated that the devices below do not support peer-to-peer 4460 * in any system where they are found in the southbridge with an AMD 4461 * IOMMU in the system. Multifunction devices that do not support 4462 * peer-to-peer between functions can claim to support a subset of ACS. 4463 * Such devices effectively enable request redirect (RR) and completion 4464 * redirect (CR) since all transactions are redirected to the upstream 4465 * root complex. 4466 * 4467 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4468 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4469 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4470 * 4471 * 1002:4385 SBx00 SMBus Controller 4472 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4473 * 1002:4383 SBx00 Azalia (Intel HDA) 4474 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4475 * 1002:4384 SBx00 PCI to PCI Bridge 4476 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4477 * 4478 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4479 * 4480 * 1022:780f [AMD] FCH PCI Bridge 4481 * 1022:7809 [AMD] FCH USB OHCI Controller 4482 */ 4483 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4484 { 4485 #ifdef CONFIG_ACPI 4486 struct acpi_table_header *header = NULL; 4487 acpi_status status; 4488 4489 /* Targeting multifunction devices on the SB (appears on root bus) */ 4490 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4491 return -ENODEV; 4492 4493 /* The IVRS table describes the AMD IOMMU */ 4494 status = acpi_get_table("IVRS", 0, &header); 4495 if (ACPI_FAILURE(status)) 4496 return -ENODEV; 4497 4498 acpi_put_table(header); 4499 4500 /* Filter out flags not applicable to multifunction */ 4501 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4502 4503 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4504 #else 4505 return -ENODEV; 4506 #endif 4507 } 4508 4509 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4510 { 4511 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4512 return false; 4513 4514 switch (dev->device) { 4515 /* 4516 * Effectively selects all downstream ports for whole ThunderX1 4517 * (which represents 8 SoCs). 4518 */ 4519 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4520 case 0xaf84: /* ThunderX2 */ 4521 case 0xb884: /* ThunderX3 */ 4522 return true; 4523 default: 4524 return false; 4525 } 4526 } 4527 4528 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4529 { 4530 if (!pci_quirk_cavium_acs_match(dev)) 4531 return -ENOTTY; 4532 4533 /* 4534 * Cavium Root Ports don't advertise an ACS capability. However, 4535 * the RTL internally implements similar protection as if ACS had 4536 * Source Validation, Request Redirection, Completion Redirection, 4537 * and Upstream Forwarding features enabled. Assert that the 4538 * hardware implements and enables equivalent ACS functionality for 4539 * these flags. 4540 */ 4541 return pci_acs_ctrl_enabled(acs_flags, 4542 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4543 } 4544 4545 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4546 { 4547 /* 4548 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4549 * transactions with others, allowing masking out these bits as if they 4550 * were unimplemented in the ACS capability. 4551 */ 4552 return pci_acs_ctrl_enabled(acs_flags, 4553 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4554 } 4555 4556 /* 4557 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4558 * But the implementation could block peer-to-peer transactions between them 4559 * and provide ACS-like functionality. 4560 */ 4561 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4562 { 4563 if (!pci_is_pcie(dev) || 4564 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4565 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4566 return -ENOTTY; 4567 4568 switch (dev->device) { 4569 case 0x0710 ... 0x071e: 4570 case 0x0721: 4571 case 0x0723 ... 0x0732: 4572 return pci_acs_ctrl_enabled(acs_flags, 4573 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4574 } 4575 4576 return false; 4577 } 4578 4579 /* 4580 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4581 * transactions and validate bus numbers in requests, but do not provide an 4582 * actual PCIe ACS capability. This is the list of device IDs known to fall 4583 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4584 */ 4585 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4586 /* Ibexpeak PCH */ 4587 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4588 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4589 /* Cougarpoint PCH */ 4590 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4591 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4592 /* Pantherpoint PCH */ 4593 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4594 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4595 /* Lynxpoint-H PCH */ 4596 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4597 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4598 /* Lynxpoint-LP PCH */ 4599 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4600 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4601 /* Wildcat PCH */ 4602 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4603 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4604 /* Patsburg (X79) PCH */ 4605 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4606 /* Wellsburg (X99) PCH */ 4607 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4608 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4609 /* Lynx Point (9 series) PCH */ 4610 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4611 }; 4612 4613 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4614 { 4615 int i; 4616 4617 /* Filter out a few obvious non-matches first */ 4618 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4619 return false; 4620 4621 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4622 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4623 return true; 4624 4625 return false; 4626 } 4627 4628 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4629 { 4630 if (!pci_quirk_intel_pch_acs_match(dev)) 4631 return -ENOTTY; 4632 4633 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4634 return pci_acs_ctrl_enabled(acs_flags, 4635 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4636 4637 return pci_acs_ctrl_enabled(acs_flags, 0); 4638 } 4639 4640 /* 4641 * These QCOM Root Ports do provide ACS-like features to disable peer 4642 * transactions and validate bus numbers in requests, but do not provide an 4643 * actual PCIe ACS capability. Hardware supports source validation but it 4644 * will report the issue as Completer Abort instead of ACS Violation. 4645 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4646 * Complex with unique segment numbers. It is not possible for one Root 4647 * Port to pass traffic to another Root Port. All PCIe transactions are 4648 * terminated inside the Root Port. 4649 */ 4650 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4651 { 4652 return pci_acs_ctrl_enabled(acs_flags, 4653 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4654 } 4655 4656 /* 4657 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4658 * number and does provide isolation features to disable peer transactions 4659 * and validate bus numbers in requests, but does not provide an ACS 4660 * capability. 4661 */ 4662 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4663 { 4664 return pci_acs_ctrl_enabled(acs_flags, 4665 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4666 } 4667 4668 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4669 { 4670 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4671 return -ENOTTY; 4672 4673 /* 4674 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4675 * but do include ACS-like functionality. The hardware doesn't support 4676 * peer-to-peer transactions via the root port and each has a unique 4677 * segment number. 4678 * 4679 * Additionally, the root ports cannot send traffic to each other. 4680 */ 4681 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4682 4683 return acs_flags ? 0 : 1; 4684 } 4685 4686 /* 4687 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4688 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4689 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4690 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4691 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4692 * control register is at offset 8 instead of 6 and we should probably use 4693 * dword accesses to them. This applies to the following PCI Device IDs, as 4694 * found in volume 1 of the datasheet[2]: 4695 * 4696 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4697 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4698 * 4699 * N.B. This doesn't fix what lspci shows. 4700 * 4701 * The 100 series chipset specification update includes this as errata #23[3]. 4702 * 4703 * The 200 series chipset (Union Point) has the same bug according to the 4704 * specification update (Intel 200 Series Chipset Family Platform Controller 4705 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4706 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4707 * chipset include: 4708 * 4709 * 0xa290-0xa29f PCI Express Root port #{0-16} 4710 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4711 * 4712 * Mobile chipsets are also affected, 7th & 8th Generation 4713 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4714 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4715 * Processor Family I/O for U Quad Core Platforms Specification Update, 4716 * August 2017, Revision 002, Document#: 334660-002)[6] 4717 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4718 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4719 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4720 * 4721 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4722 * 4723 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4724 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4725 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4726 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4727 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4728 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4729 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4730 */ 4731 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4732 { 4733 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4734 return false; 4735 4736 switch (dev->device) { 4737 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4738 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4739 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4740 return true; 4741 } 4742 4743 return false; 4744 } 4745 4746 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4747 4748 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4749 { 4750 int pos; 4751 u32 cap, ctrl; 4752 4753 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4754 return -ENOTTY; 4755 4756 pos = dev->acs_cap; 4757 if (!pos) 4758 return -ENOTTY; 4759 4760 /* see pci_acs_flags_enabled() */ 4761 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4762 acs_flags &= (cap | PCI_ACS_EC); 4763 4764 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4765 4766 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4767 } 4768 4769 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4770 { 4771 /* 4772 * SV, TB, and UF are not relevant to multifunction endpoints. 4773 * 4774 * Multifunction devices are only required to implement RR, CR, and DT 4775 * in their ACS capability if they support peer-to-peer transactions. 4776 * Devices matching this quirk have been verified by the vendor to not 4777 * perform peer-to-peer with other functions, allowing us to mask out 4778 * these bits as if they were unimplemented in the ACS capability. 4779 */ 4780 return pci_acs_ctrl_enabled(acs_flags, 4781 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4782 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4783 } 4784 4785 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4786 { 4787 /* 4788 * Intel RCiEP's are required to allow p2p only on translated 4789 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4790 * "Root-Complex Peer to Peer Considerations". 4791 */ 4792 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4793 return -ENOTTY; 4794 4795 return pci_acs_ctrl_enabled(acs_flags, 4796 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4797 } 4798 4799 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4800 { 4801 /* 4802 * iProc PAXB Root Ports don't advertise an ACS capability, but 4803 * they do not allow peer-to-peer transactions between Root Ports. 4804 * Allow each Root Port to be in a separate IOMMU group by masking 4805 * SV/RR/CR/UF bits. 4806 */ 4807 return pci_acs_ctrl_enabled(acs_flags, 4808 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4809 } 4810 4811 static const struct pci_dev_acs_enabled { 4812 u16 vendor; 4813 u16 device; 4814 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4815 } pci_dev_acs_enabled[] = { 4816 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4817 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4818 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4819 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4820 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4821 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4822 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4823 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4824 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4825 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4826 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4827 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4828 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4829 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4830 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4831 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4832 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4833 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4834 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4835 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4836 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4837 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4838 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4839 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4840 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4841 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4842 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4843 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4844 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4845 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4846 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4847 /* 82580 */ 4848 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4849 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4850 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4851 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4852 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4853 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4854 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4855 /* 82576 */ 4856 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4857 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4858 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4859 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4860 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4861 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4862 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4863 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4864 /* 82575 */ 4865 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4866 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4867 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4868 /* I350 */ 4869 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4870 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4871 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4872 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4873 /* 82571 (Quads omitted due to non-ACS switch) */ 4874 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4875 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4876 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4877 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4878 /* I219 */ 4879 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4880 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4881 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 4882 /* QCOM QDF2xxx root ports */ 4883 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 4884 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 4885 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 4886 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 4887 /* Intel PCH root ports */ 4888 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4889 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4890 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4891 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4892 /* Cavium ThunderX */ 4893 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4894 /* Cavium multi-function devices */ 4895 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 4896 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 4897 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 4898 /* APM X-Gene */ 4899 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4900 /* Ampere Computing */ 4901 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 4902 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 4903 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 4904 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 4905 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 4906 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4907 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4908 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4909 /* Broadcom multi-function device */ 4910 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 4911 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 4912 /* Amazon Annapurna Labs */ 4913 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 4914 /* Zhaoxin multi-function devices */ 4915 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 4916 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 4917 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 4918 /* NXP root ports, xx=16, 12, or 08 cores */ 4919 /* LX2xx0A : without security features + CAN-FD */ 4920 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 4921 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 4922 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 4923 /* LX2xx0C : security features + CAN-FD */ 4924 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 4925 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 4926 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 4927 /* LX2xx0E : security features + CAN */ 4928 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 4929 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 4930 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 4931 /* LX2xx0N : without security features + CAN */ 4932 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 4933 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 4934 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 4935 /* LX2xx2A : without security features + CAN-FD */ 4936 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 4937 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 4938 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 4939 /* LX2xx2C : security features + CAN-FD */ 4940 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 4941 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 4942 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 4943 /* LX2xx2E : security features + CAN */ 4944 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 4945 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 4946 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 4947 /* LX2xx2N : without security features + CAN */ 4948 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 4949 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 4950 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 4951 /* Zhaoxin Root/Downstream Ports */ 4952 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 4953 { 0 } 4954 }; 4955 4956 /* 4957 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 4958 * @dev: PCI device 4959 * @acs_flags: Bitmask of desired ACS controls 4960 * 4961 * Returns: 4962 * -ENOTTY: No quirk applies to this device; we can't tell whether the 4963 * device provides the desired controls 4964 * 0: Device does not provide all the desired controls 4965 * >0: Device provides all the controls in @acs_flags 4966 */ 4967 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4968 { 4969 const struct pci_dev_acs_enabled *i; 4970 int ret; 4971 4972 /* 4973 * Allow devices that do not expose standard PCIe ACS capabilities 4974 * or control to indicate their support here. Multi-function express 4975 * devices which do not allow internal peer-to-peer between functions, 4976 * but do not implement PCIe ACS may wish to return true here. 4977 */ 4978 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4979 if ((i->vendor == dev->vendor || 4980 i->vendor == (u16)PCI_ANY_ID) && 4981 (i->device == dev->device || 4982 i->device == (u16)PCI_ANY_ID)) { 4983 ret = i->acs_enabled(dev, acs_flags); 4984 if (ret >= 0) 4985 return ret; 4986 } 4987 } 4988 4989 return -ENOTTY; 4990 } 4991 4992 /* Config space offset of Root Complex Base Address register */ 4993 #define INTEL_LPC_RCBA_REG 0xf0 4994 /* 31:14 RCBA address */ 4995 #define INTEL_LPC_RCBA_MASK 0xffffc000 4996 /* RCBA Enable */ 4997 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4998 4999 /* Backbone Scratch Pad Register */ 5000 #define INTEL_BSPR_REG 0x1104 5001 /* Backbone Peer Non-Posted Disable */ 5002 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5003 /* Backbone Peer Posted Disable */ 5004 #define INTEL_BSPR_REG_BPPD (1 << 9) 5005 5006 /* Upstream Peer Decode Configuration Register */ 5007 #define INTEL_UPDCR_REG 0x1014 5008 /* 5:0 Peer Decode Enable bits */ 5009 #define INTEL_UPDCR_REG_MASK 0x3f 5010 5011 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5012 { 5013 u32 rcba, bspr, updcr; 5014 void __iomem *rcba_mem; 5015 5016 /* 5017 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5018 * are D28:F* and therefore get probed before LPC, thus we can't 5019 * use pci_get_slot()/pci_read_config_dword() here. 5020 */ 5021 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5022 INTEL_LPC_RCBA_REG, &rcba); 5023 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5024 return -EINVAL; 5025 5026 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5027 PAGE_ALIGN(INTEL_UPDCR_REG)); 5028 if (!rcba_mem) 5029 return -ENOMEM; 5030 5031 /* 5032 * The BSPR can disallow peer cycles, but it's set by soft strap and 5033 * therefore read-only. If both posted and non-posted peer cycles are 5034 * disallowed, we're ok. If either are allowed, then we need to use 5035 * the UPDCR to disable peer decodes for each port. This provides the 5036 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5037 */ 5038 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5039 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5040 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5041 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5042 if (updcr & INTEL_UPDCR_REG_MASK) { 5043 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5044 updcr &= ~INTEL_UPDCR_REG_MASK; 5045 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5046 } 5047 } 5048 5049 iounmap(rcba_mem); 5050 return 0; 5051 } 5052 5053 /* Miscellaneous Port Configuration register */ 5054 #define INTEL_MPC_REG 0xd8 5055 /* MPC: Invalid Receive Bus Number Check Enable */ 5056 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5057 5058 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5059 { 5060 u32 mpc; 5061 5062 /* 5063 * When enabled, the IRBNCE bit of the MPC register enables the 5064 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5065 * ensures that requester IDs fall within the bus number range 5066 * of the bridge. Enable if not already. 5067 */ 5068 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5069 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5070 pci_info(dev, "Enabling MPC IRBNCE\n"); 5071 mpc |= INTEL_MPC_REG_IRBNCE; 5072 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5073 } 5074 } 5075 5076 /* 5077 * Currently this quirk does the equivalent of 5078 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5079 * 5080 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5081 * if dev->external_facing || dev->untrusted 5082 */ 5083 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5084 { 5085 if (!pci_quirk_intel_pch_acs_match(dev)) 5086 return -ENOTTY; 5087 5088 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5089 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5090 return 0; 5091 } 5092 5093 pci_quirk_enable_intel_rp_mpc_acs(dev); 5094 5095 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5096 5097 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5098 5099 return 0; 5100 } 5101 5102 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5103 { 5104 int pos; 5105 u32 cap, ctrl; 5106 5107 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5108 return -ENOTTY; 5109 5110 pos = dev->acs_cap; 5111 if (!pos) 5112 return -ENOTTY; 5113 5114 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5115 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5116 5117 ctrl |= (cap & PCI_ACS_SV); 5118 ctrl |= (cap & PCI_ACS_RR); 5119 ctrl |= (cap & PCI_ACS_CR); 5120 ctrl |= (cap & PCI_ACS_UF); 5121 5122 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5123 ctrl |= (cap & PCI_ACS_TB); 5124 5125 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5126 5127 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5128 5129 return 0; 5130 } 5131 5132 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5133 { 5134 int pos; 5135 u32 cap, ctrl; 5136 5137 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5138 return -ENOTTY; 5139 5140 pos = dev->acs_cap; 5141 if (!pos) 5142 return -ENOTTY; 5143 5144 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5145 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5146 5147 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5148 5149 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5150 5151 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5152 5153 return 0; 5154 } 5155 5156 static const struct pci_dev_acs_ops { 5157 u16 vendor; 5158 u16 device; 5159 int (*enable_acs)(struct pci_dev *dev); 5160 int (*disable_acs_redir)(struct pci_dev *dev); 5161 } pci_dev_acs_ops[] = { 5162 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5163 .enable_acs = pci_quirk_enable_intel_pch_acs, 5164 }, 5165 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5166 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5167 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5168 }, 5169 }; 5170 5171 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5172 { 5173 const struct pci_dev_acs_ops *p; 5174 int i, ret; 5175 5176 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5177 p = &pci_dev_acs_ops[i]; 5178 if ((p->vendor == dev->vendor || 5179 p->vendor == (u16)PCI_ANY_ID) && 5180 (p->device == dev->device || 5181 p->device == (u16)PCI_ANY_ID) && 5182 p->enable_acs) { 5183 ret = p->enable_acs(dev); 5184 if (ret >= 0) 5185 return ret; 5186 } 5187 } 5188 5189 return -ENOTTY; 5190 } 5191 5192 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5193 { 5194 const struct pci_dev_acs_ops *p; 5195 int i, ret; 5196 5197 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5198 p = &pci_dev_acs_ops[i]; 5199 if ((p->vendor == dev->vendor || 5200 p->vendor == (u16)PCI_ANY_ID) && 5201 (p->device == dev->device || 5202 p->device == (u16)PCI_ANY_ID) && 5203 p->disable_acs_redir) { 5204 ret = p->disable_acs_redir(dev); 5205 if (ret >= 0) 5206 return ret; 5207 } 5208 } 5209 5210 return -ENOTTY; 5211 } 5212 5213 /* 5214 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5215 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5216 * Next Capability pointer in the MSI Capability Structure should point to 5217 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5218 * the list. 5219 */ 5220 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5221 { 5222 int pos, i = 0; 5223 u8 next_cap; 5224 u16 reg16, *cap; 5225 struct pci_cap_saved_state *state; 5226 5227 /* Bail if the hardware bug is fixed */ 5228 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5229 return; 5230 5231 /* Bail if MSI Capability Structure is not found for some reason */ 5232 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5233 if (!pos) 5234 return; 5235 5236 /* 5237 * Bail if Next Capability pointer in the MSI Capability Structure 5238 * is not the expected incorrect 0x00. 5239 */ 5240 pci_read_config_byte(pdev, pos + 1, &next_cap); 5241 if (next_cap) 5242 return; 5243 5244 /* 5245 * PCIe Capability Structure is expected to be at 0x50 and should 5246 * terminate the list (Next Capability pointer is 0x00). Verify 5247 * Capability Id and Next Capability pointer is as expected. 5248 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5249 * to correctly set kernel data structures which have already been 5250 * set incorrectly due to the hardware bug. 5251 */ 5252 pos = 0x50; 5253 pci_read_config_word(pdev, pos, ®16); 5254 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5255 u32 status; 5256 #ifndef PCI_EXP_SAVE_REGS 5257 #define PCI_EXP_SAVE_REGS 7 5258 #endif 5259 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5260 5261 pdev->pcie_cap = pos; 5262 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5263 pdev->pcie_flags_reg = reg16; 5264 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5265 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5266 5267 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5268 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 5269 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 5270 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5271 5272 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5273 return; 5274 5275 /* Save PCIe cap */ 5276 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5277 if (!state) 5278 return; 5279 5280 state->cap.cap_nr = PCI_CAP_ID_EXP; 5281 state->cap.cap_extended = 0; 5282 state->cap.size = size; 5283 cap = (u16 *)&state->cap.data[0]; 5284 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5285 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5286 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5287 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5288 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5289 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5290 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5291 hlist_add_head(&state->next, &pdev->saved_cap_space); 5292 } 5293 } 5294 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5295 5296 /* 5297 * FLR may cause the following to devices to hang: 5298 * 5299 * AMD Starship/Matisse HD Audio Controller 0x1487 5300 * AMD Starship USB 3.0 Host Controller 0x148c 5301 * AMD Matisse USB 3.0 Host Controller 0x149c 5302 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5303 * Intel 82579V Gigabit Ethernet Controller 0x1503 5304 * 5305 */ 5306 static void quirk_no_flr(struct pci_dev *dev) 5307 { 5308 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5309 } 5310 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5311 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5312 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5313 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5314 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5315 5316 static void quirk_no_ext_tags(struct pci_dev *pdev) 5317 { 5318 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5319 5320 if (!bridge) 5321 return; 5322 5323 bridge->no_ext_tags = 1; 5324 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5325 5326 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5327 } 5328 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5329 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5331 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5333 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5334 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5335 5336 #ifdef CONFIG_PCI_ATS 5337 /* 5338 * Some devices require additional driver setup to enable ATS. Don't use 5339 * ATS for those devices as ATS will be enabled before the driver has had a 5340 * chance to load and configure the device. 5341 */ 5342 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5343 { 5344 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || 5345 (pdev->device == 0x7340 && pdev->revision != 0xc5) || 5346 (pdev->device == 0x7341 && pdev->revision != 0x00)) 5347 return; 5348 5349 if (pdev->device == 0x15d8) { 5350 if (pdev->revision == 0xcf && 5351 pdev->subsystem_vendor == 0xea50 && 5352 (pdev->subsystem_device == 0xce19 || 5353 pdev->subsystem_device == 0xcc10 || 5354 pdev->subsystem_device == 0xcc08)) 5355 goto no_ats; 5356 else 5357 return; 5358 } 5359 5360 no_ats: 5361 pci_info(pdev, "disabling ATS\n"); 5362 pdev->ats_cap = 0; 5363 } 5364 5365 /* AMD Stoney platform GPU */ 5366 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5367 /* AMD Iceland dGPU */ 5368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5369 /* AMD Navi10 dGPU */ 5370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5371 /* AMD Navi14 dGPU */ 5372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5374 /* AMD Raven platform iGPU */ 5375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5376 #endif /* CONFIG_PCI_ATS */ 5377 5378 /* Freescale PCIe doesn't support MSI in RC mode */ 5379 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5380 { 5381 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5382 pdev->no_msi = 1; 5383 } 5384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5385 5386 /* 5387 * Although not allowed by the spec, some multi-function devices have 5388 * dependencies of one function (consumer) on another (supplier). For the 5389 * consumer to work in D0, the supplier must also be in D0. Create a 5390 * device link from the consumer to the supplier to enforce this 5391 * dependency. Runtime PM is allowed by default on the consumer to prevent 5392 * it from permanently keeping the supplier awake. 5393 */ 5394 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5395 unsigned int supplier, unsigned int class, 5396 unsigned int class_shift) 5397 { 5398 struct pci_dev *supplier_pdev; 5399 5400 if (PCI_FUNC(pdev->devfn) != consumer) 5401 return; 5402 5403 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5404 pdev->bus->number, 5405 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5406 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5407 pci_dev_put(supplier_pdev); 5408 return; 5409 } 5410 5411 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5412 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5413 pci_info(pdev, "D0 power state depends on %s\n", 5414 pci_name(supplier_pdev)); 5415 else 5416 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5417 pci_name(supplier_pdev)); 5418 5419 pm_runtime_allow(&pdev->dev); 5420 pci_dev_put(supplier_pdev); 5421 } 5422 5423 /* 5424 * Create device link for GPUs with integrated HDA controller for streaming 5425 * audio to attached displays. 5426 */ 5427 static void quirk_gpu_hda(struct pci_dev *hda) 5428 { 5429 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5430 } 5431 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5432 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5433 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5434 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5435 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5436 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5437 5438 /* 5439 * Create device link for GPUs with integrated USB xHCI Host 5440 * controller to VGA. 5441 */ 5442 static void quirk_gpu_usb(struct pci_dev *usb) 5443 { 5444 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5445 } 5446 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5447 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5448 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5449 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5450 5451 /* 5452 * Create device link for GPUs with integrated Type-C UCSI controller 5453 * to VGA. Currently there is no class code defined for UCSI device over PCI 5454 * so using UNKNOWN class for now and it will be updated when UCSI 5455 * over PCI gets a class code. 5456 */ 5457 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5458 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5459 { 5460 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5461 } 5462 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5463 PCI_CLASS_SERIAL_UNKNOWN, 8, 5464 quirk_gpu_usb_typec_ucsi); 5465 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5466 PCI_CLASS_SERIAL_UNKNOWN, 8, 5467 quirk_gpu_usb_typec_ucsi); 5468 5469 /* 5470 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5471 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5472 */ 5473 static void quirk_nvidia_hda(struct pci_dev *gpu) 5474 { 5475 u8 hdr_type; 5476 u32 val; 5477 5478 /* There was no integrated HDA controller before MCP89 */ 5479 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5480 return; 5481 5482 /* Bit 25 at offset 0x488 enables the HDA controller */ 5483 pci_read_config_dword(gpu, 0x488, &val); 5484 if (val & BIT(25)) 5485 return; 5486 5487 pci_info(gpu, "Enabling HDA controller\n"); 5488 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5489 5490 /* The GPU becomes a multi-function device when the HDA is enabled */ 5491 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5492 gpu->multifunction = !!(hdr_type & 0x80); 5493 } 5494 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5495 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5496 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5497 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5498 5499 /* 5500 * Some IDT switches incorrectly flag an ACS Source Validation error on 5501 * completions for config read requests even though PCIe r4.0, sec 5502 * 6.12.1.1, says that completions are never affected by ACS Source 5503 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5504 * 5505 * Item #36 - Downstream port applies ACS Source Validation to Completions 5506 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5507 * completions are never affected by ACS Source Validation. However, 5508 * completions received by a downstream port of the PCIe switch from a 5509 * device that has not yet captured a PCIe bus number are incorrectly 5510 * dropped by ACS Source Validation by the switch downstream port. 5511 * 5512 * The workaround suggested by IDT is to issue a config write to the 5513 * downstream device before issuing the first config read. This allows the 5514 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5515 * sec 2.2.9), thus avoiding the ACS error on the completion. 5516 * 5517 * However, we don't know when the device is ready to accept the config 5518 * write, so we do config reads until we receive a non-Config Request Retry 5519 * Status, then do the config write. 5520 * 5521 * To avoid hitting the erratum when doing the config reads, we disable ACS 5522 * SV around this process. 5523 */ 5524 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5525 { 5526 int pos; 5527 u16 ctrl = 0; 5528 bool found; 5529 struct pci_dev *bridge = bus->self; 5530 5531 pos = bridge->acs_cap; 5532 5533 /* Disable ACS SV before initial config reads */ 5534 if (pos) { 5535 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5536 if (ctrl & PCI_ACS_SV) 5537 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5538 ctrl & ~PCI_ACS_SV); 5539 } 5540 5541 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5542 5543 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5544 if (found) 5545 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5546 5547 /* Re-enable ACS_SV if it was previously enabled */ 5548 if (ctrl & PCI_ACS_SV) 5549 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5550 5551 return found; 5552 } 5553 5554 /* 5555 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5556 * NT endpoints via the internal switch fabric. These IDs replace the 5557 * originating requestor ID TLPs which access host memory on peer NTB 5558 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5559 * to permit access when the IOMMU is turned on. 5560 */ 5561 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5562 { 5563 void __iomem *mmio; 5564 struct ntb_info_regs __iomem *mmio_ntb; 5565 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5566 u64 partition_map; 5567 u8 partition; 5568 int pp; 5569 5570 if (pci_enable_device(pdev)) { 5571 pci_err(pdev, "Cannot enable Switchtec device\n"); 5572 return; 5573 } 5574 5575 mmio = pci_iomap(pdev, 0, 0); 5576 if (mmio == NULL) { 5577 pci_disable_device(pdev); 5578 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5579 return; 5580 } 5581 5582 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5583 5584 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5585 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5586 5587 partition = ioread8(&mmio_ntb->partition_id); 5588 5589 partition_map = ioread32(&mmio_ntb->ep_map); 5590 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5591 partition_map &= ~(1ULL << partition); 5592 5593 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5594 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5595 u32 table_sz = 0; 5596 int te; 5597 5598 if (!(partition_map & (1ULL << pp))) 5599 continue; 5600 5601 pci_dbg(pdev, "Processing partition %d\n", pp); 5602 5603 mmio_peer_ctrl = &mmio_ctrl[pp]; 5604 5605 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5606 if (!table_sz) { 5607 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5608 continue; 5609 } 5610 5611 if (table_sz > 512) { 5612 pci_warn(pdev, 5613 "Invalid Switchtec partition %d table_sz %d\n", 5614 pp, table_sz); 5615 continue; 5616 } 5617 5618 for (te = 0; te < table_sz; te++) { 5619 u32 rid_entry; 5620 u8 devfn; 5621 5622 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5623 devfn = (rid_entry >> 1) & 0xFF; 5624 pci_dbg(pdev, 5625 "Aliasing Partition %d Proxy ID %02x.%d\n", 5626 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5627 pci_add_dma_alias(pdev, devfn, 1); 5628 } 5629 } 5630 5631 pci_iounmap(pdev, mmio); 5632 pci_disable_device(pdev); 5633 } 5634 #define SWITCHTEC_QUIRK(vid) \ 5635 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5636 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5637 5638 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5639 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5640 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5641 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5642 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5643 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5644 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5645 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5646 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5647 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5648 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5649 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5650 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5651 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5652 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5653 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5654 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5655 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5656 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5657 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5658 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5659 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5660 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5661 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5662 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5663 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5664 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5665 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5666 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5667 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5668 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5669 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5670 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5671 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5672 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5673 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5674 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5675 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5676 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5677 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5678 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5679 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5680 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5681 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5682 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5683 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5684 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5685 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5686 5687 /* 5688 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5689 * These IDs are used to forward responses to the originator on the other 5690 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5691 * the IOMMU is turned on. 5692 */ 5693 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5694 { 5695 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5696 /* PLX NTB may use all 256 devfns */ 5697 pci_add_dma_alias(pdev, 0, 256); 5698 } 5699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 5700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 5701 5702 /* 5703 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 5704 * not always reset the secondary Nvidia GPU between reboots if the system 5705 * is configured to use Hybrid Graphics mode. This results in the GPU 5706 * being left in whatever state it was in during the *previous* boot, which 5707 * causes spurious interrupts from the GPU, which in turn causes us to 5708 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 5709 * this also completely breaks nouveau. 5710 * 5711 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 5712 * clean state and fixes all these issues. 5713 * 5714 * When the machine is configured in Dedicated display mode, the issue 5715 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 5716 * mode, so we can detect that and avoid resetting it. 5717 */ 5718 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 5719 { 5720 void __iomem *map; 5721 int ret; 5722 5723 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 5724 pdev->subsystem_device != 0x222e || 5725 !pci_reset_supported(pdev)) 5726 return; 5727 5728 if (pci_enable_device_mem(pdev)) 5729 return; 5730 5731 /* 5732 * Based on nvkm_device_ctor() in 5733 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 5734 */ 5735 map = pci_iomap(pdev, 0, 0x23000); 5736 if (!map) { 5737 pci_err(pdev, "Can't map MMIO space\n"); 5738 goto out_disable; 5739 } 5740 5741 /* 5742 * Make sure the GPU looks like it's been POSTed before resetting 5743 * it. 5744 */ 5745 if (ioread32(map + 0x2240c) & 0x2) { 5746 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 5747 ret = pci_reset_bus(pdev); 5748 if (ret < 0) 5749 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 5750 } 5751 5752 iounmap(map); 5753 out_disable: 5754 pci_disable_device(pdev); 5755 } 5756 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 5757 PCI_CLASS_DISPLAY_VGA, 8, 5758 quirk_reset_lenovo_thinkpad_p50_nvgpu); 5759 5760 /* 5761 * Device [1b21:2142] 5762 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 5763 */ 5764 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 5765 { 5766 pci_info(dev, "PME# does not work under D0, disabling it\n"); 5767 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 5768 } 5769 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 5770 5771 /* 5772 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 5773 * 5774 * These devices advertise PME# support in all power states but don't 5775 * reliably assert it. 5776 * 5777 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 5778 * says "The MSI Function is not implemented on this device" in chapters 5779 * 7.3.27, 7.3.29-7.3.31. 5780 */ 5781 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 5782 { 5783 #ifdef CONFIG_PCI_MSI 5784 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 5785 dev->no_msi = 1; 5786 #endif 5787 pci_info(dev, "PME# is unreliable, disabling it\n"); 5788 dev->pme_support = 0; 5789 } 5790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 5791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 5792 5793 static void apex_pci_fixup_class(struct pci_dev *pdev) 5794 { 5795 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 5796 } 5797 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 5798 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 5799 5800 /* 5801 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 5802 * ACS P2P Request Redirect is not functional 5803 * 5804 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 5805 * between upstream and downstream ports, packets are queued in an internal 5806 * buffer until CPLD packet. The workaround is to use the switch in store and 5807 * forward mode. 5808 */ 5809 #define PI7C9X2Gxxx_MODE_REG 0x74 5810 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 5811 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 5812 { 5813 struct pci_dev *upstream; 5814 u16 val; 5815 5816 /* Downstream ports only */ 5817 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 5818 return; 5819 5820 /* Check for ACS P2P Request Redirect use */ 5821 if (!pdev->acs_cap) 5822 return; 5823 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 5824 if (!(val & PCI_ACS_RR)) 5825 return; 5826 5827 upstream = pci_upstream_bridge(pdev); 5828 if (!upstream) 5829 return; 5830 5831 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 5832 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 5833 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 5834 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 5835 PI7C9X2Gxxx_STORE_FORWARD_MODE); 5836 } 5837 } 5838 /* 5839 * Apply fixup on enable and on resume, in order to apply the fix up whenever 5840 * ACS configuration changes or switch mode is reset 5841 */ 5842 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 5843 pci_fixup_pericom_acs_store_forward); 5844 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 5845 pci_fixup_pericom_acs_store_forward); 5846 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 5847 pci_fixup_pericom_acs_store_forward); 5848 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 5849 pci_fixup_pericom_acs_store_forward); 5850 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 5851 pci_fixup_pericom_acs_store_forward); 5852 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 5853 pci_fixup_pericom_acs_store_forward); 5854 5855 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 5856 { 5857 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 5858 } 5859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 5860