1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/acpi.h> 25 #include <linux/kallsyms.h> 26 #include <linux/dmi.h> 27 #include <linux/pci-aspm.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/ktime.h> 31 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 32 #include "pci.h" 33 34 /* 35 * Decoding should be disabled for a PCI device during BAR sizing to avoid 36 * conflict. But doing so may cause problems on host bridge and perhaps other 37 * key system devices. For devices that need to have mmio decoding always-on, 38 * we need to set the dev->mmio_always_on bit. 39 */ 40 static void __devinit quirk_mmio_always_on(struct pci_dev *dev) 41 { 42 dev->mmio_always_on = 1; 43 } 44 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 46 47 /* The Mellanox Tavor device gives false positive parity errors 48 * Mark this device with a broken_parity_status, to allow 49 * PCI scanning code to "skip" this now blacklisted device. 50 */ 51 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 52 { 53 dev->broken_parity_status = 1; /* This device gives false positives */ 54 } 55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 57 58 /* Deal with broken BIOS'es that neglect to enable passive release, 59 which can cause problems in combination with the 82441FX/PPro MTRRs */ 60 static void quirk_passive_release(struct pci_dev *dev) 61 { 62 struct pci_dev *d = NULL; 63 unsigned char dlc; 64 65 /* We have to make sure a particular bit is set in the PIIX3 66 ISA bridge, so we have to go out and find it. */ 67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 68 pci_read_config_byte(d, 0x82, &dlc); 69 if (!(dlc & 1<<1)) { 70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 71 dlc |= 1<<1; 72 pci_write_config_byte(d, 0x82, dlc); 73 } 74 } 75 } 76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 77 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 78 79 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 80 but VIA don't answer queries. If you happen to have good contacts at VIA 81 ask them for me please -- Alan 82 83 This appears to be BIOS not version dependent. So presumably there is a 84 chipset level fix */ 85 86 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 87 { 88 if (!isa_dma_bridge_buggy) { 89 isa_dma_bridge_buggy=1; 90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 91 } 92 } 93 /* 94 * Its not totally clear which chipsets are the problematic ones 95 * We know 82C586 and 82C596 variants are affected. 96 */ 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 104 105 /* 106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 107 * for some HT machines to use C4 w/o hanging. 108 */ 109 static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev) 110 { 111 u32 pmbase; 112 u16 pm1a; 113 114 pci_read_config_dword(dev, 0x40, &pmbase); 115 pmbase = pmbase & 0xff80; 116 pm1a = inw(pmbase); 117 118 if (pm1a & 0x10) { 119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 120 outw(0x10, pmbase); 121 } 122 } 123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 124 125 /* 126 * Chipsets where PCI->PCI transfers vanish or hang 127 */ 128 static void __devinit quirk_nopcipci(struct pci_dev *dev) 129 { 130 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 132 pci_pci_problems |= PCIPCI_FAIL; 133 } 134 } 135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 137 138 static void __devinit quirk_nopciamd(struct pci_dev *dev) 139 { 140 u8 rev; 141 pci_read_config_byte(dev, 0x08, &rev); 142 if (rev == 0x13) { 143 /* Erratum 24 */ 144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 145 pci_pci_problems |= PCIAGP_FAIL; 146 } 147 } 148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 149 150 /* 151 * Triton requires workarounds to be used by the drivers 152 */ 153 static void __devinit quirk_triton(struct pci_dev *dev) 154 { 155 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 157 pci_pci_problems |= PCIPCI_TRITON; 158 } 159 } 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 164 165 /* 166 * VIA Apollo KT133 needs PCI latency patch 167 * Made according to a windows driver based patch by George E. Breese 168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 169 * and http://www.georgebreese.com/net/software/#PCI 170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 171 * the info on which Mr Breese based his work. 172 * 173 * Updated based on further information from the site and also on 174 * information provided by VIA 175 */ 176 static void quirk_vialatency(struct pci_dev *dev) 177 { 178 struct pci_dev *p; 179 u8 busarb; 180 /* Ok we have a potential problem chipset here. Now see if we have 181 a buggy southbridge */ 182 183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 184 if (p!=NULL) { 185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 186 /* Check for buggy part revisions */ 187 if (p->revision < 0x40 || p->revision > 0x42) 188 goto exit; 189 } else { 190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 191 if (p==NULL) /* No problem parts */ 192 goto exit; 193 /* Check for buggy part revisions */ 194 if (p->revision < 0x10 || p->revision > 0x12) 195 goto exit; 196 } 197 198 /* 199 * Ok we have the problem. Now set the PCI master grant to 200 * occur every master grant. The apparent bug is that under high 201 * PCI load (quite common in Linux of course) you can get data 202 * loss when the CPU is held off the bus for 3 bus master requests 203 * This happens to include the IDE controllers.... 204 * 205 * VIA only apply this fix when an SB Live! is present but under 206 * both Linux and Windows this isn't enough, and we have seen 207 * corruption without SB Live! but with things like 3 UDMA IDE 208 * controllers. So we ignore that bit of the VIA recommendation.. 209 */ 210 211 pci_read_config_byte(dev, 0x76, &busarb); 212 /* Set bit 4 and bi 5 of byte 76 to 0x01 213 "Master priority rotation on every PCI master grant */ 214 busarb &= ~(1<<5); 215 busarb |= (1<<4); 216 pci_write_config_byte(dev, 0x76, busarb); 217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 218 exit: 219 pci_dev_put(p); 220 } 221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 224 /* Must restore this on a resume from RAM */ 225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 226 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 227 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 228 229 /* 230 * VIA Apollo VP3 needs ETBF on BT848/878 231 */ 232 static void __devinit quirk_viaetbf(struct pci_dev *dev) 233 { 234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 236 pci_pci_problems |= PCIPCI_VIAETBF; 237 } 238 } 239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 240 241 static void __devinit quirk_vsfx(struct pci_dev *dev) 242 { 243 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 245 pci_pci_problems |= PCIPCI_VSFX; 246 } 247 } 248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 249 250 /* 251 * Ali Magik requires workarounds to be used by the drivers 252 * that DMA to AGP space. Latency must be set to 0xA and triton 253 * workaround applied too 254 * [Info kindly provided by ALi] 255 */ 256 static void __init quirk_alimagik(struct pci_dev *dev) 257 { 258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 261 } 262 } 263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 265 266 /* 267 * Natoma has some interesting boundary conditions with Zoran stuff 268 * at least 269 */ 270 static void __devinit quirk_natoma(struct pci_dev *dev) 271 { 272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 274 pci_pci_problems |= PCIPCI_NATOMA; 275 } 276 } 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 283 284 /* 285 * This chip can cause PCI parity errors if config register 0xA0 is read 286 * while DMAs are occurring. 287 */ 288 static void __devinit quirk_citrine(struct pci_dev *dev) 289 { 290 dev->cfg_size = 0xA0; 291 } 292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 293 294 /* 295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 296 * If it's needed, re-allocate the region. 297 */ 298 static void __devinit quirk_s3_64M(struct pci_dev *dev) 299 { 300 struct resource *r = &dev->resource[0]; 301 302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 303 r->start = 0; 304 r->end = 0x3ffffff; 305 } 306 } 307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 309 310 /* 311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 314 * (which conflicts w/ BAR1's memory range). 315 */ 316 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) 317 { 318 if (pci_resource_len(dev, 0) != 8) { 319 struct resource *res = &dev->resource[0]; 320 res->end = res->start + 8 - 1; 321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected " 322 "(incorrect header); workaround applied.\n"); 323 } 324 } 325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 326 327 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 328 unsigned size, int nr, const char *name) 329 { 330 region &= ~(size-1); 331 if (region) { 332 struct pci_bus_region bus_region; 333 struct resource *res = dev->resource + nr; 334 335 res->name = pci_name(dev); 336 res->start = region; 337 res->end = region + size - 1; 338 res->flags = IORESOURCE_IO; 339 340 /* Convert from PCI bus to resource space. */ 341 bus_region.start = res->start; 342 bus_region.end = res->end; 343 pcibios_bus_to_resource(dev, res, &bus_region); 344 345 if (pci_claim_resource(dev, nr) == 0) 346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", 347 res, name); 348 } 349 } 350 351 /* 352 * ATI Northbridge setups MCE the processor if you even 353 * read somewhere between 0x3b0->0x3bb or read 0x3d3 354 */ 355 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 356 { 357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 359 request_region(0x3b0, 0x0C, "RadeonIGP"); 360 request_region(0x3d3, 0x01, "RadeonIGP"); 361 } 362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 363 364 /* 365 * Let's make the southbridge information explicit instead 366 * of having to worry about people probing the ACPI areas, 367 * for example.. (Yes, it happens, and if you read the wrong 368 * ACPI register it will put the machine to sleep with no 369 * way of waking it up again. Bummer). 370 * 371 * ALI M7101: Two IO regions pointed to by words at 372 * 0xE0 (64 bytes of ACPI registers) 373 * 0xE2 (32 bytes of SMB registers) 374 */ 375 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 376 { 377 u16 region; 378 379 pci_read_config_word(dev, 0xE0, ®ion); 380 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 381 pci_read_config_word(dev, 0xE2, ®ion); 382 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 383 } 384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 385 386 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 387 { 388 u32 devres; 389 u32 mask, size, base; 390 391 pci_read_config_dword(dev, port, &devres); 392 if ((devres & enable) != enable) 393 return; 394 mask = (devres >> 16) & 15; 395 base = devres & 0xffff; 396 size = 16; 397 for (;;) { 398 unsigned bit = size >> 1; 399 if ((bit & mask) == bit) 400 break; 401 size = bit; 402 } 403 /* 404 * For now we only print it out. Eventually we'll want to 405 * reserve it (at least if it's in the 0x1000+ range), but 406 * let's get enough confirmation reports first. 407 */ 408 base &= -size; 409 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 410 } 411 412 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 413 { 414 u32 devres; 415 u32 mask, size, base; 416 417 pci_read_config_dword(dev, port, &devres); 418 if ((devres & enable) != enable) 419 return; 420 base = devres & 0xffff0000; 421 mask = (devres & 0x3f) << 16; 422 size = 128 << 16; 423 for (;;) { 424 unsigned bit = size >> 1; 425 if ((bit & mask) == bit) 426 break; 427 size = bit; 428 } 429 /* 430 * For now we only print it out. Eventually we'll want to 431 * reserve it, but let's get enough confirmation reports first. 432 */ 433 base &= -size; 434 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 435 } 436 437 /* 438 * PIIX4 ACPI: Two IO regions pointed to by longwords at 439 * 0x40 (64 bytes of ACPI registers) 440 * 0x90 (16 bytes of SMB registers) 441 * and a few strange programmable PIIX4 device resources. 442 */ 443 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 444 { 445 u32 region, res_a; 446 447 pci_read_config_dword(dev, 0x40, ®ion); 448 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 449 pci_read_config_dword(dev, 0x90, ®ion); 450 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 451 452 /* Device resource A has enables for some of the other ones */ 453 pci_read_config_dword(dev, 0x5c, &res_a); 454 455 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 456 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 457 458 /* Device resource D is just bitfields for static resources */ 459 460 /* Device 12 enabled? */ 461 if (res_a & (1 << 29)) { 462 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 463 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 464 } 465 /* Device 13 enabled? */ 466 if (res_a & (1 << 30)) { 467 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 468 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 469 } 470 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 471 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 472 } 473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 475 476 #define ICH_PMBASE 0x40 477 #define ICH_ACPI_CNTL 0x44 478 #define ICH4_ACPI_EN 0x10 479 #define ICH6_ACPI_EN 0x80 480 #define ICH4_GPIOBASE 0x58 481 #define ICH4_GPIO_CNTL 0x5c 482 #define ICH4_GPIO_EN 0x10 483 #define ICH6_GPIOBASE 0x48 484 #define ICH6_GPIO_CNTL 0x4c 485 #define ICH6_GPIO_EN 0x10 486 487 /* 488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 490 * 0x58 (64 bytes of GPIO I/O space) 491 */ 492 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 493 { 494 u32 region; 495 u8 enable; 496 497 /* 498 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 499 * with low legacy (and fixed) ports. We don't know the decoding 500 * priority and can't tell whether the legacy device or the one created 501 * here is really at that address. This happens on boards with broken 502 * BIOSes. 503 */ 504 505 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 506 if (enable & ICH4_ACPI_EN) { 507 pci_read_config_dword(dev, ICH_PMBASE, ®ion); 508 region &= PCI_BASE_ADDRESS_IO_MASK; 509 if (region >= PCIBIOS_MIN_IO) 510 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, 511 "ICH4 ACPI/GPIO/TCO"); 512 } 513 514 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 515 if (enable & ICH4_GPIO_EN) { 516 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion); 517 region &= PCI_BASE_ADDRESS_IO_MASK; 518 if (region >= PCIBIOS_MIN_IO) 519 quirk_io_region(dev, region, 64, 520 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO"); 521 } 522 } 523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 533 534 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) 535 { 536 u32 region; 537 u8 enable; 538 539 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 540 if (enable & ICH6_ACPI_EN) { 541 pci_read_config_dword(dev, ICH_PMBASE, ®ion); 542 region &= PCI_BASE_ADDRESS_IO_MASK; 543 if (region >= PCIBIOS_MIN_IO) 544 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, 545 "ICH6 ACPI/GPIO/TCO"); 546 } 547 548 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 549 if (enable & ICH6_GPIO_EN) { 550 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion); 551 region &= PCI_BASE_ADDRESS_IO_MASK; 552 if (region >= PCIBIOS_MIN_IO) 553 quirk_io_region(dev, region, 64, 554 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO"); 555 } 556 } 557 558 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 559 { 560 u32 val; 561 u32 size, base; 562 563 pci_read_config_dword(dev, reg, &val); 564 565 /* Enabled? */ 566 if (!(val & 1)) 567 return; 568 base = val & 0xfffc; 569 if (dynsize) { 570 /* 571 * This is not correct. It is 16, 32 or 64 bytes depending on 572 * register D31:F0:ADh bits 5:4. 573 * 574 * But this gets us at least _part_ of it. 575 */ 576 size = 16; 577 } else { 578 size = 128; 579 } 580 base &= ~(size-1); 581 582 /* Just print it out for now. We should reserve it after more debugging */ 583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 584 } 585 586 static void __devinit quirk_ich6_lpc(struct pci_dev *dev) 587 { 588 /* Shared ACPI/GPIO decode with all ICH6+ */ 589 ich6_lpc_acpi_gpio(dev); 590 591 /* ICH6-specific generic IO decode */ 592 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 593 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 594 } 595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 597 598 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 599 { 600 u32 val; 601 u32 mask, base; 602 603 pci_read_config_dword(dev, reg, &val); 604 605 /* Enabled? */ 606 if (!(val & 1)) 607 return; 608 609 /* 610 * IO base in bits 15:2, mask in bits 23:18, both 611 * are dword-based 612 */ 613 base = val & 0xfffc; 614 mask = (val >> 16) & 0xfc; 615 mask |= 3; 616 617 /* Just print it out for now. We should reserve it after more debugging */ 618 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 619 } 620 621 /* ICH7-10 has the same common LPC generic IO decode registers */ 622 static void __devinit quirk_ich7_lpc(struct pci_dev *dev) 623 { 624 /* We share the common ACPI/GPIO decode with ICH6 */ 625 ich6_lpc_acpi_gpio(dev); 626 627 /* And have 4 ICH7+ generic decodes */ 628 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 629 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 630 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 631 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 632 } 633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 646 647 /* 648 * VIA ACPI: One IO region pointed to by longword at 649 * 0x48 or 0x20 (256 bytes of ACPI registers) 650 */ 651 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 652 { 653 u32 region; 654 655 if (dev->revision & 0x10) { 656 pci_read_config_dword(dev, 0x48, ®ion); 657 region &= PCI_BASE_ADDRESS_IO_MASK; 658 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 659 } 660 } 661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 662 663 /* 664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 665 * 0x48 (256 bytes of ACPI registers) 666 * 0x70 (128 bytes of hardware monitoring register) 667 * 0x90 (16 bytes of SMB registers) 668 */ 669 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 670 { 671 u16 hm; 672 u32 smb; 673 674 quirk_vt82c586_acpi(dev); 675 676 pci_read_config_word(dev, 0x70, &hm); 677 hm &= PCI_BASE_ADDRESS_IO_MASK; 678 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 679 680 pci_read_config_dword(dev, 0x90, &smb); 681 smb &= PCI_BASE_ADDRESS_IO_MASK; 682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 683 } 684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 685 686 /* 687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 688 * 0x88 (128 bytes of power management registers) 689 * 0xd0 (16 bytes of SMB registers) 690 */ 691 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 692 { 693 u16 pm, smb; 694 695 pci_read_config_word(dev, 0x88, &pm); 696 pm &= PCI_BASE_ADDRESS_IO_MASK; 697 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 698 699 pci_read_config_word(dev, 0xd0, &smb); 700 smb &= PCI_BASE_ADDRESS_IO_MASK; 701 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 702 } 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 704 705 /* 706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 707 * Disable fast back-to-back on the secondary bus segment 708 */ 709 static void __devinit quirk_xio2000a(struct pci_dev *dev) 710 { 711 struct pci_dev *pdev; 712 u16 command; 713 714 dev_warn(&dev->dev, "TI XIO2000a quirk detected; " 715 "secondary bus fast back-to-back transfers disabled\n"); 716 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 717 pci_read_config_word(pdev, PCI_COMMAND, &command); 718 if (command & PCI_COMMAND_FAST_BACK) 719 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 720 } 721 } 722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 723 quirk_xio2000a); 724 725 #ifdef CONFIG_X86_IO_APIC 726 727 #include <asm/io_apic.h> 728 729 /* 730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 731 * devices to the external APIC. 732 * 733 * TODO: When we have device-specific interrupt routers, 734 * this code will go away from quirks. 735 */ 736 static void quirk_via_ioapic(struct pci_dev *dev) 737 { 738 u8 tmp; 739 740 if (nr_ioapics < 1) 741 tmp = 0; /* nothing routed to external APIC */ 742 else 743 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 744 745 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 746 tmp == 0 ? "Disa" : "Ena"); 747 748 /* Offset 0x58: External APIC IRQ output control */ 749 pci_write_config_byte (dev, 0x58, tmp); 750 } 751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 752 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 753 754 /* 755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 756 * This leads to doubled level interrupt rates. 757 * Set this bit to get rid of cycle wastage. 758 * Otherwise uncritical. 759 */ 760 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 761 { 762 u8 misc_control2; 763 #define BYPASS_APIC_DEASSERT 8 764 765 pci_read_config_byte(dev, 0x5B, &misc_control2); 766 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 767 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 768 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 769 } 770 } 771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 773 774 /* 775 * The AMD io apic can hang the box when an apic irq is masked. 776 * We check all revs >= B0 (yet not in the pre production!) as the bug 777 * is currently marked NoFix 778 * 779 * We have multiple reports of hangs with this chipset that went away with 780 * noapic specified. For the moment we assume it's the erratum. We may be wrong 781 * of course. However the advice is demonstrably good even if so.. 782 */ 783 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 784 { 785 if (dev->revision >= 0x02) { 786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 787 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 788 } 789 } 790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 791 792 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 793 { 794 if (dev->devfn == 0 && dev->bus->number == 0) 795 sis_apic_bug = 1; 796 } 797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 798 #endif /* CONFIG_X86_IO_APIC */ 799 800 /* 801 * Some settings of MMRBC can lead to data corruption so block changes. 802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 803 */ 804 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 805 { 806 if (dev->subordinate && dev->revision <= 0x12) { 807 dev_info(&dev->dev, "AMD8131 rev %x detected; " 808 "disabling PCI-X MMRBC\n", dev->revision); 809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 810 } 811 } 812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 813 814 /* 815 * FIXME: it is questionable that quirk_via_acpi 816 * is needed. It shows up as an ISA bridge, and does not 817 * support the PCI_INTERRUPT_LINE register at all. Therefore 818 * it seems like setting the pci_dev's 'irq' to the 819 * value of the ACPI SCI interrupt is only done for convenience. 820 * -jgarzik 821 */ 822 static void __devinit quirk_via_acpi(struct pci_dev *d) 823 { 824 /* 825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 826 */ 827 u8 irq; 828 pci_read_config_byte(d, 0x42, &irq); 829 irq &= 0xf; 830 if (irq && (irq != 2)) 831 d->irq = irq; 832 } 833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 835 836 837 /* 838 * VIA bridges which have VLink 839 */ 840 841 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 842 843 static void quirk_via_bridge(struct pci_dev *dev) 844 { 845 /* See what bridge we have and find the device ranges */ 846 switch (dev->device) { 847 case PCI_DEVICE_ID_VIA_82C686: 848 /* The VT82C686 is special, it attaches to PCI and can have 849 any device number. All its subdevices are functions of 850 that single device. */ 851 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 852 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 853 break; 854 case PCI_DEVICE_ID_VIA_8237: 855 case PCI_DEVICE_ID_VIA_8237A: 856 via_vlink_dev_lo = 15; 857 break; 858 case PCI_DEVICE_ID_VIA_8235: 859 via_vlink_dev_lo = 16; 860 break; 861 case PCI_DEVICE_ID_VIA_8231: 862 case PCI_DEVICE_ID_VIA_8233_0: 863 case PCI_DEVICE_ID_VIA_8233A: 864 case PCI_DEVICE_ID_VIA_8233C_0: 865 via_vlink_dev_lo = 17; 866 break; 867 } 868 } 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 877 878 /** 879 * quirk_via_vlink - VIA VLink IRQ number update 880 * @dev: PCI device 881 * 882 * If the device we are dealing with is on a PIC IRQ we need to 883 * ensure that the IRQ line register which usually is not relevant 884 * for PCI cards, is actually written so that interrupts get sent 885 * to the right place. 886 * We only do this on systems where a VIA south bridge was detected, 887 * and only for VIA devices on the motherboard (see quirk_via_bridge 888 * above). 889 */ 890 891 static void quirk_via_vlink(struct pci_dev *dev) 892 { 893 u8 irq, new_irq; 894 895 /* Check if we have VLink at all */ 896 if (via_vlink_dev_lo == -1) 897 return; 898 899 new_irq = dev->irq; 900 901 /* Don't quirk interrupts outside the legacy IRQ range */ 902 if (!new_irq || new_irq > 15) 903 return; 904 905 /* Internal device ? */ 906 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 907 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 908 return; 909 910 /* This is an internal VLink device on a PIC interrupt. The BIOS 911 ought to have set this but may not have, so we redo it */ 912 913 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 914 if (new_irq != irq) { 915 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 916 irq, new_irq); 917 udelay(15); /* unknown if delay really needed */ 918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 919 } 920 } 921 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 922 923 /* 924 * VIA VT82C598 has its device ID settable and many BIOSes 925 * set it to the ID of VT82C597 for backward compatibility. 926 * We need to switch it off to be able to recognize the real 927 * type of the chip. 928 */ 929 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 930 { 931 pci_write_config_byte(dev, 0xfc, 0); 932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 933 } 934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 935 936 /* 937 * CardBus controllers have a legacy base address that enables them 938 * to respond as i82365 pcmcia controllers. We don't want them to 939 * do this even if the Linux CardBus driver is not loaded, because 940 * the Linux i82365 driver does not (and should not) handle CardBus. 941 */ 942 static void quirk_cardbus_legacy(struct pci_dev *dev) 943 { 944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 945 } 946 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 948 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 950 951 /* 952 * Following the PCI ordering rules is optional on the AMD762. I'm not 953 * sure what the designers were smoking but let's not inhale... 954 * 955 * To be fair to AMD, it follows the spec by default, its BIOS people 956 * who turn it off! 957 */ 958 static void quirk_amd_ordering(struct pci_dev *dev) 959 { 960 u32 pcic; 961 pci_read_config_dword(dev, 0x4C, &pcic); 962 if ((pcic&6)!=6) { 963 pcic |= 6; 964 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 965 pci_write_config_dword(dev, 0x4C, pcic); 966 pci_read_config_dword(dev, 0x84, &pcic); 967 pcic |= (1<<23); /* Required in this mode */ 968 pci_write_config_dword(dev, 0x84, pcic); 969 } 970 } 971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 972 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 973 974 /* 975 * DreamWorks provided workaround for Dunord I-3000 problem 976 * 977 * This card decodes and responds to addresses not apparently 978 * assigned to it. We force a larger allocation to ensure that 979 * nothing gets put too close to it. 980 */ 981 static void __devinit quirk_dunord ( struct pci_dev * dev ) 982 { 983 struct resource *r = &dev->resource [1]; 984 r->start = 0; 985 r->end = 0xffffff; 986 } 987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 988 989 /* 990 * i82380FB mobile docking controller: its PCI-to-PCI bridge 991 * is subtractive decoding (transparent), and does indicate this 992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 993 * instead of 0x01. 994 */ 995 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 996 { 997 dev->transparent = 1; 998 } 999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1001 1002 /* 1003 * Common misconfiguration of the MediaGX/Geode PCI master that will 1004 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1005 * datasheets found at http://www.national.com/analog for info on what 1006 * these bits do. <christer@weinigel.se> 1007 */ 1008 static void quirk_mediagx_master(struct pci_dev *dev) 1009 { 1010 u8 reg; 1011 pci_read_config_byte(dev, 0x41, ®); 1012 if (reg & 2) { 1013 reg &= ~2; 1014 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 1015 pci_write_config_byte(dev, 0x41, reg); 1016 } 1017 } 1018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1019 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1020 1021 /* 1022 * Ensure C0 rev restreaming is off. This is normally done by 1023 * the BIOS but in the odd case it is not the results are corruption 1024 * hence the presence of a Linux check 1025 */ 1026 static void quirk_disable_pxb(struct pci_dev *pdev) 1027 { 1028 u16 config; 1029 1030 if (pdev->revision != 0x04) /* Only C0 requires this */ 1031 return; 1032 pci_read_config_word(pdev, 0x40, &config); 1033 if (config & (1<<6)) { 1034 config &= ~(1<<6); 1035 pci_write_config_word(pdev, 0x40, config); 1036 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1037 } 1038 } 1039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1040 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1041 1042 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 1043 { 1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1045 u8 tmp; 1046 1047 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1048 if (tmp == 0x01) { 1049 pci_read_config_byte(pdev, 0x40, &tmp); 1050 pci_write_config_byte(pdev, 0x40, tmp|1); 1051 pci_write_config_byte(pdev, 0x9, 1); 1052 pci_write_config_byte(pdev, 0xa, 6); 1053 pci_write_config_byte(pdev, 0x40, tmp); 1054 1055 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1056 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1057 } 1058 } 1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1060 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1062 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1064 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1065 1066 /* 1067 * Serverworks CSB5 IDE does not fully support native mode 1068 */ 1069 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 1070 { 1071 u8 prog; 1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1073 if (prog & 5) { 1074 prog &= ~5; 1075 pdev->class &= ~5; 1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1077 /* PCI layer will sort out resources */ 1078 } 1079 } 1080 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1081 1082 /* 1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1084 */ 1085 static void __init quirk_ide_samemode(struct pci_dev *pdev) 1086 { 1087 u8 prog; 1088 1089 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1090 1091 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1092 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1093 prog &= ~5; 1094 pdev->class &= ~5; 1095 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1096 } 1097 } 1098 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1099 1100 /* 1101 * Some ATA devices break if put into D3 1102 */ 1103 1104 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) 1105 { 1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1107 } 1108 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1109 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1111 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1113 /* ALi loses some register settings that we cannot then restore */ 1114 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1116 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1117 occur when mode detecting */ 1118 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1120 1121 /* This was originally an Alpha specific thing, but it really fits here. 1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1123 */ 1124 static void __init quirk_eisa_bridge(struct pci_dev *dev) 1125 { 1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1127 } 1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1129 1130 1131 /* 1132 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1133 * is not activated. The myth is that Asus said that they do not want the 1134 * users to be irritated by just another PCI Device in the Win98 device 1135 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1136 * package 2.7.0 for details) 1137 * 1138 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1139 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1140 * becomes necessary to do this tweak in two steps -- the chosen trigger 1141 * is either the Host bridge (preferred) or on-board VGA controller. 1142 * 1143 * Note that we used to unhide the SMBus that way on Toshiba laptops 1144 * (Satellite A40 and Tecra M2) but then found that the thermal management 1145 * was done by SMM code, which could cause unsynchronized concurrent 1146 * accesses to the SMBus registers, with potentially bad effects. Thus you 1147 * should be very careful when adding new entries: if SMM is accessing the 1148 * Intel SMBus, this is a very good reason to leave it hidden. 1149 * 1150 * Likewise, many recent laptops use ACPI for thermal management. If the 1151 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1152 * natively, and keeping the SMBus hidden is the right thing to do. If you 1153 * are about to add an entry in the table below, please first disassemble 1154 * the DSDT and double-check that there is no code accessing the SMBus. 1155 */ 1156 static int asus_hides_smbus; 1157 1158 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1159 { 1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1162 switch(dev->subsystem_device) { 1163 case 0x8025: /* P4B-LX */ 1164 case 0x8070: /* P4B */ 1165 case 0x8088: /* P4B533 */ 1166 case 0x1626: /* L3C notebook */ 1167 asus_hides_smbus = 1; 1168 } 1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1170 switch(dev->subsystem_device) { 1171 case 0x80b1: /* P4GE-V */ 1172 case 0x80b2: /* P4PE */ 1173 case 0x8093: /* P4B533-V */ 1174 asus_hides_smbus = 1; 1175 } 1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1177 switch(dev->subsystem_device) { 1178 case 0x8030: /* P4T533 */ 1179 asus_hides_smbus = 1; 1180 } 1181 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1182 switch (dev->subsystem_device) { 1183 case 0x8070: /* P4G8X Deluxe */ 1184 asus_hides_smbus = 1; 1185 } 1186 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1187 switch (dev->subsystem_device) { 1188 case 0x80c9: /* PU-DLS */ 1189 asus_hides_smbus = 1; 1190 } 1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1192 switch (dev->subsystem_device) { 1193 case 0x1751: /* M2N notebook */ 1194 case 0x1821: /* M5N notebook */ 1195 case 0x1897: /* A6L notebook */ 1196 asus_hides_smbus = 1; 1197 } 1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1199 switch (dev->subsystem_device) { 1200 case 0x184b: /* W1N notebook */ 1201 case 0x186a: /* M6Ne notebook */ 1202 asus_hides_smbus = 1; 1203 } 1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1205 switch (dev->subsystem_device) { 1206 case 0x80f2: /* P4P800-X */ 1207 asus_hides_smbus = 1; 1208 } 1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1210 switch (dev->subsystem_device) { 1211 case 0x1882: /* M6V notebook */ 1212 case 0x1977: /* A6VA notebook */ 1213 asus_hides_smbus = 1; 1214 } 1215 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1216 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1217 switch(dev->subsystem_device) { 1218 case 0x088C: /* HP Compaq nc8000 */ 1219 case 0x0890: /* HP Compaq nc6000 */ 1220 asus_hides_smbus = 1; 1221 } 1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1223 switch (dev->subsystem_device) { 1224 case 0x12bc: /* HP D330L */ 1225 case 0x12bd: /* HP D530 */ 1226 case 0x006a: /* HP Compaq nx9500 */ 1227 asus_hides_smbus = 1; 1228 } 1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1230 switch (dev->subsystem_device) { 1231 case 0x12bf: /* HP xw4100 */ 1232 asus_hides_smbus = 1; 1233 } 1234 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1235 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1236 switch(dev->subsystem_device) { 1237 case 0xC00C: /* Samsung P35 notebook */ 1238 asus_hides_smbus = 1; 1239 } 1240 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1241 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1242 switch(dev->subsystem_device) { 1243 case 0x0058: /* Compaq Evo N620c */ 1244 asus_hides_smbus = 1; 1245 } 1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1247 switch(dev->subsystem_device) { 1248 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1249 /* Motherboard doesn't have Host bridge 1250 * subvendor/subdevice IDs, therefore checking 1251 * its on-board VGA controller */ 1252 asus_hides_smbus = 1; 1253 } 1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1255 switch(dev->subsystem_device) { 1256 case 0x00b8: /* Compaq Evo D510 CMT */ 1257 case 0x00b9: /* Compaq Evo D510 SFF */ 1258 case 0x00ba: /* Compaq Evo D510 USDT */ 1259 /* Motherboard doesn't have Host bridge 1260 * subvendor/subdevice IDs and on-board VGA 1261 * controller is disabled if an AGP card is 1262 * inserted, therefore checking USB UHCI 1263 * Controller #1 */ 1264 asus_hides_smbus = 1; 1265 } 1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1267 switch (dev->subsystem_device) { 1268 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1269 /* Motherboard doesn't have host bridge 1270 * subvendor/subdevice IDs, therefore checking 1271 * its on-board VGA controller */ 1272 asus_hides_smbus = 1; 1273 } 1274 } 1275 } 1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1286 1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1290 1291 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1292 { 1293 u16 val; 1294 1295 if (likely(!asus_hides_smbus)) 1296 return; 1297 1298 pci_read_config_word(dev, 0xF2, &val); 1299 if (val & 0x8) { 1300 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1301 pci_read_config_word(dev, 0xF2, &val); 1302 if (val & 0x8) 1303 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1304 else 1305 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1306 } 1307 } 1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1315 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1316 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1317 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1318 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1319 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1320 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1321 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1322 1323 /* It appears we just have one such device. If not, we have a warning */ 1324 static void __iomem *asus_rcba_base; 1325 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1326 { 1327 u32 rcba; 1328 1329 if (likely(!asus_hides_smbus)) 1330 return; 1331 WARN_ON(asus_rcba_base); 1332 1333 pci_read_config_dword(dev, 0xF0, &rcba); 1334 /* use bits 31:14, 16 kB aligned */ 1335 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1336 if (asus_rcba_base == NULL) 1337 return; 1338 } 1339 1340 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1341 { 1342 u32 val; 1343 1344 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1345 return; 1346 /* read the Function Disable register, dword mode only */ 1347 val = readl(asus_rcba_base + 0x3418); 1348 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1349 } 1350 1351 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1352 { 1353 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1354 return; 1355 iounmap(asus_rcba_base); 1356 asus_rcba_base = NULL; 1357 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1358 } 1359 1360 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1361 { 1362 asus_hides_smbus_lpc_ich6_suspend(dev); 1363 asus_hides_smbus_lpc_ich6_resume_early(dev); 1364 asus_hides_smbus_lpc_ich6_resume(dev); 1365 } 1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1367 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1368 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1369 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1370 1371 /* 1372 * SiS 96x south bridge: BIOS typically hides SMBus device... 1373 */ 1374 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1375 { 1376 u8 val = 0; 1377 pci_read_config_byte(dev, 0x77, &val); 1378 if (val & 0x10) { 1379 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1380 pci_write_config_byte(dev, 0x77, val & ~0x10); 1381 } 1382 } 1383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1387 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1388 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1389 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1390 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1391 1392 /* 1393 * ... This is further complicated by the fact that some SiS96x south 1394 * bridges pretend to be 85C503/5513 instead. In that case see if we 1395 * spotted a compatible north bridge to make sure. 1396 * (pci_find_device doesn't work yet) 1397 * 1398 * We can also enable the sis96x bit in the discovery register.. 1399 */ 1400 #define SIS_DETECT_REGISTER 0x40 1401 1402 static void quirk_sis_503(struct pci_dev *dev) 1403 { 1404 u8 reg; 1405 u16 devid; 1406 1407 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1408 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1409 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1410 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1411 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1412 return; 1413 } 1414 1415 /* 1416 * Ok, it now shows up as a 96x.. run the 96x quirk by 1417 * hand in case it has already been processed. 1418 * (depends on link order, which is apparently not guaranteed) 1419 */ 1420 dev->device = devid; 1421 quirk_sis_96x_smbus(dev); 1422 } 1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1425 1426 1427 /* 1428 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1429 * and MC97 modem controller are disabled when a second PCI soundcard is 1430 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1431 * -- bjd 1432 */ 1433 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1434 { 1435 u8 val; 1436 int asus_hides_ac97 = 0; 1437 1438 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1439 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1440 asus_hides_ac97 = 1; 1441 } 1442 1443 if (!asus_hides_ac97) 1444 return; 1445 1446 pci_read_config_byte(dev, 0x50, &val); 1447 if (val & 0xc0) { 1448 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1449 pci_read_config_byte(dev, 0x50, &val); 1450 if (val & 0xc0) 1451 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1452 else 1453 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1454 } 1455 } 1456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1457 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1458 1459 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1460 1461 /* 1462 * If we are using libata we can drive this chip properly but must 1463 * do this early on to make the additional device appear during 1464 * the PCI scanning. 1465 */ 1466 static void quirk_jmicron_ata(struct pci_dev *pdev) 1467 { 1468 u32 conf1, conf5, class; 1469 u8 hdr; 1470 1471 /* Only poke fn 0 */ 1472 if (PCI_FUNC(pdev->devfn)) 1473 return; 1474 1475 pci_read_config_dword(pdev, 0x40, &conf1); 1476 pci_read_config_dword(pdev, 0x80, &conf5); 1477 1478 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1479 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1480 1481 switch (pdev->device) { 1482 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1483 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1484 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1485 /* The controller should be in single function ahci mode */ 1486 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1487 break; 1488 1489 case PCI_DEVICE_ID_JMICRON_JMB365: 1490 case PCI_DEVICE_ID_JMICRON_JMB366: 1491 /* Redirect IDE second PATA port to the right spot */ 1492 conf5 |= (1 << 24); 1493 /* Fall through */ 1494 case PCI_DEVICE_ID_JMICRON_JMB361: 1495 case PCI_DEVICE_ID_JMICRON_JMB363: 1496 case PCI_DEVICE_ID_JMICRON_JMB369: 1497 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1498 /* Set the class codes correctly and then direct IDE 0 */ 1499 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1500 break; 1501 1502 case PCI_DEVICE_ID_JMICRON_JMB368: 1503 /* The controller should be in single function IDE mode */ 1504 conf1 |= 0x00C00000; /* Set 22, 23 */ 1505 break; 1506 } 1507 1508 pci_write_config_dword(pdev, 0x40, conf1); 1509 pci_write_config_dword(pdev, 0x80, conf5); 1510 1511 /* Update pdev accordingly */ 1512 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1513 pdev->hdr_type = hdr & 0x7f; 1514 pdev->multifunction = !!(hdr & 0x80); 1515 1516 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1517 pdev->class = class >> 8; 1518 } 1519 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1520 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1521 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1522 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1529 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1530 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1532 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1535 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1536 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1537 1538 #endif 1539 1540 #ifdef CONFIG_X86_IO_APIC 1541 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1542 { 1543 int i; 1544 1545 if ((pdev->class >> 8) != 0xff00) 1546 return; 1547 1548 /* the first BAR is the location of the IO APIC...we must 1549 * not touch this (and it's already covered by the fixmap), so 1550 * forcibly insert it into the resource tree */ 1551 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1552 insert_resource(&iomem_resource, &pdev->resource[0]); 1553 1554 /* The next five BARs all seem to be rubbish, so just clean 1555 * them out */ 1556 for (i=1; i < 6; i++) { 1557 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1558 } 1559 1560 } 1561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1562 #endif 1563 1564 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1565 { 1566 pci_msi_off(pdev); 1567 pdev->no_msi = 1; 1568 } 1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1572 1573 1574 /* 1575 * It's possible for the MSI to get corrupted if shpc and acpi 1576 * are used together on certain PXH-based systems. 1577 */ 1578 static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1579 { 1580 pci_msi_off(dev); 1581 dev->no_msi = 1; 1582 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1583 } 1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1588 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1589 1590 /* 1591 * Some Intel PCI Express chipsets have trouble with downstream 1592 * device power management. 1593 */ 1594 static void quirk_intel_pcie_pm(struct pci_dev * dev) 1595 { 1596 pci_pm_d3_delay = 120; 1597 dev->no_d1d2 = 1; 1598 } 1599 1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1621 1622 #ifdef CONFIG_X86_IO_APIC 1623 /* 1624 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1625 * remap the original interrupt in the linux kernel to the boot interrupt, so 1626 * that a PCI device's interrupt handler is installed on the boot interrupt 1627 * line instead. 1628 */ 1629 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1630 { 1631 if (noioapicquirk || noioapicreroute) 1632 return; 1633 1634 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1635 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1636 dev->vendor, dev->device); 1637 } 1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1646 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1647 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1648 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1649 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1650 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1651 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1652 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1653 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1654 1655 /* 1656 * On some chipsets we can disable the generation of legacy INTx boot 1657 * interrupts. 1658 */ 1659 1660 /* 1661 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1662 * 300641-004US, section 5.7.3. 1663 */ 1664 #define INTEL_6300_IOAPIC_ABAR 0x40 1665 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1666 1667 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1668 { 1669 u16 pci_config_word; 1670 1671 if (noioapicquirk) 1672 return; 1673 1674 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1675 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1676 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1677 1678 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1679 dev->vendor, dev->device); 1680 } 1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1682 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1683 1684 /* 1685 * disable boot interrupts on HT-1000 1686 */ 1687 #define BC_HT1000_FEATURE_REG 0x64 1688 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1689 #define BC_HT1000_MAP_IDX 0xC00 1690 #define BC_HT1000_MAP_DATA 0xC01 1691 1692 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1693 { 1694 u32 pci_config_dword; 1695 u8 irq; 1696 1697 if (noioapicquirk) 1698 return; 1699 1700 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1702 BC_HT1000_PIC_REGS_ENABLE); 1703 1704 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1705 outb(irq, BC_HT1000_MAP_IDX); 1706 outb(0x00, BC_HT1000_MAP_DATA); 1707 } 1708 1709 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1710 1711 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1712 dev->vendor, dev->device); 1713 } 1714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1715 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1716 1717 /* 1718 * disable boot interrupts on AMD and ATI chipsets 1719 */ 1720 /* 1721 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1722 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1723 * (due to an erratum). 1724 */ 1725 #define AMD_813X_MISC 0x40 1726 #define AMD_813X_NOIOAMODE (1<<0) 1727 #define AMD_813X_REV_B1 0x12 1728 #define AMD_813X_REV_B2 0x13 1729 1730 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1731 { 1732 u32 pci_config_dword; 1733 1734 if (noioapicquirk) 1735 return; 1736 if ((dev->revision == AMD_813X_REV_B1) || 1737 (dev->revision == AMD_813X_REV_B2)) 1738 return; 1739 1740 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1741 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1742 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1743 1744 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1745 dev->vendor, dev->device); 1746 } 1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1748 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1751 1752 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1753 1754 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1755 { 1756 u16 pci_config_word; 1757 1758 if (noioapicquirk) 1759 return; 1760 1761 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1762 if (!pci_config_word) { 1763 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " 1764 "already disabled\n", dev->vendor, dev->device); 1765 return; 1766 } 1767 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1769 dev->vendor, dev->device); 1770 } 1771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1772 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1773 #endif /* CONFIG_X86_IO_APIC */ 1774 1775 /* 1776 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1778 * Re-allocate the region if needed... 1779 */ 1780 static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1781 { 1782 struct resource *r = &dev->resource[0]; 1783 1784 if (r->start & 0x8) { 1785 r->start = 0; 1786 r->end = 0xf; 1787 } 1788 } 1789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1791 quirk_tc86c001_ide); 1792 1793 static void __devinit quirk_netmos(struct pci_dev *dev) 1794 { 1795 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1796 unsigned int num_serial = dev->subsystem_device & 0xf; 1797 1798 /* 1799 * These Netmos parts are multiport serial devices with optional 1800 * parallel ports. Even when parallel ports are present, they 1801 * are identified as class SERIAL, which means the serial driver 1802 * will claim them. To prevent this, mark them as class OTHER. 1803 * These combo devices should be claimed by parport_serial. 1804 * 1805 * The subdevice ID is of the form 0x00PS, where <P> is the number 1806 * of parallel ports and <S> is the number of serial ports. 1807 */ 1808 switch (dev->device) { 1809 case PCI_DEVICE_ID_NETMOS_9835: 1810 /* Well, this rule doesn't hold for the following 9835 device */ 1811 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1812 dev->subsystem_device == 0x0299) 1813 return; 1814 case PCI_DEVICE_ID_NETMOS_9735: 1815 case PCI_DEVICE_ID_NETMOS_9745: 1816 case PCI_DEVICE_ID_NETMOS_9845: 1817 case PCI_DEVICE_ID_NETMOS_9855: 1818 if (num_parallel) { 1819 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1820 "%u serial); changing class SERIAL to OTHER " 1821 "(use parport_serial)\n", 1822 dev->device, num_parallel, num_serial); 1823 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1824 (dev->class & 0xff); 1825 } 1826 } 1827 } 1828 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1829 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1830 1831 static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1832 { 1833 u16 command, pmcsr; 1834 u8 __iomem *csr; 1835 u8 cmd_hi; 1836 int pm; 1837 1838 switch (dev->device) { 1839 /* PCI IDs taken from drivers/net/e100.c */ 1840 case 0x1029: 1841 case 0x1030 ... 0x1034: 1842 case 0x1038 ... 0x103E: 1843 case 0x1050 ... 0x1057: 1844 case 0x1059: 1845 case 0x1064 ... 0x106B: 1846 case 0x1091 ... 0x1095: 1847 case 0x1209: 1848 case 0x1229: 1849 case 0x2449: 1850 case 0x2459: 1851 case 0x245D: 1852 case 0x27DC: 1853 break; 1854 default: 1855 return; 1856 } 1857 1858 /* 1859 * Some firmware hands off the e100 with interrupts enabled, 1860 * which can cause a flood of interrupts if packets are 1861 * received before the driver attaches to the device. So 1862 * disable all e100 interrupts here. The driver will 1863 * re-enable them when it's ready. 1864 */ 1865 pci_read_config_word(dev, PCI_COMMAND, &command); 1866 1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1868 return; 1869 1870 /* 1871 * Check that the device is in the D0 power state. If it's not, 1872 * there is no point to look any further. 1873 */ 1874 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1875 if (pm) { 1876 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 1877 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1878 return; 1879 } 1880 1881 /* Convert from PCI bus to resource space. */ 1882 csr = ioremap(pci_resource_start(dev, 0), 8); 1883 if (!csr) { 1884 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1885 return; 1886 } 1887 1888 cmd_hi = readb(csr + 3); 1889 if (cmd_hi == 0) { 1890 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1891 "disabling\n"); 1892 writeb(1, csr + 3); 1893 } 1894 1895 iounmap(csr); 1896 } 1897 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1898 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 1899 1900 /* 1901 * The 82575 and 82598 may experience data corruption issues when transitioning 1902 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1903 */ 1904 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) 1905 { 1906 dev_info(&dev->dev, "Disabling L0s\n"); 1907 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1908 } 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1914 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1915 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1922 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1923 1924 static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1925 { 1926 /* rev 1 ncr53c810 chips don't set the class at all which means 1927 * they don't get their resources remapped. Fix that here. 1928 */ 1929 1930 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1931 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1932 dev->class = PCI_CLASS_STORAGE_SCSI; 1933 } 1934 } 1935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1936 1937 /* Enable 1k I/O space granularity on the Intel P64H2 */ 1938 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1939 { 1940 u16 en1k; 1941 u8 io_base_lo, io_limit_lo; 1942 unsigned long base, limit; 1943 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1944 1945 pci_read_config_word(dev, 0x40, &en1k); 1946 1947 if (en1k & 0x200) { 1948 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1949 1950 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1951 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1952 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1953 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1954 1955 if (base <= limit) { 1956 res->start = base; 1957 res->end = limit + 0x3ff; 1958 } 1959 } 1960 } 1961 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1962 1963 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 1964 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 1965 * in drivers/pci/setup-bus.c 1966 */ 1967 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 1968 { 1969 u16 en1k, iobl_adr, iobl_adr_1k; 1970 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1971 1972 pci_read_config_word(dev, 0x40, &en1k); 1973 1974 if (en1k & 0x200) { 1975 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 1976 1977 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1978 1979 if (iobl_adr != iobl_adr_1k) { 1980 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", 1981 iobl_adr,iobl_adr_1k); 1982 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1983 } 1984 } 1985 } 1986 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 1987 1988 /* Under some circumstances, AER is not linked with extended capabilities. 1989 * Force it to be linked by setting the corresponding control bit in the 1990 * config space. 1991 */ 1992 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1993 { 1994 uint8_t b; 1995 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1996 if (!(b & 0x20)) { 1997 pci_write_config_byte(dev, 0xf41, b | 0x20); 1998 dev_info(&dev->dev, 1999 "Linking AER extended capability\n"); 2000 } 2001 } 2002 } 2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2004 quirk_nvidia_ck804_pcie_aer_ext_cap); 2005 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2006 quirk_nvidia_ck804_pcie_aer_ext_cap); 2007 2008 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2009 { 2010 /* 2011 * Disable PCI Bus Parking and PCI Master read caching on CX700 2012 * which causes unspecified timing errors with a VT6212L on the PCI 2013 * bus leading to USB2.0 packet loss. 2014 * 2015 * This quirk is only enabled if a second (on the external PCI bus) 2016 * VT6212L is found -- the CX700 core itself also contains a USB 2017 * host controller with the same PCI ID as the VT6212L. 2018 */ 2019 2020 /* Count VT6212L instances */ 2021 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2022 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2023 uint8_t b; 2024 2025 /* p should contain the first (internal) VT6212L -- see if we have 2026 an external one by searching again */ 2027 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2028 if (!p) 2029 return; 2030 pci_dev_put(p); 2031 2032 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2033 if (b & 0x40) { 2034 /* Turn off PCI Bus Parking */ 2035 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2036 2037 dev_info(&dev->dev, 2038 "Disabling VIA CX700 PCI parking\n"); 2039 } 2040 } 2041 2042 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2043 if (b != 0) { 2044 /* Turn off PCI Master read caching */ 2045 pci_write_config_byte(dev, 0x72, 0x0); 2046 2047 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2048 pci_write_config_byte(dev, 0x75, 0x1); 2049 2050 /* Disable "Read FIFO Timer" */ 2051 pci_write_config_byte(dev, 0x77, 0x0); 2052 2053 dev_info(&dev->dev, 2054 "Disabling VIA CX700 PCI caching\n"); 2055 } 2056 } 2057 } 2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2059 2060 /* 2061 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2062 * VPD end tag will hang the device. This problem was initially 2063 * observed when a vpd entry was created in sysfs 2064 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2065 * will dump 32k of data. Reading a full 32k will cause an access 2066 * beyond the VPD end tag causing the device to hang. Once the device 2067 * is hung, the bnx2 driver will not be able to reset the device. 2068 * We believe that it is legal to read beyond the end tag and 2069 * therefore the solution is to limit the read/write length. 2070 */ 2071 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2072 { 2073 /* 2074 * Only disable the VPD capability for 5706, 5706S, 5708, 2075 * 5708S and 5709 rev. A 2076 */ 2077 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2078 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2079 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2080 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2081 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2082 (dev->revision & 0xf0) == 0x0)) { 2083 if (dev->vpd) 2084 dev->vpd->len = 0x80; 2085 } 2086 } 2087 2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2089 PCI_DEVICE_ID_NX2_5706, 2090 quirk_brcm_570x_limit_vpd); 2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2092 PCI_DEVICE_ID_NX2_5706S, 2093 quirk_brcm_570x_limit_vpd); 2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2095 PCI_DEVICE_ID_NX2_5708, 2096 quirk_brcm_570x_limit_vpd); 2097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2098 PCI_DEVICE_ID_NX2_5708S, 2099 quirk_brcm_570x_limit_vpd); 2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2101 PCI_DEVICE_ID_NX2_5709, 2102 quirk_brcm_570x_limit_vpd); 2103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2104 PCI_DEVICE_ID_NX2_5709S, 2105 quirk_brcm_570x_limit_vpd); 2106 2107 static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2108 { 2109 u32 rev; 2110 2111 pci_read_config_dword(dev, 0xf4, &rev); 2112 2113 /* Only CAP the MRRS if the device is a 5719 A0 */ 2114 if (rev == 0x05719000) { 2115 int readrq = pcie_get_readrq(dev); 2116 if (readrq > 2048) 2117 pcie_set_readrq(dev, 2048); 2118 } 2119 } 2120 2121 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2122 PCI_DEVICE_ID_TIGON3_5719, 2123 quirk_brcm_5719_limit_mrrs); 2124 2125 /* Originally in EDAC sources for i82875P: 2126 * Intel tells BIOS developers to hide device 6 which 2127 * configures the overflow device access containing 2128 * the DRBs - this is where we expose device 6. 2129 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2130 */ 2131 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) 2132 { 2133 u8 reg; 2134 2135 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2136 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2137 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2138 } 2139 } 2140 2141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2142 quirk_unhide_mch_dev6); 2143 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2144 quirk_unhide_mch_dev6); 2145 2146 #ifdef CONFIG_TILE 2147 /* 2148 * The Tilera TILEmpower platform needs to set the link speed 2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2151 * capability register of the PEX8624 PCIe switch. The switch 2152 * supports link speed auto negotiation, but falsely sets 2153 * the link speed to 5GT/s. 2154 */ 2155 static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev) 2156 { 2157 if (tile_plx_gen1) { 2158 pci_write_config_dword(dev, 0x98, 0x1); 2159 mdelay(50); 2160 } 2161 } 2162 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2163 #endif /* CONFIG_TILE */ 2164 2165 #ifdef CONFIG_PCI_MSI 2166 /* Some chipsets do not support MSI. We cannot easily rely on setting 2167 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2168 * some other busses controlled by the chipset even if Linux is not 2169 * aware of it. Instead of setting the flag on all busses in the 2170 * machine, simply disable MSI globally. 2171 */ 2172 static void __init quirk_disable_all_msi(struct pci_dev *dev) 2173 { 2174 pci_no_msi(); 2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2176 } 2177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2184 2185 /* Disable MSI on chipsets that are known to not support it */ 2186 static void __devinit quirk_disable_msi(struct pci_dev *dev) 2187 { 2188 if (dev->subordinate) { 2189 dev_warn(&dev->dev, "MSI quirk detected; " 2190 "subordinate MSI disabled\n"); 2191 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2192 } 2193 } 2194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2197 2198 /* 2199 * The APC bridge device in AMD 780 family northbridges has some random 2200 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2201 * we use the possible vendor/device IDs of the host bridge for the 2202 * declared quirk, and search for the APC bridge by slot number. 2203 */ 2204 static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2205 { 2206 struct pci_dev *apc_bridge; 2207 2208 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2209 if (apc_bridge) { 2210 if (apc_bridge->device == 0x9602) 2211 quirk_disable_msi(apc_bridge); 2212 pci_dev_put(apc_bridge); 2213 } 2214 } 2215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2217 2218 /* Go through the list of Hypertransport capabilities and 2219 * return 1 if a HT MSI capability is found and enabled */ 2220 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 2221 { 2222 int pos, ttl = 48; 2223 2224 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2225 while (pos && ttl--) { 2226 u8 flags; 2227 2228 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2229 &flags) == 0) 2230 { 2231 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2232 flags & HT_MSI_FLAGS_ENABLE ? 2233 "enabled" : "disabled"); 2234 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2235 } 2236 2237 pos = pci_find_next_ht_capability(dev, pos, 2238 HT_CAPTYPE_MSI_MAPPING); 2239 } 2240 return 0; 2241 } 2242 2243 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2244 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 2245 { 2246 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2247 dev_warn(&dev->dev, "MSI quirk detected; " 2248 "subordinate MSI disabled\n"); 2249 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2250 } 2251 } 2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2253 quirk_msi_ht_cap); 2254 2255 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2256 * MSI are supported if the MSI capability set in any of these mappings. 2257 */ 2258 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2259 { 2260 struct pci_dev *pdev; 2261 2262 if (!dev->subordinate) 2263 return; 2264 2265 /* check HT MSI cap on this chipset and the root one. 2266 * a single one having MSI is enough to be sure that MSI are supported. 2267 */ 2268 pdev = pci_get_slot(dev->bus, 0); 2269 if (!pdev) 2270 return; 2271 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2272 dev_warn(&dev->dev, "MSI quirk detected; " 2273 "subordinate MSI disabled\n"); 2274 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2275 } 2276 pci_dev_put(pdev); 2277 } 2278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2279 quirk_nvidia_ck804_msi_ht_cap); 2280 2281 /* Force enable MSI mapping capability on HT bridges */ 2282 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 2283 { 2284 int pos, ttl = 48; 2285 2286 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2287 while (pos && ttl--) { 2288 u8 flags; 2289 2290 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2291 &flags) == 0) { 2292 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2293 2294 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2295 flags | HT_MSI_FLAGS_ENABLE); 2296 } 2297 pos = pci_find_next_ht_capability(dev, pos, 2298 HT_CAPTYPE_MSI_MAPPING); 2299 } 2300 } 2301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2302 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2303 ht_enable_msi_mapping); 2304 2305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2306 ht_enable_msi_mapping); 2307 2308 /* The P5N32-SLI motherboards from Asus have a problem with msi 2309 * for the MCP55 NIC. It is not yet determined whether the msi problem 2310 * also affects other devices. As for now, turn off msi for this device. 2311 */ 2312 static void __devinit nvenet_msi_disable(struct pci_dev *dev) 2313 { 2314 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2315 2316 if (board_name && 2317 (strstr(board_name, "P5N32-SLI PREMIUM") || 2318 strstr(board_name, "P5N32-E SLI"))) { 2319 dev_info(&dev->dev, 2320 "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2321 dev->no_msi = 1; 2322 } 2323 } 2324 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2325 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2326 nvenet_msi_disable); 2327 2328 /* 2329 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing 2330 * config register. This register controls the routing of legacy interrupts 2331 * from devices that route through the MCP55. If this register is misprogramed 2332 * interrupts are only sent to the bsp, unlike conventional systems where the 2333 * irq is broadxast to all online cpus. Not having this register set 2334 * properly prevents kdump from booting up properly, so lets make sure that 2335 * we have it set correctly. 2336 * Note this is an undocumented register. 2337 */ 2338 static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2339 { 2340 u32 cfg; 2341 2342 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2343 return; 2344 2345 pci_read_config_dword(dev, 0x74, &cfg); 2346 2347 if (cfg & ((1 << 2) | (1 << 15))) { 2348 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2349 cfg &= ~((1 << 2) | (1 << 15)); 2350 pci_write_config_dword(dev, 0x74, cfg); 2351 } 2352 } 2353 2354 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2355 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2356 nvbridge_check_legacy_irq_routing); 2357 2358 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2359 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2360 nvbridge_check_legacy_irq_routing); 2361 2362 static int __devinit ht_check_msi_mapping(struct pci_dev *dev) 2363 { 2364 int pos, ttl = 48; 2365 int found = 0; 2366 2367 /* check if there is HT MSI cap or enabled on this device */ 2368 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2369 while (pos && ttl--) { 2370 u8 flags; 2371 2372 if (found < 1) 2373 found = 1; 2374 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2375 &flags) == 0) { 2376 if (flags & HT_MSI_FLAGS_ENABLE) { 2377 if (found < 2) { 2378 found = 2; 2379 break; 2380 } 2381 } 2382 } 2383 pos = pci_find_next_ht_capability(dev, pos, 2384 HT_CAPTYPE_MSI_MAPPING); 2385 } 2386 2387 return found; 2388 } 2389 2390 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) 2391 { 2392 struct pci_dev *dev; 2393 int pos; 2394 int i, dev_no; 2395 int found = 0; 2396 2397 dev_no = host_bridge->devfn >> 3; 2398 for (i = dev_no + 1; i < 0x20; i++) { 2399 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2400 if (!dev) 2401 continue; 2402 2403 /* found next host bridge ?*/ 2404 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2405 if (pos != 0) { 2406 pci_dev_put(dev); 2407 break; 2408 } 2409 2410 if (ht_check_msi_mapping(dev)) { 2411 found = 1; 2412 pci_dev_put(dev); 2413 break; 2414 } 2415 pci_dev_put(dev); 2416 } 2417 2418 return found; 2419 } 2420 2421 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2422 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2423 2424 static int __devinit is_end_of_ht_chain(struct pci_dev *dev) 2425 { 2426 int pos, ctrl_off; 2427 int end = 0; 2428 u16 flags, ctrl; 2429 2430 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2431 2432 if (!pos) 2433 goto out; 2434 2435 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2436 2437 ctrl_off = ((flags >> 10) & 1) ? 2438 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2439 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2440 2441 if (ctrl & (1 << 6)) 2442 end = 1; 2443 2444 out: 2445 return end; 2446 } 2447 2448 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) 2449 { 2450 struct pci_dev *host_bridge; 2451 int pos; 2452 int i, dev_no; 2453 int found = 0; 2454 2455 dev_no = dev->devfn >> 3; 2456 for (i = dev_no; i >= 0; i--) { 2457 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2458 if (!host_bridge) 2459 continue; 2460 2461 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2462 if (pos != 0) { 2463 found = 1; 2464 break; 2465 } 2466 pci_dev_put(host_bridge); 2467 } 2468 2469 if (!found) 2470 return; 2471 2472 /* don't enable end_device/host_bridge with leaf directly here */ 2473 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2474 host_bridge_with_leaf(host_bridge)) 2475 goto out; 2476 2477 /* root did that ! */ 2478 if (msi_ht_cap_enabled(host_bridge)) 2479 goto out; 2480 2481 ht_enable_msi_mapping(dev); 2482 2483 out: 2484 pci_dev_put(host_bridge); 2485 } 2486 2487 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) 2488 { 2489 int pos, ttl = 48; 2490 2491 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2492 while (pos && ttl--) { 2493 u8 flags; 2494 2495 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2496 &flags) == 0) { 2497 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2498 2499 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2500 flags & ~HT_MSI_FLAGS_ENABLE); 2501 } 2502 pos = pci_find_next_ht_capability(dev, pos, 2503 HT_CAPTYPE_MSI_MAPPING); 2504 } 2505 } 2506 2507 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2508 { 2509 struct pci_dev *host_bridge; 2510 int pos; 2511 int found; 2512 2513 if (!pci_msi_enabled()) 2514 return; 2515 2516 /* check if there is HT MSI cap or enabled on this device */ 2517 found = ht_check_msi_mapping(dev); 2518 2519 /* no HT MSI CAP */ 2520 if (found == 0) 2521 return; 2522 2523 /* 2524 * HT MSI mapping should be disabled on devices that are below 2525 * a non-Hypertransport host bridge. Locate the host bridge... 2526 */ 2527 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2528 if (host_bridge == NULL) { 2529 dev_warn(&dev->dev, 2530 "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2531 return; 2532 } 2533 2534 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2535 if (pos != 0) { 2536 /* Host bridge is to HT */ 2537 if (found == 1) { 2538 /* it is not enabled, try to enable it */ 2539 if (all) 2540 ht_enable_msi_mapping(dev); 2541 else 2542 nv_ht_enable_msi_mapping(dev); 2543 } 2544 return; 2545 } 2546 2547 /* HT MSI is not enabled */ 2548 if (found == 1) 2549 return; 2550 2551 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2552 ht_disable_msi_mapping(dev); 2553 } 2554 2555 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2556 { 2557 return __nv_msi_ht_cap_quirk(dev, 1); 2558 } 2559 2560 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2561 { 2562 return __nv_msi_ht_cap_quirk(dev, 0); 2563 } 2564 2565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2566 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2567 2568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2570 2571 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) 2572 { 2573 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2574 } 2575 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2576 { 2577 struct pci_dev *p; 2578 2579 /* SB700 MSI issue will be fixed at HW level from revision A21, 2580 * we need check PCI REVISION ID of SMBus controller to get SB700 2581 * revision. 2582 */ 2583 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2584 NULL); 2585 if (!p) 2586 return; 2587 2588 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2589 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2590 pci_dev_put(p); 2591 } 2592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2593 PCI_DEVICE_ID_TIGON3_5780, 2594 quirk_msi_intx_disable_bug); 2595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2596 PCI_DEVICE_ID_TIGON3_5780S, 2597 quirk_msi_intx_disable_bug); 2598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2599 PCI_DEVICE_ID_TIGON3_5714, 2600 quirk_msi_intx_disable_bug); 2601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2602 PCI_DEVICE_ID_TIGON3_5714S, 2603 quirk_msi_intx_disable_bug); 2604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2605 PCI_DEVICE_ID_TIGON3_5715, 2606 quirk_msi_intx_disable_bug); 2607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2608 PCI_DEVICE_ID_TIGON3_5715S, 2609 quirk_msi_intx_disable_bug); 2610 2611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2612 quirk_msi_intx_disable_ati_bug); 2613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2614 quirk_msi_intx_disable_ati_bug); 2615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2616 quirk_msi_intx_disable_ati_bug); 2617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2618 quirk_msi_intx_disable_ati_bug); 2619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2620 quirk_msi_intx_disable_ati_bug); 2621 2622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2623 quirk_msi_intx_disable_bug); 2624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2625 quirk_msi_intx_disable_bug); 2626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2627 quirk_msi_intx_disable_bug); 2628 2629 #endif /* CONFIG_PCI_MSI */ 2630 2631 /* Allow manual resource allocation for PCI hotplug bridges 2632 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2633 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2634 * kernel fails to allocate resources when hotplug device is 2635 * inserted and PCI bus is rescanned. 2636 */ 2637 static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) 2638 { 2639 dev->is_hotplug_bridge = 1; 2640 } 2641 2642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2643 2644 /* 2645 * This is a quirk for the Ricoh MMC controller found as a part of 2646 * some mulifunction chips. 2647 2648 * This is very similar and based on the ricoh_mmc driver written by 2649 * Philip Langdale. Thank you for these magic sequences. 2650 * 2651 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2652 * and one or both of cardbus or firewire. 2653 * 2654 * It happens that they implement SD and MMC 2655 * support as separate controllers (and PCI functions). The linux SDHCI 2656 * driver supports MMC cards but the chip detects MMC cards in hardware 2657 * and directs them to the MMC controller - so the SDHCI driver never sees 2658 * them. 2659 * 2660 * To get around this, we must disable the useless MMC controller. 2661 * At that point, the SDHCI controller will start seeing them 2662 * It seems to be the case that the relevant PCI registers to deactivate the 2663 * MMC controller live on PCI function 0, which might be the cardbus controller 2664 * or the firewire controller, depending on the particular chip in question 2665 * 2666 * This has to be done early, because as soon as we disable the MMC controller 2667 * other pci functions shift up one level, e.g. function #2 becomes function 2668 * #1, and this will confuse the pci core. 2669 */ 2670 2671 #ifdef CONFIG_MMC_RICOH_MMC 2672 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2673 { 2674 /* disable via cardbus interface */ 2675 u8 write_enable; 2676 u8 write_target; 2677 u8 disable; 2678 2679 /* disable must be done via function #0 */ 2680 if (PCI_FUNC(dev->devfn)) 2681 return; 2682 2683 pci_read_config_byte(dev, 0xB7, &disable); 2684 if (disable & 0x02) 2685 return; 2686 2687 pci_read_config_byte(dev, 0x8E, &write_enable); 2688 pci_write_config_byte(dev, 0x8E, 0xAA); 2689 pci_read_config_byte(dev, 0x8D, &write_target); 2690 pci_write_config_byte(dev, 0x8D, 0xB7); 2691 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2692 pci_write_config_byte(dev, 0x8E, write_enable); 2693 pci_write_config_byte(dev, 0x8D, write_target); 2694 2695 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2696 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2697 } 2698 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2699 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2700 2701 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2702 { 2703 /* disable via firewire interface */ 2704 u8 write_enable; 2705 u8 disable; 2706 2707 /* disable must be done via function #0 */ 2708 if (PCI_FUNC(dev->devfn)) 2709 return; 2710 /* 2711 * RICOH 0xe823 SD/MMC card reader fails to recognize 2712 * certain types of SD/MMC cards. Lowering the SD base 2713 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2714 * 2715 * 0x150 - SD2.0 mode enable for changing base clock 2716 * frequency to 50Mhz 2717 * 0xe1 - Base clock frequency 2718 * 0x32 - 50Mhz new clock frequency 2719 * 0xf9 - Key register for 0x150 2720 * 0xfc - key register for 0xe1 2721 */ 2722 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2723 pci_write_config_byte(dev, 0xf9, 0xfc); 2724 pci_write_config_byte(dev, 0x150, 0x10); 2725 pci_write_config_byte(dev, 0xf9, 0x00); 2726 pci_write_config_byte(dev, 0xfc, 0x01); 2727 pci_write_config_byte(dev, 0xe1, 0x32); 2728 pci_write_config_byte(dev, 0xfc, 0x00); 2729 2730 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2731 } 2732 2733 pci_read_config_byte(dev, 0xCB, &disable); 2734 2735 if (disable & 0x02) 2736 return; 2737 2738 pci_read_config_byte(dev, 0xCA, &write_enable); 2739 pci_write_config_byte(dev, 0xCA, 0x57); 2740 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2741 pci_write_config_byte(dev, 0xCA, write_enable); 2742 2743 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2744 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2745 2746 } 2747 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2749 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2751 #endif /*CONFIG_MMC_RICOH_MMC*/ 2752 2753 #ifdef CONFIG_DMAR_TABLE 2754 #define VTUNCERRMSK_REG 0x1ac 2755 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2756 /* 2757 * This is a quirk for masking vt-d spec defined errors to platform error 2758 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2759 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2760 * on the RAS config settings of the platform) when a vt-d fault happens. 2761 * The resulting SMI caused the system to hang. 2762 * 2763 * VT-d spec related errors are already handled by the VT-d OS code, so no 2764 * need to report the same error through other channels. 2765 */ 2766 static void vtd_mask_spec_errors(struct pci_dev *dev) 2767 { 2768 u32 word; 2769 2770 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2771 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2772 } 2773 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2774 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2775 #endif 2776 2777 static void __devinit fixup_ti816x_class(struct pci_dev* dev) 2778 { 2779 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2780 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); 2781 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; 2782 } 2783 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2784 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); 2785 2786 /* Some PCIe devices do not work reliably with the claimed maximum 2787 * payload size supported. 2788 */ 2789 static void __devinit fixup_mpss_256(struct pci_dev *dev) 2790 { 2791 dev->pcie_mpss = 1; /* 256 bytes */ 2792 } 2793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2794 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2796 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2797 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2798 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2799 2800 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2801 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2802 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2803 * until all of the devices are discovered and buses walked, read completion 2804 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2805 * it is possible to hotplug a device with MPS of 256B. 2806 */ 2807 static void __devinit quirk_intel_mc_errata(struct pci_dev *dev) 2808 { 2809 int err; 2810 u16 rcc; 2811 2812 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 2813 return; 2814 2815 /* Intel errata specifies bits to change but does not say what they are. 2816 * Keeping them magical until such time as the registers and values can 2817 * be explained. 2818 */ 2819 err = pci_read_config_word(dev, 0x48, &rcc); 2820 if (err) { 2821 dev_err(&dev->dev, "Error attempting to read the read " 2822 "completion coalescing register.\n"); 2823 return; 2824 } 2825 2826 if (!(rcc & (1 << 10))) 2827 return; 2828 2829 rcc &= ~(1 << 10); 2830 2831 err = pci_write_config_word(dev, 0x48, rcc); 2832 if (err) { 2833 dev_err(&dev->dev, "Error attempting to write the read " 2834 "completion coalescing register.\n"); 2835 return; 2836 } 2837 2838 pr_info_once("Read completion coalescing disabled due to hardware " 2839 "errata relating to 256B MPS.\n"); 2840 } 2841 /* Intel 5000 series memory controllers and ports 2-7 */ 2842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2856 /* Intel 5100 series memory controllers and ports 2-7 */ 2857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2868 2869 2870 static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev) 2871 { 2872 ktime_t calltime, delta, rettime; 2873 unsigned long long duration; 2874 2875 printk(KERN_DEBUG "calling %pF @ %i for %s\n", 2876 fn, task_pid_nr(current), dev_name(&dev->dev)); 2877 calltime = ktime_get(); 2878 fn(dev); 2879 rettime = ktime_get(); 2880 delta = ktime_sub(rettime, calltime); 2881 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 2882 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs for %s\n", 2883 fn, duration, dev_name(&dev->dev)); 2884 } 2885 2886 /* 2887 * Some BIOS implementations leave the Intel GPU interrupts enabled, 2888 * even though no one is handling them (f.e. i915 driver is never loaded). 2889 * Additionally the interrupt destination is not set up properly 2890 * and the interrupt ends up -somewhere-. 2891 * 2892 * These spurious interrupts are "sticky" and the kernel disables 2893 * the (shared) interrupt line after 100.000+ generated interrupts. 2894 * 2895 * Fix it by disabling the still enabled interrupts. 2896 * This resolves crashes often seen on monitor unplug. 2897 */ 2898 #define I915_DEIER_REG 0x4400c 2899 static void __devinit disable_igfx_irq(struct pci_dev *dev) 2900 { 2901 void __iomem *regs = pci_iomap(dev, 0, 0); 2902 if (regs == NULL) { 2903 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 2904 return; 2905 } 2906 2907 /* Check if any interrupt line is still enabled */ 2908 if (readl(regs + I915_DEIER_REG) != 0) { 2909 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; " 2910 "disabling\n"); 2911 2912 writel(0, regs + I915_DEIER_REG); 2913 } 2914 2915 pci_iounmap(dev, regs); 2916 } 2917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 2918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 2919 2920 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2921 struct pci_fixup *end) 2922 { 2923 for (; f < end; f++) 2924 if ((f->class == (u32) (dev->class >> f->class_shift) || 2925 f->class == (u32) PCI_ANY_ID) && 2926 (f->vendor == dev->vendor || 2927 f->vendor == (u16) PCI_ANY_ID) && 2928 (f->device == dev->device || 2929 f->device == (u16) PCI_ANY_ID)) { 2930 dev_dbg(&dev->dev, "calling %pF\n", f->hook); 2931 if (initcall_debug) 2932 do_one_fixup_debug(f->hook, dev); 2933 else 2934 f->hook(dev); 2935 } 2936 } 2937 2938 extern struct pci_fixup __start_pci_fixups_early[]; 2939 extern struct pci_fixup __end_pci_fixups_early[]; 2940 extern struct pci_fixup __start_pci_fixups_header[]; 2941 extern struct pci_fixup __end_pci_fixups_header[]; 2942 extern struct pci_fixup __start_pci_fixups_final[]; 2943 extern struct pci_fixup __end_pci_fixups_final[]; 2944 extern struct pci_fixup __start_pci_fixups_enable[]; 2945 extern struct pci_fixup __end_pci_fixups_enable[]; 2946 extern struct pci_fixup __start_pci_fixups_resume[]; 2947 extern struct pci_fixup __end_pci_fixups_resume[]; 2948 extern struct pci_fixup __start_pci_fixups_resume_early[]; 2949 extern struct pci_fixup __end_pci_fixups_resume_early[]; 2950 extern struct pci_fixup __start_pci_fixups_suspend[]; 2951 extern struct pci_fixup __end_pci_fixups_suspend[]; 2952 2953 2954 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2955 { 2956 struct pci_fixup *start, *end; 2957 2958 switch(pass) { 2959 case pci_fixup_early: 2960 start = __start_pci_fixups_early; 2961 end = __end_pci_fixups_early; 2962 break; 2963 2964 case pci_fixup_header: 2965 start = __start_pci_fixups_header; 2966 end = __end_pci_fixups_header; 2967 break; 2968 2969 case pci_fixup_final: 2970 start = __start_pci_fixups_final; 2971 end = __end_pci_fixups_final; 2972 break; 2973 2974 case pci_fixup_enable: 2975 start = __start_pci_fixups_enable; 2976 end = __end_pci_fixups_enable; 2977 break; 2978 2979 case pci_fixup_resume: 2980 start = __start_pci_fixups_resume; 2981 end = __end_pci_fixups_resume; 2982 break; 2983 2984 case pci_fixup_resume_early: 2985 start = __start_pci_fixups_resume_early; 2986 end = __end_pci_fixups_resume_early; 2987 break; 2988 2989 case pci_fixup_suspend: 2990 start = __start_pci_fixups_suspend; 2991 end = __end_pci_fixups_suspend; 2992 break; 2993 2994 default: 2995 /* stupid compiler warning, you would think with an enum... */ 2996 return; 2997 } 2998 pci_do_fixups(dev, start, end); 2999 } 3000 EXPORT_SYMBOL(pci_fixup_device); 3001 3002 static int __init pci_apply_final_quirks(void) 3003 { 3004 struct pci_dev *dev = NULL; 3005 u8 cls = 0; 3006 u8 tmp; 3007 3008 if (pci_cache_line_size) 3009 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3010 pci_cache_line_size << 2); 3011 3012 for_each_pci_dev(dev) { 3013 pci_fixup_device(pci_fixup_final, dev); 3014 /* 3015 * If arch hasn't set it explicitly yet, use the CLS 3016 * value shared by all PCI devices. If there's a 3017 * mismatch, fall back to the default value. 3018 */ 3019 if (!pci_cache_line_size) { 3020 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3021 if (!cls) 3022 cls = tmp; 3023 if (!tmp || cls == tmp) 3024 continue; 3025 3026 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " 3027 "using %u bytes\n", cls << 2, tmp << 2, 3028 pci_dfl_cache_line_size << 2); 3029 pci_cache_line_size = pci_dfl_cache_line_size; 3030 } 3031 } 3032 if (!pci_cache_line_size) { 3033 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3034 cls << 2, pci_dfl_cache_line_size << 2); 3035 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3036 } 3037 3038 return 0; 3039 } 3040 3041 fs_initcall_sync(pci_apply_final_quirks); 3042 3043 /* 3044 * Followings are device-specific reset methods which can be used to 3045 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3046 * not available. 3047 */ 3048 static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 3049 { 3050 int pos; 3051 3052 /* only implement PCI_CLASS_SERIAL_USB at present */ 3053 if (dev->class == PCI_CLASS_SERIAL_USB) { 3054 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 3055 if (!pos) 3056 return -ENOTTY; 3057 3058 if (probe) 3059 return 0; 3060 3061 pci_write_config_byte(dev, pos + 0x4, 1); 3062 msleep(100); 3063 3064 return 0; 3065 } else { 3066 return -ENOTTY; 3067 } 3068 } 3069 3070 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3071 { 3072 int pos; 3073 3074 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 3075 if (!pos) 3076 return -ENOTTY; 3077 3078 if (probe) 3079 return 0; 3080 3081 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, 3082 PCI_EXP_DEVCTL_BCR_FLR); 3083 msleep(100); 3084 3085 return 0; 3086 } 3087 3088 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3089 3090 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3091 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3092 reset_intel_82599_sfp_virtfn }, 3093 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3094 reset_intel_generic_dev }, 3095 { 0 } 3096 }; 3097 3098 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3099 { 3100 const struct pci_dev_reset_methods *i; 3101 3102 for (i = pci_dev_reset_methods; i->reset; i++) { 3103 if ((i->vendor == dev->vendor || 3104 i->vendor == (u16)PCI_ANY_ID) && 3105 (i->device == dev->device || 3106 i->device == (u16)PCI_ANY_ID)) 3107 return i->reset(dev, probe); 3108 } 3109 3110 return -ENOTTY; 3111 } 3112