1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <linux/nvme.h> 29 #include <linux/platform_data/x86/apple.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/switchtec.h> 32 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 33 #include "pci.h" 34 35 static ktime_t fixup_debug_start(struct pci_dev *dev, 36 void (*fn)(struct pci_dev *dev)) 37 { 38 if (initcall_debug) 39 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current)); 40 41 return ktime_get(); 42 } 43 44 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 45 void (*fn)(struct pci_dev *dev)) 46 { 47 ktime_t delta, rettime; 48 unsigned long long duration; 49 50 rettime = ktime_get(); 51 delta = ktime_sub(rettime, calltime); 52 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 53 if (initcall_debug || duration > 10000) 54 pci_info(dev, "%pF took %lld usecs\n", fn, duration); 55 } 56 57 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 58 struct pci_fixup *end) 59 { 60 ktime_t calltime; 61 62 for (; f < end; f++) 63 if ((f->class == (u32) (dev->class >> f->class_shift) || 64 f->class == (u32) PCI_ANY_ID) && 65 (f->vendor == dev->vendor || 66 f->vendor == (u16) PCI_ANY_ID) && 67 (f->device == dev->device || 68 f->device == (u16) PCI_ANY_ID)) { 69 void (*hook)(struct pci_dev *dev); 70 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 71 hook = offset_to_ptr(&f->hook_offset); 72 #else 73 hook = f->hook; 74 #endif 75 calltime = fixup_debug_start(dev, hook); 76 hook(dev); 77 fixup_debug_report(dev, calltime, hook); 78 } 79 } 80 81 extern struct pci_fixup __start_pci_fixups_early[]; 82 extern struct pci_fixup __end_pci_fixups_early[]; 83 extern struct pci_fixup __start_pci_fixups_header[]; 84 extern struct pci_fixup __end_pci_fixups_header[]; 85 extern struct pci_fixup __start_pci_fixups_final[]; 86 extern struct pci_fixup __end_pci_fixups_final[]; 87 extern struct pci_fixup __start_pci_fixups_enable[]; 88 extern struct pci_fixup __end_pci_fixups_enable[]; 89 extern struct pci_fixup __start_pci_fixups_resume[]; 90 extern struct pci_fixup __end_pci_fixups_resume[]; 91 extern struct pci_fixup __start_pci_fixups_resume_early[]; 92 extern struct pci_fixup __end_pci_fixups_resume_early[]; 93 extern struct pci_fixup __start_pci_fixups_suspend[]; 94 extern struct pci_fixup __end_pci_fixups_suspend[]; 95 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 96 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 97 98 static bool pci_apply_fixup_final_quirks; 99 100 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 101 { 102 struct pci_fixup *start, *end; 103 104 switch (pass) { 105 case pci_fixup_early: 106 start = __start_pci_fixups_early; 107 end = __end_pci_fixups_early; 108 break; 109 110 case pci_fixup_header: 111 start = __start_pci_fixups_header; 112 end = __end_pci_fixups_header; 113 break; 114 115 case pci_fixup_final: 116 if (!pci_apply_fixup_final_quirks) 117 return; 118 start = __start_pci_fixups_final; 119 end = __end_pci_fixups_final; 120 break; 121 122 case pci_fixup_enable: 123 start = __start_pci_fixups_enable; 124 end = __end_pci_fixups_enable; 125 break; 126 127 case pci_fixup_resume: 128 start = __start_pci_fixups_resume; 129 end = __end_pci_fixups_resume; 130 break; 131 132 case pci_fixup_resume_early: 133 start = __start_pci_fixups_resume_early; 134 end = __end_pci_fixups_resume_early; 135 break; 136 137 case pci_fixup_suspend: 138 start = __start_pci_fixups_suspend; 139 end = __end_pci_fixups_suspend; 140 break; 141 142 case pci_fixup_suspend_late: 143 start = __start_pci_fixups_suspend_late; 144 end = __end_pci_fixups_suspend_late; 145 break; 146 147 default: 148 /* stupid compiler warning, you would think with an enum... */ 149 return; 150 } 151 pci_do_fixups(dev, start, end); 152 } 153 EXPORT_SYMBOL(pci_fixup_device); 154 155 static int __init pci_apply_final_quirks(void) 156 { 157 struct pci_dev *dev = NULL; 158 u8 cls = 0; 159 u8 tmp; 160 161 if (pci_cache_line_size) 162 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 163 pci_cache_line_size << 2); 164 165 pci_apply_fixup_final_quirks = true; 166 for_each_pci_dev(dev) { 167 pci_fixup_device(pci_fixup_final, dev); 168 /* 169 * If arch hasn't set it explicitly yet, use the CLS 170 * value shared by all PCI devices. If there's a 171 * mismatch, fall back to the default value. 172 */ 173 if (!pci_cache_line_size) { 174 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 175 if (!cls) 176 cls = tmp; 177 if (!tmp || cls == tmp) 178 continue; 179 180 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 181 cls << 2, tmp << 2, 182 pci_dfl_cache_line_size << 2); 183 pci_cache_line_size = pci_dfl_cache_line_size; 184 } 185 } 186 187 if (!pci_cache_line_size) { 188 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 189 cls << 2, pci_dfl_cache_line_size << 2); 190 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 191 } 192 193 return 0; 194 } 195 fs_initcall_sync(pci_apply_final_quirks); 196 197 /* 198 * Decoding should be disabled for a PCI device during BAR sizing to avoid 199 * conflict. But doing so may cause problems on host bridge and perhaps other 200 * key system devices. For devices that need to have mmio decoding always-on, 201 * we need to set the dev->mmio_always_on bit. 202 */ 203 static void quirk_mmio_always_on(struct pci_dev *dev) 204 { 205 dev->mmio_always_on = 1; 206 } 207 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 208 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 209 210 /* 211 * The Mellanox Tavor device gives false positive parity errors. Mark this 212 * device with a broken_parity_status to allow PCI scanning code to "skip" 213 * this now blacklisted device. 214 */ 215 static void quirk_mellanox_tavor(struct pci_dev *dev) 216 { 217 dev->broken_parity_status = 1; /* This device gives false positives */ 218 } 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 221 222 /* 223 * Deal with broken BIOSes that neglect to enable passive release, 224 * which can cause problems in combination with the 82441FX/PPro MTRRs 225 */ 226 static void quirk_passive_release(struct pci_dev *dev) 227 { 228 struct pci_dev *d = NULL; 229 unsigned char dlc; 230 231 /* 232 * We have to make sure a particular bit is set in the PIIX3 233 * ISA bridge, so we have to go out and find it. 234 */ 235 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 236 pci_read_config_byte(d, 0x82, &dlc); 237 if (!(dlc & 1<<1)) { 238 pci_info(d, "PIIX3: Enabling Passive Release\n"); 239 dlc |= 1<<1; 240 pci_write_config_byte(d, 0x82, dlc); 241 } 242 } 243 } 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 245 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 246 247 /* 248 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 249 * workaround but VIA don't answer queries. If you happen to have good 250 * contacts at VIA ask them for me please -- Alan 251 * 252 * This appears to be BIOS not version dependent. So presumably there is a 253 * chipset level fix. 254 */ 255 static void quirk_isa_dma_hangs(struct pci_dev *dev) 256 { 257 if (!isa_dma_bridge_buggy) { 258 isa_dma_bridge_buggy = 1; 259 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 260 } 261 } 262 /* 263 * It's not totally clear which chipsets are the problematic ones. We know 264 * 82C586 and 82C596 variants are affected. 265 */ 266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 273 274 /* 275 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 276 * for some HT machines to use C4 w/o hanging. 277 */ 278 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 279 { 280 u32 pmbase; 281 u16 pm1a; 282 283 pci_read_config_dword(dev, 0x40, &pmbase); 284 pmbase = pmbase & 0xff80; 285 pm1a = inw(pmbase); 286 287 if (pm1a & 0x10) { 288 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 289 outw(0x10, pmbase); 290 } 291 } 292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 293 294 /* Chipsets where PCI->PCI transfers vanish or hang */ 295 static void quirk_nopcipci(struct pci_dev *dev) 296 { 297 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 298 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 299 pci_pci_problems |= PCIPCI_FAIL; 300 } 301 } 302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 304 305 static void quirk_nopciamd(struct pci_dev *dev) 306 { 307 u8 rev; 308 pci_read_config_byte(dev, 0x08, &rev); 309 if (rev == 0x13) { 310 /* Erratum 24 */ 311 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 312 pci_pci_problems |= PCIAGP_FAIL; 313 } 314 } 315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 316 317 /* Triton requires workarounds to be used by the drivers */ 318 static void quirk_triton(struct pci_dev *dev) 319 { 320 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 321 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 322 pci_pci_problems |= PCIPCI_TRITON; 323 } 324 } 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 329 330 /* 331 * VIA Apollo KT133 needs PCI latency patch 332 * Made according to a Windows driver-based patch by George E. Breese; 333 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 334 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 335 * which Mr Breese based his work. 336 * 337 * Updated based on further information from the site and also on 338 * information provided by VIA 339 */ 340 static void quirk_vialatency(struct pci_dev *dev) 341 { 342 struct pci_dev *p; 343 u8 busarb; 344 345 /* 346 * Ok, we have a potential problem chipset here. Now see if we have 347 * a buggy southbridge. 348 */ 349 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 350 if (p != NULL) { 351 352 /* 353 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 354 * thanks Dan Hollis. 355 * Check for buggy part revisions 356 */ 357 if (p->revision < 0x40 || p->revision > 0x42) 358 goto exit; 359 } else { 360 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 361 if (p == NULL) /* No problem parts */ 362 goto exit; 363 364 /* Check for buggy part revisions */ 365 if (p->revision < 0x10 || p->revision > 0x12) 366 goto exit; 367 } 368 369 /* 370 * Ok we have the problem. Now set the PCI master grant to occur 371 * every master grant. The apparent bug is that under high PCI load 372 * (quite common in Linux of course) you can get data loss when the 373 * CPU is held off the bus for 3 bus master requests. This happens 374 * to include the IDE controllers.... 375 * 376 * VIA only apply this fix when an SB Live! is present but under 377 * both Linux and Windows this isn't enough, and we have seen 378 * corruption without SB Live! but with things like 3 UDMA IDE 379 * controllers. So we ignore that bit of the VIA recommendation.. 380 */ 381 pci_read_config_byte(dev, 0x76, &busarb); 382 383 /* 384 * Set bit 4 and bit 5 of byte 76 to 0x01 385 * "Master priority rotation on every PCI master grant" 386 */ 387 busarb &= ~(1<<5); 388 busarb |= (1<<4); 389 pci_write_config_byte(dev, 0x76, busarb); 390 pci_info(dev, "Applying VIA southbridge workaround\n"); 391 exit: 392 pci_dev_put(p); 393 } 394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 397 /* Must restore this on a resume from RAM */ 398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 399 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 400 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 401 402 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 403 static void quirk_viaetbf(struct pci_dev *dev) 404 { 405 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 406 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 407 pci_pci_problems |= PCIPCI_VIAETBF; 408 } 409 } 410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 411 412 static void quirk_vsfx(struct pci_dev *dev) 413 { 414 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 415 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 416 pci_pci_problems |= PCIPCI_VSFX; 417 } 418 } 419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 420 421 /* 422 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 423 * space. Latency must be set to 0xA and Triton workaround applied too. 424 * [Info kindly provided by ALi] 425 */ 426 static void quirk_alimagik(struct pci_dev *dev) 427 { 428 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 429 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 430 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 431 } 432 } 433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 435 436 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 437 static void quirk_natoma(struct pci_dev *dev) 438 { 439 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 440 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 441 pci_pci_problems |= PCIPCI_NATOMA; 442 } 443 } 444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 450 451 /* 452 * This chip can cause PCI parity errors if config register 0xA0 is read 453 * while DMAs are occurring. 454 */ 455 static void quirk_citrine(struct pci_dev *dev) 456 { 457 dev->cfg_size = 0xA0; 458 } 459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 460 461 /* 462 * This chip can cause bus lockups if config addresses above 0x600 463 * are read or written. 464 */ 465 static void quirk_nfp6000(struct pci_dev *dev) 466 { 467 dev->cfg_size = 0x600; 468 } 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 473 474 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 475 static void quirk_extend_bar_to_page(struct pci_dev *dev) 476 { 477 int i; 478 479 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { 480 struct resource *r = &dev->resource[i]; 481 482 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 483 r->end = PAGE_SIZE - 1; 484 r->start = 0; 485 r->flags |= IORESOURCE_UNSET; 486 pci_info(dev, "expanded BAR %d to page size: %pR\n", 487 i, r); 488 } 489 } 490 } 491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 492 493 /* 494 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 495 * If it's needed, re-allocate the region. 496 */ 497 static void quirk_s3_64M(struct pci_dev *dev) 498 { 499 struct resource *r = &dev->resource[0]; 500 501 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 502 r->flags |= IORESOURCE_UNSET; 503 r->start = 0; 504 r->end = 0x3ffffff; 505 } 506 } 507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 509 510 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 511 const char *name) 512 { 513 u32 region; 514 struct pci_bus_region bus_region; 515 struct resource *res = dev->resource + pos; 516 517 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 518 519 if (!region) 520 return; 521 522 res->name = pci_name(dev); 523 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 524 res->flags |= 525 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 526 region &= ~(size - 1); 527 528 /* Convert from PCI bus to resource space */ 529 bus_region.start = region; 530 bus_region.end = region + size - 1; 531 pcibios_bus_to_resource(dev->bus, res, &bus_region); 532 533 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 534 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 535 } 536 537 /* 538 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 539 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 540 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 541 * (which conflicts w/ BAR1's memory range). 542 * 543 * CS553x's ISA PCI BARs may also be read-only (ref: 544 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 545 */ 546 static void quirk_cs5536_vsa(struct pci_dev *dev) 547 { 548 static char *name = "CS5536 ISA bridge"; 549 550 if (pci_resource_len(dev, 0) != 8) { 551 quirk_io(dev, 0, 8, name); /* SMB */ 552 quirk_io(dev, 1, 256, name); /* GPIO */ 553 quirk_io(dev, 2, 64, name); /* MFGPT */ 554 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 555 name); 556 } 557 } 558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 559 560 static void quirk_io_region(struct pci_dev *dev, int port, 561 unsigned size, int nr, const char *name) 562 { 563 u16 region; 564 struct pci_bus_region bus_region; 565 struct resource *res = dev->resource + nr; 566 567 pci_read_config_word(dev, port, ®ion); 568 region &= ~(size - 1); 569 570 if (!region) 571 return; 572 573 res->name = pci_name(dev); 574 res->flags = IORESOURCE_IO; 575 576 /* Convert from PCI bus to resource space */ 577 bus_region.start = region; 578 bus_region.end = region + size - 1; 579 pcibios_bus_to_resource(dev->bus, res, &bus_region); 580 581 if (!pci_claim_resource(dev, nr)) 582 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 583 } 584 585 /* 586 * ATI Northbridge setups MCE the processor if you even read somewhere 587 * between 0x3b0->0x3bb or read 0x3d3 588 */ 589 static void quirk_ati_exploding_mce(struct pci_dev *dev) 590 { 591 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 592 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 593 request_region(0x3b0, 0x0C, "RadeonIGP"); 594 request_region(0x3d3, 0x01, "RadeonIGP"); 595 } 596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 597 598 /* 599 * In the AMD NL platform, this device ([1022:7912]) has a class code of 600 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 601 * claim it. 602 * 603 * But the dwc3 driver is a more specific driver for this device, and we'd 604 * prefer to use it instead of xhci. To prevent xhci from claiming the 605 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 606 * defines as "USB device (not host controller)". The dwc3 driver can then 607 * claim it based on its Vendor and Device ID. 608 */ 609 static void quirk_amd_nl_class(struct pci_dev *pdev) 610 { 611 u32 class = pdev->class; 612 613 /* Use "USB Device (not host controller)" class */ 614 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 615 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 616 class, pdev->class); 617 } 618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 619 quirk_amd_nl_class); 620 621 /* 622 * Let's make the southbridge information explicit instead of having to 623 * worry about people probing the ACPI areas, for example.. (Yes, it 624 * happens, and if you read the wrong ACPI register it will put the machine 625 * to sleep with no way of waking it up again. Bummer). 626 * 627 * ALI M7101: Two IO regions pointed to by words at 628 * 0xE0 (64 bytes of ACPI registers) 629 * 0xE2 (32 bytes of SMB registers) 630 */ 631 static void quirk_ali7101_acpi(struct pci_dev *dev) 632 { 633 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 634 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 635 } 636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 637 638 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 639 { 640 u32 devres; 641 u32 mask, size, base; 642 643 pci_read_config_dword(dev, port, &devres); 644 if ((devres & enable) != enable) 645 return; 646 mask = (devres >> 16) & 15; 647 base = devres & 0xffff; 648 size = 16; 649 for (;;) { 650 unsigned bit = size >> 1; 651 if ((bit & mask) == bit) 652 break; 653 size = bit; 654 } 655 /* 656 * For now we only print it out. Eventually we'll want to 657 * reserve it (at least if it's in the 0x1000+ range), but 658 * let's get enough confirmation reports first. 659 */ 660 base &= -size; 661 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 662 } 663 664 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 665 { 666 u32 devres; 667 u32 mask, size, base; 668 669 pci_read_config_dword(dev, port, &devres); 670 if ((devres & enable) != enable) 671 return; 672 base = devres & 0xffff0000; 673 mask = (devres & 0x3f) << 16; 674 size = 128 << 16; 675 for (;;) { 676 unsigned bit = size >> 1; 677 if ((bit & mask) == bit) 678 break; 679 size = bit; 680 } 681 682 /* 683 * For now we only print it out. Eventually we'll want to 684 * reserve it, but let's get enough confirmation reports first. 685 */ 686 base &= -size; 687 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 688 } 689 690 /* 691 * PIIX4 ACPI: Two IO regions pointed to by longwords at 692 * 0x40 (64 bytes of ACPI registers) 693 * 0x90 (16 bytes of SMB registers) 694 * and a few strange programmable PIIX4 device resources. 695 */ 696 static void quirk_piix4_acpi(struct pci_dev *dev) 697 { 698 u32 res_a; 699 700 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 701 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 702 703 /* Device resource A has enables for some of the other ones */ 704 pci_read_config_dword(dev, 0x5c, &res_a); 705 706 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 707 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 708 709 /* Device resource D is just bitfields for static resources */ 710 711 /* Device 12 enabled? */ 712 if (res_a & (1 << 29)) { 713 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 714 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 715 } 716 /* Device 13 enabled? */ 717 if (res_a & (1 << 30)) { 718 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 719 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 720 } 721 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 722 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 723 } 724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 725 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 726 727 #define ICH_PMBASE 0x40 728 #define ICH_ACPI_CNTL 0x44 729 #define ICH4_ACPI_EN 0x10 730 #define ICH6_ACPI_EN 0x80 731 #define ICH4_GPIOBASE 0x58 732 #define ICH4_GPIO_CNTL 0x5c 733 #define ICH4_GPIO_EN 0x10 734 #define ICH6_GPIOBASE 0x48 735 #define ICH6_GPIO_CNTL 0x4c 736 #define ICH6_GPIO_EN 0x10 737 738 /* 739 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 740 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 741 * 0x58 (64 bytes of GPIO I/O space) 742 */ 743 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 744 { 745 u8 enable; 746 747 /* 748 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 749 * with low legacy (and fixed) ports. We don't know the decoding 750 * priority and can't tell whether the legacy device or the one created 751 * here is really at that address. This happens on boards with broken 752 * BIOSes. 753 */ 754 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 755 if (enable & ICH4_ACPI_EN) 756 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 757 "ICH4 ACPI/GPIO/TCO"); 758 759 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 760 if (enable & ICH4_GPIO_EN) 761 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 762 "ICH4 GPIO"); 763 } 764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 768 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 774 775 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 776 { 777 u8 enable; 778 779 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 780 if (enable & ICH6_ACPI_EN) 781 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 782 "ICH6 ACPI/GPIO/TCO"); 783 784 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 785 if (enable & ICH6_GPIO_EN) 786 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 787 "ICH6 GPIO"); 788 } 789 790 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 791 const char *name, int dynsize) 792 { 793 u32 val; 794 u32 size, base; 795 796 pci_read_config_dword(dev, reg, &val); 797 798 /* Enabled? */ 799 if (!(val & 1)) 800 return; 801 base = val & 0xfffc; 802 if (dynsize) { 803 /* 804 * This is not correct. It is 16, 32 or 64 bytes depending on 805 * register D31:F0:ADh bits 5:4. 806 * 807 * But this gets us at least _part_ of it. 808 */ 809 size = 16; 810 } else { 811 size = 128; 812 } 813 base &= ~(size-1); 814 815 /* 816 * Just print it out for now. We should reserve it after more 817 * debugging. 818 */ 819 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 820 } 821 822 static void quirk_ich6_lpc(struct pci_dev *dev) 823 { 824 /* Shared ACPI/GPIO decode with all ICH6+ */ 825 ich6_lpc_acpi_gpio(dev); 826 827 /* ICH6-specific generic IO decode */ 828 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 829 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 830 } 831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 833 834 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 835 const char *name) 836 { 837 u32 val; 838 u32 mask, base; 839 840 pci_read_config_dword(dev, reg, &val); 841 842 /* Enabled? */ 843 if (!(val & 1)) 844 return; 845 846 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 847 base = val & 0xfffc; 848 mask = (val >> 16) & 0xfc; 849 mask |= 3; 850 851 /* 852 * Just print it out for now. We should reserve it after more 853 * debugging. 854 */ 855 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 856 } 857 858 /* ICH7-10 has the same common LPC generic IO decode registers */ 859 static void quirk_ich7_lpc(struct pci_dev *dev) 860 { 861 /* We share the common ACPI/GPIO decode with ICH6 */ 862 ich6_lpc_acpi_gpio(dev); 863 864 /* And have 4 ICH7+ generic decodes */ 865 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 866 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 867 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 868 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 869 } 870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 883 884 /* 885 * VIA ACPI: One IO region pointed to by longword at 886 * 0x48 or 0x20 (256 bytes of ACPI registers) 887 */ 888 static void quirk_vt82c586_acpi(struct pci_dev *dev) 889 { 890 if (dev->revision & 0x10) 891 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 892 "vt82c586 ACPI"); 893 } 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 895 896 /* 897 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 898 * 0x48 (256 bytes of ACPI registers) 899 * 0x70 (128 bytes of hardware monitoring register) 900 * 0x90 (16 bytes of SMB registers) 901 */ 902 static void quirk_vt82c686_acpi(struct pci_dev *dev) 903 { 904 quirk_vt82c586_acpi(dev); 905 906 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 907 "vt82c686 HW-mon"); 908 909 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 910 } 911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 912 913 /* 914 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 915 * 0x88 (128 bytes of power management registers) 916 * 0xd0 (16 bytes of SMB registers) 917 */ 918 static void quirk_vt8235_acpi(struct pci_dev *dev) 919 { 920 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 921 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 922 } 923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 924 925 /* 926 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 927 * back-to-back: Disable fast back-to-back on the secondary bus segment 928 */ 929 static void quirk_xio2000a(struct pci_dev *dev) 930 { 931 struct pci_dev *pdev; 932 u16 command; 933 934 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 935 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 936 pci_read_config_word(pdev, PCI_COMMAND, &command); 937 if (command & PCI_COMMAND_FAST_BACK) 938 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 939 } 940 } 941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 942 quirk_xio2000a); 943 944 #ifdef CONFIG_X86_IO_APIC 945 946 #include <asm/io_apic.h> 947 948 /* 949 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 950 * devices to the external APIC. 951 * 952 * TODO: When we have device-specific interrupt routers, this code will go 953 * away from quirks. 954 */ 955 static void quirk_via_ioapic(struct pci_dev *dev) 956 { 957 u8 tmp; 958 959 if (nr_ioapics < 1) 960 tmp = 0; /* nothing routed to external APIC */ 961 else 962 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 963 964 pci_info(dev, "%sbling VIA external APIC routing\n", 965 tmp == 0 ? "Disa" : "Ena"); 966 967 /* Offset 0x58: External APIC IRQ output control */ 968 pci_write_config_byte(dev, 0x58, tmp); 969 } 970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 971 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 972 973 /* 974 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 975 * This leads to doubled level interrupt rates. 976 * Set this bit to get rid of cycle wastage. 977 * Otherwise uncritical. 978 */ 979 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 980 { 981 u8 misc_control2; 982 #define BYPASS_APIC_DEASSERT 8 983 984 pci_read_config_byte(dev, 0x5B, &misc_control2); 985 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 986 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 987 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 988 } 989 } 990 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 991 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 992 993 /* 994 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 995 * We check all revs >= B0 (yet not in the pre production!) as the bug 996 * is currently marked NoFix 997 * 998 * We have multiple reports of hangs with this chipset that went away with 999 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1000 * of course. However the advice is demonstrably good even if so. 1001 */ 1002 static void quirk_amd_ioapic(struct pci_dev *dev) 1003 { 1004 if (dev->revision >= 0x02) { 1005 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1006 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1007 } 1008 } 1009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1010 #endif /* CONFIG_X86_IO_APIC */ 1011 1012 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1013 1014 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1015 { 1016 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1017 if (dev->subsystem_device == 0xa118) 1018 dev->sriov->link = dev->devfn; 1019 } 1020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1021 #endif 1022 1023 /* 1024 * Some settings of MMRBC can lead to data corruption so block changes. 1025 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1026 */ 1027 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1028 { 1029 if (dev->subordinate && dev->revision <= 0x12) { 1030 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1031 dev->revision); 1032 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1033 } 1034 } 1035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1036 1037 /* 1038 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1039 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1040 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1041 * of the ACPI SCI interrupt is only done for convenience. 1042 * -jgarzik 1043 */ 1044 static void quirk_via_acpi(struct pci_dev *d) 1045 { 1046 u8 irq; 1047 1048 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1049 pci_read_config_byte(d, 0x42, &irq); 1050 irq &= 0xf; 1051 if (irq && (irq != 2)) 1052 d->irq = irq; 1053 } 1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1056 1057 /* VIA bridges which have VLink */ 1058 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1059 1060 static void quirk_via_bridge(struct pci_dev *dev) 1061 { 1062 /* See what bridge we have and find the device ranges */ 1063 switch (dev->device) { 1064 case PCI_DEVICE_ID_VIA_82C686: 1065 /* 1066 * The VT82C686 is special; it attaches to PCI and can have 1067 * any device number. All its subdevices are functions of 1068 * that single device. 1069 */ 1070 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1071 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1072 break; 1073 case PCI_DEVICE_ID_VIA_8237: 1074 case PCI_DEVICE_ID_VIA_8237A: 1075 via_vlink_dev_lo = 15; 1076 break; 1077 case PCI_DEVICE_ID_VIA_8235: 1078 via_vlink_dev_lo = 16; 1079 break; 1080 case PCI_DEVICE_ID_VIA_8231: 1081 case PCI_DEVICE_ID_VIA_8233_0: 1082 case PCI_DEVICE_ID_VIA_8233A: 1083 case PCI_DEVICE_ID_VIA_8233C_0: 1084 via_vlink_dev_lo = 17; 1085 break; 1086 } 1087 } 1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1096 1097 /* 1098 * quirk_via_vlink - VIA VLink IRQ number update 1099 * @dev: PCI device 1100 * 1101 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1102 * the IRQ line register which usually is not relevant for PCI cards, is 1103 * actually written so that interrupts get sent to the right place. 1104 * 1105 * We only do this on systems where a VIA south bridge was detected, and 1106 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1107 */ 1108 static void quirk_via_vlink(struct pci_dev *dev) 1109 { 1110 u8 irq, new_irq; 1111 1112 /* Check if we have VLink at all */ 1113 if (via_vlink_dev_lo == -1) 1114 return; 1115 1116 new_irq = dev->irq; 1117 1118 /* Don't quirk interrupts outside the legacy IRQ range */ 1119 if (!new_irq || new_irq > 15) 1120 return; 1121 1122 /* Internal device ? */ 1123 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1124 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1125 return; 1126 1127 /* 1128 * This is an internal VLink device on a PIC interrupt. The BIOS 1129 * ought to have set this but may not have, so we redo it. 1130 */ 1131 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1132 if (new_irq != irq) { 1133 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1134 irq, new_irq); 1135 udelay(15); /* unknown if delay really needed */ 1136 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1137 } 1138 } 1139 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1140 1141 /* 1142 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1143 * of VT82C597 for backward compatibility. We need to switch it off to be 1144 * able to recognize the real type of the chip. 1145 */ 1146 static void quirk_vt82c598_id(struct pci_dev *dev) 1147 { 1148 pci_write_config_byte(dev, 0xfc, 0); 1149 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1150 } 1151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1152 1153 /* 1154 * CardBus controllers have a legacy base address that enables them to 1155 * respond as i82365 pcmcia controllers. We don't want them to do this 1156 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1157 * driver does not (and should not) handle CardBus. 1158 */ 1159 static void quirk_cardbus_legacy(struct pci_dev *dev) 1160 { 1161 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1162 } 1163 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1164 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1165 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1166 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1167 1168 /* 1169 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1170 * what the designers were smoking but let's not inhale... 1171 * 1172 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1173 * turn it off! 1174 */ 1175 static void quirk_amd_ordering(struct pci_dev *dev) 1176 { 1177 u32 pcic; 1178 pci_read_config_dword(dev, 0x4C, &pcic); 1179 if ((pcic & 6) != 6) { 1180 pcic |= 6; 1181 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1182 pci_write_config_dword(dev, 0x4C, pcic); 1183 pci_read_config_dword(dev, 0x84, &pcic); 1184 pcic |= (1 << 23); /* Required in this mode */ 1185 pci_write_config_dword(dev, 0x84, pcic); 1186 } 1187 } 1188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1189 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1190 1191 /* 1192 * DreamWorks-provided workaround for Dunord I-3000 problem 1193 * 1194 * This card decodes and responds to addresses not apparently assigned to 1195 * it. We force a larger allocation to ensure that nothing gets put too 1196 * close to it. 1197 */ 1198 static void quirk_dunord(struct pci_dev *dev) 1199 { 1200 struct resource *r = &dev->resource[1]; 1201 1202 r->flags |= IORESOURCE_UNSET; 1203 r->start = 0; 1204 r->end = 0xffffff; 1205 } 1206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1207 1208 /* 1209 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1210 * decoding (transparent), and does indicate this in the ProgIf. 1211 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1212 */ 1213 static void quirk_transparent_bridge(struct pci_dev *dev) 1214 { 1215 dev->transparent = 1; 1216 } 1217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1219 1220 /* 1221 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1222 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1223 * found at http://www.national.com/analog for info on what these bits do. 1224 * <christer@weinigel.se> 1225 */ 1226 static void quirk_mediagx_master(struct pci_dev *dev) 1227 { 1228 u8 reg; 1229 1230 pci_read_config_byte(dev, 0x41, ®); 1231 if (reg & 2) { 1232 reg &= ~2; 1233 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1234 reg); 1235 pci_write_config_byte(dev, 0x41, reg); 1236 } 1237 } 1238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1240 1241 /* 1242 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1243 * in the odd case it is not the results are corruption hence the presence 1244 * of a Linux check. 1245 */ 1246 static void quirk_disable_pxb(struct pci_dev *pdev) 1247 { 1248 u16 config; 1249 1250 if (pdev->revision != 0x04) /* Only C0 requires this */ 1251 return; 1252 pci_read_config_word(pdev, 0x40, &config); 1253 if (config & (1<<6)) { 1254 config &= ~(1<<6); 1255 pci_write_config_word(pdev, 0x40, config); 1256 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1257 } 1258 } 1259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1260 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1261 1262 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1263 { 1264 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1265 u8 tmp; 1266 1267 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1268 if (tmp == 0x01) { 1269 pci_read_config_byte(pdev, 0x40, &tmp); 1270 pci_write_config_byte(pdev, 0x40, tmp|1); 1271 pci_write_config_byte(pdev, 0x9, 1); 1272 pci_write_config_byte(pdev, 0xa, 6); 1273 pci_write_config_byte(pdev, 0x40, tmp); 1274 1275 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1276 pci_info(pdev, "set SATA to AHCI mode\n"); 1277 } 1278 } 1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1280 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1282 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1284 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1286 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1287 1288 /* Serverworks CSB5 IDE does not fully support native mode */ 1289 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1290 { 1291 u8 prog; 1292 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1293 if (prog & 5) { 1294 prog &= ~5; 1295 pdev->class &= ~5; 1296 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1297 /* PCI layer will sort out resources */ 1298 } 1299 } 1300 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1301 1302 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1303 static void quirk_ide_samemode(struct pci_dev *pdev) 1304 { 1305 u8 prog; 1306 1307 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1308 1309 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1310 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1311 prog &= ~5; 1312 pdev->class &= ~5; 1313 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1314 } 1315 } 1316 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1317 1318 /* Some ATA devices break if put into D3 */ 1319 static void quirk_no_ata_d3(struct pci_dev *pdev) 1320 { 1321 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1322 } 1323 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1324 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1325 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1326 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1327 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1328 /* ALi loses some register settings that we cannot then restore */ 1329 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1330 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1331 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1332 occur when mode detecting */ 1333 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1334 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1335 1336 /* 1337 * This was originally an Alpha-specific thing, but it really fits here. 1338 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1339 */ 1340 static void quirk_eisa_bridge(struct pci_dev *dev) 1341 { 1342 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1343 } 1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1345 1346 /* 1347 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1348 * is not activated. The myth is that Asus said that they do not want the 1349 * users to be irritated by just another PCI Device in the Win98 device 1350 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1351 * package 2.7.0 for details) 1352 * 1353 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1354 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1355 * becomes necessary to do this tweak in two steps -- the chosen trigger 1356 * is either the Host bridge (preferred) or on-board VGA controller. 1357 * 1358 * Note that we used to unhide the SMBus that way on Toshiba laptops 1359 * (Satellite A40 and Tecra M2) but then found that the thermal management 1360 * was done by SMM code, which could cause unsynchronized concurrent 1361 * accesses to the SMBus registers, with potentially bad effects. Thus you 1362 * should be very careful when adding new entries: if SMM is accessing the 1363 * Intel SMBus, this is a very good reason to leave it hidden. 1364 * 1365 * Likewise, many recent laptops use ACPI for thermal management. If the 1366 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1367 * natively, and keeping the SMBus hidden is the right thing to do. If you 1368 * are about to add an entry in the table below, please first disassemble 1369 * the DSDT and double-check that there is no code accessing the SMBus. 1370 */ 1371 static int asus_hides_smbus; 1372 1373 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1374 { 1375 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1376 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1377 switch (dev->subsystem_device) { 1378 case 0x8025: /* P4B-LX */ 1379 case 0x8070: /* P4B */ 1380 case 0x8088: /* P4B533 */ 1381 case 0x1626: /* L3C notebook */ 1382 asus_hides_smbus = 1; 1383 } 1384 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1385 switch (dev->subsystem_device) { 1386 case 0x80b1: /* P4GE-V */ 1387 case 0x80b2: /* P4PE */ 1388 case 0x8093: /* P4B533-V */ 1389 asus_hides_smbus = 1; 1390 } 1391 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1392 switch (dev->subsystem_device) { 1393 case 0x8030: /* P4T533 */ 1394 asus_hides_smbus = 1; 1395 } 1396 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1397 switch (dev->subsystem_device) { 1398 case 0x8070: /* P4G8X Deluxe */ 1399 asus_hides_smbus = 1; 1400 } 1401 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1402 switch (dev->subsystem_device) { 1403 case 0x80c9: /* PU-DLS */ 1404 asus_hides_smbus = 1; 1405 } 1406 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1407 switch (dev->subsystem_device) { 1408 case 0x1751: /* M2N notebook */ 1409 case 0x1821: /* M5N notebook */ 1410 case 0x1897: /* A6L notebook */ 1411 asus_hides_smbus = 1; 1412 } 1413 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1414 switch (dev->subsystem_device) { 1415 case 0x184b: /* W1N notebook */ 1416 case 0x186a: /* M6Ne notebook */ 1417 asus_hides_smbus = 1; 1418 } 1419 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1420 switch (dev->subsystem_device) { 1421 case 0x80f2: /* P4P800-X */ 1422 asus_hides_smbus = 1; 1423 } 1424 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1425 switch (dev->subsystem_device) { 1426 case 0x1882: /* M6V notebook */ 1427 case 0x1977: /* A6VA notebook */ 1428 asus_hides_smbus = 1; 1429 } 1430 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1431 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1432 switch (dev->subsystem_device) { 1433 case 0x088C: /* HP Compaq nc8000 */ 1434 case 0x0890: /* HP Compaq nc6000 */ 1435 asus_hides_smbus = 1; 1436 } 1437 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1438 switch (dev->subsystem_device) { 1439 case 0x12bc: /* HP D330L */ 1440 case 0x12bd: /* HP D530 */ 1441 case 0x006a: /* HP Compaq nx9500 */ 1442 asus_hides_smbus = 1; 1443 } 1444 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1445 switch (dev->subsystem_device) { 1446 case 0x12bf: /* HP xw4100 */ 1447 asus_hides_smbus = 1; 1448 } 1449 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1450 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1451 switch (dev->subsystem_device) { 1452 case 0xC00C: /* Samsung P35 notebook */ 1453 asus_hides_smbus = 1; 1454 } 1455 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1456 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1457 switch (dev->subsystem_device) { 1458 case 0x0058: /* Compaq Evo N620c */ 1459 asus_hides_smbus = 1; 1460 } 1461 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1462 switch (dev->subsystem_device) { 1463 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1464 /* Motherboard doesn't have Host bridge 1465 * subvendor/subdevice IDs, therefore checking 1466 * its on-board VGA controller */ 1467 asus_hides_smbus = 1; 1468 } 1469 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1470 switch (dev->subsystem_device) { 1471 case 0x00b8: /* Compaq Evo D510 CMT */ 1472 case 0x00b9: /* Compaq Evo D510 SFF */ 1473 case 0x00ba: /* Compaq Evo D510 USDT */ 1474 /* Motherboard doesn't have Host bridge 1475 * subvendor/subdevice IDs and on-board VGA 1476 * controller is disabled if an AGP card is 1477 * inserted, therefore checking USB UHCI 1478 * Controller #1 */ 1479 asus_hides_smbus = 1; 1480 } 1481 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1482 switch (dev->subsystem_device) { 1483 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1484 /* Motherboard doesn't have host bridge 1485 * subvendor/subdevice IDs, therefore checking 1486 * its on-board VGA controller */ 1487 asus_hides_smbus = 1; 1488 } 1489 } 1490 } 1491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1501 1502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1505 1506 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1507 { 1508 u16 val; 1509 1510 if (likely(!asus_hides_smbus)) 1511 return; 1512 1513 pci_read_config_word(dev, 0xF2, &val); 1514 if (val & 0x8) { 1515 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1516 pci_read_config_word(dev, 0xF2, &val); 1517 if (val & 0x8) 1518 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1519 val); 1520 else 1521 pci_info(dev, "Enabled i801 SMBus device\n"); 1522 } 1523 } 1524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1532 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1535 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1536 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1537 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1538 1539 /* It appears we just have one such device. If not, we have a warning */ 1540 static void __iomem *asus_rcba_base; 1541 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1542 { 1543 u32 rcba; 1544 1545 if (likely(!asus_hides_smbus)) 1546 return; 1547 WARN_ON(asus_rcba_base); 1548 1549 pci_read_config_dword(dev, 0xF0, &rcba); 1550 /* use bits 31:14, 16 kB aligned */ 1551 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1552 if (asus_rcba_base == NULL) 1553 return; 1554 } 1555 1556 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1557 { 1558 u32 val; 1559 1560 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1561 return; 1562 1563 /* read the Function Disable register, dword mode only */ 1564 val = readl(asus_rcba_base + 0x3418); 1565 1566 /* enable the SMBus device */ 1567 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1568 } 1569 1570 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1571 { 1572 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1573 return; 1574 1575 iounmap(asus_rcba_base); 1576 asus_rcba_base = NULL; 1577 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1578 } 1579 1580 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1581 { 1582 asus_hides_smbus_lpc_ich6_suspend(dev); 1583 asus_hides_smbus_lpc_ich6_resume_early(dev); 1584 asus_hides_smbus_lpc_ich6_resume(dev); 1585 } 1586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1587 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1588 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1590 1591 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1592 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1593 { 1594 u8 val = 0; 1595 pci_read_config_byte(dev, 0x77, &val); 1596 if (val & 0x10) { 1597 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1598 pci_write_config_byte(dev, 0x77, val & ~0x10); 1599 } 1600 } 1601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1605 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1606 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1609 1610 /* 1611 * ... This is further complicated by the fact that some SiS96x south 1612 * bridges pretend to be 85C503/5513 instead. In that case see if we 1613 * spotted a compatible north bridge to make sure. 1614 * (pci_find_device() doesn't work yet) 1615 * 1616 * We can also enable the sis96x bit in the discovery register.. 1617 */ 1618 #define SIS_DETECT_REGISTER 0x40 1619 1620 static void quirk_sis_503(struct pci_dev *dev) 1621 { 1622 u8 reg; 1623 u16 devid; 1624 1625 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1626 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1627 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1628 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1629 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1630 return; 1631 } 1632 1633 /* 1634 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1635 * it has already been processed. (Depends on link order, which is 1636 * apparently not guaranteed) 1637 */ 1638 dev->device = devid; 1639 quirk_sis_96x_smbus(dev); 1640 } 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1642 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1643 1644 /* 1645 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1646 * and MC97 modem controller are disabled when a second PCI soundcard is 1647 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1648 * -- bjd 1649 */ 1650 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1651 { 1652 u8 val; 1653 int asus_hides_ac97 = 0; 1654 1655 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1656 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1657 asus_hides_ac97 = 1; 1658 } 1659 1660 if (!asus_hides_ac97) 1661 return; 1662 1663 pci_read_config_byte(dev, 0x50, &val); 1664 if (val & 0xc0) { 1665 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1666 pci_read_config_byte(dev, 0x50, &val); 1667 if (val & 0xc0) 1668 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1669 val); 1670 else 1671 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1672 } 1673 } 1674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1675 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1676 1677 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1678 1679 /* 1680 * If we are using libata we can drive this chip properly but must do this 1681 * early on to make the additional device appear during the PCI scanning. 1682 */ 1683 static void quirk_jmicron_ata(struct pci_dev *pdev) 1684 { 1685 u32 conf1, conf5, class; 1686 u8 hdr; 1687 1688 /* Only poke fn 0 */ 1689 if (PCI_FUNC(pdev->devfn)) 1690 return; 1691 1692 pci_read_config_dword(pdev, 0x40, &conf1); 1693 pci_read_config_dword(pdev, 0x80, &conf5); 1694 1695 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1696 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1697 1698 switch (pdev->device) { 1699 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1700 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1701 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1702 /* The controller should be in single function ahci mode */ 1703 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1704 break; 1705 1706 case PCI_DEVICE_ID_JMICRON_JMB365: 1707 case PCI_DEVICE_ID_JMICRON_JMB366: 1708 /* Redirect IDE second PATA port to the right spot */ 1709 conf5 |= (1 << 24); 1710 /* Fall through */ 1711 case PCI_DEVICE_ID_JMICRON_JMB361: 1712 case PCI_DEVICE_ID_JMICRON_JMB363: 1713 case PCI_DEVICE_ID_JMICRON_JMB369: 1714 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1715 /* Set the class codes correctly and then direct IDE 0 */ 1716 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1717 break; 1718 1719 case PCI_DEVICE_ID_JMICRON_JMB368: 1720 /* The controller should be in single function IDE mode */ 1721 conf1 |= 0x00C00000; /* Set 22, 23 */ 1722 break; 1723 } 1724 1725 pci_write_config_dword(pdev, 0x40, conf1); 1726 pci_write_config_dword(pdev, 0x80, conf5); 1727 1728 /* Update pdev accordingly */ 1729 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1730 pdev->hdr_type = hdr & 0x7f; 1731 pdev->multifunction = !!(hdr & 0x80); 1732 1733 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1734 pdev->class = class >> 8; 1735 } 1736 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1737 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1738 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1739 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1740 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1741 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1742 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1743 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1744 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1745 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1746 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1747 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1751 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1752 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1753 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1754 1755 #endif 1756 1757 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1758 { 1759 if (dev->multifunction) { 1760 device_disable_async_suspend(&dev->dev); 1761 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1762 } 1763 } 1764 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1765 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1767 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1768 1769 #ifdef CONFIG_X86_IO_APIC 1770 static void quirk_alder_ioapic(struct pci_dev *pdev) 1771 { 1772 int i; 1773 1774 if ((pdev->class >> 8) != 0xff00) 1775 return; 1776 1777 /* 1778 * The first BAR is the location of the IO-APIC... we must 1779 * not touch this (and it's already covered by the fixmap), so 1780 * forcibly insert it into the resource tree. 1781 */ 1782 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1783 insert_resource(&iomem_resource, &pdev->resource[0]); 1784 1785 /* 1786 * The next five BARs all seem to be rubbish, so just clean 1787 * them out. 1788 */ 1789 for (i = 1; i < 6; i++) 1790 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1791 } 1792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1793 #endif 1794 1795 static void quirk_pcie_mch(struct pci_dev *pdev) 1796 { 1797 pdev->no_msi = 1; 1798 } 1799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1802 1803 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1804 1805 /* 1806 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1807 * together on certain PXH-based systems. 1808 */ 1809 static void quirk_pcie_pxh(struct pci_dev *dev) 1810 { 1811 dev->no_msi = 1; 1812 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1813 } 1814 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1815 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1816 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1817 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1818 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1819 1820 /* 1821 * Some Intel PCI Express chipsets have trouble with downstream device 1822 * power management. 1823 */ 1824 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1825 { 1826 pci_pm_d3_delay = 120; 1827 dev->no_d1d2 = 1; 1828 } 1829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1850 1851 static void quirk_radeon_pm(struct pci_dev *dev) 1852 { 1853 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1854 dev->subsystem_device == 0x00e2) { 1855 if (dev->d3_delay < 20) { 1856 dev->d3_delay = 20; 1857 pci_info(dev, "extending delay after power-on from D3 to %d msec\n", 1858 dev->d3_delay); 1859 } 1860 } 1861 } 1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1863 1864 #ifdef CONFIG_X86_IO_APIC 1865 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1866 { 1867 noioapicreroute = 1; 1868 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1869 1870 return 0; 1871 } 1872 1873 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1874 /* 1875 * Systems to exclude from boot interrupt reroute quirks 1876 */ 1877 { 1878 .callback = dmi_disable_ioapicreroute, 1879 .ident = "ASUSTek Computer INC. M2N-LR", 1880 .matches = { 1881 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1882 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1883 }, 1884 }, 1885 {} 1886 }; 1887 1888 /* 1889 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1890 * remap the original interrupt in the Linux kernel to the boot interrupt, so 1891 * that a PCI device's interrupt handler is installed on the boot interrupt 1892 * line instead. 1893 */ 1894 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1895 { 1896 dmi_check_system(boot_interrupt_dmi_table); 1897 if (noioapicquirk || noioapicreroute) 1898 return; 1899 1900 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1901 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 1902 dev->vendor, dev->device); 1903 } 1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1912 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1913 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1914 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1915 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1916 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1917 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1918 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1919 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1920 1921 /* 1922 * On some chipsets we can disable the generation of legacy INTx boot 1923 * interrupts. 1924 */ 1925 1926 /* 1927 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 1928 * 300641-004US, section 5.7.3. 1929 */ 1930 #define INTEL_6300_IOAPIC_ABAR 0x40 1931 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1932 1933 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1934 { 1935 u16 pci_config_word; 1936 1937 if (noioapicquirk) 1938 return; 1939 1940 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1941 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1942 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1943 1944 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1945 dev->vendor, dev->device); 1946 } 1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1948 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1949 1950 /* Disable boot interrupts on HT-1000 */ 1951 #define BC_HT1000_FEATURE_REG 0x64 1952 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1953 #define BC_HT1000_MAP_IDX 0xC00 1954 #define BC_HT1000_MAP_DATA 0xC01 1955 1956 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1957 { 1958 u32 pci_config_dword; 1959 u8 irq; 1960 1961 if (noioapicquirk) 1962 return; 1963 1964 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1965 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1966 BC_HT1000_PIC_REGS_ENABLE); 1967 1968 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1969 outb(irq, BC_HT1000_MAP_IDX); 1970 outb(0x00, BC_HT1000_MAP_DATA); 1971 } 1972 1973 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1974 1975 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1976 dev->vendor, dev->device); 1977 } 1978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1979 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1980 1981 /* Disable boot interrupts on AMD and ATI chipsets */ 1982 1983 /* 1984 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1985 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1986 * (due to an erratum). 1987 */ 1988 #define AMD_813X_MISC 0x40 1989 #define AMD_813X_NOIOAMODE (1<<0) 1990 #define AMD_813X_REV_B1 0x12 1991 #define AMD_813X_REV_B2 0x13 1992 1993 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1994 { 1995 u32 pci_config_dword; 1996 1997 if (noioapicquirk) 1998 return; 1999 if ((dev->revision == AMD_813X_REV_B1) || 2000 (dev->revision == AMD_813X_REV_B2)) 2001 return; 2002 2003 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2004 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2005 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2006 2007 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2008 dev->vendor, dev->device); 2009 } 2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2011 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2013 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2014 2015 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2016 2017 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2018 { 2019 u16 pci_config_word; 2020 2021 if (noioapicquirk) 2022 return; 2023 2024 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2025 if (!pci_config_word) { 2026 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2027 dev->vendor, dev->device); 2028 return; 2029 } 2030 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2031 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2032 dev->vendor, dev->device); 2033 } 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2035 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2036 #endif /* CONFIG_X86_IO_APIC */ 2037 2038 /* 2039 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2040 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2041 * Re-allocate the region if needed... 2042 */ 2043 static void quirk_tc86c001_ide(struct pci_dev *dev) 2044 { 2045 struct resource *r = &dev->resource[0]; 2046 2047 if (r->start & 0x8) { 2048 r->flags |= IORESOURCE_UNSET; 2049 r->start = 0; 2050 r->end = 0xf; 2051 } 2052 } 2053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2054 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2055 quirk_tc86c001_ide); 2056 2057 /* 2058 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2059 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2060 * being read correctly if bit 7 of the base address is set. 2061 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2062 * Re-allocate the regions to a 256-byte boundary if necessary. 2063 */ 2064 static void quirk_plx_pci9050(struct pci_dev *dev) 2065 { 2066 unsigned int bar; 2067 2068 /* Fixed in revision 2 (PCI 9052). */ 2069 if (dev->revision >= 2) 2070 return; 2071 for (bar = 0; bar <= 1; bar++) 2072 if (pci_resource_len(dev, bar) == 0x80 && 2073 (pci_resource_start(dev, bar) & 0x80)) { 2074 struct resource *r = &dev->resource[bar]; 2075 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2076 bar); 2077 r->flags |= IORESOURCE_UNSET; 2078 r->start = 0; 2079 r->end = 0xff; 2080 } 2081 } 2082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2083 quirk_plx_pci9050); 2084 /* 2085 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2086 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2087 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2088 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2089 * 2090 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2091 * driver. 2092 */ 2093 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2094 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2095 2096 static void quirk_netmos(struct pci_dev *dev) 2097 { 2098 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2099 unsigned int num_serial = dev->subsystem_device & 0xf; 2100 2101 /* 2102 * These Netmos parts are multiport serial devices with optional 2103 * parallel ports. Even when parallel ports are present, they 2104 * are identified as class SERIAL, which means the serial driver 2105 * will claim them. To prevent this, mark them as class OTHER. 2106 * These combo devices should be claimed by parport_serial. 2107 * 2108 * The subdevice ID is of the form 0x00PS, where <P> is the number 2109 * of parallel ports and <S> is the number of serial ports. 2110 */ 2111 switch (dev->device) { 2112 case PCI_DEVICE_ID_NETMOS_9835: 2113 /* Well, this rule doesn't hold for the following 9835 device */ 2114 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2115 dev->subsystem_device == 0x0299) 2116 return; 2117 /* else: fall through */ 2118 case PCI_DEVICE_ID_NETMOS_9735: 2119 case PCI_DEVICE_ID_NETMOS_9745: 2120 case PCI_DEVICE_ID_NETMOS_9845: 2121 case PCI_DEVICE_ID_NETMOS_9855: 2122 if (num_parallel) { 2123 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2124 dev->device, num_parallel, num_serial); 2125 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2126 (dev->class & 0xff); 2127 } 2128 } 2129 } 2130 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2131 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2132 2133 static void quirk_e100_interrupt(struct pci_dev *dev) 2134 { 2135 u16 command, pmcsr; 2136 u8 __iomem *csr; 2137 u8 cmd_hi; 2138 2139 switch (dev->device) { 2140 /* PCI IDs taken from drivers/net/e100.c */ 2141 case 0x1029: 2142 case 0x1030 ... 0x1034: 2143 case 0x1038 ... 0x103E: 2144 case 0x1050 ... 0x1057: 2145 case 0x1059: 2146 case 0x1064 ... 0x106B: 2147 case 0x1091 ... 0x1095: 2148 case 0x1209: 2149 case 0x1229: 2150 case 0x2449: 2151 case 0x2459: 2152 case 0x245D: 2153 case 0x27DC: 2154 break; 2155 default: 2156 return; 2157 } 2158 2159 /* 2160 * Some firmware hands off the e100 with interrupts enabled, 2161 * which can cause a flood of interrupts if packets are 2162 * received before the driver attaches to the device. So 2163 * disable all e100 interrupts here. The driver will 2164 * re-enable them when it's ready. 2165 */ 2166 pci_read_config_word(dev, PCI_COMMAND, &command); 2167 2168 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2169 return; 2170 2171 /* 2172 * Check that the device is in the D0 power state. If it's not, 2173 * there is no point to look any further. 2174 */ 2175 if (dev->pm_cap) { 2176 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2177 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2178 return; 2179 } 2180 2181 /* Convert from PCI bus to resource space. */ 2182 csr = ioremap(pci_resource_start(dev, 0), 8); 2183 if (!csr) { 2184 pci_warn(dev, "Can't map e100 registers\n"); 2185 return; 2186 } 2187 2188 cmd_hi = readb(csr + 3); 2189 if (cmd_hi == 0) { 2190 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2191 writeb(1, csr + 3); 2192 } 2193 2194 iounmap(csr); 2195 } 2196 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2197 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2198 2199 /* 2200 * The 82575 and 82598 may experience data corruption issues when transitioning 2201 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2202 */ 2203 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2204 { 2205 pci_info(dev, "Disabling L0s\n"); 2206 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2207 } 2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2222 2223 static void fixup_rev1_53c810(struct pci_dev *dev) 2224 { 2225 u32 class = dev->class; 2226 2227 /* 2228 * rev 1 ncr53c810 chips don't set the class at all which means 2229 * they don't get their resources remapped. Fix that here. 2230 */ 2231 if (class) 2232 return; 2233 2234 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2235 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2236 class, dev->class); 2237 } 2238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2239 2240 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2241 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2242 { 2243 u16 en1k; 2244 2245 pci_read_config_word(dev, 0x40, &en1k); 2246 2247 if (en1k & 0x200) { 2248 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2249 dev->io_window_1k = 1; 2250 } 2251 } 2252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2253 2254 /* 2255 * Under some circumstances, AER is not linked with extended capabilities. 2256 * Force it to be linked by setting the corresponding control bit in the 2257 * config space. 2258 */ 2259 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2260 { 2261 uint8_t b; 2262 2263 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2264 if (!(b & 0x20)) { 2265 pci_write_config_byte(dev, 0xf41, b | 0x20); 2266 pci_info(dev, "Linking AER extended capability\n"); 2267 } 2268 } 2269 } 2270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2271 quirk_nvidia_ck804_pcie_aer_ext_cap); 2272 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2273 quirk_nvidia_ck804_pcie_aer_ext_cap); 2274 2275 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2276 { 2277 /* 2278 * Disable PCI Bus Parking and PCI Master read caching on CX700 2279 * which causes unspecified timing errors with a VT6212L on the PCI 2280 * bus leading to USB2.0 packet loss. 2281 * 2282 * This quirk is only enabled if a second (on the external PCI bus) 2283 * VT6212L is found -- the CX700 core itself also contains a USB 2284 * host controller with the same PCI ID as the VT6212L. 2285 */ 2286 2287 /* Count VT6212L instances */ 2288 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2289 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2290 uint8_t b; 2291 2292 /* 2293 * p should contain the first (internal) VT6212L -- see if we have 2294 * an external one by searching again. 2295 */ 2296 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2297 if (!p) 2298 return; 2299 pci_dev_put(p); 2300 2301 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2302 if (b & 0x40) { 2303 /* Turn off PCI Bus Parking */ 2304 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2305 2306 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2307 } 2308 } 2309 2310 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2311 if (b != 0) { 2312 /* Turn off PCI Master read caching */ 2313 pci_write_config_byte(dev, 0x72, 0x0); 2314 2315 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2316 pci_write_config_byte(dev, 0x75, 0x1); 2317 2318 /* Disable "Read FIFO Timer" */ 2319 pci_write_config_byte(dev, 0x77, 0x0); 2320 2321 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2322 } 2323 } 2324 } 2325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2326 2327 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2328 { 2329 u32 rev; 2330 2331 pci_read_config_dword(dev, 0xf4, &rev); 2332 2333 /* Only CAP the MRRS if the device is a 5719 A0 */ 2334 if (rev == 0x05719000) { 2335 int readrq = pcie_get_readrq(dev); 2336 if (readrq > 2048) 2337 pcie_set_readrq(dev, 2048); 2338 } 2339 } 2340 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2341 PCI_DEVICE_ID_TIGON3_5719, 2342 quirk_brcm_5719_limit_mrrs); 2343 2344 #ifdef CONFIG_PCIE_IPROC_PLATFORM 2345 static void quirk_paxc_bridge(struct pci_dev *pdev) 2346 { 2347 /* 2348 * The PCI config space is shared with the PAXC root port and the first 2349 * Ethernet device. So, we need to workaround this by telling the PCI 2350 * code that the bridge is not an Ethernet device. 2351 */ 2352 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2353 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2354 2355 /* 2356 * MPSS is not being set properly (as it is currently 0). This is 2357 * because that area of the PCI config space is hard coded to zero, and 2358 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2359 * so that the MPS can be set to the real max value. 2360 */ 2361 pdev->pcie_mpss = 2; 2362 } 2363 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); 2364 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2365 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge); 2366 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge); 2367 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge); 2368 #endif 2369 2370 /* 2371 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2372 * hide device 6 which configures the overflow device access containing the 2373 * DRBs - this is where we expose device 6. 2374 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2375 */ 2376 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2377 { 2378 u8 reg; 2379 2380 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2381 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2382 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2383 } 2384 } 2385 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2386 quirk_unhide_mch_dev6); 2387 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2388 quirk_unhide_mch_dev6); 2389 2390 #ifdef CONFIG_PCI_MSI 2391 /* 2392 * Some chipsets do not support MSI. We cannot easily rely on setting 2393 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2394 * other buses controlled by the chipset even if Linux is not aware of it. 2395 * Instead of setting the flag on all buses in the machine, simply disable 2396 * MSI globally. 2397 */ 2398 static void quirk_disable_all_msi(struct pci_dev *dev) 2399 { 2400 pci_no_msi(); 2401 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2402 } 2403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2411 2412 /* Disable MSI on chipsets that are known to not support it */ 2413 static void quirk_disable_msi(struct pci_dev *dev) 2414 { 2415 if (dev->subordinate) { 2416 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2417 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2418 } 2419 } 2420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2423 2424 /* 2425 * The APC bridge device in AMD 780 family northbridges has some random 2426 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2427 * we use the possible vendor/device IDs of the host bridge for the 2428 * declared quirk, and search for the APC bridge by slot number. 2429 */ 2430 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2431 { 2432 struct pci_dev *apc_bridge; 2433 2434 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2435 if (apc_bridge) { 2436 if (apc_bridge->device == 0x9602) 2437 quirk_disable_msi(apc_bridge); 2438 pci_dev_put(apc_bridge); 2439 } 2440 } 2441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2443 2444 /* 2445 * Go through the list of HyperTransport capabilities and return 1 if a HT 2446 * MSI capability is found and enabled. 2447 */ 2448 static int msi_ht_cap_enabled(struct pci_dev *dev) 2449 { 2450 int pos, ttl = PCI_FIND_CAP_TTL; 2451 2452 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2453 while (pos && ttl--) { 2454 u8 flags; 2455 2456 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2457 &flags) == 0) { 2458 pci_info(dev, "Found %s HT MSI Mapping\n", 2459 flags & HT_MSI_FLAGS_ENABLE ? 2460 "enabled" : "disabled"); 2461 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2462 } 2463 2464 pos = pci_find_next_ht_capability(dev, pos, 2465 HT_CAPTYPE_MSI_MAPPING); 2466 } 2467 return 0; 2468 } 2469 2470 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2471 static void quirk_msi_ht_cap(struct pci_dev *dev) 2472 { 2473 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2474 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2475 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2476 } 2477 } 2478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2479 quirk_msi_ht_cap); 2480 2481 /* 2482 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2483 * if the MSI capability is set in any of these mappings. 2484 */ 2485 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2486 { 2487 struct pci_dev *pdev; 2488 2489 if (!dev->subordinate) 2490 return; 2491 2492 /* 2493 * Check HT MSI cap on this chipset and the root one. A single one 2494 * having MSI is enough to be sure that MSI is supported. 2495 */ 2496 pdev = pci_get_slot(dev->bus, 0); 2497 if (!pdev) 2498 return; 2499 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2500 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2501 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2502 } 2503 pci_dev_put(pdev); 2504 } 2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2506 quirk_nvidia_ck804_msi_ht_cap); 2507 2508 /* Force enable MSI mapping capability on HT bridges */ 2509 static void ht_enable_msi_mapping(struct pci_dev *dev) 2510 { 2511 int pos, ttl = PCI_FIND_CAP_TTL; 2512 2513 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2514 while (pos && ttl--) { 2515 u8 flags; 2516 2517 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2518 &flags) == 0) { 2519 pci_info(dev, "Enabling HT MSI Mapping\n"); 2520 2521 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2522 flags | HT_MSI_FLAGS_ENABLE); 2523 } 2524 pos = pci_find_next_ht_capability(dev, pos, 2525 HT_CAPTYPE_MSI_MAPPING); 2526 } 2527 } 2528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2529 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2530 ht_enable_msi_mapping); 2531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2532 ht_enable_msi_mapping); 2533 2534 /* 2535 * The P5N32-SLI motherboards from Asus have a problem with MSI 2536 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2537 * also affects other devices. As for now, turn off MSI for this device. 2538 */ 2539 static void nvenet_msi_disable(struct pci_dev *dev) 2540 { 2541 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2542 2543 if (board_name && 2544 (strstr(board_name, "P5N32-SLI PREMIUM") || 2545 strstr(board_name, "P5N32-E SLI"))) { 2546 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2547 dev->no_msi = 1; 2548 } 2549 } 2550 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2551 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2552 nvenet_msi_disable); 2553 2554 /* 2555 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2556 * config register. This register controls the routing of legacy 2557 * interrupts from devices that route through the MCP55. If this register 2558 * is misprogrammed, interrupts are only sent to the BSP, unlike 2559 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2560 * having this register set properly prevents kdump from booting up 2561 * properly, so let's make sure that we have it set correctly. 2562 * Note that this is an undocumented register. 2563 */ 2564 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2565 { 2566 u32 cfg; 2567 2568 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2569 return; 2570 2571 pci_read_config_dword(dev, 0x74, &cfg); 2572 2573 if (cfg & ((1 << 2) | (1 << 15))) { 2574 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n"); 2575 cfg &= ~((1 << 2) | (1 << 15)); 2576 pci_write_config_dword(dev, 0x74, cfg); 2577 } 2578 } 2579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2580 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2581 nvbridge_check_legacy_irq_routing); 2582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2583 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2584 nvbridge_check_legacy_irq_routing); 2585 2586 static int ht_check_msi_mapping(struct pci_dev *dev) 2587 { 2588 int pos, ttl = PCI_FIND_CAP_TTL; 2589 int found = 0; 2590 2591 /* Check if there is HT MSI cap or enabled on this device */ 2592 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2593 while (pos && ttl--) { 2594 u8 flags; 2595 2596 if (found < 1) 2597 found = 1; 2598 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2599 &flags) == 0) { 2600 if (flags & HT_MSI_FLAGS_ENABLE) { 2601 if (found < 2) { 2602 found = 2; 2603 break; 2604 } 2605 } 2606 } 2607 pos = pci_find_next_ht_capability(dev, pos, 2608 HT_CAPTYPE_MSI_MAPPING); 2609 } 2610 2611 return found; 2612 } 2613 2614 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2615 { 2616 struct pci_dev *dev; 2617 int pos; 2618 int i, dev_no; 2619 int found = 0; 2620 2621 dev_no = host_bridge->devfn >> 3; 2622 for (i = dev_no + 1; i < 0x20; i++) { 2623 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2624 if (!dev) 2625 continue; 2626 2627 /* found next host bridge? */ 2628 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2629 if (pos != 0) { 2630 pci_dev_put(dev); 2631 break; 2632 } 2633 2634 if (ht_check_msi_mapping(dev)) { 2635 found = 1; 2636 pci_dev_put(dev); 2637 break; 2638 } 2639 pci_dev_put(dev); 2640 } 2641 2642 return found; 2643 } 2644 2645 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2646 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2647 2648 static int is_end_of_ht_chain(struct pci_dev *dev) 2649 { 2650 int pos, ctrl_off; 2651 int end = 0; 2652 u16 flags, ctrl; 2653 2654 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2655 2656 if (!pos) 2657 goto out; 2658 2659 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2660 2661 ctrl_off = ((flags >> 10) & 1) ? 2662 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2663 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2664 2665 if (ctrl & (1 << 6)) 2666 end = 1; 2667 2668 out: 2669 return end; 2670 } 2671 2672 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2673 { 2674 struct pci_dev *host_bridge; 2675 int pos; 2676 int i, dev_no; 2677 int found = 0; 2678 2679 dev_no = dev->devfn >> 3; 2680 for (i = dev_no; i >= 0; i--) { 2681 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2682 if (!host_bridge) 2683 continue; 2684 2685 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2686 if (pos != 0) { 2687 found = 1; 2688 break; 2689 } 2690 pci_dev_put(host_bridge); 2691 } 2692 2693 if (!found) 2694 return; 2695 2696 /* don't enable end_device/host_bridge with leaf directly here */ 2697 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2698 host_bridge_with_leaf(host_bridge)) 2699 goto out; 2700 2701 /* root did that ! */ 2702 if (msi_ht_cap_enabled(host_bridge)) 2703 goto out; 2704 2705 ht_enable_msi_mapping(dev); 2706 2707 out: 2708 pci_dev_put(host_bridge); 2709 } 2710 2711 static void ht_disable_msi_mapping(struct pci_dev *dev) 2712 { 2713 int pos, ttl = PCI_FIND_CAP_TTL; 2714 2715 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2716 while (pos && ttl--) { 2717 u8 flags; 2718 2719 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2720 &flags) == 0) { 2721 pci_info(dev, "Disabling HT MSI Mapping\n"); 2722 2723 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2724 flags & ~HT_MSI_FLAGS_ENABLE); 2725 } 2726 pos = pci_find_next_ht_capability(dev, pos, 2727 HT_CAPTYPE_MSI_MAPPING); 2728 } 2729 } 2730 2731 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2732 { 2733 struct pci_dev *host_bridge; 2734 int pos; 2735 int found; 2736 2737 if (!pci_msi_enabled()) 2738 return; 2739 2740 /* check if there is HT MSI cap or enabled on this device */ 2741 found = ht_check_msi_mapping(dev); 2742 2743 /* no HT MSI CAP */ 2744 if (found == 0) 2745 return; 2746 2747 /* 2748 * HT MSI mapping should be disabled on devices that are below 2749 * a non-Hypertransport host bridge. Locate the host bridge... 2750 */ 2751 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2752 PCI_DEVFN(0, 0)); 2753 if (host_bridge == NULL) { 2754 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2755 return; 2756 } 2757 2758 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2759 if (pos != 0) { 2760 /* Host bridge is to HT */ 2761 if (found == 1) { 2762 /* it is not enabled, try to enable it */ 2763 if (all) 2764 ht_enable_msi_mapping(dev); 2765 else 2766 nv_ht_enable_msi_mapping(dev); 2767 } 2768 goto out; 2769 } 2770 2771 /* HT MSI is not enabled */ 2772 if (found == 1) 2773 goto out; 2774 2775 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2776 ht_disable_msi_mapping(dev); 2777 2778 out: 2779 pci_dev_put(host_bridge); 2780 } 2781 2782 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2783 { 2784 return __nv_msi_ht_cap_quirk(dev, 1); 2785 } 2786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2787 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2788 2789 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2790 { 2791 return __nv_msi_ht_cap_quirk(dev, 0); 2792 } 2793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2794 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2795 2796 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2797 { 2798 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2799 } 2800 2801 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2802 { 2803 struct pci_dev *p; 2804 2805 /* 2806 * SB700 MSI issue will be fixed at HW level from revision A21; 2807 * we need check PCI REVISION ID of SMBus controller to get SB700 2808 * revision. 2809 */ 2810 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2811 NULL); 2812 if (!p) 2813 return; 2814 2815 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2816 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2817 pci_dev_put(p); 2818 } 2819 2820 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2821 { 2822 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2823 if (dev->revision < 0x18) { 2824 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2825 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2826 } 2827 } 2828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2829 PCI_DEVICE_ID_TIGON3_5780, 2830 quirk_msi_intx_disable_bug); 2831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2832 PCI_DEVICE_ID_TIGON3_5780S, 2833 quirk_msi_intx_disable_bug); 2834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2835 PCI_DEVICE_ID_TIGON3_5714, 2836 quirk_msi_intx_disable_bug); 2837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2838 PCI_DEVICE_ID_TIGON3_5714S, 2839 quirk_msi_intx_disable_bug); 2840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2841 PCI_DEVICE_ID_TIGON3_5715, 2842 quirk_msi_intx_disable_bug); 2843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2844 PCI_DEVICE_ID_TIGON3_5715S, 2845 quirk_msi_intx_disable_bug); 2846 2847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2848 quirk_msi_intx_disable_ati_bug); 2849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2850 quirk_msi_intx_disable_ati_bug); 2851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2852 quirk_msi_intx_disable_ati_bug); 2853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2854 quirk_msi_intx_disable_ati_bug); 2855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2856 quirk_msi_intx_disable_ati_bug); 2857 2858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2859 quirk_msi_intx_disable_bug); 2860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2861 quirk_msi_intx_disable_bug); 2862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2863 quirk_msi_intx_disable_bug); 2864 2865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2866 quirk_msi_intx_disable_bug); 2867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2868 quirk_msi_intx_disable_bug); 2869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2870 quirk_msi_intx_disable_bug); 2871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2872 quirk_msi_intx_disable_bug); 2873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2874 quirk_msi_intx_disable_bug); 2875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2876 quirk_msi_intx_disable_bug); 2877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2878 quirk_msi_intx_disable_qca_bug); 2879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2880 quirk_msi_intx_disable_qca_bug); 2881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2882 quirk_msi_intx_disable_qca_bug); 2883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2884 quirk_msi_intx_disable_qca_bug); 2885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2886 quirk_msi_intx_disable_qca_bug); 2887 #endif /* CONFIG_PCI_MSI */ 2888 2889 /* 2890 * Allow manual resource allocation for PCI hotplug bridges via 2891 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 2892 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 2893 * allocate resources when hotplug device is inserted and PCI bus is 2894 * rescanned. 2895 */ 2896 static void quirk_hotplug_bridge(struct pci_dev *dev) 2897 { 2898 dev->is_hotplug_bridge = 1; 2899 } 2900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2901 2902 /* 2903 * This is a quirk for the Ricoh MMC controller found as a part of some 2904 * multifunction chips. 2905 * 2906 * This is very similar and based on the ricoh_mmc driver written by 2907 * Philip Langdale. Thank you for these magic sequences. 2908 * 2909 * These chips implement the four main memory card controllers (SD, MMC, 2910 * MS, xD) and one or both of CardBus or FireWire. 2911 * 2912 * It happens that they implement SD and MMC support as separate 2913 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 2914 * cards but the chip detects MMC cards in hardware and directs them to the 2915 * MMC controller - so the SDHCI driver never sees them. 2916 * 2917 * To get around this, we must disable the useless MMC controller. At that 2918 * point, the SDHCI controller will start seeing them. It seems to be the 2919 * case that the relevant PCI registers to deactivate the MMC controller 2920 * live on PCI function 0, which might be the CardBus controller or the 2921 * FireWire controller, depending on the particular chip in question 2922 * 2923 * This has to be done early, because as soon as we disable the MMC controller 2924 * other PCI functions shift up one level, e.g. function #2 becomes function 2925 * #1, and this will confuse the PCI core. 2926 */ 2927 #ifdef CONFIG_MMC_RICOH_MMC 2928 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2929 { 2930 u8 write_enable; 2931 u8 write_target; 2932 u8 disable; 2933 2934 /* 2935 * Disable via CardBus interface 2936 * 2937 * This must be done via function #0 2938 */ 2939 if (PCI_FUNC(dev->devfn)) 2940 return; 2941 2942 pci_read_config_byte(dev, 0xB7, &disable); 2943 if (disable & 0x02) 2944 return; 2945 2946 pci_read_config_byte(dev, 0x8E, &write_enable); 2947 pci_write_config_byte(dev, 0x8E, 0xAA); 2948 pci_read_config_byte(dev, 0x8D, &write_target); 2949 pci_write_config_byte(dev, 0x8D, 0xB7); 2950 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2951 pci_write_config_byte(dev, 0x8E, write_enable); 2952 pci_write_config_byte(dev, 0x8D, write_target); 2953 2954 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 2955 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2956 } 2957 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2958 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2959 2960 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2961 { 2962 u8 write_enable; 2963 u8 disable; 2964 2965 /* 2966 * Disable via FireWire interface 2967 * 2968 * This must be done via function #0 2969 */ 2970 if (PCI_FUNC(dev->devfn)) 2971 return; 2972 /* 2973 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2974 * certain types of SD/MMC cards. Lowering the SD base clock 2975 * frequency from 200Mhz to 50Mhz fixes this issue. 2976 * 2977 * 0x150 - SD2.0 mode enable for changing base clock 2978 * frequency to 50Mhz 2979 * 0xe1 - Base clock frequency 2980 * 0x32 - 50Mhz new clock frequency 2981 * 0xf9 - Key register for 0x150 2982 * 0xfc - key register for 0xe1 2983 */ 2984 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2985 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2986 pci_write_config_byte(dev, 0xf9, 0xfc); 2987 pci_write_config_byte(dev, 0x150, 0x10); 2988 pci_write_config_byte(dev, 0xf9, 0x00); 2989 pci_write_config_byte(dev, 0xfc, 0x01); 2990 pci_write_config_byte(dev, 0xe1, 0x32); 2991 pci_write_config_byte(dev, 0xfc, 0x00); 2992 2993 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 2994 } 2995 2996 pci_read_config_byte(dev, 0xCB, &disable); 2997 2998 if (disable & 0x02) 2999 return; 3000 3001 pci_read_config_byte(dev, 0xCA, &write_enable); 3002 pci_write_config_byte(dev, 0xCA, 0x57); 3003 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3004 pci_write_config_byte(dev, 0xCA, write_enable); 3005 3006 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3007 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3008 3009 } 3010 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3011 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3012 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3013 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3014 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3015 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3016 #endif /*CONFIG_MMC_RICOH_MMC*/ 3017 3018 #ifdef CONFIG_DMAR_TABLE 3019 #define VTUNCERRMSK_REG 0x1ac 3020 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3021 /* 3022 * This is a quirk for masking VT-d spec-defined errors to platform error 3023 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3024 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3025 * on the RAS config settings of the platform) when a VT-d fault happens. 3026 * The resulting SMI caused the system to hang. 3027 * 3028 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3029 * need to report the same error through other channels. 3030 */ 3031 static void vtd_mask_spec_errors(struct pci_dev *dev) 3032 { 3033 u32 word; 3034 3035 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3036 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3037 } 3038 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3039 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3040 #endif 3041 3042 static void fixup_ti816x_class(struct pci_dev *dev) 3043 { 3044 u32 class = dev->class; 3045 3046 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3047 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3048 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3049 class, dev->class); 3050 } 3051 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3052 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3053 3054 /* 3055 * Some PCIe devices do not work reliably with the claimed maximum 3056 * payload size supported. 3057 */ 3058 static void fixup_mpss_256(struct pci_dev *dev) 3059 { 3060 dev->pcie_mpss = 1; /* 256 bytes */ 3061 } 3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3063 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3065 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3067 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3068 3069 /* 3070 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3071 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3072 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3073 * until all of the devices are discovered and buses walked, read completion 3074 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3075 * it is possible to hotplug a device with MPS of 256B. 3076 */ 3077 static void quirk_intel_mc_errata(struct pci_dev *dev) 3078 { 3079 int err; 3080 u16 rcc; 3081 3082 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3083 pcie_bus_config == PCIE_BUS_DEFAULT) 3084 return; 3085 3086 /* 3087 * Intel erratum specifies bits to change but does not say what 3088 * they are. Keeping them magical until such time as the registers 3089 * and values can be explained. 3090 */ 3091 err = pci_read_config_word(dev, 0x48, &rcc); 3092 if (err) { 3093 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3094 return; 3095 } 3096 3097 if (!(rcc & (1 << 10))) 3098 return; 3099 3100 rcc &= ~(1 << 10); 3101 3102 err = pci_write_config_word(dev, 0x48, rcc); 3103 if (err) { 3104 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3105 return; 3106 } 3107 3108 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3109 } 3110 /* Intel 5000 series memory controllers and ports 2-7 */ 3111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3125 /* Intel 5100 series memory controllers and ports 2-7 */ 3126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3137 3138 /* 3139 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3140 * To work around this, query the size it should be configured to by the 3141 * device and modify the resource end to correspond to this new size. 3142 */ 3143 static void quirk_intel_ntb(struct pci_dev *dev) 3144 { 3145 int rc; 3146 u8 val; 3147 3148 rc = pci_read_config_byte(dev, 0x00D0, &val); 3149 if (rc) 3150 return; 3151 3152 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3153 3154 rc = pci_read_config_byte(dev, 0x00D1, &val); 3155 if (rc) 3156 return; 3157 3158 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3159 } 3160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3162 3163 /* 3164 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3165 * though no one is handling them (e.g., if the i915 driver is never 3166 * loaded). Additionally the interrupt destination is not set up properly 3167 * and the interrupt ends up -somewhere-. 3168 * 3169 * These spurious interrupts are "sticky" and the kernel disables the 3170 * (shared) interrupt line after 100,000+ generated interrupts. 3171 * 3172 * Fix it by disabling the still enabled interrupts. This resolves crashes 3173 * often seen on monitor unplug. 3174 */ 3175 #define I915_DEIER_REG 0x4400c 3176 static void disable_igfx_irq(struct pci_dev *dev) 3177 { 3178 void __iomem *regs = pci_iomap(dev, 0, 0); 3179 if (regs == NULL) { 3180 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3181 return; 3182 } 3183 3184 /* Check if any interrupt line is still enabled */ 3185 if (readl(regs + I915_DEIER_REG) != 0) { 3186 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3187 3188 writel(0, regs + I915_DEIER_REG); 3189 } 3190 3191 pci_iounmap(dev, regs); 3192 } 3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3196 3197 /* 3198 * PCI devices which are on Intel chips can skip the 10ms delay 3199 * before entering D3 mode. 3200 */ 3201 static void quirk_remove_d3_delay(struct pci_dev *dev) 3202 { 3203 dev->d3_delay = 0; 3204 } 3205 /* C600 Series devices do not need 10ms d3_delay */ 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3209 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ 3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3221 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3231 3232 /* 3233 * Some devices may pass our check in pci_intx_mask_supported() if 3234 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3235 * support this feature. 3236 */ 3237 static void quirk_broken_intx_masking(struct pci_dev *dev) 3238 { 3239 dev->broken_intx_masking = 1; 3240 } 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3242 quirk_broken_intx_masking); 3243 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3244 quirk_broken_intx_masking); 3245 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3246 quirk_broken_intx_masking); 3247 3248 /* 3249 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3250 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3251 * 3252 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3253 */ 3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3255 quirk_broken_intx_masking); 3256 3257 /* 3258 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3259 * DisINTx can be set but the interrupt status bit is non-functional. 3260 */ 3261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3277 3278 static u16 mellanox_broken_intx_devs[] = { 3279 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3280 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3281 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3282 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3283 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3284 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3285 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3286 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3287 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3288 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3289 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3290 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3291 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3292 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3293 }; 3294 3295 #define CONNECTX_4_CURR_MAX_MINOR 99 3296 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3297 3298 /* 3299 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3300 * If so, don't mark it as broken. 3301 * FW minor > 99 means older FW version format and no INTx masking support. 3302 * FW minor < 14 means new FW version format and no INTx masking support. 3303 */ 3304 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3305 { 3306 __be32 __iomem *fw_ver; 3307 u16 fw_major; 3308 u16 fw_minor; 3309 u16 fw_subminor; 3310 u32 fw_maj_min; 3311 u32 fw_sub_min; 3312 int i; 3313 3314 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3315 if (pdev->device == mellanox_broken_intx_devs[i]) { 3316 pdev->broken_intx_masking = 1; 3317 return; 3318 } 3319 } 3320 3321 /* 3322 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3323 * support so shouldn't be checked further 3324 */ 3325 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3326 return; 3327 3328 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3329 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3330 return; 3331 3332 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3333 if (pci_enable_device_mem(pdev)) { 3334 pci_warn(pdev, "Can't enable device memory\n"); 3335 return; 3336 } 3337 3338 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3339 if (!fw_ver) { 3340 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3341 goto out; 3342 } 3343 3344 /* Reading from resource space should be 32b aligned */ 3345 fw_maj_min = ioread32be(fw_ver); 3346 fw_sub_min = ioread32be(fw_ver + 1); 3347 fw_major = fw_maj_min & 0xffff; 3348 fw_minor = fw_maj_min >> 16; 3349 fw_subminor = fw_sub_min & 0xffff; 3350 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3351 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3352 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3353 fw_major, fw_minor, fw_subminor, pdev->device == 3354 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3355 pdev->broken_intx_masking = 1; 3356 } 3357 3358 iounmap(fw_ver); 3359 3360 out: 3361 pci_disable_device(pdev); 3362 } 3363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3364 mellanox_check_broken_intx_masking); 3365 3366 static void quirk_no_bus_reset(struct pci_dev *dev) 3367 { 3368 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3369 } 3370 3371 /* 3372 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3373 * The device will throw a Link Down error on AER-capable systems and 3374 * regardless of AER, config space of the device is never accessible again 3375 * and typically causes the system to hang or reset when access is attempted. 3376 * http://www.spinics.net/lists/linux-pci/msg34797.html 3377 */ 3378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3382 3383 /* 3384 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3385 * reset when used with certain child devices. After the reset, config 3386 * accesses to the child may fail. 3387 */ 3388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3389 3390 static void quirk_no_pm_reset(struct pci_dev *dev) 3391 { 3392 /* 3393 * We can't do a bus reset on root bus devices, but an ineffective 3394 * PM reset may be better than nothing. 3395 */ 3396 if (!pci_is_root_bus(dev->bus)) 3397 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3398 } 3399 3400 /* 3401 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3402 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3403 * to have no effect on the device: it retains the framebuffer contents and 3404 * monitor sync. Advertising this support makes other layers, like VFIO, 3405 * assume pci_reset_function() is viable for this device. Mark it as 3406 * unavailable to skip it when testing reset methods. 3407 */ 3408 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3409 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3410 3411 /* 3412 * Thunderbolt controllers with broken MSI hotplug signaling: 3413 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3414 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3415 */ 3416 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3417 { 3418 if (pdev->is_hotplug_bridge && 3419 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3420 pdev->revision <= 1)) 3421 pdev->no_msi = 1; 3422 } 3423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3424 quirk_thunderbolt_hotplug_msi); 3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3426 quirk_thunderbolt_hotplug_msi); 3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3428 quirk_thunderbolt_hotplug_msi); 3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3430 quirk_thunderbolt_hotplug_msi); 3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3432 quirk_thunderbolt_hotplug_msi); 3433 3434 #ifdef CONFIG_ACPI 3435 /* 3436 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3437 * 3438 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3439 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3440 * be present after resume if a device was plugged in before suspend. 3441 * 3442 * The Thunderbolt controller consists of a PCIe switch with downstream 3443 * bridges leading to the NHI and to the tunnel PCI bridges. 3444 * 3445 * This quirk cuts power to the whole chip. Therefore we have to apply it 3446 * during suspend_noirq of the upstream bridge. 3447 * 3448 * Power is automagically restored before resume. No action is needed. 3449 */ 3450 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3451 { 3452 acpi_handle bridge, SXIO, SXFP, SXLV; 3453 3454 if (!x86_apple_machine) 3455 return; 3456 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3457 return; 3458 bridge = ACPI_HANDLE(&dev->dev); 3459 if (!bridge) 3460 return; 3461 3462 /* 3463 * SXIO and SXLV are present only on machines requiring this quirk. 3464 * Thunderbolt bridges in external devices might have the same 3465 * device ID as those on the host, but they will not have the 3466 * associated ACPI methods. This implicitly checks that we are at 3467 * the right bridge. 3468 */ 3469 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3470 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3471 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3472 return; 3473 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3474 3475 /* magic sequence */ 3476 acpi_execute_simple_method(SXIO, NULL, 1); 3477 acpi_execute_simple_method(SXFP, NULL, 0); 3478 msleep(300); 3479 acpi_execute_simple_method(SXLV, NULL, 0); 3480 acpi_execute_simple_method(SXIO, NULL, 0); 3481 acpi_execute_simple_method(SXLV, NULL, 0); 3482 } 3483 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3484 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3485 quirk_apple_poweroff_thunderbolt); 3486 3487 /* 3488 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels 3489 * 3490 * During suspend the Thunderbolt controller is reset and all PCI 3491 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3492 * during resume. We have to manually wait for the NHI since there is 3493 * no parent child relationship between the NHI and the tunneled 3494 * bridges. 3495 */ 3496 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3497 { 3498 struct pci_dev *sibling = NULL; 3499 struct pci_dev *nhi = NULL; 3500 3501 if (!x86_apple_machine) 3502 return; 3503 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3504 return; 3505 3506 /* 3507 * Find the NHI and confirm that we are a bridge on the Thunderbolt 3508 * host controller and not on a Thunderbolt endpoint. 3509 */ 3510 sibling = pci_get_slot(dev->bus, 0x0); 3511 if (sibling == dev) 3512 goto out; /* we are the downstream bridge to the NHI */ 3513 if (!sibling || !sibling->subordinate) 3514 goto out; 3515 nhi = pci_get_slot(sibling->subordinate, 0x0); 3516 if (!nhi) 3517 goto out; 3518 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3519 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && 3520 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && 3521 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && 3522 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3523 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3524 goto out; 3525 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n"); 3526 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3527 out: 3528 pci_dev_put(nhi); 3529 pci_dev_put(sibling); 3530 } 3531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3532 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3533 quirk_apple_wait_for_thunderbolt); 3534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3535 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3536 quirk_apple_wait_for_thunderbolt); 3537 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3538 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, 3539 quirk_apple_wait_for_thunderbolt); 3540 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3541 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, 3542 quirk_apple_wait_for_thunderbolt); 3543 #endif 3544 3545 /* 3546 * Following are device-specific reset methods which can be used to 3547 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3548 * not available. 3549 */ 3550 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3551 { 3552 /* 3553 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3554 * 3555 * The 82599 supports FLR on VFs, but FLR support is reported only 3556 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3557 * Thus we must call pcie_flr() directly without first checking if it is 3558 * supported. 3559 */ 3560 if (!probe) 3561 pcie_flr(dev); 3562 return 0; 3563 } 3564 3565 #define SOUTH_CHICKEN2 0xc2004 3566 #define PCH_PP_STATUS 0xc7200 3567 #define PCH_PP_CONTROL 0xc7204 3568 #define MSG_CTL 0x45010 3569 #define NSDE_PWR_STATE 0xd0100 3570 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3571 3572 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3573 { 3574 void __iomem *mmio_base; 3575 unsigned long timeout; 3576 u32 val; 3577 3578 if (probe) 3579 return 0; 3580 3581 mmio_base = pci_iomap(dev, 0, 0); 3582 if (!mmio_base) 3583 return -ENOMEM; 3584 3585 iowrite32(0x00000002, mmio_base + MSG_CTL); 3586 3587 /* 3588 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3589 * driver loaded sets the right bits. However, this's a reset and 3590 * the bits have been set by i915 previously, so we clobber 3591 * SOUTH_CHICKEN2 register directly here. 3592 */ 3593 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3594 3595 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3596 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3597 3598 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3599 do { 3600 val = ioread32(mmio_base + PCH_PP_STATUS); 3601 if ((val & 0xb0000000) == 0) 3602 goto reset_complete; 3603 msleep(10); 3604 } while (time_before(jiffies, timeout)); 3605 pci_warn(dev, "timeout during reset\n"); 3606 3607 reset_complete: 3608 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3609 3610 pci_iounmap(dev, mmio_base); 3611 return 0; 3612 } 3613 3614 /* Device-specific reset method for Chelsio T4-based adapters */ 3615 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3616 { 3617 u16 old_command; 3618 u16 msix_flags; 3619 3620 /* 3621 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3622 * that we have no device-specific reset method. 3623 */ 3624 if ((dev->device & 0xf000) != 0x4000) 3625 return -ENOTTY; 3626 3627 /* 3628 * If this is the "probe" phase, return 0 indicating that we can 3629 * reset this device. 3630 */ 3631 if (probe) 3632 return 0; 3633 3634 /* 3635 * T4 can wedge if there are DMAs in flight within the chip and Bus 3636 * Master has been disabled. We need to have it on till the Function 3637 * Level Reset completes. (BUS_MASTER is disabled in 3638 * pci_reset_function()). 3639 */ 3640 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3641 pci_write_config_word(dev, PCI_COMMAND, 3642 old_command | PCI_COMMAND_MASTER); 3643 3644 /* 3645 * Perform the actual device function reset, saving and restoring 3646 * configuration information around the reset. 3647 */ 3648 pci_save_state(dev); 3649 3650 /* 3651 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3652 * are disabled when an MSI-X interrupt message needs to be delivered. 3653 * So we briefly re-enable MSI-X interrupts for the duration of the 3654 * FLR. The pci_restore_state() below will restore the original 3655 * MSI-X state. 3656 */ 3657 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3658 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3659 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3660 msix_flags | 3661 PCI_MSIX_FLAGS_ENABLE | 3662 PCI_MSIX_FLAGS_MASKALL); 3663 3664 pcie_flr(dev); 3665 3666 /* 3667 * Restore the configuration information (BAR values, etc.) including 3668 * the original PCI Configuration Space Command word, and return 3669 * success. 3670 */ 3671 pci_restore_state(dev); 3672 pci_write_config_word(dev, PCI_COMMAND, old_command); 3673 return 0; 3674 } 3675 3676 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3677 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3678 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3679 3680 /* 3681 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 3682 * FLR where config space reads from the device return -1. We seem to be 3683 * able to avoid this condition if we disable the NVMe controller prior to 3684 * FLR. This quirk is generic for any NVMe class device requiring similar 3685 * assistance to quiesce the device prior to FLR. 3686 * 3687 * NVMe specification: https://nvmexpress.org/resources/specifications/ 3688 * Revision 1.0e: 3689 * Chapter 2: Required and optional PCI config registers 3690 * Chapter 3: NVMe control registers 3691 * Chapter 7.3: Reset behavior 3692 */ 3693 static int nvme_disable_and_flr(struct pci_dev *dev, int probe) 3694 { 3695 void __iomem *bar; 3696 u16 cmd; 3697 u32 cfg; 3698 3699 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 3700 !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) 3701 return -ENOTTY; 3702 3703 if (probe) 3704 return 0; 3705 3706 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 3707 if (!bar) 3708 return -ENOTTY; 3709 3710 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3711 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 3712 3713 cfg = readl(bar + NVME_REG_CC); 3714 3715 /* Disable controller if enabled */ 3716 if (cfg & NVME_CC_ENABLE) { 3717 u32 cap = readl(bar + NVME_REG_CAP); 3718 unsigned long timeout; 3719 3720 /* 3721 * Per nvme_disable_ctrl() skip shutdown notification as it 3722 * could complete commands to the admin queue. We only intend 3723 * to quiesce the device before reset. 3724 */ 3725 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 3726 3727 writel(cfg, bar + NVME_REG_CC); 3728 3729 /* 3730 * Some controllers require an additional delay here, see 3731 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 3732 * supported by this quirk. 3733 */ 3734 3735 /* Cap register provides max timeout in 500ms increments */ 3736 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 3737 3738 for (;;) { 3739 u32 status = readl(bar + NVME_REG_CSTS); 3740 3741 /* Ready status becomes zero on disable complete */ 3742 if (!(status & NVME_CSTS_RDY)) 3743 break; 3744 3745 msleep(100); 3746 3747 if (time_after(jiffies, timeout)) { 3748 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 3749 break; 3750 } 3751 } 3752 } 3753 3754 pci_iounmap(dev, bar); 3755 3756 pcie_flr(dev); 3757 3758 return 0; 3759 } 3760 3761 /* 3762 * Intel DC P3700 NVMe controller will timeout waiting for ready status 3763 * to change after NVMe enable if the driver starts interacting with the 3764 * device too soon after FLR. A 250ms delay after FLR has heuristically 3765 * proven to produce reliably working results for device assignment cases. 3766 */ 3767 static int delay_250ms_after_flr(struct pci_dev *dev, int probe) 3768 { 3769 if (!pcie_has_flr(dev)) 3770 return -ENOTTY; 3771 3772 if (probe) 3773 return 0; 3774 3775 pcie_flr(dev); 3776 3777 msleep(250); 3778 3779 return 0; 3780 } 3781 3782 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3783 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3784 reset_intel_82599_sfp_virtfn }, 3785 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3786 reset_ivb_igd }, 3787 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3788 reset_ivb_igd }, 3789 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 3790 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 3791 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3792 reset_chelsio_generic_dev }, 3793 { 0 } 3794 }; 3795 3796 /* 3797 * These device-specific reset methods are here rather than in a driver 3798 * because when a host assigns a device to a guest VM, the host may need 3799 * to reset the device but probably doesn't have a driver for it. 3800 */ 3801 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3802 { 3803 const struct pci_dev_reset_methods *i; 3804 3805 for (i = pci_dev_reset_methods; i->reset; i++) { 3806 if ((i->vendor == dev->vendor || 3807 i->vendor == (u16)PCI_ANY_ID) && 3808 (i->device == dev->device || 3809 i->device == (u16)PCI_ANY_ID)) 3810 return i->reset(dev, probe); 3811 } 3812 3813 return -ENOTTY; 3814 } 3815 3816 static void quirk_dma_func0_alias(struct pci_dev *dev) 3817 { 3818 if (PCI_FUNC(dev->devfn) != 0) 3819 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3820 } 3821 3822 /* 3823 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3824 * 3825 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3826 */ 3827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3829 3830 static void quirk_dma_func1_alias(struct pci_dev *dev) 3831 { 3832 if (PCI_FUNC(dev->devfn) != 1) 3833 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); 3834 } 3835 3836 /* 3837 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3838 * SKUs function 1 is present and is a legacy IDE controller, in other 3839 * SKUs this function is not present, making this a ghost requester. 3840 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3841 */ 3842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3843 quirk_dma_func1_alias); 3844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3845 quirk_dma_func1_alias); 3846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 3847 quirk_dma_func1_alias); 3848 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3850 quirk_dma_func1_alias); 3851 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3853 quirk_dma_func1_alias); 3854 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3856 quirk_dma_func1_alias); 3857 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3859 quirk_dma_func1_alias); 3860 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 3861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 3862 quirk_dma_func1_alias); 3863 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3865 quirk_dma_func1_alias); 3866 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 3867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 3868 quirk_dma_func1_alias); 3869 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3871 quirk_dma_func1_alias); 3872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3873 quirk_dma_func1_alias); 3874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 3875 quirk_dma_func1_alias); 3876 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3878 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3879 quirk_dma_func1_alias); 3880 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 3881 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 3882 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 3883 quirk_dma_func1_alias); 3884 3885 /* 3886 * Some devices DMA with the wrong devfn, not just the wrong function. 3887 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3888 * the alias is "fixed" and independent of the device devfn. 3889 * 3890 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3891 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3892 * single device on the secondary bus. In reality, the single exposed 3893 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3894 * that provides a bridge to the internal bus of the I/O processor. The 3895 * controller supports private devices, which can be hidden from PCI config 3896 * space. In the case of the Adaptec 3405, a private device at 01.0 3897 * appears to be the DMA engine, which therefore needs to become a DMA 3898 * alias for the device. 3899 */ 3900 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3901 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3902 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3903 .driver_data = PCI_DEVFN(1, 0) }, 3904 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3905 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 3906 .driver_data = PCI_DEVFN(1, 0) }, 3907 { 0 } 3908 }; 3909 3910 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3911 { 3912 const struct pci_device_id *id; 3913 3914 id = pci_match_id(fixed_dma_alias_tbl, dev); 3915 if (id) 3916 pci_add_dma_alias(dev, id->driver_data); 3917 } 3918 3919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3920 3921 /* 3922 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3923 * using the wrong DMA alias for the device. Some of these devices can be 3924 * used as either forward or reverse bridges, so we need to test whether the 3925 * device is operating in the correct mode. We could probably apply this 3926 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3927 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3928 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3929 */ 3930 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3931 { 3932 if (!pci_is_root_bus(pdev->bus) && 3933 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3934 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3935 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3936 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3937 } 3938 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3940 quirk_use_pcie_bridge_dma_alias); 3941 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3942 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3943 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3944 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3945 /* ITE 8893 has the same problem as the 8892 */ 3946 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 3947 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3948 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3949 3950 /* 3951 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 3952 * be added as aliases to the DMA device in order to allow buffer access 3953 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 3954 * programmed in the EEPROM. 3955 */ 3956 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 3957 { 3958 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); 3959 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); 3960 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); 3961 } 3962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 3963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 3964 3965 /* 3966 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 3967 * associated not at the root bus, but at a bridge below. This quirk avoids 3968 * generating invalid DMA aliases. 3969 */ 3970 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 3971 { 3972 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 3973 } 3974 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 3975 quirk_bridge_cavm_thrx2_pcie_root); 3976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 3977 quirk_bridge_cavm_thrx2_pcie_root); 3978 3979 /* 3980 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 3981 * class code. Fix it. 3982 */ 3983 static void quirk_tw686x_class(struct pci_dev *pdev) 3984 { 3985 u32 class = pdev->class; 3986 3987 /* Use "Multimedia controller" class */ 3988 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 3989 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 3990 class, pdev->class); 3991 } 3992 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 3993 quirk_tw686x_class); 3994 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 3995 quirk_tw686x_class); 3996 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 3997 quirk_tw686x_class); 3998 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 3999 quirk_tw686x_class); 4000 4001 /* 4002 * Some devices have problems with Transaction Layer Packets with the Relaxed 4003 * Ordering Attribute set. Such devices should mark themselves and other 4004 * device drivers should check before sending TLPs with RO set. 4005 */ 4006 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4007 { 4008 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4009 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4010 } 4011 4012 /* 4013 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4014 * Complex have a Flow Control Credit issue which can cause performance 4015 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4016 */ 4017 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4018 quirk_relaxedordering_disable); 4019 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4020 quirk_relaxedordering_disable); 4021 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4022 quirk_relaxedordering_disable); 4023 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4024 quirk_relaxedordering_disable); 4025 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4026 quirk_relaxedordering_disable); 4027 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4028 quirk_relaxedordering_disable); 4029 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4030 quirk_relaxedordering_disable); 4031 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4032 quirk_relaxedordering_disable); 4033 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4034 quirk_relaxedordering_disable); 4035 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4036 quirk_relaxedordering_disable); 4037 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4038 quirk_relaxedordering_disable); 4039 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4040 quirk_relaxedordering_disable); 4041 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4042 quirk_relaxedordering_disable); 4043 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4044 quirk_relaxedordering_disable); 4045 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4046 quirk_relaxedordering_disable); 4047 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4048 quirk_relaxedordering_disable); 4049 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4050 quirk_relaxedordering_disable); 4051 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4052 quirk_relaxedordering_disable); 4053 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4054 quirk_relaxedordering_disable); 4055 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4056 quirk_relaxedordering_disable); 4057 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4058 quirk_relaxedordering_disable); 4059 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4060 quirk_relaxedordering_disable); 4061 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4062 quirk_relaxedordering_disable); 4063 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4064 quirk_relaxedordering_disable); 4065 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4066 quirk_relaxedordering_disable); 4067 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4068 quirk_relaxedordering_disable); 4069 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4070 quirk_relaxedordering_disable); 4071 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4072 quirk_relaxedordering_disable); 4073 4074 /* 4075 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4076 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4077 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4078 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4079 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4080 * November 10, 2010). As a result, on this platform we can't use Relaxed 4081 * Ordering for Upstream TLPs. 4082 */ 4083 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4084 quirk_relaxedordering_disable); 4085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4086 quirk_relaxedordering_disable); 4087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4088 quirk_relaxedordering_disable); 4089 4090 /* 4091 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4092 * values for the Attribute as were supplied in the header of the 4093 * corresponding Request, except as explicitly allowed when IDO is used." 4094 * 4095 * If a non-compliant device generates a completion with a different 4096 * attribute than the request, the receiver may accept it (which itself 4097 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4098 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4099 * device access timeout. 4100 * 4101 * If the non-compliant device generates completions with zero attributes 4102 * (instead of copying the attributes from the request), we can work around 4103 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4104 * upstream devices so they always generate requests with zero attributes. 4105 * 4106 * This affects other devices under the same Root Port, but since these 4107 * attributes are performance hints, there should be no functional problem. 4108 * 4109 * Note that Configuration Space accesses are never supposed to have TLP 4110 * Attributes, so we're safe waiting till after any Configuration Space 4111 * accesses to do the Root Port fixup. 4112 */ 4113 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4114 { 4115 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 4116 4117 if (!root_port) { 4118 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4119 return; 4120 } 4121 4122 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4123 dev_name(&pdev->dev)); 4124 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4125 PCI_EXP_DEVCTL_RELAX_EN | 4126 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4127 } 4128 4129 /* 4130 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4131 * Completion it generates. 4132 */ 4133 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4134 { 4135 /* 4136 * This mask/compare operation selects for Physical Function 4 on a 4137 * T5. We only need to fix up the Root Port once for any of the 4138 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4139 * 0x54xx so we use that one. 4140 */ 4141 if ((pdev->device & 0xff00) == 0x5400) 4142 quirk_disable_root_port_attributes(pdev); 4143 } 4144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4145 quirk_chelsio_T5_disable_root_port_attributes); 4146 4147 /* 4148 * AMD has indicated that the devices below do not support peer-to-peer 4149 * in any system where they are found in the southbridge with an AMD 4150 * IOMMU in the system. Multifunction devices that do not support 4151 * peer-to-peer between functions can claim to support a subset of ACS. 4152 * Such devices effectively enable request redirect (RR) and completion 4153 * redirect (CR) since all transactions are redirected to the upstream 4154 * root complex. 4155 * 4156 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 4157 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 4158 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 4159 * 4160 * 1002:4385 SBx00 SMBus Controller 4161 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4162 * 1002:4383 SBx00 Azalia (Intel HDA) 4163 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4164 * 1002:4384 SBx00 PCI to PCI Bridge 4165 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4166 * 4167 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4168 * 4169 * 1022:780f [AMD] FCH PCI Bridge 4170 * 1022:7809 [AMD] FCH USB OHCI Controller 4171 */ 4172 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4173 { 4174 #ifdef CONFIG_ACPI 4175 struct acpi_table_header *header = NULL; 4176 acpi_status status; 4177 4178 /* Targeting multifunction devices on the SB (appears on root bus) */ 4179 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4180 return -ENODEV; 4181 4182 /* The IVRS table describes the AMD IOMMU */ 4183 status = acpi_get_table("IVRS", 0, &header); 4184 if (ACPI_FAILURE(status)) 4185 return -ENODEV; 4186 4187 /* Filter out flags not applicable to multifunction */ 4188 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4189 4190 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 4191 #else 4192 return -ENODEV; 4193 #endif 4194 } 4195 4196 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4197 { 4198 /* 4199 * Effectively selects all downstream ports for whole ThunderX 1 4200 * family by 0xf800 mask (which represents 8 SoCs), while the lower 4201 * bits of device ID are used to indicate which subdevice is used 4202 * within the SoC. 4203 */ 4204 return (pci_is_pcie(dev) && 4205 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && 4206 ((dev->device & 0xf800) == 0xa000)); 4207 } 4208 4209 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4210 { 4211 /* 4212 * Cavium root ports don't advertise an ACS capability. However, 4213 * the RTL internally implements similar protection as if ACS had 4214 * Request Redirection, Completion Redirection, Source Validation, 4215 * and Upstream Forwarding features enabled. Assert that the 4216 * hardware implements and enables equivalent ACS functionality for 4217 * these flags. 4218 */ 4219 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF); 4220 4221 if (!pci_quirk_cavium_acs_match(dev)) 4222 return -ENOTTY; 4223 4224 return acs_flags ? 0 : 1; 4225 } 4226 4227 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4228 { 4229 /* 4230 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4231 * transactions with others, allowing masking out these bits as if they 4232 * were unimplemented in the ACS capability. 4233 */ 4234 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4235 4236 return acs_flags ? 0 : 1; 4237 } 4238 4239 /* 4240 * Many Intel PCH root ports do provide ACS-like features to disable peer 4241 * transactions and validate bus numbers in requests, but do not provide an 4242 * actual PCIe ACS capability. This is the list of device IDs known to fall 4243 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4244 */ 4245 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4246 /* Ibexpeak PCH */ 4247 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4248 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4249 /* Cougarpoint PCH */ 4250 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4251 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4252 /* Pantherpoint PCH */ 4253 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4254 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4255 /* Lynxpoint-H PCH */ 4256 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4257 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4258 /* Lynxpoint-LP PCH */ 4259 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4260 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4261 /* Wildcat PCH */ 4262 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4263 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4264 /* Patsburg (X79) PCH */ 4265 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4266 /* Wellsburg (X99) PCH */ 4267 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4268 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4269 /* Lynx Point (9 series) PCH */ 4270 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4271 }; 4272 4273 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4274 { 4275 int i; 4276 4277 /* Filter out a few obvious non-matches first */ 4278 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4279 return false; 4280 4281 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4282 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4283 return true; 4284 4285 return false; 4286 } 4287 4288 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 4289 4290 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4291 { 4292 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 4293 INTEL_PCH_ACS_FLAGS : 0; 4294 4295 if (!pci_quirk_intel_pch_acs_match(dev)) 4296 return -ENOTTY; 4297 4298 return acs_flags & ~flags ? 0 : 1; 4299 } 4300 4301 /* 4302 * These QCOM root ports do provide ACS-like features to disable peer 4303 * transactions and validate bus numbers in requests, but do not provide an 4304 * actual PCIe ACS capability. Hardware supports source validation but it 4305 * will report the issue as Completer Abort instead of ACS Violation. 4306 * Hardware doesn't support peer-to-peer and each root port is a root 4307 * complex with unique segment numbers. It is not possible for one root 4308 * port to pass traffic to another root port. All PCIe transactions are 4309 * terminated inside the root port. 4310 */ 4311 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4312 { 4313 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4314 int ret = acs_flags & ~flags ? 0 : 1; 4315 4316 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret); 4317 4318 return ret; 4319 } 4320 4321 /* 4322 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4323 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4324 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4325 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4326 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4327 * control register is at offset 8 instead of 6 and we should probably use 4328 * dword accesses to them. This applies to the following PCI Device IDs, as 4329 * found in volume 1 of the datasheet[2]: 4330 * 4331 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4332 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4333 * 4334 * N.B. This doesn't fix what lspci shows. 4335 * 4336 * The 100 series chipset specification update includes this as errata #23[3]. 4337 * 4338 * The 200 series chipset (Union Point) has the same bug according to the 4339 * specification update (Intel 200 Series Chipset Family Platform Controller 4340 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4341 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4342 * chipset include: 4343 * 4344 * 0xa290-0xa29f PCI Express Root port #{0-16} 4345 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4346 * 4347 * Mobile chipsets are also affected, 7th & 8th Generation 4348 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4349 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4350 * Processor Family I/O for U Quad Core Platforms Specification Update, 4351 * August 2017, Revision 002, Document#: 334660-002)[6] 4352 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4353 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4354 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4355 * 4356 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4357 * 4358 * The 300 series chipset suffers from the same bug so include those root 4359 * ports here as well. 4360 * 4361 * 0xa32c-0xa343 PCI Express Root port #{0-24} 4362 * 4363 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4364 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4365 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4366 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4367 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4368 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4369 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4370 */ 4371 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4372 { 4373 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4374 return false; 4375 4376 switch (dev->device) { 4377 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4378 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4379 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4380 case 0xa32c ... 0xa343: /* 300 series */ 4381 return true; 4382 } 4383 4384 return false; 4385 } 4386 4387 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4388 4389 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4390 { 4391 int pos; 4392 u32 cap, ctrl; 4393 4394 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4395 return -ENOTTY; 4396 4397 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4398 if (!pos) 4399 return -ENOTTY; 4400 4401 /* see pci_acs_flags_enabled() */ 4402 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4403 acs_flags &= (cap | PCI_ACS_EC); 4404 4405 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4406 4407 return acs_flags & ~ctrl ? 0 : 1; 4408 } 4409 4410 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4411 { 4412 /* 4413 * SV, TB, and UF are not relevant to multifunction endpoints. 4414 * 4415 * Multifunction devices are only required to implement RR, CR, and DT 4416 * in their ACS capability if they support peer-to-peer transactions. 4417 * Devices matching this quirk have been verified by the vendor to not 4418 * perform peer-to-peer with other functions, allowing us to mask out 4419 * these bits as if they were unimplemented in the ACS capability. 4420 */ 4421 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4422 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4423 4424 return acs_flags ? 0 : 1; 4425 } 4426 4427 static const struct pci_dev_acs_enabled { 4428 u16 vendor; 4429 u16 device; 4430 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4431 } pci_dev_acs_enabled[] = { 4432 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4433 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4434 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4435 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4436 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4437 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4438 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4439 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4440 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4441 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4442 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4443 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4444 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4445 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4446 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4447 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4448 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4449 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4450 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4451 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4452 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4453 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4454 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4455 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4456 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4457 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4458 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4459 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4460 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4461 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4462 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4463 /* 82580 */ 4464 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4465 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4466 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4467 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4468 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4469 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4470 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4471 /* 82576 */ 4472 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4473 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4474 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4475 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4476 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4477 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4478 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4479 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4480 /* 82575 */ 4481 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4482 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4483 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4484 /* I350 */ 4485 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4486 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4487 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4488 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4489 /* 82571 (Quads omitted due to non-ACS switch) */ 4490 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4491 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4492 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4493 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4494 /* I219 */ 4495 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4496 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4497 /* QCOM QDF2xxx root ports */ 4498 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 4499 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 4500 /* Intel PCH root ports */ 4501 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4502 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4503 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4504 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4505 /* Cavium ThunderX */ 4506 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4507 /* APM X-Gene */ 4508 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4509 /* Ampere Computing */ 4510 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 4511 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 4512 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 4513 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 4514 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 4515 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4516 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4517 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4518 { 0 } 4519 }; 4520 4521 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4522 { 4523 const struct pci_dev_acs_enabled *i; 4524 int ret; 4525 4526 /* 4527 * Allow devices that do not expose standard PCIe ACS capabilities 4528 * or control to indicate their support here. Multi-function express 4529 * devices which do not allow internal peer-to-peer between functions, 4530 * but do not implement PCIe ACS may wish to return true here. 4531 */ 4532 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4533 if ((i->vendor == dev->vendor || 4534 i->vendor == (u16)PCI_ANY_ID) && 4535 (i->device == dev->device || 4536 i->device == (u16)PCI_ANY_ID)) { 4537 ret = i->acs_enabled(dev, acs_flags); 4538 if (ret >= 0) 4539 return ret; 4540 } 4541 } 4542 4543 return -ENOTTY; 4544 } 4545 4546 /* Config space offset of Root Complex Base Address register */ 4547 #define INTEL_LPC_RCBA_REG 0xf0 4548 /* 31:14 RCBA address */ 4549 #define INTEL_LPC_RCBA_MASK 0xffffc000 4550 /* RCBA Enable */ 4551 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4552 4553 /* Backbone Scratch Pad Register */ 4554 #define INTEL_BSPR_REG 0x1104 4555 /* Backbone Peer Non-Posted Disable */ 4556 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4557 /* Backbone Peer Posted Disable */ 4558 #define INTEL_BSPR_REG_BPPD (1 << 9) 4559 4560 /* Upstream Peer Decode Configuration Register */ 4561 #define INTEL_UPDCR_REG 0x1114 4562 /* 5:0 Peer Decode Enable bits */ 4563 #define INTEL_UPDCR_REG_MASK 0x3f 4564 4565 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4566 { 4567 u32 rcba, bspr, updcr; 4568 void __iomem *rcba_mem; 4569 4570 /* 4571 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4572 * are D28:F* and therefore get probed before LPC, thus we can't 4573 * use pci_get_slot()/pci_read_config_dword() here. 4574 */ 4575 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4576 INTEL_LPC_RCBA_REG, &rcba); 4577 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4578 return -EINVAL; 4579 4580 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 4581 PAGE_ALIGN(INTEL_UPDCR_REG)); 4582 if (!rcba_mem) 4583 return -ENOMEM; 4584 4585 /* 4586 * The BSPR can disallow peer cycles, but it's set by soft strap and 4587 * therefore read-only. If both posted and non-posted peer cycles are 4588 * disallowed, we're ok. If either are allowed, then we need to use 4589 * the UPDCR to disable peer decodes for each port. This provides the 4590 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4591 */ 4592 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4593 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4594 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4595 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4596 if (updcr & INTEL_UPDCR_REG_MASK) { 4597 pci_info(dev, "Disabling UPDCR peer decodes\n"); 4598 updcr &= ~INTEL_UPDCR_REG_MASK; 4599 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4600 } 4601 } 4602 4603 iounmap(rcba_mem); 4604 return 0; 4605 } 4606 4607 /* Miscellaneous Port Configuration register */ 4608 #define INTEL_MPC_REG 0xd8 4609 /* MPC: Invalid Receive Bus Number Check Enable */ 4610 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4611 4612 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4613 { 4614 u32 mpc; 4615 4616 /* 4617 * When enabled, the IRBNCE bit of the MPC register enables the 4618 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4619 * ensures that requester IDs fall within the bus number range 4620 * of the bridge. Enable if not already. 4621 */ 4622 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4623 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4624 pci_info(dev, "Enabling MPC IRBNCE\n"); 4625 mpc |= INTEL_MPC_REG_IRBNCE; 4626 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4627 } 4628 } 4629 4630 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4631 { 4632 if (!pci_quirk_intel_pch_acs_match(dev)) 4633 return -ENOTTY; 4634 4635 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4636 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 4637 return 0; 4638 } 4639 4640 pci_quirk_enable_intel_rp_mpc_acs(dev); 4641 4642 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4643 4644 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 4645 4646 return 0; 4647 } 4648 4649 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4650 { 4651 int pos; 4652 u32 cap, ctrl; 4653 4654 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4655 return -ENOTTY; 4656 4657 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4658 if (!pos) 4659 return -ENOTTY; 4660 4661 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4662 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4663 4664 ctrl |= (cap & PCI_ACS_SV); 4665 ctrl |= (cap & PCI_ACS_RR); 4666 ctrl |= (cap & PCI_ACS_CR); 4667 ctrl |= (cap & PCI_ACS_UF); 4668 4669 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4670 4671 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4672 4673 return 0; 4674 } 4675 4676 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 4677 { 4678 int pos; 4679 u32 cap, ctrl; 4680 4681 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4682 return -ENOTTY; 4683 4684 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4685 if (!pos) 4686 return -ENOTTY; 4687 4688 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4689 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4690 4691 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 4692 4693 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4694 4695 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 4696 4697 return 0; 4698 } 4699 4700 static const struct pci_dev_acs_ops { 4701 u16 vendor; 4702 u16 device; 4703 int (*enable_acs)(struct pci_dev *dev); 4704 int (*disable_acs_redir)(struct pci_dev *dev); 4705 } pci_dev_acs_ops[] = { 4706 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 4707 .enable_acs = pci_quirk_enable_intel_pch_acs, 4708 }, 4709 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 4710 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 4711 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 4712 }, 4713 }; 4714 4715 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4716 { 4717 const struct pci_dev_acs_ops *p; 4718 int i, ret; 4719 4720 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 4721 p = &pci_dev_acs_ops[i]; 4722 if ((p->vendor == dev->vendor || 4723 p->vendor == (u16)PCI_ANY_ID) && 4724 (p->device == dev->device || 4725 p->device == (u16)PCI_ANY_ID) && 4726 p->enable_acs) { 4727 ret = p->enable_acs(dev); 4728 if (ret >= 0) 4729 return ret; 4730 } 4731 } 4732 4733 return -ENOTTY; 4734 } 4735 4736 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 4737 { 4738 const struct pci_dev_acs_ops *p; 4739 int i, ret; 4740 4741 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 4742 p = &pci_dev_acs_ops[i]; 4743 if ((p->vendor == dev->vendor || 4744 p->vendor == (u16)PCI_ANY_ID) && 4745 (p->device == dev->device || 4746 p->device == (u16)PCI_ANY_ID) && 4747 p->disable_acs_redir) { 4748 ret = p->disable_acs_redir(dev); 4749 if (ret >= 0) 4750 return ret; 4751 } 4752 } 4753 4754 return -ENOTTY; 4755 } 4756 4757 /* 4758 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 4759 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4760 * Next Capability pointer in the MSI Capability Structure should point to 4761 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4762 * the list. 4763 */ 4764 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4765 { 4766 int pos, i = 0; 4767 u8 next_cap; 4768 u16 reg16, *cap; 4769 struct pci_cap_saved_state *state; 4770 4771 /* Bail if the hardware bug is fixed */ 4772 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4773 return; 4774 4775 /* Bail if MSI Capability Structure is not found for some reason */ 4776 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4777 if (!pos) 4778 return; 4779 4780 /* 4781 * Bail if Next Capability pointer in the MSI Capability Structure 4782 * is not the expected incorrect 0x00. 4783 */ 4784 pci_read_config_byte(pdev, pos + 1, &next_cap); 4785 if (next_cap) 4786 return; 4787 4788 /* 4789 * PCIe Capability Structure is expected to be at 0x50 and should 4790 * terminate the list (Next Capability pointer is 0x00). Verify 4791 * Capability Id and Next Capability pointer is as expected. 4792 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4793 * to correctly set kernel data structures which have already been 4794 * set incorrectly due to the hardware bug. 4795 */ 4796 pos = 0x50; 4797 pci_read_config_word(pdev, pos, ®16); 4798 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4799 u32 status; 4800 #ifndef PCI_EXP_SAVE_REGS 4801 #define PCI_EXP_SAVE_REGS 7 4802 #endif 4803 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4804 4805 pdev->pcie_cap = pos; 4806 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4807 pdev->pcie_flags_reg = reg16; 4808 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4809 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4810 4811 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4812 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4813 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4814 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4815 4816 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4817 return; 4818 4819 /* Save PCIe cap */ 4820 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4821 if (!state) 4822 return; 4823 4824 state->cap.cap_nr = PCI_CAP_ID_EXP; 4825 state->cap.cap_extended = 0; 4826 state->cap.size = size; 4827 cap = (u16 *)&state->cap.data[0]; 4828 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4829 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4830 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4831 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4832 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4833 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4834 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4835 hlist_add_head(&state->next, &pdev->saved_cap_space); 4836 } 4837 } 4838 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4839 4840 /* FLR may cause some 82579 devices to hang */ 4841 static void quirk_intel_no_flr(struct pci_dev *dev) 4842 { 4843 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4844 } 4845 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); 4846 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); 4847 4848 static void quirk_no_ext_tags(struct pci_dev *pdev) 4849 { 4850 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 4851 4852 if (!bridge) 4853 return; 4854 4855 bridge->no_ext_tags = 1; 4856 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 4857 4858 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 4859 } 4860 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 4861 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 4862 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 4863 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 4864 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 4865 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 4866 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 4867 4868 #ifdef CONFIG_PCI_ATS 4869 /* 4870 * Some devices have a broken ATS implementation causing IOMMU stalls. 4871 * Don't use ATS for those devices. 4872 */ 4873 static void quirk_no_ats(struct pci_dev *pdev) 4874 { 4875 pci_info(pdev, "disabling ATS (broken on this device)\n"); 4876 pdev->ats_cap = 0; 4877 } 4878 4879 /* AMD Stoney platform GPU */ 4880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); 4881 #endif /* CONFIG_PCI_ATS */ 4882 4883 /* Freescale PCIe doesn't support MSI in RC mode */ 4884 static void quirk_fsl_no_msi(struct pci_dev *pdev) 4885 { 4886 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 4887 pdev->no_msi = 1; 4888 } 4889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 4890 4891 /* 4892 * GPUs with integrated HDA controller for streaming audio to attached displays 4893 * need a device link from the HDA controller (consumer) to the GPU (supplier) 4894 * so that the GPU is powered up whenever the HDA controller is accessed. 4895 * The GPU and HDA controller are functions 0 and 1 of the same PCI device. 4896 * The device link stays in place until shutdown (or removal of the PCI device 4897 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller 4898 * to prevent it from permanently keeping the GPU awake. 4899 */ 4900 static void quirk_gpu_hda(struct pci_dev *hda) 4901 { 4902 struct pci_dev *gpu; 4903 4904 if (PCI_FUNC(hda->devfn) != 1) 4905 return; 4906 4907 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), 4908 hda->bus->number, 4909 PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); 4910 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { 4911 pci_dev_put(gpu); 4912 return; 4913 } 4914 4915 if (!device_link_add(&hda->dev, &gpu->dev, 4916 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 4917 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); 4918 4919 pm_runtime_allow(&hda->dev); 4920 pci_dev_put(gpu); 4921 } 4922 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 4923 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4924 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 4925 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4926 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 4927 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4928 4929 /* 4930 * Some IDT switches incorrectly flag an ACS Source Validation error on 4931 * completions for config read requests even though PCIe r4.0, sec 4932 * 6.12.1.1, says that completions are never affected by ACS Source 4933 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 4934 * 4935 * Item #36 - Downstream port applies ACS Source Validation to Completions 4936 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 4937 * completions are never affected by ACS Source Validation. However, 4938 * completions received by a downstream port of the PCIe switch from a 4939 * device that has not yet captured a PCIe bus number are incorrectly 4940 * dropped by ACS Source Validation by the switch downstream port. 4941 * 4942 * The workaround suggested by IDT is to issue a config write to the 4943 * downstream device before issuing the first config read. This allows the 4944 * downstream device to capture its bus and device numbers (see PCIe r4.0, 4945 * sec 2.2.9), thus avoiding the ACS error on the completion. 4946 * 4947 * However, we don't know when the device is ready to accept the config 4948 * write, so we do config reads until we receive a non-Config Request Retry 4949 * Status, then do the config write. 4950 * 4951 * To avoid hitting the erratum when doing the config reads, we disable ACS 4952 * SV around this process. 4953 */ 4954 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 4955 { 4956 int pos; 4957 u16 ctrl = 0; 4958 bool found; 4959 struct pci_dev *bridge = bus->self; 4960 4961 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS); 4962 4963 /* Disable ACS SV before initial config reads */ 4964 if (pos) { 4965 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 4966 if (ctrl & PCI_ACS_SV) 4967 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 4968 ctrl & ~PCI_ACS_SV); 4969 } 4970 4971 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 4972 4973 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 4974 if (found) 4975 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 4976 4977 /* Re-enable ACS_SV if it was previously enabled */ 4978 if (ctrl & PCI_ACS_SV) 4979 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 4980 4981 return found; 4982 } 4983 4984 /* 4985 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 4986 * NT endpoints via the internal switch fabric. These IDs replace the 4987 * originating requestor ID TLPs which access host memory on peer NTB 4988 * ports. Therefore, all proxy IDs must be aliased to the NTB device 4989 * to permit access when the IOMMU is turned on. 4990 */ 4991 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 4992 { 4993 void __iomem *mmio; 4994 struct ntb_info_regs __iomem *mmio_ntb; 4995 struct ntb_ctrl_regs __iomem *mmio_ctrl; 4996 struct sys_info_regs __iomem *mmio_sys_info; 4997 u64 partition_map; 4998 u8 partition; 4999 int pp; 5000 5001 if (pci_enable_device(pdev)) { 5002 pci_err(pdev, "Cannot enable Switchtec device\n"); 5003 return; 5004 } 5005 5006 mmio = pci_iomap(pdev, 0, 0); 5007 if (mmio == NULL) { 5008 pci_disable_device(pdev); 5009 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5010 return; 5011 } 5012 5013 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5014 5015 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5016 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5017 mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET; 5018 5019 partition = ioread8(&mmio_ntb->partition_id); 5020 5021 partition_map = ioread32(&mmio_ntb->ep_map); 5022 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5023 partition_map &= ~(1ULL << partition); 5024 5025 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5026 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5027 u32 table_sz = 0; 5028 int te; 5029 5030 if (!(partition_map & (1ULL << pp))) 5031 continue; 5032 5033 pci_dbg(pdev, "Processing partition %d\n", pp); 5034 5035 mmio_peer_ctrl = &mmio_ctrl[pp]; 5036 5037 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5038 if (!table_sz) { 5039 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5040 continue; 5041 } 5042 5043 if (table_sz > 512) { 5044 pci_warn(pdev, 5045 "Invalid Switchtec partition %d table_sz %d\n", 5046 pp, table_sz); 5047 continue; 5048 } 5049 5050 for (te = 0; te < table_sz; te++) { 5051 u32 rid_entry; 5052 u8 devfn; 5053 5054 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5055 devfn = (rid_entry >> 1) & 0xFF; 5056 pci_dbg(pdev, 5057 "Aliasing Partition %d Proxy ID %02x.%d\n", 5058 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5059 pci_add_dma_alias(pdev, devfn); 5060 } 5061 } 5062 5063 pci_iounmap(pdev, mmio); 5064 pci_disable_device(pdev); 5065 } 5066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531, 5067 quirk_switchtec_ntb_dma_alias); 5068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532, 5069 quirk_switchtec_ntb_dma_alias); 5070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533, 5071 quirk_switchtec_ntb_dma_alias); 5072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534, 5073 quirk_switchtec_ntb_dma_alias); 5074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535, 5075 quirk_switchtec_ntb_dma_alias); 5076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536, 5077 quirk_switchtec_ntb_dma_alias); 5078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543, 5079 quirk_switchtec_ntb_dma_alias); 5080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544, 5081 quirk_switchtec_ntb_dma_alias); 5082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545, 5083 quirk_switchtec_ntb_dma_alias); 5084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546, 5085 quirk_switchtec_ntb_dma_alias); 5086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551, 5087 quirk_switchtec_ntb_dma_alias); 5088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552, 5089 quirk_switchtec_ntb_dma_alias); 5090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553, 5091 quirk_switchtec_ntb_dma_alias); 5092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554, 5093 quirk_switchtec_ntb_dma_alias); 5094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555, 5095 quirk_switchtec_ntb_dma_alias); 5096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556, 5097 quirk_switchtec_ntb_dma_alias); 5098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561, 5099 quirk_switchtec_ntb_dma_alias); 5100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562, 5101 quirk_switchtec_ntb_dma_alias); 5102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563, 5103 quirk_switchtec_ntb_dma_alias); 5104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564, 5105 quirk_switchtec_ntb_dma_alias); 5106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565, 5107 quirk_switchtec_ntb_dma_alias); 5108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566, 5109 quirk_switchtec_ntb_dma_alias); 5110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571, 5111 quirk_switchtec_ntb_dma_alias); 5112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572, 5113 quirk_switchtec_ntb_dma_alias); 5114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573, 5115 quirk_switchtec_ntb_dma_alias); 5116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574, 5117 quirk_switchtec_ntb_dma_alias); 5118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575, 5119 quirk_switchtec_ntb_dma_alias); 5120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576, 5121 quirk_switchtec_ntb_dma_alias); 5122