1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/acpi.h> 21 #include <linux/kallsyms.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 29 #include "pci.h" 30 31 /* 32 * Decoding should be disabled for a PCI device during BAR sizing to avoid 33 * conflict. But doing so may cause problems on host bridge and perhaps other 34 * key system devices. For devices that need to have mmio decoding always-on, 35 * we need to set the dev->mmio_always_on bit. 36 */ 37 static void quirk_mmio_always_on(struct pci_dev *dev) 38 { 39 dev->mmio_always_on = 1; 40 } 41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 43 44 /* The Mellanox Tavor device gives false positive parity errors 45 * Mark this device with a broken_parity_status, to allow 46 * PCI scanning code to "skip" this now blacklisted device. 47 */ 48 static void quirk_mellanox_tavor(struct pci_dev *dev) 49 { 50 dev->broken_parity_status = 1; /* This device gives false positives */ 51 } 52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 54 55 /* Deal with broken BIOSes that neglect to enable passive release, 56 which can cause problems in combination with the 82441FX/PPro MTRRs */ 57 static void quirk_passive_release(struct pci_dev *dev) 58 { 59 struct pci_dev *d = NULL; 60 unsigned char dlc; 61 62 /* We have to make sure a particular bit is set in the PIIX3 63 ISA bridge, so we have to go out and find it. */ 64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 65 pci_read_config_byte(d, 0x82, &dlc); 66 if (!(dlc & 1<<1)) { 67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 68 dlc |= 1<<1; 69 pci_write_config_byte(d, 0x82, dlc); 70 } 71 } 72 } 73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 75 76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 77 but VIA don't answer queries. If you happen to have good contacts at VIA 78 ask them for me please -- Alan 79 80 This appears to be BIOS not version dependent. So presumably there is a 81 chipset level fix */ 82 83 static void quirk_isa_dma_hangs(struct pci_dev *dev) 84 { 85 if (!isa_dma_bridge_buggy) { 86 isa_dma_bridge_buggy = 1; 87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 88 } 89 } 90 /* 91 * Its not totally clear which chipsets are the problematic ones 92 * We know 82C586 and 82C596 variants are affected. 93 */ 94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 101 102 /* 103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 104 * for some HT machines to use C4 w/o hanging. 105 */ 106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 107 { 108 u32 pmbase; 109 u16 pm1a; 110 111 pci_read_config_dword(dev, 0x40, &pmbase); 112 pmbase = pmbase & 0xff80; 113 pm1a = inw(pmbase); 114 115 if (pm1a & 0x10) { 116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 117 outw(0x10, pmbase); 118 } 119 } 120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 121 122 /* 123 * Chipsets where PCI->PCI transfers vanish or hang 124 */ 125 static void quirk_nopcipci(struct pci_dev *dev) 126 { 127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 129 pci_pci_problems |= PCIPCI_FAIL; 130 } 131 } 132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 134 135 static void quirk_nopciamd(struct pci_dev *dev) 136 { 137 u8 rev; 138 pci_read_config_byte(dev, 0x08, &rev); 139 if (rev == 0x13) { 140 /* Erratum 24 */ 141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 142 pci_pci_problems |= PCIAGP_FAIL; 143 } 144 } 145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 146 147 /* 148 * Triton requires workarounds to be used by the drivers 149 */ 150 static void quirk_triton(struct pci_dev *dev) 151 { 152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 154 pci_pci_problems |= PCIPCI_TRITON; 155 } 156 } 157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 161 162 /* 163 * VIA Apollo KT133 needs PCI latency patch 164 * Made according to a windows driver based patch by George E. Breese 165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 167 * the info on which Mr Breese based his work. 168 * 169 * Updated based on further information from the site and also on 170 * information provided by VIA 171 */ 172 static void quirk_vialatency(struct pci_dev *dev) 173 { 174 struct pci_dev *p; 175 u8 busarb; 176 /* Ok we have a potential problem chipset here. Now see if we have 177 a buggy southbridge */ 178 179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 180 if (p != NULL) { 181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 182 /* Check for buggy part revisions */ 183 if (p->revision < 0x40 || p->revision > 0x42) 184 goto exit; 185 } else { 186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 187 if (p == NULL) /* No problem parts */ 188 goto exit; 189 /* Check for buggy part revisions */ 190 if (p->revision < 0x10 || p->revision > 0x12) 191 goto exit; 192 } 193 194 /* 195 * Ok we have the problem. Now set the PCI master grant to 196 * occur every master grant. The apparent bug is that under high 197 * PCI load (quite common in Linux of course) you can get data 198 * loss when the CPU is held off the bus for 3 bus master requests 199 * This happens to include the IDE controllers.... 200 * 201 * VIA only apply this fix when an SB Live! is present but under 202 * both Linux and Windows this isn't enough, and we have seen 203 * corruption without SB Live! but with things like 3 UDMA IDE 204 * controllers. So we ignore that bit of the VIA recommendation.. 205 */ 206 207 pci_read_config_byte(dev, 0x76, &busarb); 208 /* Set bit 4 and bi 5 of byte 76 to 0x01 209 "Master priority rotation on every PCI master grant */ 210 busarb &= ~(1<<5); 211 busarb |= (1<<4); 212 pci_write_config_byte(dev, 0x76, busarb); 213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 214 exit: 215 pci_dev_put(p); 216 } 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 220 /* Must restore this on a resume from RAM */ 221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 224 225 /* 226 * VIA Apollo VP3 needs ETBF on BT848/878 227 */ 228 static void quirk_viaetbf(struct pci_dev *dev) 229 { 230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 232 pci_pci_problems |= PCIPCI_VIAETBF; 233 } 234 } 235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 236 237 static void quirk_vsfx(struct pci_dev *dev) 238 { 239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 241 pci_pci_problems |= PCIPCI_VSFX; 242 } 243 } 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 245 246 /* 247 * Ali Magik requires workarounds to be used by the drivers 248 * that DMA to AGP space. Latency must be set to 0xA and triton 249 * workaround applied too 250 * [Info kindly provided by ALi] 251 */ 252 static void quirk_alimagik(struct pci_dev *dev) 253 { 254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 257 } 258 } 259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 261 262 /* 263 * Natoma has some interesting boundary conditions with Zoran stuff 264 * at least 265 */ 266 static void quirk_natoma(struct pci_dev *dev) 267 { 268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 270 pci_pci_problems |= PCIPCI_NATOMA; 271 } 272 } 273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 279 280 /* 281 * This chip can cause PCI parity errors if config register 0xA0 is read 282 * while DMAs are occurring. 283 */ 284 static void quirk_citrine(struct pci_dev *dev) 285 { 286 dev->cfg_size = 0xA0; 287 } 288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 289 290 /* 291 * This chip can cause bus lockups if config addresses above 0x600 292 * are read or written. 293 */ 294 static void quirk_nfp6000(struct pci_dev *dev) 295 { 296 dev->cfg_size = 0x600; 297 } 298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 301 302 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 303 static void quirk_extend_bar_to_page(struct pci_dev *dev) 304 { 305 int i; 306 307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) { 308 struct resource *r = &dev->resource[i]; 309 310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 311 r->end = PAGE_SIZE - 1; 312 r->start = 0; 313 r->flags |= IORESOURCE_UNSET; 314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 315 i, r); 316 } 317 } 318 } 319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 320 321 /* 322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 323 * If it's needed, re-allocate the region. 324 */ 325 static void quirk_s3_64M(struct pci_dev *dev) 326 { 327 struct resource *r = &dev->resource[0]; 328 329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 330 r->flags |= IORESOURCE_UNSET; 331 r->start = 0; 332 r->end = 0x3ffffff; 333 } 334 } 335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 337 338 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 339 const char *name) 340 { 341 u32 region; 342 struct pci_bus_region bus_region; 343 struct resource *res = dev->resource + pos; 344 345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 346 347 if (!region) 348 return; 349 350 res->name = pci_name(dev); 351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 352 res->flags |= 353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 354 region &= ~(size - 1); 355 356 /* Convert from PCI bus to resource space */ 357 bus_region.start = region; 358 bus_region.end = region + size - 1; 359 pcibios_bus_to_resource(dev->bus, res, &bus_region); 360 361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 363 } 364 365 /* 366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 369 * (which conflicts w/ BAR1's memory range). 370 * 371 * CS553x's ISA PCI BARs may also be read-only (ref: 372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 373 */ 374 static void quirk_cs5536_vsa(struct pci_dev *dev) 375 { 376 static char *name = "CS5536 ISA bridge"; 377 378 if (pci_resource_len(dev, 0) != 8) { 379 quirk_io(dev, 0, 8, name); /* SMB */ 380 quirk_io(dev, 1, 256, name); /* GPIO */ 381 quirk_io(dev, 2, 64, name); /* MFGPT */ 382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 383 name); 384 } 385 } 386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 387 388 static void quirk_io_region(struct pci_dev *dev, int port, 389 unsigned size, int nr, const char *name) 390 { 391 u16 region; 392 struct pci_bus_region bus_region; 393 struct resource *res = dev->resource + nr; 394 395 pci_read_config_word(dev, port, ®ion); 396 region &= ~(size - 1); 397 398 if (!region) 399 return; 400 401 res->name = pci_name(dev); 402 res->flags = IORESOURCE_IO; 403 404 /* Convert from PCI bus to resource space */ 405 bus_region.start = region; 406 bus_region.end = region + size - 1; 407 pcibios_bus_to_resource(dev->bus, res, &bus_region); 408 409 if (!pci_claim_resource(dev, nr)) 410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 411 } 412 413 /* 414 * ATI Northbridge setups MCE the processor if you even 415 * read somewhere between 0x3b0->0x3bb or read 0x3d3 416 */ 417 static void quirk_ati_exploding_mce(struct pci_dev *dev) 418 { 419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 421 request_region(0x3b0, 0x0C, "RadeonIGP"); 422 request_region(0x3d3, 0x01, "RadeonIGP"); 423 } 424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 425 426 /* 427 * In the AMD NL platform, this device ([1022:7912]) has a class code of 428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 429 * claim it. 430 * But the dwc3 driver is a more specific driver for this device, and we'd 431 * prefer to use it instead of xhci. To prevent xhci from claiming the 432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 433 * defines as "USB device (not host controller)". The dwc3 driver can then 434 * claim it based on its Vendor and Device ID. 435 */ 436 static void quirk_amd_nl_class(struct pci_dev *pdev) 437 { 438 u32 class = pdev->class; 439 440 /* Use "USB Device (not host controller)" class */ 441 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 443 class, pdev->class); 444 } 445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 446 quirk_amd_nl_class); 447 448 /* 449 * Let's make the southbridge information explicit instead 450 * of having to worry about people probing the ACPI areas, 451 * for example.. (Yes, it happens, and if you read the wrong 452 * ACPI register it will put the machine to sleep with no 453 * way of waking it up again. Bummer). 454 * 455 * ALI M7101: Two IO regions pointed to by words at 456 * 0xE0 (64 bytes of ACPI registers) 457 * 0xE2 (32 bytes of SMB registers) 458 */ 459 static void quirk_ali7101_acpi(struct pci_dev *dev) 460 { 461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 463 } 464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 465 466 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 467 { 468 u32 devres; 469 u32 mask, size, base; 470 471 pci_read_config_dword(dev, port, &devres); 472 if ((devres & enable) != enable) 473 return; 474 mask = (devres >> 16) & 15; 475 base = devres & 0xffff; 476 size = 16; 477 for (;;) { 478 unsigned bit = size >> 1; 479 if ((bit & mask) == bit) 480 break; 481 size = bit; 482 } 483 /* 484 * For now we only print it out. Eventually we'll want to 485 * reserve it (at least if it's in the 0x1000+ range), but 486 * let's get enough confirmation reports first. 487 */ 488 base &= -size; 489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 490 base + size - 1); 491 } 492 493 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 494 { 495 u32 devres; 496 u32 mask, size, base; 497 498 pci_read_config_dword(dev, port, &devres); 499 if ((devres & enable) != enable) 500 return; 501 base = devres & 0xffff0000; 502 mask = (devres & 0x3f) << 16; 503 size = 128 << 16; 504 for (;;) { 505 unsigned bit = size >> 1; 506 if ((bit & mask) == bit) 507 break; 508 size = bit; 509 } 510 /* 511 * For now we only print it out. Eventually we'll want to 512 * reserve it, but let's get enough confirmation reports first. 513 */ 514 base &= -size; 515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 516 base + size - 1); 517 } 518 519 /* 520 * PIIX4 ACPI: Two IO regions pointed to by longwords at 521 * 0x40 (64 bytes of ACPI registers) 522 * 0x90 (16 bytes of SMB registers) 523 * and a few strange programmable PIIX4 device resources. 524 */ 525 static void quirk_piix4_acpi(struct pci_dev *dev) 526 { 527 u32 res_a; 528 529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 531 532 /* Device resource A has enables for some of the other ones */ 533 pci_read_config_dword(dev, 0x5c, &res_a); 534 535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 537 538 /* Device resource D is just bitfields for static resources */ 539 540 /* Device 12 enabled? */ 541 if (res_a & (1 << 29)) { 542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 544 } 545 /* Device 13 enabled? */ 546 if (res_a & (1 << 30)) { 547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 549 } 550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 552 } 553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 555 556 #define ICH_PMBASE 0x40 557 #define ICH_ACPI_CNTL 0x44 558 #define ICH4_ACPI_EN 0x10 559 #define ICH6_ACPI_EN 0x80 560 #define ICH4_GPIOBASE 0x58 561 #define ICH4_GPIO_CNTL 0x5c 562 #define ICH4_GPIO_EN 0x10 563 #define ICH6_GPIOBASE 0x48 564 #define ICH6_GPIO_CNTL 0x4c 565 #define ICH6_GPIO_EN 0x10 566 567 /* 568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 570 * 0x58 (64 bytes of GPIO I/O space) 571 */ 572 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 573 { 574 u8 enable; 575 576 /* 577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 578 * with low legacy (and fixed) ports. We don't know the decoding 579 * priority and can't tell whether the legacy device or the one created 580 * here is really at that address. This happens on boards with broken 581 * BIOSes. 582 */ 583 584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 585 if (enable & ICH4_ACPI_EN) 586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 587 "ICH4 ACPI/GPIO/TCO"); 588 589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 590 if (enable & ICH4_GPIO_EN) 591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 592 "ICH4 GPIO"); 593 } 594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 604 605 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 606 { 607 u8 enable; 608 609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 610 if (enable & ICH6_ACPI_EN) 611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 612 "ICH6 ACPI/GPIO/TCO"); 613 614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 615 if (enable & ICH6_GPIO_EN) 616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 617 "ICH6 GPIO"); 618 } 619 620 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 621 { 622 u32 val; 623 u32 size, base; 624 625 pci_read_config_dword(dev, reg, &val); 626 627 /* Enabled? */ 628 if (!(val & 1)) 629 return; 630 base = val & 0xfffc; 631 if (dynsize) { 632 /* 633 * This is not correct. It is 16, 32 or 64 bytes depending on 634 * register D31:F0:ADh bits 5:4. 635 * 636 * But this gets us at least _part_ of it. 637 */ 638 size = 16; 639 } else { 640 size = 128; 641 } 642 base &= ~(size-1); 643 644 /* Just print it out for now. We should reserve it after more debugging */ 645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 646 } 647 648 static void quirk_ich6_lpc(struct pci_dev *dev) 649 { 650 /* Shared ACPI/GPIO decode with all ICH6+ */ 651 ich6_lpc_acpi_gpio(dev); 652 653 /* ICH6-specific generic IO decode */ 654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 656 } 657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 659 660 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 661 { 662 u32 val; 663 u32 mask, base; 664 665 pci_read_config_dword(dev, reg, &val); 666 667 /* Enabled? */ 668 if (!(val & 1)) 669 return; 670 671 /* 672 * IO base in bits 15:2, mask in bits 23:18, both 673 * are dword-based 674 */ 675 base = val & 0xfffc; 676 mask = (val >> 16) & 0xfc; 677 mask |= 3; 678 679 /* Just print it out for now. We should reserve it after more debugging */ 680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 681 } 682 683 /* ICH7-10 has the same common LPC generic IO decode registers */ 684 static void quirk_ich7_lpc(struct pci_dev *dev) 685 { 686 /* We share the common ACPI/GPIO decode with ICH6 */ 687 ich6_lpc_acpi_gpio(dev); 688 689 /* And have 4 ICH7+ generic decodes */ 690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 694 } 695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 708 709 /* 710 * VIA ACPI: One IO region pointed to by longword at 711 * 0x48 or 0x20 (256 bytes of ACPI registers) 712 */ 713 static void quirk_vt82c586_acpi(struct pci_dev *dev) 714 { 715 if (dev->revision & 0x10) 716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 717 "vt82c586 ACPI"); 718 } 719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 720 721 /* 722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 723 * 0x48 (256 bytes of ACPI registers) 724 * 0x70 (128 bytes of hardware monitoring register) 725 * 0x90 (16 bytes of SMB registers) 726 */ 727 static void quirk_vt82c686_acpi(struct pci_dev *dev) 728 { 729 quirk_vt82c586_acpi(dev); 730 731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 732 "vt82c686 HW-mon"); 733 734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 735 } 736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 737 738 /* 739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 740 * 0x88 (128 bytes of power management registers) 741 * 0xd0 (16 bytes of SMB registers) 742 */ 743 static void quirk_vt8235_acpi(struct pci_dev *dev) 744 { 745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 747 } 748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 749 750 /* 751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 752 * Disable fast back-to-back on the secondary bus segment 753 */ 754 static void quirk_xio2000a(struct pci_dev *dev) 755 { 756 struct pci_dev *pdev; 757 u16 command; 758 759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 761 pci_read_config_word(pdev, PCI_COMMAND, &command); 762 if (command & PCI_COMMAND_FAST_BACK) 763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 764 } 765 } 766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 767 quirk_xio2000a); 768 769 #ifdef CONFIG_X86_IO_APIC 770 771 #include <asm/io_apic.h> 772 773 /* 774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 775 * devices to the external APIC. 776 * 777 * TODO: When we have device-specific interrupt routers, 778 * this code will go away from quirks. 779 */ 780 static void quirk_via_ioapic(struct pci_dev *dev) 781 { 782 u8 tmp; 783 784 if (nr_ioapics < 1) 785 tmp = 0; /* nothing routed to external APIC */ 786 else 787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 788 789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 790 tmp == 0 ? "Disa" : "Ena"); 791 792 /* Offset 0x58: External APIC IRQ output control */ 793 pci_write_config_byte(dev, 0x58, tmp); 794 } 795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 797 798 /* 799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 800 * This leads to doubled level interrupt rates. 801 * Set this bit to get rid of cycle wastage. 802 * Otherwise uncritical. 803 */ 804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 805 { 806 u8 misc_control2; 807 #define BYPASS_APIC_DEASSERT 8 808 809 pci_read_config_byte(dev, 0x5B, &misc_control2); 810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 813 } 814 } 815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 817 818 /* 819 * The AMD io apic can hang the box when an apic irq is masked. 820 * We check all revs >= B0 (yet not in the pre production!) as the bug 821 * is currently marked NoFix 822 * 823 * We have multiple reports of hangs with this chipset that went away with 824 * noapic specified. For the moment we assume it's the erratum. We may be wrong 825 * of course. However the advice is demonstrably good even if so.. 826 */ 827 static void quirk_amd_ioapic(struct pci_dev *dev) 828 { 829 if (dev->revision >= 0x02) { 830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 832 } 833 } 834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 835 #endif /* CONFIG_X86_IO_APIC */ 836 837 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 838 839 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 840 { 841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */ 842 if (dev->subsystem_device == 0xa118) 843 dev->sriov->link = dev->devfn; 844 } 845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 846 #endif 847 848 /* 849 * Some settings of MMRBC can lead to data corruption so block changes. 850 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 851 */ 852 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 853 { 854 if (dev->subordinate && dev->revision <= 0x12) { 855 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 856 dev->revision); 857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 858 } 859 } 860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 861 862 /* 863 * FIXME: it is questionable that quirk_via_acpi 864 * is needed. It shows up as an ISA bridge, and does not 865 * support the PCI_INTERRUPT_LINE register at all. Therefore 866 * it seems like setting the pci_dev's 'irq' to the 867 * value of the ACPI SCI interrupt is only done for convenience. 868 * -jgarzik 869 */ 870 static void quirk_via_acpi(struct pci_dev *d) 871 { 872 /* 873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 874 */ 875 u8 irq; 876 pci_read_config_byte(d, 0x42, &irq); 877 irq &= 0xf; 878 if (irq && (irq != 2)) 879 d->irq = irq; 880 } 881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 883 884 885 /* 886 * VIA bridges which have VLink 887 */ 888 889 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 890 891 static void quirk_via_bridge(struct pci_dev *dev) 892 { 893 /* See what bridge we have and find the device ranges */ 894 switch (dev->device) { 895 case PCI_DEVICE_ID_VIA_82C686: 896 /* The VT82C686 is special, it attaches to PCI and can have 897 any device number. All its subdevices are functions of 898 that single device. */ 899 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 900 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 901 break; 902 case PCI_DEVICE_ID_VIA_8237: 903 case PCI_DEVICE_ID_VIA_8237A: 904 via_vlink_dev_lo = 15; 905 break; 906 case PCI_DEVICE_ID_VIA_8235: 907 via_vlink_dev_lo = 16; 908 break; 909 case PCI_DEVICE_ID_VIA_8231: 910 case PCI_DEVICE_ID_VIA_8233_0: 911 case PCI_DEVICE_ID_VIA_8233A: 912 case PCI_DEVICE_ID_VIA_8233C_0: 913 via_vlink_dev_lo = 17; 914 break; 915 } 916 } 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 925 926 /** 927 * quirk_via_vlink - VIA VLink IRQ number update 928 * @dev: PCI device 929 * 930 * If the device we are dealing with is on a PIC IRQ we need to 931 * ensure that the IRQ line register which usually is not relevant 932 * for PCI cards, is actually written so that interrupts get sent 933 * to the right place. 934 * We only do this on systems where a VIA south bridge was detected, 935 * and only for VIA devices on the motherboard (see quirk_via_bridge 936 * above). 937 */ 938 939 static void quirk_via_vlink(struct pci_dev *dev) 940 { 941 u8 irq, new_irq; 942 943 /* Check if we have VLink at all */ 944 if (via_vlink_dev_lo == -1) 945 return; 946 947 new_irq = dev->irq; 948 949 /* Don't quirk interrupts outside the legacy IRQ range */ 950 if (!new_irq || new_irq > 15) 951 return; 952 953 /* Internal device ? */ 954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 956 return; 957 958 /* This is an internal VLink device on a PIC interrupt. The BIOS 959 ought to have set this but may not have, so we redo it */ 960 961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 962 if (new_irq != irq) { 963 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 964 irq, new_irq); 965 udelay(15); /* unknown if delay really needed */ 966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 967 } 968 } 969 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 970 971 /* 972 * VIA VT82C598 has its device ID settable and many BIOSes 973 * set it to the ID of VT82C597 for backward compatibility. 974 * We need to switch it off to be able to recognize the real 975 * type of the chip. 976 */ 977 static void quirk_vt82c598_id(struct pci_dev *dev) 978 { 979 pci_write_config_byte(dev, 0xfc, 0); 980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 981 } 982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 983 984 /* 985 * CardBus controllers have a legacy base address that enables them 986 * to respond as i82365 pcmcia controllers. We don't want them to 987 * do this even if the Linux CardBus driver is not loaded, because 988 * the Linux i82365 driver does not (and should not) handle CardBus. 989 */ 990 static void quirk_cardbus_legacy(struct pci_dev *dev) 991 { 992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 993 } 994 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 996 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 998 999 /* 1000 * Following the PCI ordering rules is optional on the AMD762. I'm not 1001 * sure what the designers were smoking but let's not inhale... 1002 * 1003 * To be fair to AMD, it follows the spec by default, its BIOS people 1004 * who turn it off! 1005 */ 1006 static void quirk_amd_ordering(struct pci_dev *dev) 1007 { 1008 u32 pcic; 1009 pci_read_config_dword(dev, 0x4C, &pcic); 1010 if ((pcic & 6) != 6) { 1011 pcic |= 6; 1012 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1013 pci_write_config_dword(dev, 0x4C, pcic); 1014 pci_read_config_dword(dev, 0x84, &pcic); 1015 pcic |= (1 << 23); /* Required in this mode */ 1016 pci_write_config_dword(dev, 0x84, pcic); 1017 } 1018 } 1019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1021 1022 /* 1023 * DreamWorks provided workaround for Dunord I-3000 problem 1024 * 1025 * This card decodes and responds to addresses not apparently 1026 * assigned to it. We force a larger allocation to ensure that 1027 * nothing gets put too close to it. 1028 */ 1029 static void quirk_dunord(struct pci_dev *dev) 1030 { 1031 struct resource *r = &dev->resource[1]; 1032 1033 r->flags |= IORESOURCE_UNSET; 1034 r->start = 0; 1035 r->end = 0xffffff; 1036 } 1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1038 1039 /* 1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1041 * is subtractive decoding (transparent), and does indicate this 1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1043 * instead of 0x01. 1044 */ 1045 static void quirk_transparent_bridge(struct pci_dev *dev) 1046 { 1047 dev->transparent = 1; 1048 } 1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1051 1052 /* 1053 * Common misconfiguration of the MediaGX/Geode PCI master that will 1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1055 * datasheets found at http://www.national.com/analog for info on what 1056 * these bits do. <christer@weinigel.se> 1057 */ 1058 static void quirk_mediagx_master(struct pci_dev *dev) 1059 { 1060 u8 reg; 1061 1062 pci_read_config_byte(dev, 0x41, ®); 1063 if (reg & 2) { 1064 reg &= ~2; 1065 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1066 reg); 1067 pci_write_config_byte(dev, 0x41, reg); 1068 } 1069 } 1070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1072 1073 /* 1074 * Ensure C0 rev restreaming is off. This is normally done by 1075 * the BIOS but in the odd case it is not the results are corruption 1076 * hence the presence of a Linux check 1077 */ 1078 static void quirk_disable_pxb(struct pci_dev *pdev) 1079 { 1080 u16 config; 1081 1082 if (pdev->revision != 0x04) /* Only C0 requires this */ 1083 return; 1084 pci_read_config_word(pdev, 0x40, &config); 1085 if (config & (1<<6)) { 1086 config &= ~(1<<6); 1087 pci_write_config_word(pdev, 0x40, config); 1088 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1089 } 1090 } 1091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1093 1094 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1095 { 1096 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1097 u8 tmp; 1098 1099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1100 if (tmp == 0x01) { 1101 pci_read_config_byte(pdev, 0x40, &tmp); 1102 pci_write_config_byte(pdev, 0x40, tmp|1); 1103 pci_write_config_byte(pdev, 0x9, 1); 1104 pci_write_config_byte(pdev, 0xa, 6); 1105 pci_write_config_byte(pdev, 0x40, tmp); 1106 1107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1108 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1109 } 1110 } 1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1112 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1119 1120 /* 1121 * Serverworks CSB5 IDE does not fully support native mode 1122 */ 1123 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1124 { 1125 u8 prog; 1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1127 if (prog & 5) { 1128 prog &= ~5; 1129 pdev->class &= ~5; 1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1131 /* PCI layer will sort out resources */ 1132 } 1133 } 1134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1135 1136 /* 1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1138 */ 1139 static void quirk_ide_samemode(struct pci_dev *pdev) 1140 { 1141 u8 prog; 1142 1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1144 1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1146 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1147 prog &= ~5; 1148 pdev->class &= ~5; 1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1150 } 1151 } 1152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1153 1154 /* 1155 * Some ATA devices break if put into D3 1156 */ 1157 1158 static void quirk_no_ata_d3(struct pci_dev *pdev) 1159 { 1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1161 } 1162 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1163 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1167 /* ALi loses some register settings that we cannot then restore */ 1168 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1170 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1171 occur when mode detecting */ 1172 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1174 1175 /* This was originally an Alpha specific thing, but it really fits here. 1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1177 */ 1178 static void quirk_eisa_bridge(struct pci_dev *dev) 1179 { 1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1181 } 1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1183 1184 1185 /* 1186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1187 * is not activated. The myth is that Asus said that they do not want the 1188 * users to be irritated by just another PCI Device in the Win98 device 1189 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1190 * package 2.7.0 for details) 1191 * 1192 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1193 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1194 * becomes necessary to do this tweak in two steps -- the chosen trigger 1195 * is either the Host bridge (preferred) or on-board VGA controller. 1196 * 1197 * Note that we used to unhide the SMBus that way on Toshiba laptops 1198 * (Satellite A40 and Tecra M2) but then found that the thermal management 1199 * was done by SMM code, which could cause unsynchronized concurrent 1200 * accesses to the SMBus registers, with potentially bad effects. Thus you 1201 * should be very careful when adding new entries: if SMM is accessing the 1202 * Intel SMBus, this is a very good reason to leave it hidden. 1203 * 1204 * Likewise, many recent laptops use ACPI for thermal management. If the 1205 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1206 * natively, and keeping the SMBus hidden is the right thing to do. If you 1207 * are about to add an entry in the table below, please first disassemble 1208 * the DSDT and double-check that there is no code accessing the SMBus. 1209 */ 1210 static int asus_hides_smbus; 1211 1212 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1213 { 1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1216 switch (dev->subsystem_device) { 1217 case 0x8025: /* P4B-LX */ 1218 case 0x8070: /* P4B */ 1219 case 0x8088: /* P4B533 */ 1220 case 0x1626: /* L3C notebook */ 1221 asus_hides_smbus = 1; 1222 } 1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1224 switch (dev->subsystem_device) { 1225 case 0x80b1: /* P4GE-V */ 1226 case 0x80b2: /* P4PE */ 1227 case 0x8093: /* P4B533-V */ 1228 asus_hides_smbus = 1; 1229 } 1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1231 switch (dev->subsystem_device) { 1232 case 0x8030: /* P4T533 */ 1233 asus_hides_smbus = 1; 1234 } 1235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1236 switch (dev->subsystem_device) { 1237 case 0x8070: /* P4G8X Deluxe */ 1238 asus_hides_smbus = 1; 1239 } 1240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1241 switch (dev->subsystem_device) { 1242 case 0x80c9: /* PU-DLS */ 1243 asus_hides_smbus = 1; 1244 } 1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1246 switch (dev->subsystem_device) { 1247 case 0x1751: /* M2N notebook */ 1248 case 0x1821: /* M5N notebook */ 1249 case 0x1897: /* A6L notebook */ 1250 asus_hides_smbus = 1; 1251 } 1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1253 switch (dev->subsystem_device) { 1254 case 0x184b: /* W1N notebook */ 1255 case 0x186a: /* M6Ne notebook */ 1256 asus_hides_smbus = 1; 1257 } 1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1259 switch (dev->subsystem_device) { 1260 case 0x80f2: /* P4P800-X */ 1261 asus_hides_smbus = 1; 1262 } 1263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1264 switch (dev->subsystem_device) { 1265 case 0x1882: /* M6V notebook */ 1266 case 0x1977: /* A6VA notebook */ 1267 asus_hides_smbus = 1; 1268 } 1269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1271 switch (dev->subsystem_device) { 1272 case 0x088C: /* HP Compaq nc8000 */ 1273 case 0x0890: /* HP Compaq nc6000 */ 1274 asus_hides_smbus = 1; 1275 } 1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1277 switch (dev->subsystem_device) { 1278 case 0x12bc: /* HP D330L */ 1279 case 0x12bd: /* HP D530 */ 1280 case 0x006a: /* HP Compaq nx9500 */ 1281 asus_hides_smbus = 1; 1282 } 1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1284 switch (dev->subsystem_device) { 1285 case 0x12bf: /* HP xw4100 */ 1286 asus_hides_smbus = 1; 1287 } 1288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1290 switch (dev->subsystem_device) { 1291 case 0xC00C: /* Samsung P35 notebook */ 1292 asus_hides_smbus = 1; 1293 } 1294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1296 switch (dev->subsystem_device) { 1297 case 0x0058: /* Compaq Evo N620c */ 1298 asus_hides_smbus = 1; 1299 } 1300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1301 switch (dev->subsystem_device) { 1302 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1303 /* Motherboard doesn't have Host bridge 1304 * subvendor/subdevice IDs, therefore checking 1305 * its on-board VGA controller */ 1306 asus_hides_smbus = 1; 1307 } 1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1309 switch (dev->subsystem_device) { 1310 case 0x00b8: /* Compaq Evo D510 CMT */ 1311 case 0x00b9: /* Compaq Evo D510 SFF */ 1312 case 0x00ba: /* Compaq Evo D510 USDT */ 1313 /* Motherboard doesn't have Host bridge 1314 * subvendor/subdevice IDs and on-board VGA 1315 * controller is disabled if an AGP card is 1316 * inserted, therefore checking USB UHCI 1317 * Controller #1 */ 1318 asus_hides_smbus = 1; 1319 } 1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1321 switch (dev->subsystem_device) { 1322 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1323 /* Motherboard doesn't have host bridge 1324 * subvendor/subdevice IDs, therefore checking 1325 * its on-board VGA controller */ 1326 asus_hides_smbus = 1; 1327 } 1328 } 1329 } 1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1340 1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1344 1345 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1346 { 1347 u16 val; 1348 1349 if (likely(!asus_hides_smbus)) 1350 return; 1351 1352 pci_read_config_word(dev, 0xF2, &val); 1353 if (val & 0x8) { 1354 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1355 pci_read_config_word(dev, 0xF2, &val); 1356 if (val & 0x8) 1357 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1358 val); 1359 else 1360 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1361 } 1362 } 1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1377 1378 /* It appears we just have one such device. If not, we have a warning */ 1379 static void __iomem *asus_rcba_base; 1380 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1381 { 1382 u32 rcba; 1383 1384 if (likely(!asus_hides_smbus)) 1385 return; 1386 WARN_ON(asus_rcba_base); 1387 1388 pci_read_config_dword(dev, 0xF0, &rcba); 1389 /* use bits 31:14, 16 kB aligned */ 1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1391 if (asus_rcba_base == NULL) 1392 return; 1393 } 1394 1395 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1396 { 1397 u32 val; 1398 1399 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1400 return; 1401 /* read the Function Disable register, dword mode only */ 1402 val = readl(asus_rcba_base + 0x3418); 1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1404 } 1405 1406 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1407 { 1408 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1409 return; 1410 iounmap(asus_rcba_base); 1411 asus_rcba_base = NULL; 1412 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1413 } 1414 1415 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1416 { 1417 asus_hides_smbus_lpc_ich6_suspend(dev); 1418 asus_hides_smbus_lpc_ich6_resume_early(dev); 1419 asus_hides_smbus_lpc_ich6_resume(dev); 1420 } 1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1422 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1425 1426 /* 1427 * SiS 96x south bridge: BIOS typically hides SMBus device... 1428 */ 1429 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1430 { 1431 u8 val = 0; 1432 pci_read_config_byte(dev, 0x77, &val); 1433 if (val & 0x10) { 1434 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1435 pci_write_config_byte(dev, 0x77, val & ~0x10); 1436 } 1437 } 1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1442 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1446 1447 /* 1448 * ... This is further complicated by the fact that some SiS96x south 1449 * bridges pretend to be 85C503/5513 instead. In that case see if we 1450 * spotted a compatible north bridge to make sure. 1451 * (pci_find_device doesn't work yet) 1452 * 1453 * We can also enable the sis96x bit in the discovery register.. 1454 */ 1455 #define SIS_DETECT_REGISTER 0x40 1456 1457 static void quirk_sis_503(struct pci_dev *dev) 1458 { 1459 u8 reg; 1460 u16 devid; 1461 1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1467 return; 1468 } 1469 1470 /* 1471 * Ok, it now shows up as a 96x.. run the 96x quirk by 1472 * hand in case it has already been processed. 1473 * (depends on link order, which is apparently not guaranteed) 1474 */ 1475 dev->device = devid; 1476 quirk_sis_96x_smbus(dev); 1477 } 1478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1479 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1480 1481 1482 /* 1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1484 * and MC97 modem controller are disabled when a second PCI soundcard is 1485 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1486 * -- bjd 1487 */ 1488 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1489 { 1490 u8 val; 1491 int asus_hides_ac97 = 0; 1492 1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1494 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1495 asus_hides_ac97 = 1; 1496 } 1497 1498 if (!asus_hides_ac97) 1499 return; 1500 1501 pci_read_config_byte(dev, 0x50, &val); 1502 if (val & 0xc0) { 1503 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1504 pci_read_config_byte(dev, 0x50, &val); 1505 if (val & 0xc0) 1506 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1507 val); 1508 else 1509 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1510 } 1511 } 1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1514 1515 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1516 1517 /* 1518 * If we are using libata we can drive this chip properly but must 1519 * do this early on to make the additional device appear during 1520 * the PCI scanning. 1521 */ 1522 static void quirk_jmicron_ata(struct pci_dev *pdev) 1523 { 1524 u32 conf1, conf5, class; 1525 u8 hdr; 1526 1527 /* Only poke fn 0 */ 1528 if (PCI_FUNC(pdev->devfn)) 1529 return; 1530 1531 pci_read_config_dword(pdev, 0x40, &conf1); 1532 pci_read_config_dword(pdev, 0x80, &conf5); 1533 1534 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1535 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1536 1537 switch (pdev->device) { 1538 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1539 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1540 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1541 /* The controller should be in single function ahci mode */ 1542 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1543 break; 1544 1545 case PCI_DEVICE_ID_JMICRON_JMB365: 1546 case PCI_DEVICE_ID_JMICRON_JMB366: 1547 /* Redirect IDE second PATA port to the right spot */ 1548 conf5 |= (1 << 24); 1549 /* Fall through */ 1550 case PCI_DEVICE_ID_JMICRON_JMB361: 1551 case PCI_DEVICE_ID_JMICRON_JMB363: 1552 case PCI_DEVICE_ID_JMICRON_JMB369: 1553 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1554 /* Set the class codes correctly and then direct IDE 0 */ 1555 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1556 break; 1557 1558 case PCI_DEVICE_ID_JMICRON_JMB368: 1559 /* The controller should be in single function IDE mode */ 1560 conf1 |= 0x00C00000; /* Set 22, 23 */ 1561 break; 1562 } 1563 1564 pci_write_config_dword(pdev, 0x40, conf1); 1565 pci_write_config_dword(pdev, 0x80, conf5); 1566 1567 /* Update pdev accordingly */ 1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1569 pdev->hdr_type = hdr & 0x7f; 1570 pdev->multifunction = !!(hdr & 0x80); 1571 1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1573 pdev->class = class >> 8; 1574 } 1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1584 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1593 1594 #endif 1595 1596 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1597 { 1598 if (dev->multifunction) { 1599 device_disable_async_suspend(&dev->dev); 1600 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1601 } 1602 } 1603 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1604 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1607 1608 #ifdef CONFIG_X86_IO_APIC 1609 static void quirk_alder_ioapic(struct pci_dev *pdev) 1610 { 1611 int i; 1612 1613 if ((pdev->class >> 8) != 0xff00) 1614 return; 1615 1616 /* the first BAR is the location of the IO APIC...we must 1617 * not touch this (and it's already covered by the fixmap), so 1618 * forcibly insert it into the resource tree */ 1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1620 insert_resource(&iomem_resource, &pdev->resource[0]); 1621 1622 /* The next five BARs all seem to be rubbish, so just clean 1623 * them out */ 1624 for (i = 1; i < 6; i++) 1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1626 } 1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1628 #endif 1629 1630 static void quirk_pcie_mch(struct pci_dev *pdev) 1631 { 1632 pdev->no_msi = 1; 1633 } 1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch); 1638 1639 1640 /* 1641 * It's possible for the MSI to get corrupted if shpc and acpi 1642 * are used together on certain PXH-based systems. 1643 */ 1644 static void quirk_pcie_pxh(struct pci_dev *dev) 1645 { 1646 dev->no_msi = 1; 1647 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1648 } 1649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1654 1655 /* 1656 * Some Intel PCI Express chipsets have trouble with downstream 1657 * device power management. 1658 */ 1659 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1660 { 1661 pci_pm_d3_delay = 120; 1662 dev->no_d1d2 = 1; 1663 } 1664 1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1686 1687 #ifdef CONFIG_X86_IO_APIC 1688 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1689 { 1690 noioapicreroute = 1; 1691 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1692 1693 return 0; 1694 } 1695 1696 static struct dmi_system_id boot_interrupt_dmi_table[] = { 1697 /* 1698 * Systems to exclude from boot interrupt reroute quirks 1699 */ 1700 { 1701 .callback = dmi_disable_ioapicreroute, 1702 .ident = "ASUSTek Computer INC. M2N-LR", 1703 .matches = { 1704 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1705 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1706 }, 1707 }, 1708 {} 1709 }; 1710 1711 /* 1712 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1713 * remap the original interrupt in the linux kernel to the boot interrupt, so 1714 * that a PCI device's interrupt handler is installed on the boot interrupt 1715 * line instead. 1716 */ 1717 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1718 { 1719 dmi_check_system(boot_interrupt_dmi_table); 1720 if (noioapicquirk || noioapicreroute) 1721 return; 1722 1723 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1724 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1725 dev->vendor, dev->device); 1726 } 1727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1732 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1735 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1736 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1737 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1738 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1739 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1740 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1741 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1742 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1743 1744 /* 1745 * On some chipsets we can disable the generation of legacy INTx boot 1746 * interrupts. 1747 */ 1748 1749 /* 1750 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1751 * 300641-004US, section 5.7.3. 1752 */ 1753 #define INTEL_6300_IOAPIC_ABAR 0x40 1754 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1755 1756 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1757 { 1758 u16 pci_config_word; 1759 1760 if (noioapicquirk) 1761 return; 1762 1763 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1764 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1765 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1766 1767 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1768 dev->vendor, dev->device); 1769 } 1770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1771 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1772 1773 /* 1774 * disable boot interrupts on HT-1000 1775 */ 1776 #define BC_HT1000_FEATURE_REG 0x64 1777 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1778 #define BC_HT1000_MAP_IDX 0xC00 1779 #define BC_HT1000_MAP_DATA 0xC01 1780 1781 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1782 { 1783 u32 pci_config_dword; 1784 u8 irq; 1785 1786 if (noioapicquirk) 1787 return; 1788 1789 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1790 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1791 BC_HT1000_PIC_REGS_ENABLE); 1792 1793 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1794 outb(irq, BC_HT1000_MAP_IDX); 1795 outb(0x00, BC_HT1000_MAP_DATA); 1796 } 1797 1798 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1799 1800 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1801 dev->vendor, dev->device); 1802 } 1803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1804 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1805 1806 /* 1807 * disable boot interrupts on AMD and ATI chipsets 1808 */ 1809 /* 1810 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1811 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1812 * (due to an erratum). 1813 */ 1814 #define AMD_813X_MISC 0x40 1815 #define AMD_813X_NOIOAMODE (1<<0) 1816 #define AMD_813X_REV_B1 0x12 1817 #define AMD_813X_REV_B2 0x13 1818 1819 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1820 { 1821 u32 pci_config_dword; 1822 1823 if (noioapicquirk) 1824 return; 1825 if ((dev->revision == AMD_813X_REV_B1) || 1826 (dev->revision == AMD_813X_REV_B2)) 1827 return; 1828 1829 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1830 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1831 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1832 1833 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1834 dev->vendor, dev->device); 1835 } 1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1837 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1839 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1840 1841 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1842 1843 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1844 { 1845 u16 pci_config_word; 1846 1847 if (noioapicquirk) 1848 return; 1849 1850 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1851 if (!pci_config_word) { 1852 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1853 dev->vendor, dev->device); 1854 return; 1855 } 1856 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1857 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1858 dev->vendor, dev->device); 1859 } 1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1861 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1862 #endif /* CONFIG_X86_IO_APIC */ 1863 1864 /* 1865 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1866 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1867 * Re-allocate the region if needed... 1868 */ 1869 static void quirk_tc86c001_ide(struct pci_dev *dev) 1870 { 1871 struct resource *r = &dev->resource[0]; 1872 1873 if (r->start & 0x8) { 1874 r->flags |= IORESOURCE_UNSET; 1875 r->start = 0; 1876 r->end = 0xf; 1877 } 1878 } 1879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1880 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1881 quirk_tc86c001_ide); 1882 1883 /* 1884 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1885 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1886 * being read correctly if bit 7 of the base address is set. 1887 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1888 * Re-allocate the regions to a 256-byte boundary if necessary. 1889 */ 1890 static void quirk_plx_pci9050(struct pci_dev *dev) 1891 { 1892 unsigned int bar; 1893 1894 /* Fixed in revision 2 (PCI 9052). */ 1895 if (dev->revision >= 2) 1896 return; 1897 for (bar = 0; bar <= 1; bar++) 1898 if (pci_resource_len(dev, bar) == 0x80 && 1899 (pci_resource_start(dev, bar) & 0x80)) { 1900 struct resource *r = &dev->resource[bar]; 1901 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1902 bar); 1903 r->flags |= IORESOURCE_UNSET; 1904 r->start = 0; 1905 r->end = 0xff; 1906 } 1907 } 1908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1909 quirk_plx_pci9050); 1910 /* 1911 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1912 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1913 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1914 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1915 * 1916 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1917 * driver. 1918 */ 1919 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1920 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1921 1922 static void quirk_netmos(struct pci_dev *dev) 1923 { 1924 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1925 unsigned int num_serial = dev->subsystem_device & 0xf; 1926 1927 /* 1928 * These Netmos parts are multiport serial devices with optional 1929 * parallel ports. Even when parallel ports are present, they 1930 * are identified as class SERIAL, which means the serial driver 1931 * will claim them. To prevent this, mark them as class OTHER. 1932 * These combo devices should be claimed by parport_serial. 1933 * 1934 * The subdevice ID is of the form 0x00PS, where <P> is the number 1935 * of parallel ports and <S> is the number of serial ports. 1936 */ 1937 switch (dev->device) { 1938 case PCI_DEVICE_ID_NETMOS_9835: 1939 /* Well, this rule doesn't hold for the following 9835 device */ 1940 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1941 dev->subsystem_device == 0x0299) 1942 return; 1943 case PCI_DEVICE_ID_NETMOS_9735: 1944 case PCI_DEVICE_ID_NETMOS_9745: 1945 case PCI_DEVICE_ID_NETMOS_9845: 1946 case PCI_DEVICE_ID_NETMOS_9855: 1947 if (num_parallel) { 1948 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1949 dev->device, num_parallel, num_serial); 1950 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1951 (dev->class & 0xff); 1952 } 1953 } 1954 } 1955 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1956 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1957 1958 /* 1959 * Quirk non-zero PCI functions to route VPD access through function 0 for 1960 * devices that share VPD resources between functions. The functions are 1961 * expected to be identical devices. 1962 */ 1963 static void quirk_f0_vpd_link(struct pci_dev *dev) 1964 { 1965 struct pci_dev *f0; 1966 1967 if (!PCI_FUNC(dev->devfn)) 1968 return; 1969 1970 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 1971 if (!f0) 1972 return; 1973 1974 if (f0->vpd && dev->class == f0->class && 1975 dev->vendor == f0->vendor && dev->device == f0->device) 1976 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; 1977 1978 pci_dev_put(f0); 1979 } 1980 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1981 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link); 1982 1983 static void quirk_e100_interrupt(struct pci_dev *dev) 1984 { 1985 u16 command, pmcsr; 1986 u8 __iomem *csr; 1987 u8 cmd_hi; 1988 1989 switch (dev->device) { 1990 /* PCI IDs taken from drivers/net/e100.c */ 1991 case 0x1029: 1992 case 0x1030 ... 0x1034: 1993 case 0x1038 ... 0x103E: 1994 case 0x1050 ... 0x1057: 1995 case 0x1059: 1996 case 0x1064 ... 0x106B: 1997 case 0x1091 ... 0x1095: 1998 case 0x1209: 1999 case 0x1229: 2000 case 0x2449: 2001 case 0x2459: 2002 case 0x245D: 2003 case 0x27DC: 2004 break; 2005 default: 2006 return; 2007 } 2008 2009 /* 2010 * Some firmware hands off the e100 with interrupts enabled, 2011 * which can cause a flood of interrupts if packets are 2012 * received before the driver attaches to the device. So 2013 * disable all e100 interrupts here. The driver will 2014 * re-enable them when it's ready. 2015 */ 2016 pci_read_config_word(dev, PCI_COMMAND, &command); 2017 2018 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2019 return; 2020 2021 /* 2022 * Check that the device is in the D0 power state. If it's not, 2023 * there is no point to look any further. 2024 */ 2025 if (dev->pm_cap) { 2026 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2027 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2028 return; 2029 } 2030 2031 /* Convert from PCI bus to resource space. */ 2032 csr = ioremap(pci_resource_start(dev, 0), 8); 2033 if (!csr) { 2034 dev_warn(&dev->dev, "Can't map e100 registers\n"); 2035 return; 2036 } 2037 2038 cmd_hi = readb(csr + 3); 2039 if (cmd_hi == 0) { 2040 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 2041 writeb(1, csr + 3); 2042 } 2043 2044 iounmap(csr); 2045 } 2046 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2047 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2048 2049 /* 2050 * The 82575 and 82598 may experience data corruption issues when transitioning 2051 * out of L0S. To prevent this we need to disable L0S on the pci-e link 2052 */ 2053 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2054 { 2055 dev_info(&dev->dev, "Disabling L0s\n"); 2056 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2057 } 2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2072 2073 static void fixup_rev1_53c810(struct pci_dev *dev) 2074 { 2075 u32 class = dev->class; 2076 2077 /* 2078 * rev 1 ncr53c810 chips don't set the class at all which means 2079 * they don't get their resources remapped. Fix that here. 2080 */ 2081 if (class) 2082 return; 2083 2084 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2085 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2086 class, dev->class); 2087 } 2088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2089 2090 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2091 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2092 { 2093 u16 en1k; 2094 2095 pci_read_config_word(dev, 0x40, &en1k); 2096 2097 if (en1k & 0x200) { 2098 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2099 dev->io_window_1k = 1; 2100 } 2101 } 2102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2103 2104 /* Under some circumstances, AER is not linked with extended capabilities. 2105 * Force it to be linked by setting the corresponding control bit in the 2106 * config space. 2107 */ 2108 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2109 { 2110 uint8_t b; 2111 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2112 if (!(b & 0x20)) { 2113 pci_write_config_byte(dev, 0xf41, b | 0x20); 2114 dev_info(&dev->dev, "Linking AER extended capability\n"); 2115 } 2116 } 2117 } 2118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2119 quirk_nvidia_ck804_pcie_aer_ext_cap); 2120 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2121 quirk_nvidia_ck804_pcie_aer_ext_cap); 2122 2123 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2124 { 2125 /* 2126 * Disable PCI Bus Parking and PCI Master read caching on CX700 2127 * which causes unspecified timing errors with a VT6212L on the PCI 2128 * bus leading to USB2.0 packet loss. 2129 * 2130 * This quirk is only enabled if a second (on the external PCI bus) 2131 * VT6212L is found -- the CX700 core itself also contains a USB 2132 * host controller with the same PCI ID as the VT6212L. 2133 */ 2134 2135 /* Count VT6212L instances */ 2136 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2137 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2138 uint8_t b; 2139 2140 /* p should contain the first (internal) VT6212L -- see if we have 2141 an external one by searching again */ 2142 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2143 if (!p) 2144 return; 2145 pci_dev_put(p); 2146 2147 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2148 if (b & 0x40) { 2149 /* Turn off PCI Bus Parking */ 2150 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2151 2152 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2153 } 2154 } 2155 2156 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2157 if (b != 0) { 2158 /* Turn off PCI Master read caching */ 2159 pci_write_config_byte(dev, 0x72, 0x0); 2160 2161 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2162 pci_write_config_byte(dev, 0x75, 0x1); 2163 2164 /* Disable "Read FIFO Timer" */ 2165 pci_write_config_byte(dev, 0x77, 0x0); 2166 2167 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2168 } 2169 } 2170 } 2171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2172 2173 /* 2174 * If a device follows the VPD format spec, the PCI core will not read or 2175 * write past the VPD End Tag. But some vendors do not follow the VPD 2176 * format spec, so we can't tell how much data is safe to access. Devices 2177 * may behave unpredictably if we access too much. Blacklist these devices 2178 * so we don't touch VPD at all. 2179 */ 2180 static void quirk_blacklist_vpd(struct pci_dev *dev) 2181 { 2182 if (dev->vpd) { 2183 dev->vpd->len = 0; 2184 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); 2185 } 2186 } 2187 2188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd); 2189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd); 2190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd); 2191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd); 2192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd); 2193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd); 2194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd); 2195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd); 2196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd); 2197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd); 2198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd); 2199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, 2200 quirk_blacklist_vpd); 2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd); 2202 2203 /* 2204 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2205 * VPD end tag will hang the device. This problem was initially 2206 * observed when a vpd entry was created in sysfs 2207 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2208 * will dump 32k of data. Reading a full 32k will cause an access 2209 * beyond the VPD end tag causing the device to hang. Once the device 2210 * is hung, the bnx2 driver will not be able to reset the device. 2211 * We believe that it is legal to read beyond the end tag and 2212 * therefore the solution is to limit the read/write length. 2213 */ 2214 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2215 { 2216 /* 2217 * Only disable the VPD capability for 5706, 5706S, 5708, 2218 * 5708S and 5709 rev. A 2219 */ 2220 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2221 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2222 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2223 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2224 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2225 (dev->revision & 0xf0) == 0x0)) { 2226 if (dev->vpd) 2227 dev->vpd->len = 0x80; 2228 } 2229 } 2230 2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2232 PCI_DEVICE_ID_NX2_5706, 2233 quirk_brcm_570x_limit_vpd); 2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2235 PCI_DEVICE_ID_NX2_5706S, 2236 quirk_brcm_570x_limit_vpd); 2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2238 PCI_DEVICE_ID_NX2_5708, 2239 quirk_brcm_570x_limit_vpd); 2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2241 PCI_DEVICE_ID_NX2_5708S, 2242 quirk_brcm_570x_limit_vpd); 2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2244 PCI_DEVICE_ID_NX2_5709, 2245 quirk_brcm_570x_limit_vpd); 2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2247 PCI_DEVICE_ID_NX2_5709S, 2248 quirk_brcm_570x_limit_vpd); 2249 2250 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2251 { 2252 u32 rev; 2253 2254 pci_read_config_dword(dev, 0xf4, &rev); 2255 2256 /* Only CAP the MRRS if the device is a 5719 A0 */ 2257 if (rev == 0x05719000) { 2258 int readrq = pcie_get_readrq(dev); 2259 if (readrq > 2048) 2260 pcie_set_readrq(dev, 2048); 2261 } 2262 } 2263 2264 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2265 PCI_DEVICE_ID_TIGON3_5719, 2266 quirk_brcm_5719_limit_mrrs); 2267 2268 #ifdef CONFIG_PCIE_IPROC_PLATFORM 2269 static void quirk_paxc_bridge(struct pci_dev *pdev) 2270 { 2271 /* The PCI config space is shared with the PAXC root port and the first 2272 * Ethernet device. So, we need to workaround this by telling the PCI 2273 * code that the bridge is not an Ethernet device. 2274 */ 2275 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2276 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2277 2278 /* MPSS is not being set properly (as it is currently 0). This is 2279 * because that area of the PCI config space is hard coded to zero, and 2280 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2281 * so that the MPS can be set to the real max value. 2282 */ 2283 pdev->pcie_mpss = 2; 2284 } 2285 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); 2286 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2287 #endif 2288 2289 /* Originally in EDAC sources for i82875P: 2290 * Intel tells BIOS developers to hide device 6 which 2291 * configures the overflow device access containing 2292 * the DRBs - this is where we expose device 6. 2293 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2294 */ 2295 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2296 { 2297 u8 reg; 2298 2299 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2300 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2301 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2302 } 2303 } 2304 2305 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2306 quirk_unhide_mch_dev6); 2307 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2308 quirk_unhide_mch_dev6); 2309 2310 #ifdef CONFIG_TILEPRO 2311 /* 2312 * The Tilera TILEmpower tilepro platform needs to set the link speed 2313 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2314 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2315 * capability register of the PEX8624 PCIe switch. The switch 2316 * supports link speed auto negotiation, but falsely sets 2317 * the link speed to 5GT/s. 2318 */ 2319 static void quirk_tile_plx_gen1(struct pci_dev *dev) 2320 { 2321 if (tile_plx_gen1) { 2322 pci_write_config_dword(dev, 0x98, 0x1); 2323 mdelay(50); 2324 } 2325 } 2326 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2327 #endif /* CONFIG_TILEPRO */ 2328 2329 #ifdef CONFIG_PCI_MSI 2330 /* Some chipsets do not support MSI. We cannot easily rely on setting 2331 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2332 * some other buses controlled by the chipset even if Linux is not 2333 * aware of it. Instead of setting the flag on all buses in the 2334 * machine, simply disable MSI globally. 2335 */ 2336 static void quirk_disable_all_msi(struct pci_dev *dev) 2337 { 2338 pci_no_msi(); 2339 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2340 } 2341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2349 2350 /* Disable MSI on chipsets that are known to not support it */ 2351 static void quirk_disable_msi(struct pci_dev *dev) 2352 { 2353 if (dev->subordinate) { 2354 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2355 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2356 } 2357 } 2358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2361 2362 /* 2363 * The APC bridge device in AMD 780 family northbridges has some random 2364 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2365 * we use the possible vendor/device IDs of the host bridge for the 2366 * declared quirk, and search for the APC bridge by slot number. 2367 */ 2368 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2369 { 2370 struct pci_dev *apc_bridge; 2371 2372 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2373 if (apc_bridge) { 2374 if (apc_bridge->device == 0x9602) 2375 quirk_disable_msi(apc_bridge); 2376 pci_dev_put(apc_bridge); 2377 } 2378 } 2379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2381 2382 /* Go through the list of Hypertransport capabilities and 2383 * return 1 if a HT MSI capability is found and enabled */ 2384 static int msi_ht_cap_enabled(struct pci_dev *dev) 2385 { 2386 int pos, ttl = PCI_FIND_CAP_TTL; 2387 2388 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2389 while (pos && ttl--) { 2390 u8 flags; 2391 2392 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2393 &flags) == 0) { 2394 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2395 flags & HT_MSI_FLAGS_ENABLE ? 2396 "enabled" : "disabled"); 2397 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2398 } 2399 2400 pos = pci_find_next_ht_capability(dev, pos, 2401 HT_CAPTYPE_MSI_MAPPING); 2402 } 2403 return 0; 2404 } 2405 2406 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2407 static void quirk_msi_ht_cap(struct pci_dev *dev) 2408 { 2409 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2410 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2411 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2412 } 2413 } 2414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2415 quirk_msi_ht_cap); 2416 2417 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2418 * MSI are supported if the MSI capability set in any of these mappings. 2419 */ 2420 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2421 { 2422 struct pci_dev *pdev; 2423 2424 if (!dev->subordinate) 2425 return; 2426 2427 /* check HT MSI cap on this chipset and the root one. 2428 * a single one having MSI is enough to be sure that MSI are supported. 2429 */ 2430 pdev = pci_get_slot(dev->bus, 0); 2431 if (!pdev) 2432 return; 2433 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2434 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2435 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2436 } 2437 pci_dev_put(pdev); 2438 } 2439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2440 quirk_nvidia_ck804_msi_ht_cap); 2441 2442 /* Force enable MSI mapping capability on HT bridges */ 2443 static void ht_enable_msi_mapping(struct pci_dev *dev) 2444 { 2445 int pos, ttl = PCI_FIND_CAP_TTL; 2446 2447 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2448 while (pos && ttl--) { 2449 u8 flags; 2450 2451 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2452 &flags) == 0) { 2453 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2454 2455 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2456 flags | HT_MSI_FLAGS_ENABLE); 2457 } 2458 pos = pci_find_next_ht_capability(dev, pos, 2459 HT_CAPTYPE_MSI_MAPPING); 2460 } 2461 } 2462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2463 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2464 ht_enable_msi_mapping); 2465 2466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2467 ht_enable_msi_mapping); 2468 2469 /* The P5N32-SLI motherboards from Asus have a problem with msi 2470 * for the MCP55 NIC. It is not yet determined whether the msi problem 2471 * also affects other devices. As for now, turn off msi for this device. 2472 */ 2473 static void nvenet_msi_disable(struct pci_dev *dev) 2474 { 2475 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2476 2477 if (board_name && 2478 (strstr(board_name, "P5N32-SLI PREMIUM") || 2479 strstr(board_name, "P5N32-E SLI"))) { 2480 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2481 dev->no_msi = 1; 2482 } 2483 } 2484 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2485 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2486 nvenet_msi_disable); 2487 2488 /* 2489 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2490 * config register. This register controls the routing of legacy 2491 * interrupts from devices that route through the MCP55. If this register 2492 * is misprogrammed, interrupts are only sent to the BSP, unlike 2493 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2494 * having this register set properly prevents kdump from booting up 2495 * properly, so let's make sure that we have it set correctly. 2496 * Note that this is an undocumented register. 2497 */ 2498 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2499 { 2500 u32 cfg; 2501 2502 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2503 return; 2504 2505 pci_read_config_dword(dev, 0x74, &cfg); 2506 2507 if (cfg & ((1 << 2) | (1 << 15))) { 2508 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2509 cfg &= ~((1 << 2) | (1 << 15)); 2510 pci_write_config_dword(dev, 0x74, cfg); 2511 } 2512 } 2513 2514 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2515 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2516 nvbridge_check_legacy_irq_routing); 2517 2518 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2519 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2520 nvbridge_check_legacy_irq_routing); 2521 2522 static int ht_check_msi_mapping(struct pci_dev *dev) 2523 { 2524 int pos, ttl = PCI_FIND_CAP_TTL; 2525 int found = 0; 2526 2527 /* check if there is HT MSI cap or enabled on this device */ 2528 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2529 while (pos && ttl--) { 2530 u8 flags; 2531 2532 if (found < 1) 2533 found = 1; 2534 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2535 &flags) == 0) { 2536 if (flags & HT_MSI_FLAGS_ENABLE) { 2537 if (found < 2) { 2538 found = 2; 2539 break; 2540 } 2541 } 2542 } 2543 pos = pci_find_next_ht_capability(dev, pos, 2544 HT_CAPTYPE_MSI_MAPPING); 2545 } 2546 2547 return found; 2548 } 2549 2550 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2551 { 2552 struct pci_dev *dev; 2553 int pos; 2554 int i, dev_no; 2555 int found = 0; 2556 2557 dev_no = host_bridge->devfn >> 3; 2558 for (i = dev_no + 1; i < 0x20; i++) { 2559 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2560 if (!dev) 2561 continue; 2562 2563 /* found next host bridge ?*/ 2564 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2565 if (pos != 0) { 2566 pci_dev_put(dev); 2567 break; 2568 } 2569 2570 if (ht_check_msi_mapping(dev)) { 2571 found = 1; 2572 pci_dev_put(dev); 2573 break; 2574 } 2575 pci_dev_put(dev); 2576 } 2577 2578 return found; 2579 } 2580 2581 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2582 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2583 2584 static int is_end_of_ht_chain(struct pci_dev *dev) 2585 { 2586 int pos, ctrl_off; 2587 int end = 0; 2588 u16 flags, ctrl; 2589 2590 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2591 2592 if (!pos) 2593 goto out; 2594 2595 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2596 2597 ctrl_off = ((flags >> 10) & 1) ? 2598 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2599 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2600 2601 if (ctrl & (1 << 6)) 2602 end = 1; 2603 2604 out: 2605 return end; 2606 } 2607 2608 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2609 { 2610 struct pci_dev *host_bridge; 2611 int pos; 2612 int i, dev_no; 2613 int found = 0; 2614 2615 dev_no = dev->devfn >> 3; 2616 for (i = dev_no; i >= 0; i--) { 2617 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2618 if (!host_bridge) 2619 continue; 2620 2621 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2622 if (pos != 0) { 2623 found = 1; 2624 break; 2625 } 2626 pci_dev_put(host_bridge); 2627 } 2628 2629 if (!found) 2630 return; 2631 2632 /* don't enable end_device/host_bridge with leaf directly here */ 2633 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2634 host_bridge_with_leaf(host_bridge)) 2635 goto out; 2636 2637 /* root did that ! */ 2638 if (msi_ht_cap_enabled(host_bridge)) 2639 goto out; 2640 2641 ht_enable_msi_mapping(dev); 2642 2643 out: 2644 pci_dev_put(host_bridge); 2645 } 2646 2647 static void ht_disable_msi_mapping(struct pci_dev *dev) 2648 { 2649 int pos, ttl = PCI_FIND_CAP_TTL; 2650 2651 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2652 while (pos && ttl--) { 2653 u8 flags; 2654 2655 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2656 &flags) == 0) { 2657 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2658 2659 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2660 flags & ~HT_MSI_FLAGS_ENABLE); 2661 } 2662 pos = pci_find_next_ht_capability(dev, pos, 2663 HT_CAPTYPE_MSI_MAPPING); 2664 } 2665 } 2666 2667 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2668 { 2669 struct pci_dev *host_bridge; 2670 int pos; 2671 int found; 2672 2673 if (!pci_msi_enabled()) 2674 return; 2675 2676 /* check if there is HT MSI cap or enabled on this device */ 2677 found = ht_check_msi_mapping(dev); 2678 2679 /* no HT MSI CAP */ 2680 if (found == 0) 2681 return; 2682 2683 /* 2684 * HT MSI mapping should be disabled on devices that are below 2685 * a non-Hypertransport host bridge. Locate the host bridge... 2686 */ 2687 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2688 if (host_bridge == NULL) { 2689 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2690 return; 2691 } 2692 2693 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2694 if (pos != 0) { 2695 /* Host bridge is to HT */ 2696 if (found == 1) { 2697 /* it is not enabled, try to enable it */ 2698 if (all) 2699 ht_enable_msi_mapping(dev); 2700 else 2701 nv_ht_enable_msi_mapping(dev); 2702 } 2703 goto out; 2704 } 2705 2706 /* HT MSI is not enabled */ 2707 if (found == 1) 2708 goto out; 2709 2710 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2711 ht_disable_msi_mapping(dev); 2712 2713 out: 2714 pci_dev_put(host_bridge); 2715 } 2716 2717 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2718 { 2719 return __nv_msi_ht_cap_quirk(dev, 1); 2720 } 2721 2722 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2723 { 2724 return __nv_msi_ht_cap_quirk(dev, 0); 2725 } 2726 2727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2728 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2729 2730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2731 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2732 2733 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2734 { 2735 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2736 } 2737 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2738 { 2739 struct pci_dev *p; 2740 2741 /* SB700 MSI issue will be fixed at HW level from revision A21, 2742 * we need check PCI REVISION ID of SMBus controller to get SB700 2743 * revision. 2744 */ 2745 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2746 NULL); 2747 if (!p) 2748 return; 2749 2750 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2751 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2752 pci_dev_put(p); 2753 } 2754 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2755 { 2756 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2757 if (dev->revision < 0x18) { 2758 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2759 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2760 } 2761 } 2762 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2763 PCI_DEVICE_ID_TIGON3_5780, 2764 quirk_msi_intx_disable_bug); 2765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2766 PCI_DEVICE_ID_TIGON3_5780S, 2767 quirk_msi_intx_disable_bug); 2768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2769 PCI_DEVICE_ID_TIGON3_5714, 2770 quirk_msi_intx_disable_bug); 2771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2772 PCI_DEVICE_ID_TIGON3_5714S, 2773 quirk_msi_intx_disable_bug); 2774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2775 PCI_DEVICE_ID_TIGON3_5715, 2776 quirk_msi_intx_disable_bug); 2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2778 PCI_DEVICE_ID_TIGON3_5715S, 2779 quirk_msi_intx_disable_bug); 2780 2781 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2782 quirk_msi_intx_disable_ati_bug); 2783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2784 quirk_msi_intx_disable_ati_bug); 2785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2786 quirk_msi_intx_disable_ati_bug); 2787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2788 quirk_msi_intx_disable_ati_bug); 2789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2790 quirk_msi_intx_disable_ati_bug); 2791 2792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2793 quirk_msi_intx_disable_bug); 2794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2795 quirk_msi_intx_disable_bug); 2796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2797 quirk_msi_intx_disable_bug); 2798 2799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2800 quirk_msi_intx_disable_bug); 2801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2802 quirk_msi_intx_disable_bug); 2803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2804 quirk_msi_intx_disable_bug); 2805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2806 quirk_msi_intx_disable_bug); 2807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2808 quirk_msi_intx_disable_bug); 2809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2810 quirk_msi_intx_disable_bug); 2811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2812 quirk_msi_intx_disable_qca_bug); 2813 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2814 quirk_msi_intx_disable_qca_bug); 2815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2816 quirk_msi_intx_disable_qca_bug); 2817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2818 quirk_msi_intx_disable_qca_bug); 2819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2820 quirk_msi_intx_disable_qca_bug); 2821 #endif /* CONFIG_PCI_MSI */ 2822 2823 /* Allow manual resource allocation for PCI hotplug bridges 2824 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2825 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2826 * kernel fails to allocate resources when hotplug device is 2827 * inserted and PCI bus is rescanned. 2828 */ 2829 static void quirk_hotplug_bridge(struct pci_dev *dev) 2830 { 2831 dev->is_hotplug_bridge = 1; 2832 } 2833 2834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2835 2836 /* 2837 * This is a quirk for the Ricoh MMC controller found as a part of 2838 * some mulifunction chips. 2839 2840 * This is very similar and based on the ricoh_mmc driver written by 2841 * Philip Langdale. Thank you for these magic sequences. 2842 * 2843 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2844 * and one or both of cardbus or firewire. 2845 * 2846 * It happens that they implement SD and MMC 2847 * support as separate controllers (and PCI functions). The linux SDHCI 2848 * driver supports MMC cards but the chip detects MMC cards in hardware 2849 * and directs them to the MMC controller - so the SDHCI driver never sees 2850 * them. 2851 * 2852 * To get around this, we must disable the useless MMC controller. 2853 * At that point, the SDHCI controller will start seeing them 2854 * It seems to be the case that the relevant PCI registers to deactivate the 2855 * MMC controller live on PCI function 0, which might be the cardbus controller 2856 * or the firewire controller, depending on the particular chip in question 2857 * 2858 * This has to be done early, because as soon as we disable the MMC controller 2859 * other pci functions shift up one level, e.g. function #2 becomes function 2860 * #1, and this will confuse the pci core. 2861 */ 2862 2863 #ifdef CONFIG_MMC_RICOH_MMC 2864 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2865 { 2866 /* disable via cardbus interface */ 2867 u8 write_enable; 2868 u8 write_target; 2869 u8 disable; 2870 2871 /* disable must be done via function #0 */ 2872 if (PCI_FUNC(dev->devfn)) 2873 return; 2874 2875 pci_read_config_byte(dev, 0xB7, &disable); 2876 if (disable & 0x02) 2877 return; 2878 2879 pci_read_config_byte(dev, 0x8E, &write_enable); 2880 pci_write_config_byte(dev, 0x8E, 0xAA); 2881 pci_read_config_byte(dev, 0x8D, &write_target); 2882 pci_write_config_byte(dev, 0x8D, 0xB7); 2883 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2884 pci_write_config_byte(dev, 0x8E, write_enable); 2885 pci_write_config_byte(dev, 0x8D, write_target); 2886 2887 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2888 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2889 } 2890 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2892 2893 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2894 { 2895 /* disable via firewire interface */ 2896 u8 write_enable; 2897 u8 disable; 2898 2899 /* disable must be done via function #0 */ 2900 if (PCI_FUNC(dev->devfn)) 2901 return; 2902 /* 2903 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2904 * certain types of SD/MMC cards. Lowering the SD base 2905 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2906 * 2907 * 0x150 - SD2.0 mode enable for changing base clock 2908 * frequency to 50Mhz 2909 * 0xe1 - Base clock frequency 2910 * 0x32 - 50Mhz new clock frequency 2911 * 0xf9 - Key register for 0x150 2912 * 0xfc - key register for 0xe1 2913 */ 2914 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2915 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2916 pci_write_config_byte(dev, 0xf9, 0xfc); 2917 pci_write_config_byte(dev, 0x150, 0x10); 2918 pci_write_config_byte(dev, 0xf9, 0x00); 2919 pci_write_config_byte(dev, 0xfc, 0x01); 2920 pci_write_config_byte(dev, 0xe1, 0x32); 2921 pci_write_config_byte(dev, 0xfc, 0x00); 2922 2923 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2924 } 2925 2926 pci_read_config_byte(dev, 0xCB, &disable); 2927 2928 if (disable & 0x02) 2929 return; 2930 2931 pci_read_config_byte(dev, 0xCA, &write_enable); 2932 pci_write_config_byte(dev, 0xCA, 0x57); 2933 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2934 pci_write_config_byte(dev, 0xCA, write_enable); 2935 2936 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2937 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2938 2939 } 2940 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2941 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2942 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2943 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2944 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2945 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2946 #endif /*CONFIG_MMC_RICOH_MMC*/ 2947 2948 #ifdef CONFIG_DMAR_TABLE 2949 #define VTUNCERRMSK_REG 0x1ac 2950 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2951 /* 2952 * This is a quirk for masking vt-d spec defined errors to platform error 2953 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2954 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2955 * on the RAS config settings of the platform) when a vt-d fault happens. 2956 * The resulting SMI caused the system to hang. 2957 * 2958 * VT-d spec related errors are already handled by the VT-d OS code, so no 2959 * need to report the same error through other channels. 2960 */ 2961 static void vtd_mask_spec_errors(struct pci_dev *dev) 2962 { 2963 u32 word; 2964 2965 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2966 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2967 } 2968 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2969 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2970 #endif 2971 2972 static void fixup_ti816x_class(struct pci_dev *dev) 2973 { 2974 u32 class = dev->class; 2975 2976 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2977 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 2978 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", 2979 class, dev->class); 2980 } 2981 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2982 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 2983 2984 /* Some PCIe devices do not work reliably with the claimed maximum 2985 * payload size supported. 2986 */ 2987 static void fixup_mpss_256(struct pci_dev *dev) 2988 { 2989 dev->pcie_mpss = 1; /* 256 bytes */ 2990 } 2991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2992 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2994 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2996 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2997 2998 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2999 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3000 * Since there is no way of knowing what the PCIE MPS on each fabric will be 3001 * until all of the devices are discovered and buses walked, read completion 3002 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3003 * it is possible to hotplug a device with MPS of 256B. 3004 */ 3005 static void quirk_intel_mc_errata(struct pci_dev *dev) 3006 { 3007 int err; 3008 u16 rcc; 3009 3010 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3011 pcie_bus_config == PCIE_BUS_DEFAULT) 3012 return; 3013 3014 /* Intel errata specifies bits to change but does not say what they are. 3015 * Keeping them magical until such time as the registers and values can 3016 * be explained. 3017 */ 3018 err = pci_read_config_word(dev, 0x48, &rcc); 3019 if (err) { 3020 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 3021 return; 3022 } 3023 3024 if (!(rcc & (1 << 10))) 3025 return; 3026 3027 rcc &= ~(1 << 10); 3028 3029 err = pci_write_config_word(dev, 0x48, rcc); 3030 if (err) { 3031 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 3032 return; 3033 } 3034 3035 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 3036 } 3037 /* Intel 5000 series memory controllers and ports 2-7 */ 3038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3040 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3041 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3043 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3045 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3052 /* Intel 5100 series memory controllers and ports 2-7 */ 3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3064 3065 3066 /* 3067 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 3068 * work around this, query the size it should be configured to by the device and 3069 * modify the resource end to correspond to this new size. 3070 */ 3071 static void quirk_intel_ntb(struct pci_dev *dev) 3072 { 3073 int rc; 3074 u8 val; 3075 3076 rc = pci_read_config_byte(dev, 0x00D0, &val); 3077 if (rc) 3078 return; 3079 3080 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3081 3082 rc = pci_read_config_byte(dev, 0x00D1, &val); 3083 if (rc) 3084 return; 3085 3086 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3087 } 3088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3090 3091 static ktime_t fixup_debug_start(struct pci_dev *dev, 3092 void (*fn)(struct pci_dev *dev)) 3093 { 3094 ktime_t calltime = 0; 3095 3096 dev_dbg(&dev->dev, "calling %pF\n", fn); 3097 if (initcall_debug) { 3098 pr_debug("calling %pF @ %i for %s\n", 3099 fn, task_pid_nr(current), dev_name(&dev->dev)); 3100 calltime = ktime_get(); 3101 } 3102 3103 return calltime; 3104 } 3105 3106 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 3107 void (*fn)(struct pci_dev *dev)) 3108 { 3109 ktime_t delta, rettime; 3110 unsigned long long duration; 3111 3112 if (initcall_debug) { 3113 rettime = ktime_get(); 3114 delta = ktime_sub(rettime, calltime); 3115 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 3116 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 3117 fn, duration, dev_name(&dev->dev)); 3118 } 3119 } 3120 3121 /* 3122 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3123 * even though no one is handling them (f.e. i915 driver is never loaded). 3124 * Additionally the interrupt destination is not set up properly 3125 * and the interrupt ends up -somewhere-. 3126 * 3127 * These spurious interrupts are "sticky" and the kernel disables 3128 * the (shared) interrupt line after 100.000+ generated interrupts. 3129 * 3130 * Fix it by disabling the still enabled interrupts. 3131 * This resolves crashes often seen on monitor unplug. 3132 */ 3133 #define I915_DEIER_REG 0x4400c 3134 static void disable_igfx_irq(struct pci_dev *dev) 3135 { 3136 void __iomem *regs = pci_iomap(dev, 0, 0); 3137 if (regs == NULL) { 3138 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 3139 return; 3140 } 3141 3142 /* Check if any interrupt line is still enabled */ 3143 if (readl(regs + I915_DEIER_REG) != 0) { 3144 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3145 3146 writel(0, regs + I915_DEIER_REG); 3147 } 3148 3149 pci_iounmap(dev, regs); 3150 } 3151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3154 3155 /* 3156 * PCI devices which are on Intel chips can skip the 10ms delay 3157 * before entering D3 mode. 3158 */ 3159 static void quirk_remove_d3_delay(struct pci_dev *dev) 3160 { 3161 dev->d3_delay = 0; 3162 } 3163 /* C600 Series devices do not need 10ms d3_delay */ 3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3167 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ 3168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3169 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3179 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3189 3190 /* 3191 * Some devices may pass our check in pci_intx_mask_supported() if 3192 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3193 * support this feature. 3194 */ 3195 static void quirk_broken_intx_masking(struct pci_dev *dev) 3196 { 3197 dev->broken_intx_masking = 1; 3198 } 3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3200 quirk_broken_intx_masking); 3201 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3202 quirk_broken_intx_masking); 3203 3204 /* 3205 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3206 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3207 * 3208 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3209 */ 3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3211 quirk_broken_intx_masking); 3212 3213 /* 3214 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3215 * DisINTx can be set but the interrupt status bit is non-functional. 3216 */ 3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, 3218 quirk_broken_intx_masking); 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, 3220 quirk_broken_intx_masking); 3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, 3222 quirk_broken_intx_masking); 3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, 3224 quirk_broken_intx_masking); 3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, 3226 quirk_broken_intx_masking); 3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, 3228 quirk_broken_intx_masking); 3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, 3230 quirk_broken_intx_masking); 3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, 3232 quirk_broken_intx_masking); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, 3234 quirk_broken_intx_masking); 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, 3236 quirk_broken_intx_masking); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, 3238 quirk_broken_intx_masking); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, 3240 quirk_broken_intx_masking); 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, 3242 quirk_broken_intx_masking); 3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, 3244 quirk_broken_intx_masking); 3245 3246 static u16 mellanox_broken_intx_devs[] = { 3247 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3248 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3249 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3250 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3251 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3252 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3253 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3254 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3255 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3256 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3257 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3258 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3259 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3260 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3261 }; 3262 3263 #define CONNECTX_4_CURR_MAX_MINOR 99 3264 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3265 3266 /* 3267 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3268 * If so, don't mark it as broken. 3269 * FW minor > 99 means older FW version format and no INTx masking support. 3270 * FW minor < 14 means new FW version format and no INTx masking support. 3271 */ 3272 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3273 { 3274 __be32 __iomem *fw_ver; 3275 u16 fw_major; 3276 u16 fw_minor; 3277 u16 fw_subminor; 3278 u32 fw_maj_min; 3279 u32 fw_sub_min; 3280 int i; 3281 3282 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3283 if (pdev->device == mellanox_broken_intx_devs[i]) { 3284 pdev->broken_intx_masking = 1; 3285 return; 3286 } 3287 } 3288 3289 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx 3290 * support so shouldn't be checked further 3291 */ 3292 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3293 return; 3294 3295 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3296 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3297 return; 3298 3299 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3300 if (pci_enable_device_mem(pdev)) { 3301 dev_warn(&pdev->dev, "Can't enable device memory\n"); 3302 return; 3303 } 3304 3305 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3306 if (!fw_ver) { 3307 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n"); 3308 goto out; 3309 } 3310 3311 /* Reading from resource space should be 32b aligned */ 3312 fw_maj_min = ioread32be(fw_ver); 3313 fw_sub_min = ioread32be(fw_ver + 1); 3314 fw_major = fw_maj_min & 0xffff; 3315 fw_minor = fw_maj_min >> 16; 3316 fw_subminor = fw_sub_min & 0xffff; 3317 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3318 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3319 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3320 fw_major, fw_minor, fw_subminor, pdev->device == 3321 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3322 pdev->broken_intx_masking = 1; 3323 } 3324 3325 iounmap(fw_ver); 3326 3327 out: 3328 pci_disable_device(pdev); 3329 } 3330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3331 mellanox_check_broken_intx_masking); 3332 3333 static void quirk_no_bus_reset(struct pci_dev *dev) 3334 { 3335 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3336 } 3337 3338 /* 3339 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3340 * The device will throw a Link Down error on AER-capable systems and 3341 * regardless of AER, config space of the device is never accessible again 3342 * and typically causes the system to hang or reset when access is attempted. 3343 * http://www.spinics.net/lists/linux-pci/msg34797.html 3344 */ 3345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3349 3350 static void quirk_no_pm_reset(struct pci_dev *dev) 3351 { 3352 /* 3353 * We can't do a bus reset on root bus devices, but an ineffective 3354 * PM reset may be better than nothing. 3355 */ 3356 if (!pci_is_root_bus(dev->bus)) 3357 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3358 } 3359 3360 /* 3361 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3362 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3363 * to have no effect on the device: it retains the framebuffer contents and 3364 * monitor sync. Advertising this support makes other layers, like VFIO, 3365 * assume pci_reset_function() is viable for this device. Mark it as 3366 * unavailable to skip it when testing reset methods. 3367 */ 3368 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3369 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3370 3371 /* 3372 * Thunderbolt controllers with broken MSI hotplug signaling: 3373 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3374 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3375 */ 3376 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3377 { 3378 if (pdev->is_hotplug_bridge && 3379 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3380 pdev->revision <= 1)) 3381 pdev->no_msi = 1; 3382 } 3383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3384 quirk_thunderbolt_hotplug_msi); 3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3386 quirk_thunderbolt_hotplug_msi); 3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3388 quirk_thunderbolt_hotplug_msi); 3389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3390 quirk_thunderbolt_hotplug_msi); 3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3392 quirk_thunderbolt_hotplug_msi); 3393 3394 static void quirk_chelsio_extend_vpd(struct pci_dev *dev) 3395 { 3396 pci_set_vpd_size(dev, 8192); 3397 } 3398 3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd); 3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd); 3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd); 3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd); 3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd); 3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd); 3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd); 3406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd); 3407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd); 3408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd); 3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd); 3410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd); 3411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd); 3412 3413 #ifdef CONFIG_ACPI 3414 /* 3415 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3416 * 3417 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3418 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3419 * be present after resume if a device was plugged in before suspend. 3420 * 3421 * The thunderbolt controller consists of a pcie switch with downstream 3422 * bridges leading to the NHI and to the tunnel pci bridges. 3423 * 3424 * This quirk cuts power to the whole chip. Therefore we have to apply it 3425 * during suspend_noirq of the upstream bridge. 3426 * 3427 * Power is automagically restored before resume. No action is needed. 3428 */ 3429 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3430 { 3431 acpi_handle bridge, SXIO, SXFP, SXLV; 3432 3433 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3434 return; 3435 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3436 return; 3437 bridge = ACPI_HANDLE(&dev->dev); 3438 if (!bridge) 3439 return; 3440 /* 3441 * SXIO and SXLV are present only on machines requiring this quirk. 3442 * TB bridges in external devices might have the same device id as those 3443 * on the host, but they will not have the associated ACPI methods. This 3444 * implicitly checks that we are at the right bridge. 3445 */ 3446 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3447 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3448 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3449 return; 3450 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3451 3452 /* magic sequence */ 3453 acpi_execute_simple_method(SXIO, NULL, 1); 3454 acpi_execute_simple_method(SXFP, NULL, 0); 3455 msleep(300); 3456 acpi_execute_simple_method(SXLV, NULL, 0); 3457 acpi_execute_simple_method(SXIO, NULL, 0); 3458 acpi_execute_simple_method(SXLV, NULL, 0); 3459 } 3460 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3461 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3462 quirk_apple_poweroff_thunderbolt); 3463 3464 /* 3465 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3466 * 3467 * During suspend the thunderbolt controller is reset and all pci 3468 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3469 * during resume. We have to manually wait for the NHI since there is 3470 * no parent child relationship between the NHI and the tunneled 3471 * bridges. 3472 */ 3473 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3474 { 3475 struct pci_dev *sibling = NULL; 3476 struct pci_dev *nhi = NULL; 3477 3478 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3479 return; 3480 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3481 return; 3482 /* 3483 * Find the NHI and confirm that we are a bridge on the tb host 3484 * controller and not on a tb endpoint. 3485 */ 3486 sibling = pci_get_slot(dev->bus, 0x0); 3487 if (sibling == dev) 3488 goto out; /* we are the downstream bridge to the NHI */ 3489 if (!sibling || !sibling->subordinate) 3490 goto out; 3491 nhi = pci_get_slot(sibling->subordinate, 0x0); 3492 if (!nhi) 3493 goto out; 3494 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3495 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && 3496 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && 3497 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && 3498 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3499 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3500 goto out; 3501 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3502 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3503 out: 3504 pci_dev_put(nhi); 3505 pci_dev_put(sibling); 3506 } 3507 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3508 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3509 quirk_apple_wait_for_thunderbolt); 3510 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3511 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3512 quirk_apple_wait_for_thunderbolt); 3513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3514 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, 3515 quirk_apple_wait_for_thunderbolt); 3516 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3517 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, 3518 quirk_apple_wait_for_thunderbolt); 3519 #endif 3520 3521 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3522 struct pci_fixup *end) 3523 { 3524 ktime_t calltime; 3525 3526 for (; f < end; f++) 3527 if ((f->class == (u32) (dev->class >> f->class_shift) || 3528 f->class == (u32) PCI_ANY_ID) && 3529 (f->vendor == dev->vendor || 3530 f->vendor == (u16) PCI_ANY_ID) && 3531 (f->device == dev->device || 3532 f->device == (u16) PCI_ANY_ID)) { 3533 calltime = fixup_debug_start(dev, f->hook); 3534 f->hook(dev); 3535 fixup_debug_report(dev, calltime, f->hook); 3536 } 3537 } 3538 3539 extern struct pci_fixup __start_pci_fixups_early[]; 3540 extern struct pci_fixup __end_pci_fixups_early[]; 3541 extern struct pci_fixup __start_pci_fixups_header[]; 3542 extern struct pci_fixup __end_pci_fixups_header[]; 3543 extern struct pci_fixup __start_pci_fixups_final[]; 3544 extern struct pci_fixup __end_pci_fixups_final[]; 3545 extern struct pci_fixup __start_pci_fixups_enable[]; 3546 extern struct pci_fixup __end_pci_fixups_enable[]; 3547 extern struct pci_fixup __start_pci_fixups_resume[]; 3548 extern struct pci_fixup __end_pci_fixups_resume[]; 3549 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3550 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3551 extern struct pci_fixup __start_pci_fixups_suspend[]; 3552 extern struct pci_fixup __end_pci_fixups_suspend[]; 3553 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3554 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3555 3556 static bool pci_apply_fixup_final_quirks; 3557 3558 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3559 { 3560 struct pci_fixup *start, *end; 3561 3562 switch (pass) { 3563 case pci_fixup_early: 3564 start = __start_pci_fixups_early; 3565 end = __end_pci_fixups_early; 3566 break; 3567 3568 case pci_fixup_header: 3569 start = __start_pci_fixups_header; 3570 end = __end_pci_fixups_header; 3571 break; 3572 3573 case pci_fixup_final: 3574 if (!pci_apply_fixup_final_quirks) 3575 return; 3576 start = __start_pci_fixups_final; 3577 end = __end_pci_fixups_final; 3578 break; 3579 3580 case pci_fixup_enable: 3581 start = __start_pci_fixups_enable; 3582 end = __end_pci_fixups_enable; 3583 break; 3584 3585 case pci_fixup_resume: 3586 start = __start_pci_fixups_resume; 3587 end = __end_pci_fixups_resume; 3588 break; 3589 3590 case pci_fixup_resume_early: 3591 start = __start_pci_fixups_resume_early; 3592 end = __end_pci_fixups_resume_early; 3593 break; 3594 3595 case pci_fixup_suspend: 3596 start = __start_pci_fixups_suspend; 3597 end = __end_pci_fixups_suspend; 3598 break; 3599 3600 case pci_fixup_suspend_late: 3601 start = __start_pci_fixups_suspend_late; 3602 end = __end_pci_fixups_suspend_late; 3603 break; 3604 3605 default: 3606 /* stupid compiler warning, you would think with an enum... */ 3607 return; 3608 } 3609 pci_do_fixups(dev, start, end); 3610 } 3611 EXPORT_SYMBOL(pci_fixup_device); 3612 3613 3614 static int __init pci_apply_final_quirks(void) 3615 { 3616 struct pci_dev *dev = NULL; 3617 u8 cls = 0; 3618 u8 tmp; 3619 3620 if (pci_cache_line_size) 3621 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3622 pci_cache_line_size << 2); 3623 3624 pci_apply_fixup_final_quirks = true; 3625 for_each_pci_dev(dev) { 3626 pci_fixup_device(pci_fixup_final, dev); 3627 /* 3628 * If arch hasn't set it explicitly yet, use the CLS 3629 * value shared by all PCI devices. If there's a 3630 * mismatch, fall back to the default value. 3631 */ 3632 if (!pci_cache_line_size) { 3633 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3634 if (!cls) 3635 cls = tmp; 3636 if (!tmp || cls == tmp) 3637 continue; 3638 3639 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3640 cls << 2, tmp << 2, 3641 pci_dfl_cache_line_size << 2); 3642 pci_cache_line_size = pci_dfl_cache_line_size; 3643 } 3644 } 3645 3646 if (!pci_cache_line_size) { 3647 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3648 cls << 2, pci_dfl_cache_line_size << 2); 3649 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3650 } 3651 3652 return 0; 3653 } 3654 3655 fs_initcall_sync(pci_apply_final_quirks); 3656 3657 /* 3658 * Following are device-specific reset methods which can be used to 3659 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3660 * not available. 3661 */ 3662 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3663 { 3664 /* 3665 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3666 * 3667 * The 82599 supports FLR on VFs, but FLR support is reported only 3668 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3669 * Thus we must call pcie_flr() directly without first checking if it is 3670 * supported. 3671 */ 3672 if (!probe) 3673 pcie_flr(dev); 3674 return 0; 3675 } 3676 3677 #define SOUTH_CHICKEN2 0xc2004 3678 #define PCH_PP_STATUS 0xc7200 3679 #define PCH_PP_CONTROL 0xc7204 3680 #define MSG_CTL 0x45010 3681 #define NSDE_PWR_STATE 0xd0100 3682 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3683 3684 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3685 { 3686 void __iomem *mmio_base; 3687 unsigned long timeout; 3688 u32 val; 3689 3690 if (probe) 3691 return 0; 3692 3693 mmio_base = pci_iomap(dev, 0, 0); 3694 if (!mmio_base) 3695 return -ENOMEM; 3696 3697 iowrite32(0x00000002, mmio_base + MSG_CTL); 3698 3699 /* 3700 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3701 * driver loaded sets the right bits. However, this's a reset and 3702 * the bits have been set by i915 previously, so we clobber 3703 * SOUTH_CHICKEN2 register directly here. 3704 */ 3705 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3706 3707 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3708 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3709 3710 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3711 do { 3712 val = ioread32(mmio_base + PCH_PP_STATUS); 3713 if ((val & 0xb0000000) == 0) 3714 goto reset_complete; 3715 msleep(10); 3716 } while (time_before(jiffies, timeout)); 3717 dev_warn(&dev->dev, "timeout during reset\n"); 3718 3719 reset_complete: 3720 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3721 3722 pci_iounmap(dev, mmio_base); 3723 return 0; 3724 } 3725 3726 /* 3727 * Device-specific reset method for Chelsio T4-based adapters. 3728 */ 3729 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3730 { 3731 u16 old_command; 3732 u16 msix_flags; 3733 3734 /* 3735 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3736 * that we have no device-specific reset method. 3737 */ 3738 if ((dev->device & 0xf000) != 0x4000) 3739 return -ENOTTY; 3740 3741 /* 3742 * If this is the "probe" phase, return 0 indicating that we can 3743 * reset this device. 3744 */ 3745 if (probe) 3746 return 0; 3747 3748 /* 3749 * T4 can wedge if there are DMAs in flight within the chip and Bus 3750 * Master has been disabled. We need to have it on till the Function 3751 * Level Reset completes. (BUS_MASTER is disabled in 3752 * pci_reset_function()). 3753 */ 3754 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3755 pci_write_config_word(dev, PCI_COMMAND, 3756 old_command | PCI_COMMAND_MASTER); 3757 3758 /* 3759 * Perform the actual device function reset, saving and restoring 3760 * configuration information around the reset. 3761 */ 3762 pci_save_state(dev); 3763 3764 /* 3765 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3766 * are disabled when an MSI-X interrupt message needs to be delivered. 3767 * So we briefly re-enable MSI-X interrupts for the duration of the 3768 * FLR. The pci_restore_state() below will restore the original 3769 * MSI-X state. 3770 */ 3771 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3772 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3773 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3774 msix_flags | 3775 PCI_MSIX_FLAGS_ENABLE | 3776 PCI_MSIX_FLAGS_MASKALL); 3777 3778 pcie_flr(dev); 3779 3780 /* 3781 * Restore the configuration information (BAR values, etc.) including 3782 * the original PCI Configuration Space Command word, and return 3783 * success. 3784 */ 3785 pci_restore_state(dev); 3786 pci_write_config_word(dev, PCI_COMMAND, old_command); 3787 return 0; 3788 } 3789 3790 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3791 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3792 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3793 3794 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3795 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3796 reset_intel_82599_sfp_virtfn }, 3797 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3798 reset_ivb_igd }, 3799 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3800 reset_ivb_igd }, 3801 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3802 reset_chelsio_generic_dev }, 3803 { 0 } 3804 }; 3805 3806 /* 3807 * These device-specific reset methods are here rather than in a driver 3808 * because when a host assigns a device to a guest VM, the host may need 3809 * to reset the device but probably doesn't have a driver for it. 3810 */ 3811 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3812 { 3813 const struct pci_dev_reset_methods *i; 3814 3815 for (i = pci_dev_reset_methods; i->reset; i++) { 3816 if ((i->vendor == dev->vendor || 3817 i->vendor == (u16)PCI_ANY_ID) && 3818 (i->device == dev->device || 3819 i->device == (u16)PCI_ANY_ID)) 3820 return i->reset(dev, probe); 3821 } 3822 3823 return -ENOTTY; 3824 } 3825 3826 static void quirk_dma_func0_alias(struct pci_dev *dev) 3827 { 3828 if (PCI_FUNC(dev->devfn) != 0) 3829 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3830 } 3831 3832 /* 3833 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3834 * 3835 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3836 */ 3837 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3838 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3839 3840 static void quirk_dma_func1_alias(struct pci_dev *dev) 3841 { 3842 if (PCI_FUNC(dev->devfn) != 1) 3843 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); 3844 } 3845 3846 /* 3847 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3848 * SKUs function 1 is present and is a legacy IDE controller, in other 3849 * SKUs this function is not present, making this a ghost requester. 3850 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3851 */ 3852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3853 quirk_dma_func1_alias); 3854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3855 quirk_dma_func1_alias); 3856 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3858 quirk_dma_func1_alias); 3859 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3861 quirk_dma_func1_alias); 3862 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3864 quirk_dma_func1_alias); 3865 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3867 quirk_dma_func1_alias); 3868 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3870 quirk_dma_func1_alias); 3871 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3873 quirk_dma_func1_alias); 3874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3875 quirk_dma_func1_alias); 3876 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3878 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3879 quirk_dma_func1_alias); 3880 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 3881 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 3882 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 3883 quirk_dma_func1_alias); 3884 3885 /* 3886 * Some devices DMA with the wrong devfn, not just the wrong function. 3887 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3888 * the alias is "fixed" and independent of the device devfn. 3889 * 3890 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3891 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3892 * single device on the secondary bus. In reality, the single exposed 3893 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3894 * that provides a bridge to the internal bus of the I/O processor. The 3895 * controller supports private devices, which can be hidden from PCI config 3896 * space. In the case of the Adaptec 3405, a private device at 01.0 3897 * appears to be the DMA engine, which therefore needs to become a DMA 3898 * alias for the device. 3899 */ 3900 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3901 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3902 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3903 .driver_data = PCI_DEVFN(1, 0) }, 3904 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3905 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 3906 .driver_data = PCI_DEVFN(1, 0) }, 3907 { 0 } 3908 }; 3909 3910 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3911 { 3912 const struct pci_device_id *id; 3913 3914 id = pci_match_id(fixed_dma_alias_tbl, dev); 3915 if (id) 3916 pci_add_dma_alias(dev, id->driver_data); 3917 } 3918 3919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3920 3921 /* 3922 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3923 * using the wrong DMA alias for the device. Some of these devices can be 3924 * used as either forward or reverse bridges, so we need to test whether the 3925 * device is operating in the correct mode. We could probably apply this 3926 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3927 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3928 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3929 */ 3930 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3931 { 3932 if (!pci_is_root_bus(pdev->bus) && 3933 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3934 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3935 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3936 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3937 } 3938 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3940 quirk_use_pcie_bridge_dma_alias); 3941 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3942 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3943 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3944 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3945 /* ITE 8893 has the same problem as the 8892 */ 3946 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 3947 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3948 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3949 3950 /* 3951 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 3952 * be added as aliases to the DMA device in order to allow buffer access 3953 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 3954 * programmed in the EEPROM. 3955 */ 3956 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 3957 { 3958 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); 3959 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); 3960 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); 3961 } 3962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 3963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 3964 3965 /* 3966 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 3967 * associated not at the root bus, but at a bridge below. This quirk avoids 3968 * generating invalid DMA aliases. 3969 */ 3970 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 3971 { 3972 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 3973 } 3974 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 3975 quirk_bridge_cavm_thrx2_pcie_root); 3976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 3977 quirk_bridge_cavm_thrx2_pcie_root); 3978 3979 /* 3980 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 3981 * class code. Fix it. 3982 */ 3983 static void quirk_tw686x_class(struct pci_dev *pdev) 3984 { 3985 u32 class = pdev->class; 3986 3987 /* Use "Multimedia controller" class */ 3988 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 3989 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 3990 class, pdev->class); 3991 } 3992 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 3993 quirk_tw686x_class); 3994 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 3995 quirk_tw686x_class); 3996 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 3997 quirk_tw686x_class); 3998 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 3999 quirk_tw686x_class); 4000 4001 /* 4002 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4003 * values for the Attribute as were supplied in the header of the 4004 * corresponding Request, except as explicitly allowed when IDO is used." 4005 * 4006 * If a non-compliant device generates a completion with a different 4007 * attribute than the request, the receiver may accept it (which itself 4008 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4009 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4010 * device access timeout. 4011 * 4012 * If the non-compliant device generates completions with zero attributes 4013 * (instead of copying the attributes from the request), we can work around 4014 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4015 * upstream devices so they always generate requests with zero attributes. 4016 * 4017 * This affects other devices under the same Root Port, but since these 4018 * attributes are performance hints, there should be no functional problem. 4019 * 4020 * Note that Configuration Space accesses are never supposed to have TLP 4021 * Attributes, so we're safe waiting till after any Configuration Space 4022 * accesses to do the Root Port fixup. 4023 */ 4024 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4025 { 4026 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 4027 4028 if (!root_port) { 4029 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n"); 4030 return; 4031 } 4032 4033 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4034 dev_name(&pdev->dev)); 4035 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4036 PCI_EXP_DEVCTL_RELAX_EN | 4037 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4038 } 4039 4040 /* 4041 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4042 * Completion it generates. 4043 */ 4044 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4045 { 4046 /* 4047 * This mask/compare operation selects for Physical Function 4 on a 4048 * T5. We only need to fix up the Root Port once for any of the 4049 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4050 * 0x54xx so we use that one, 4051 */ 4052 if ((pdev->device & 0xff00) == 0x5400) 4053 quirk_disable_root_port_attributes(pdev); 4054 } 4055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4056 quirk_chelsio_T5_disable_root_port_attributes); 4057 4058 /* 4059 * AMD has indicated that the devices below do not support peer-to-peer 4060 * in any system where they are found in the southbridge with an AMD 4061 * IOMMU in the system. Multifunction devices that do not support 4062 * peer-to-peer between functions can claim to support a subset of ACS. 4063 * Such devices effectively enable request redirect (RR) and completion 4064 * redirect (CR) since all transactions are redirected to the upstream 4065 * root complex. 4066 * 4067 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 4068 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 4069 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 4070 * 4071 * 1002:4385 SBx00 SMBus Controller 4072 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4073 * 1002:4383 SBx00 Azalia (Intel HDA) 4074 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4075 * 1002:4384 SBx00 PCI to PCI Bridge 4076 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4077 * 4078 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4079 * 4080 * 1022:780f [AMD] FCH PCI Bridge 4081 * 1022:7809 [AMD] FCH USB OHCI Controller 4082 */ 4083 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4084 { 4085 #ifdef CONFIG_ACPI 4086 struct acpi_table_header *header = NULL; 4087 acpi_status status; 4088 4089 /* Targeting multifunction devices on the SB (appears on root bus) */ 4090 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4091 return -ENODEV; 4092 4093 /* The IVRS table describes the AMD IOMMU */ 4094 status = acpi_get_table("IVRS", 0, &header); 4095 if (ACPI_FAILURE(status)) 4096 return -ENODEV; 4097 4098 /* Filter out flags not applicable to multifunction */ 4099 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4100 4101 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 4102 #else 4103 return -ENODEV; 4104 #endif 4105 } 4106 4107 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4108 { 4109 /* 4110 * Cavium devices matching this quirk do not perform peer-to-peer 4111 * with other functions, allowing masking out these bits as if they 4112 * were unimplemented in the ACS capability. 4113 */ 4114 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4115 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4116 4117 if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff))) 4118 return -ENOTTY; 4119 4120 return acs_flags ? 0 : 1; 4121 } 4122 4123 /* 4124 * Many Intel PCH root ports do provide ACS-like features to disable peer 4125 * transactions and validate bus numbers in requests, but do not provide an 4126 * actual PCIe ACS capability. This is the list of device IDs known to fall 4127 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4128 */ 4129 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4130 /* Ibexpeak PCH */ 4131 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4132 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4133 /* Cougarpoint PCH */ 4134 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4135 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4136 /* Pantherpoint PCH */ 4137 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4138 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4139 /* Lynxpoint-H PCH */ 4140 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4141 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4142 /* Lynxpoint-LP PCH */ 4143 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4144 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4145 /* Wildcat PCH */ 4146 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4147 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4148 /* Patsburg (X79) PCH */ 4149 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4150 /* Wellsburg (X99) PCH */ 4151 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4152 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4153 /* Lynx Point (9 series) PCH */ 4154 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4155 }; 4156 4157 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4158 { 4159 int i; 4160 4161 /* Filter out a few obvious non-matches first */ 4162 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4163 return false; 4164 4165 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4166 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4167 return true; 4168 4169 return false; 4170 } 4171 4172 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 4173 4174 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4175 { 4176 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 4177 INTEL_PCH_ACS_FLAGS : 0; 4178 4179 if (!pci_quirk_intel_pch_acs_match(dev)) 4180 return -ENOTTY; 4181 4182 return acs_flags & ~flags ? 0 : 1; 4183 } 4184 4185 /* 4186 * These QCOM root ports do provide ACS-like features to disable peer 4187 * transactions and validate bus numbers in requests, but do not provide an 4188 * actual PCIe ACS capability. Hardware supports source validation but it 4189 * will report the issue as Completer Abort instead of ACS Violation. 4190 * Hardware doesn't support peer-to-peer and each root port is a root 4191 * complex with unique segment numbers. It is not possible for one root 4192 * port to pass traffic to another root port. All PCIe transactions are 4193 * terminated inside the root port. 4194 */ 4195 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4196 { 4197 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4198 int ret = acs_flags & ~flags ? 0 : 1; 4199 4200 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); 4201 4202 return ret; 4203 } 4204 4205 /* 4206 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4207 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4208 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4209 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4210 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4211 * control register is at offset 8 instead of 6 and we should probably use 4212 * dword accesses to them. This applies to the following PCI Device IDs, as 4213 * found in volume 1 of the datasheet[2]: 4214 * 4215 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4216 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4217 * 4218 * N.B. This doesn't fix what lspci shows. 4219 * 4220 * The 100 series chipset specification update includes this as errata #23[3]. 4221 * 4222 * The 200 series chipset (Union Point) has the same bug according to the 4223 * specification update (Intel 200 Series Chipset Family Platform Controller 4224 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4225 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4226 * chipset include: 4227 * 4228 * 0xa290-0xa29f PCI Express Root port #{0-16} 4229 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4230 * 4231 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4232 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4233 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4234 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4235 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4236 */ 4237 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4238 { 4239 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4240 return false; 4241 4242 switch (dev->device) { 4243 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4244 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4245 return true; 4246 } 4247 4248 return false; 4249 } 4250 4251 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4252 4253 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4254 { 4255 int pos; 4256 u32 cap, ctrl; 4257 4258 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4259 return -ENOTTY; 4260 4261 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4262 if (!pos) 4263 return -ENOTTY; 4264 4265 /* see pci_acs_flags_enabled() */ 4266 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4267 acs_flags &= (cap | PCI_ACS_EC); 4268 4269 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4270 4271 return acs_flags & ~ctrl ? 0 : 1; 4272 } 4273 4274 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4275 { 4276 /* 4277 * SV, TB, and UF are not relevant to multifunction endpoints. 4278 * 4279 * Multifunction devices are only required to implement RR, CR, and DT 4280 * in their ACS capability if they support peer-to-peer transactions. 4281 * Devices matching this quirk have been verified by the vendor to not 4282 * perform peer-to-peer with other functions, allowing us to mask out 4283 * these bits as if they were unimplemented in the ACS capability. 4284 */ 4285 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4286 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4287 4288 return acs_flags ? 0 : 1; 4289 } 4290 4291 static const struct pci_dev_acs_enabled { 4292 u16 vendor; 4293 u16 device; 4294 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4295 } pci_dev_acs_enabled[] = { 4296 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4297 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4298 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4299 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4300 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4301 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4302 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4303 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4304 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4305 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4306 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4307 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4308 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4309 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4310 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4311 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4312 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4313 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4314 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4315 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4316 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4317 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4318 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4319 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4320 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4321 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4322 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4323 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4324 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4325 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4326 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4327 /* 82580 */ 4328 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4329 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4330 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4331 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4332 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4333 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4334 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4335 /* 82576 */ 4336 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4337 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4338 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4339 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4340 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4341 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4342 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4343 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4344 /* 82575 */ 4345 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4346 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4347 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4348 /* I350 */ 4349 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4350 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4351 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4352 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4353 /* 82571 (Quads omitted due to non-ACS switch) */ 4354 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4355 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4356 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4357 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4358 /* I219 */ 4359 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4360 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4361 /* QCOM QDF2xxx root ports */ 4362 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs }, 4363 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs }, 4364 /* Intel PCH root ports */ 4365 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4366 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4367 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4368 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4369 /* Cavium ThunderX */ 4370 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4371 { 0 } 4372 }; 4373 4374 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4375 { 4376 const struct pci_dev_acs_enabled *i; 4377 int ret; 4378 4379 /* 4380 * Allow devices that do not expose standard PCIe ACS capabilities 4381 * or control to indicate their support here. Multi-function express 4382 * devices which do not allow internal peer-to-peer between functions, 4383 * but do not implement PCIe ACS may wish to return true here. 4384 */ 4385 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4386 if ((i->vendor == dev->vendor || 4387 i->vendor == (u16)PCI_ANY_ID) && 4388 (i->device == dev->device || 4389 i->device == (u16)PCI_ANY_ID)) { 4390 ret = i->acs_enabled(dev, acs_flags); 4391 if (ret >= 0) 4392 return ret; 4393 } 4394 } 4395 4396 return -ENOTTY; 4397 } 4398 4399 /* Config space offset of Root Complex Base Address register */ 4400 #define INTEL_LPC_RCBA_REG 0xf0 4401 /* 31:14 RCBA address */ 4402 #define INTEL_LPC_RCBA_MASK 0xffffc000 4403 /* RCBA Enable */ 4404 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4405 4406 /* Backbone Scratch Pad Register */ 4407 #define INTEL_BSPR_REG 0x1104 4408 /* Backbone Peer Non-Posted Disable */ 4409 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4410 /* Backbone Peer Posted Disable */ 4411 #define INTEL_BSPR_REG_BPPD (1 << 9) 4412 4413 /* Upstream Peer Decode Configuration Register */ 4414 #define INTEL_UPDCR_REG 0x1114 4415 /* 5:0 Peer Decode Enable bits */ 4416 #define INTEL_UPDCR_REG_MASK 0x3f 4417 4418 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4419 { 4420 u32 rcba, bspr, updcr; 4421 void __iomem *rcba_mem; 4422 4423 /* 4424 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4425 * are D28:F* and therefore get probed before LPC, thus we can't 4426 * use pci_get_slot/pci_read_config_dword here. 4427 */ 4428 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4429 INTEL_LPC_RCBA_REG, &rcba); 4430 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4431 return -EINVAL; 4432 4433 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 4434 PAGE_ALIGN(INTEL_UPDCR_REG)); 4435 if (!rcba_mem) 4436 return -ENOMEM; 4437 4438 /* 4439 * The BSPR can disallow peer cycles, but it's set by soft strap and 4440 * therefore read-only. If both posted and non-posted peer cycles are 4441 * disallowed, we're ok. If either are allowed, then we need to use 4442 * the UPDCR to disable peer decodes for each port. This provides the 4443 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4444 */ 4445 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4446 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4447 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4448 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4449 if (updcr & INTEL_UPDCR_REG_MASK) { 4450 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 4451 updcr &= ~INTEL_UPDCR_REG_MASK; 4452 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4453 } 4454 } 4455 4456 iounmap(rcba_mem); 4457 return 0; 4458 } 4459 4460 /* Miscellaneous Port Configuration register */ 4461 #define INTEL_MPC_REG 0xd8 4462 /* MPC: Invalid Receive Bus Number Check Enable */ 4463 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4464 4465 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4466 { 4467 u32 mpc; 4468 4469 /* 4470 * When enabled, the IRBNCE bit of the MPC register enables the 4471 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4472 * ensures that requester IDs fall within the bus number range 4473 * of the bridge. Enable if not already. 4474 */ 4475 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4476 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4477 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 4478 mpc |= INTEL_MPC_REG_IRBNCE; 4479 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4480 } 4481 } 4482 4483 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4484 { 4485 if (!pci_quirk_intel_pch_acs_match(dev)) 4486 return -ENOTTY; 4487 4488 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4489 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 4490 return 0; 4491 } 4492 4493 pci_quirk_enable_intel_rp_mpc_acs(dev); 4494 4495 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4496 4497 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 4498 4499 return 0; 4500 } 4501 4502 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4503 { 4504 int pos; 4505 u32 cap, ctrl; 4506 4507 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4508 return -ENOTTY; 4509 4510 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4511 if (!pos) 4512 return -ENOTTY; 4513 4514 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4515 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4516 4517 ctrl |= (cap & PCI_ACS_SV); 4518 ctrl |= (cap & PCI_ACS_RR); 4519 ctrl |= (cap & PCI_ACS_CR); 4520 ctrl |= (cap & PCI_ACS_UF); 4521 4522 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4523 4524 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4525 4526 return 0; 4527 } 4528 4529 static const struct pci_dev_enable_acs { 4530 u16 vendor; 4531 u16 device; 4532 int (*enable_acs)(struct pci_dev *dev); 4533 } pci_dev_enable_acs[] = { 4534 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 4535 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs }, 4536 { 0 } 4537 }; 4538 4539 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4540 { 4541 const struct pci_dev_enable_acs *i; 4542 int ret; 4543 4544 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4545 if ((i->vendor == dev->vendor || 4546 i->vendor == (u16)PCI_ANY_ID) && 4547 (i->device == dev->device || 4548 i->device == (u16)PCI_ANY_ID)) { 4549 ret = i->enable_acs(dev); 4550 if (ret >= 0) 4551 return ret; 4552 } 4553 } 4554 4555 return -ENOTTY; 4556 } 4557 4558 /* 4559 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with 4560 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4561 * Next Capability pointer in the MSI Capability Structure should point to 4562 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4563 * the list. 4564 */ 4565 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4566 { 4567 int pos, i = 0; 4568 u8 next_cap; 4569 u16 reg16, *cap; 4570 struct pci_cap_saved_state *state; 4571 4572 /* Bail if the hardware bug is fixed */ 4573 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4574 return; 4575 4576 /* Bail if MSI Capability Structure is not found for some reason */ 4577 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4578 if (!pos) 4579 return; 4580 4581 /* 4582 * Bail if Next Capability pointer in the MSI Capability Structure 4583 * is not the expected incorrect 0x00. 4584 */ 4585 pci_read_config_byte(pdev, pos + 1, &next_cap); 4586 if (next_cap) 4587 return; 4588 4589 /* 4590 * PCIe Capability Structure is expected to be at 0x50 and should 4591 * terminate the list (Next Capability pointer is 0x00). Verify 4592 * Capability Id and Next Capability pointer is as expected. 4593 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4594 * to correctly set kernel data structures which have already been 4595 * set incorrectly due to the hardware bug. 4596 */ 4597 pos = 0x50; 4598 pci_read_config_word(pdev, pos, ®16); 4599 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4600 u32 status; 4601 #ifndef PCI_EXP_SAVE_REGS 4602 #define PCI_EXP_SAVE_REGS 7 4603 #endif 4604 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4605 4606 pdev->pcie_cap = pos; 4607 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4608 pdev->pcie_flags_reg = reg16; 4609 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4610 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4611 4612 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4613 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4614 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4615 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4616 4617 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4618 return; 4619 4620 /* 4621 * Save PCIE cap 4622 */ 4623 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4624 if (!state) 4625 return; 4626 4627 state->cap.cap_nr = PCI_CAP_ID_EXP; 4628 state->cap.cap_extended = 0; 4629 state->cap.size = size; 4630 cap = (u16 *)&state->cap.data[0]; 4631 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4632 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4633 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4634 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4635 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4636 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4637 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4638 hlist_add_head(&state->next, &pdev->saved_cap_space); 4639 } 4640 } 4641 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4642 4643 /* 4644 * VMD-enabled root ports will change the source ID for all messages 4645 * to the VMD device. Rather than doing device matching with the source 4646 * ID, the AER driver should traverse the child device tree, reading 4647 * AER registers to find the faulting device. 4648 */ 4649 static void quirk_no_aersid(struct pci_dev *pdev) 4650 { 4651 /* VMD Domain */ 4652 if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000) 4653 pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID; 4654 } 4655 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid); 4656 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid); 4657 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid); 4658 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid); 4659 4660 /* FLR may cause some 82579 devices to hang. */ 4661 static void quirk_intel_no_flr(struct pci_dev *dev) 4662 { 4663 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4664 } 4665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); 4666 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); 4667