1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_device.h> 12 #include <linux/of_pci.h> 13 #include <linux/pci_hotplug.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/cpumask.h> 17 #include <linux/aer.h> 18 #include <linux/acpi.h> 19 #include <linux/hypervisor.h> 20 #include <linux/irqdomain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/bitfield.h> 23 #include "pci.h" 24 25 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 26 #define CARDBUS_RESERVE_BUSNR 3 27 28 static struct resource busn_resource = { 29 .name = "PCI busn", 30 .start = 0, 31 .end = 255, 32 .flags = IORESOURCE_BUS, 33 }; 34 35 /* Ugh. Need to stop exporting this to modules. */ 36 LIST_HEAD(pci_root_buses); 37 EXPORT_SYMBOL(pci_root_buses); 38 39 static LIST_HEAD(pci_domain_busn_res_list); 40 41 struct pci_domain_busn_res { 42 struct list_head list; 43 struct resource res; 44 int domain_nr; 45 }; 46 47 static struct resource *get_pci_domain_busn_res(int domain_nr) 48 { 49 struct pci_domain_busn_res *r; 50 51 list_for_each_entry(r, &pci_domain_busn_res_list, list) 52 if (r->domain_nr == domain_nr) 53 return &r->res; 54 55 r = kzalloc(sizeof(*r), GFP_KERNEL); 56 if (!r) 57 return NULL; 58 59 r->domain_nr = domain_nr; 60 r->res.start = 0; 61 r->res.end = 0xff; 62 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 63 64 list_add_tail(&r->list, &pci_domain_busn_res_list); 65 66 return &r->res; 67 } 68 69 /* 70 * Some device drivers need know if PCI is initiated. 71 * Basically, we think PCI is not initiated when there 72 * is no device to be found on the pci_bus_type. 73 */ 74 int no_pci_devices(void) 75 { 76 struct device *dev; 77 int no_devices; 78 79 dev = bus_find_next_device(&pci_bus_type, NULL); 80 no_devices = (dev == NULL); 81 put_device(dev); 82 return no_devices; 83 } 84 EXPORT_SYMBOL(no_pci_devices); 85 86 /* 87 * PCI Bus Class 88 */ 89 static void release_pcibus_dev(struct device *dev) 90 { 91 struct pci_bus *pci_bus = to_pci_bus(dev); 92 93 put_device(pci_bus->bridge); 94 pci_bus_remove_resources(pci_bus); 95 pci_release_bus_of_node(pci_bus); 96 kfree(pci_bus); 97 } 98 99 static struct class pcibus_class = { 100 .name = "pci_bus", 101 .dev_release = &release_pcibus_dev, 102 .dev_groups = pcibus_groups, 103 }; 104 105 static int __init pcibus_class_init(void) 106 { 107 return class_register(&pcibus_class); 108 } 109 postcore_initcall(pcibus_class_init); 110 111 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 112 { 113 u64 size = mask & maxbase; /* Find the significant bits */ 114 if (!size) 115 return 0; 116 117 /* 118 * Get the lowest of them to find the decode size, and from that 119 * the extent. 120 */ 121 size = size & ~(size-1); 122 123 /* 124 * base == maxbase can be valid only if the BAR has already been 125 * programmed with all 1s. 126 */ 127 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 128 return 0; 129 130 return size; 131 } 132 133 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 134 { 135 u32 mem_type; 136 unsigned long flags; 137 138 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 139 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 140 flags |= IORESOURCE_IO; 141 return flags; 142 } 143 144 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 145 flags |= IORESOURCE_MEM; 146 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 147 flags |= IORESOURCE_PREFETCH; 148 149 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 150 switch (mem_type) { 151 case PCI_BASE_ADDRESS_MEM_TYPE_32: 152 break; 153 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 154 /* 1M mem BAR treated as 32-bit BAR */ 155 break; 156 case PCI_BASE_ADDRESS_MEM_TYPE_64: 157 flags |= IORESOURCE_MEM_64; 158 break; 159 default: 160 /* mem unknown type treated as 32-bit BAR */ 161 break; 162 } 163 return flags; 164 } 165 166 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 167 168 /** 169 * __pci_read_base - Read a PCI BAR 170 * @dev: the PCI device 171 * @type: type of the BAR 172 * @res: resource buffer to be filled in 173 * @pos: BAR position in the config space 174 * 175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 176 */ 177 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 178 struct resource *res, unsigned int pos) 179 { 180 u32 l = 0, sz = 0, mask; 181 u64 l64, sz64, mask64; 182 u16 orig_cmd; 183 struct pci_bus_region region, inverted_region; 184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 186 187 /* No printks while decoding is disabled! */ 188 if (!dev->mmio_always_on) { 189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 191 pci_write_config_word(dev, PCI_COMMAND, 192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 193 } 194 } 195 196 res->name = pci_name(dev); 197 198 pci_read_config_dword(dev, pos, &l); 199 pci_write_config_dword(dev, pos, l | mask); 200 pci_read_config_dword(dev, pos, &sz); 201 pci_write_config_dword(dev, pos, l); 202 203 /* 204 * All bits set in sz means the device isn't working properly. 205 * If the BAR isn't implemented, all bits must be 0. If it's a 206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 207 * 1 must be clear. 208 */ 209 if (PCI_POSSIBLE_ERROR(sz)) 210 sz = 0; 211 212 /* 213 * I don't know how l can have all bits set. Copied from old code. 214 * Maybe it fixes a bug on some ancient platform. 215 */ 216 if (PCI_POSSIBLE_ERROR(l)) 217 l = 0; 218 219 if (type == pci_bar_unknown) { 220 res->flags = decode_bar(dev, l); 221 res->flags |= IORESOURCE_SIZEALIGN; 222 if (res->flags & IORESOURCE_IO) { 223 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 226 } else { 227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 230 } 231 } else { 232 if (l & PCI_ROM_ADDRESS_ENABLE) 233 res->flags |= IORESOURCE_ROM_ENABLE; 234 l64 = l & PCI_ROM_ADDRESS_MASK; 235 sz64 = sz & PCI_ROM_ADDRESS_MASK; 236 mask64 = PCI_ROM_ADDRESS_MASK; 237 } 238 239 if (res->flags & IORESOURCE_MEM_64) { 240 pci_read_config_dword(dev, pos + 4, &l); 241 pci_write_config_dword(dev, pos + 4, ~0); 242 pci_read_config_dword(dev, pos + 4, &sz); 243 pci_write_config_dword(dev, pos + 4, l); 244 245 l64 |= ((u64)l << 32); 246 sz64 |= ((u64)sz << 32); 247 mask64 |= ((u64)~0 << 32); 248 } 249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 252 253 if (!sz64) 254 goto fail; 255 256 sz64 = pci_size(l64, sz64, mask64); 257 if (!sz64) { 258 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 259 pos); 260 goto fail; 261 } 262 263 if (res->flags & IORESOURCE_MEM_64) { 264 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 265 && sz64 > 0x100000000ULL) { 266 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 267 res->start = 0; 268 res->end = 0; 269 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 270 pos, (unsigned long long)sz64); 271 goto out; 272 } 273 274 if ((sizeof(pci_bus_addr_t) < 8) && l) { 275 /* Above 32-bit boundary; try to reallocate */ 276 res->flags |= IORESOURCE_UNSET; 277 res->start = 0; 278 res->end = sz64 - 1; 279 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 280 pos, (unsigned long long)l64); 281 goto out; 282 } 283 } 284 285 region.start = l64; 286 region.end = l64 + sz64 - 1; 287 288 pcibios_bus_to_resource(dev->bus, res, ®ion); 289 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 290 291 /* 292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 293 * the corresponding resource address (the physical address used by 294 * the CPU. Converting that resource address back to a bus address 295 * should yield the original BAR value: 296 * 297 * resource_to_bus(bus_to_resource(A)) == A 298 * 299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 300 * be claimed by the device. 301 */ 302 if (inverted_region.start != region.start) { 303 res->flags |= IORESOURCE_UNSET; 304 res->start = 0; 305 res->end = region.end - region.start; 306 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 307 pos, (unsigned long long)region.start); 308 } 309 310 goto out; 311 312 313 fail: 314 res->flags = 0; 315 out: 316 if (res->flags) 317 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 318 319 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 320 } 321 322 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 323 { 324 unsigned int pos, reg; 325 326 if (dev->non_compliant_bars) 327 return; 328 329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 330 if (dev->is_virtfn) 331 return; 332 333 for (pos = 0; pos < howmany; pos++) { 334 struct resource *res = &dev->resource[pos]; 335 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 337 } 338 339 if (rom) { 340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 341 dev->rom_base_reg = rom; 342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 344 __pci_read_base(dev, pci_bar_mem32, res, rom); 345 } 346 } 347 348 static void pci_read_bridge_windows(struct pci_dev *bridge) 349 { 350 u16 io; 351 u32 pmem, tmp; 352 353 pci_read_config_word(bridge, PCI_IO_BASE, &io); 354 if (!io) { 355 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 356 pci_read_config_word(bridge, PCI_IO_BASE, &io); 357 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 358 } 359 if (io) 360 bridge->io_window = 1; 361 362 /* 363 * DECchip 21050 pass 2 errata: the bridge may miss an address 364 * disconnect boundary by one PCI data phase. Workaround: do not 365 * use prefetching on this device. 366 */ 367 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 368 return; 369 370 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 371 if (!pmem) { 372 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 373 0xffe0fff0); 374 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 376 } 377 if (!pmem) 378 return; 379 380 bridge->pref_window = 1; 381 382 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 383 384 /* 385 * Bridge claims to have a 64-bit prefetchable memory 386 * window; verify that the upper bits are actually 387 * writable. 388 */ 389 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 390 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 391 0xffffffff); 392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 394 if (tmp) 395 bridge->pref_64_window = 1; 396 } 397 } 398 399 static void pci_read_bridge_io(struct pci_bus *child) 400 { 401 struct pci_dev *dev = child->self; 402 u8 io_base_lo, io_limit_lo; 403 unsigned long io_mask, io_granularity, base, limit; 404 struct pci_bus_region region; 405 struct resource *res; 406 407 io_mask = PCI_IO_RANGE_MASK; 408 io_granularity = 0x1000; 409 if (dev->io_window_1k) { 410 /* Support 1K I/O space granularity */ 411 io_mask = PCI_IO_1K_RANGE_MASK; 412 io_granularity = 0x400; 413 } 414 415 res = child->resource[0]; 416 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 417 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 418 base = (io_base_lo & io_mask) << 8; 419 limit = (io_limit_lo & io_mask) << 8; 420 421 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 422 u16 io_base_hi, io_limit_hi; 423 424 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 425 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 426 base |= ((unsigned long) io_base_hi << 16); 427 limit |= ((unsigned long) io_limit_hi << 16); 428 } 429 430 if (base <= limit) { 431 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 432 region.start = base; 433 region.end = limit + io_granularity - 1; 434 pcibios_bus_to_resource(dev->bus, res, ®ion); 435 pci_info(dev, " bridge window %pR\n", res); 436 } 437 } 438 439 static void pci_read_bridge_mmio(struct pci_bus *child) 440 { 441 struct pci_dev *dev = child->self; 442 u16 mem_base_lo, mem_limit_lo; 443 unsigned long base, limit; 444 struct pci_bus_region region; 445 struct resource *res; 446 447 res = child->resource[1]; 448 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 449 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 450 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 452 if (base <= limit) { 453 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 454 region.start = base; 455 region.end = limit + 0xfffff; 456 pcibios_bus_to_resource(dev->bus, res, ®ion); 457 pci_info(dev, " bridge window %pR\n", res); 458 } 459 } 460 461 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 462 { 463 struct pci_dev *dev = child->self; 464 u16 mem_base_lo, mem_limit_lo; 465 u64 base64, limit64; 466 pci_bus_addr_t base, limit; 467 struct pci_bus_region region; 468 struct resource *res; 469 470 res = child->resource[2]; 471 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 472 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 473 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 474 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 475 476 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 477 u32 mem_base_hi, mem_limit_hi; 478 479 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 480 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 481 482 /* 483 * Some bridges set the base > limit by default, and some 484 * (broken) BIOSes do not initialize them. If we find 485 * this, just assume they are not being used. 486 */ 487 if (mem_base_hi <= mem_limit_hi) { 488 base64 |= (u64) mem_base_hi << 32; 489 limit64 |= (u64) mem_limit_hi << 32; 490 } 491 } 492 493 base = (pci_bus_addr_t) base64; 494 limit = (pci_bus_addr_t) limit64; 495 496 if (base != base64) { 497 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 498 (unsigned long long) base64); 499 return; 500 } 501 502 if (base <= limit) { 503 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 504 IORESOURCE_MEM | IORESOURCE_PREFETCH; 505 if (res->flags & PCI_PREF_RANGE_TYPE_64) 506 res->flags |= IORESOURCE_MEM_64; 507 region.start = base; 508 region.end = limit + 0xfffff; 509 pcibios_bus_to_resource(dev->bus, res, ®ion); 510 pci_info(dev, " bridge window %pR\n", res); 511 } 512 } 513 514 void pci_read_bridge_bases(struct pci_bus *child) 515 { 516 struct pci_dev *dev = child->self; 517 struct resource *res; 518 int i; 519 520 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 521 return; 522 523 pci_info(dev, "PCI bridge to %pR%s\n", 524 &child->busn_res, 525 dev->transparent ? " (subtractive decode)" : ""); 526 527 pci_bus_remove_resources(child); 528 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 529 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 530 531 pci_read_bridge_io(child); 532 pci_read_bridge_mmio(child); 533 pci_read_bridge_mmio_pref(child); 534 535 if (dev->transparent) { 536 pci_bus_for_each_resource(child->parent, res) { 537 if (res && res->flags) { 538 pci_bus_add_resource(child, res, 539 PCI_SUBTRACTIVE_DECODE); 540 pci_info(dev, " bridge window %pR (subtractive decode)\n", 541 res); 542 } 543 } 544 } 545 } 546 547 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 548 { 549 struct pci_bus *b; 550 551 b = kzalloc(sizeof(*b), GFP_KERNEL); 552 if (!b) 553 return NULL; 554 555 INIT_LIST_HEAD(&b->node); 556 INIT_LIST_HEAD(&b->children); 557 INIT_LIST_HEAD(&b->devices); 558 INIT_LIST_HEAD(&b->slots); 559 INIT_LIST_HEAD(&b->resources); 560 b->max_bus_speed = PCI_SPEED_UNKNOWN; 561 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 562 #ifdef CONFIG_PCI_DOMAINS_GENERIC 563 if (parent) 564 b->domain_nr = parent->domain_nr; 565 #endif 566 return b; 567 } 568 569 static void pci_release_host_bridge_dev(struct device *dev) 570 { 571 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 572 573 if (bridge->release_fn) 574 bridge->release_fn(bridge); 575 576 pci_free_resource_list(&bridge->windows); 577 pci_free_resource_list(&bridge->dma_ranges); 578 kfree(bridge); 579 } 580 581 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 582 { 583 INIT_LIST_HEAD(&bridge->windows); 584 INIT_LIST_HEAD(&bridge->dma_ranges); 585 586 /* 587 * We assume we can manage these PCIe features. Some systems may 588 * reserve these for use by the platform itself, e.g., an ACPI BIOS 589 * may implement its own AER handling and use _OSC to prevent the 590 * OS from interfering. 591 */ 592 bridge->native_aer = 1; 593 bridge->native_pcie_hotplug = 1; 594 bridge->native_shpc_hotplug = 1; 595 bridge->native_pme = 1; 596 bridge->native_ltr = 1; 597 bridge->native_dpc = 1; 598 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 599 bridge->native_cxl_error = 1; 600 601 device_initialize(&bridge->dev); 602 } 603 604 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 605 { 606 struct pci_host_bridge *bridge; 607 608 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 609 if (!bridge) 610 return NULL; 611 612 pci_init_host_bridge(bridge); 613 bridge->dev.release = pci_release_host_bridge_dev; 614 615 return bridge; 616 } 617 EXPORT_SYMBOL(pci_alloc_host_bridge); 618 619 static void devm_pci_alloc_host_bridge_release(void *data) 620 { 621 pci_free_host_bridge(data); 622 } 623 624 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 625 size_t priv) 626 { 627 int ret; 628 struct pci_host_bridge *bridge; 629 630 bridge = pci_alloc_host_bridge(priv); 631 if (!bridge) 632 return NULL; 633 634 bridge->dev.parent = dev; 635 636 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 637 bridge); 638 if (ret) 639 return NULL; 640 641 ret = devm_of_pci_bridge_init(dev, bridge); 642 if (ret) 643 return NULL; 644 645 return bridge; 646 } 647 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 648 649 void pci_free_host_bridge(struct pci_host_bridge *bridge) 650 { 651 put_device(&bridge->dev); 652 } 653 EXPORT_SYMBOL(pci_free_host_bridge); 654 655 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 656 static const unsigned char pcix_bus_speed[] = { 657 PCI_SPEED_UNKNOWN, /* 0 */ 658 PCI_SPEED_66MHz_PCIX, /* 1 */ 659 PCI_SPEED_100MHz_PCIX, /* 2 */ 660 PCI_SPEED_133MHz_PCIX, /* 3 */ 661 PCI_SPEED_UNKNOWN, /* 4 */ 662 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 663 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 664 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 665 PCI_SPEED_UNKNOWN, /* 8 */ 666 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 667 PCI_SPEED_100MHz_PCIX_266, /* A */ 668 PCI_SPEED_133MHz_PCIX_266, /* B */ 669 PCI_SPEED_UNKNOWN, /* C */ 670 PCI_SPEED_66MHz_PCIX_533, /* D */ 671 PCI_SPEED_100MHz_PCIX_533, /* E */ 672 PCI_SPEED_133MHz_PCIX_533 /* F */ 673 }; 674 675 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 676 const unsigned char pcie_link_speed[] = { 677 PCI_SPEED_UNKNOWN, /* 0 */ 678 PCIE_SPEED_2_5GT, /* 1 */ 679 PCIE_SPEED_5_0GT, /* 2 */ 680 PCIE_SPEED_8_0GT, /* 3 */ 681 PCIE_SPEED_16_0GT, /* 4 */ 682 PCIE_SPEED_32_0GT, /* 5 */ 683 PCIE_SPEED_64_0GT, /* 6 */ 684 PCI_SPEED_UNKNOWN, /* 7 */ 685 PCI_SPEED_UNKNOWN, /* 8 */ 686 PCI_SPEED_UNKNOWN, /* 9 */ 687 PCI_SPEED_UNKNOWN, /* A */ 688 PCI_SPEED_UNKNOWN, /* B */ 689 PCI_SPEED_UNKNOWN, /* C */ 690 PCI_SPEED_UNKNOWN, /* D */ 691 PCI_SPEED_UNKNOWN, /* E */ 692 PCI_SPEED_UNKNOWN /* F */ 693 }; 694 EXPORT_SYMBOL_GPL(pcie_link_speed); 695 696 const char *pci_speed_string(enum pci_bus_speed speed) 697 { 698 /* Indexed by the pci_bus_speed enum */ 699 static const char *speed_strings[] = { 700 "33 MHz PCI", /* 0x00 */ 701 "66 MHz PCI", /* 0x01 */ 702 "66 MHz PCI-X", /* 0x02 */ 703 "100 MHz PCI-X", /* 0x03 */ 704 "133 MHz PCI-X", /* 0x04 */ 705 NULL, /* 0x05 */ 706 NULL, /* 0x06 */ 707 NULL, /* 0x07 */ 708 NULL, /* 0x08 */ 709 "66 MHz PCI-X 266", /* 0x09 */ 710 "100 MHz PCI-X 266", /* 0x0a */ 711 "133 MHz PCI-X 266", /* 0x0b */ 712 "Unknown AGP", /* 0x0c */ 713 "1x AGP", /* 0x0d */ 714 "2x AGP", /* 0x0e */ 715 "4x AGP", /* 0x0f */ 716 "8x AGP", /* 0x10 */ 717 "66 MHz PCI-X 533", /* 0x11 */ 718 "100 MHz PCI-X 533", /* 0x12 */ 719 "133 MHz PCI-X 533", /* 0x13 */ 720 "2.5 GT/s PCIe", /* 0x14 */ 721 "5.0 GT/s PCIe", /* 0x15 */ 722 "8.0 GT/s PCIe", /* 0x16 */ 723 "16.0 GT/s PCIe", /* 0x17 */ 724 "32.0 GT/s PCIe", /* 0x18 */ 725 "64.0 GT/s PCIe", /* 0x19 */ 726 }; 727 728 if (speed < ARRAY_SIZE(speed_strings)) 729 return speed_strings[speed]; 730 return "Unknown"; 731 } 732 EXPORT_SYMBOL_GPL(pci_speed_string); 733 734 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 735 { 736 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 737 } 738 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 739 740 static unsigned char agp_speeds[] = { 741 AGP_UNKNOWN, 742 AGP_1X, 743 AGP_2X, 744 AGP_4X, 745 AGP_8X 746 }; 747 748 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 749 { 750 int index = 0; 751 752 if (agpstat & 4) 753 index = 3; 754 else if (agpstat & 2) 755 index = 2; 756 else if (agpstat & 1) 757 index = 1; 758 else 759 goto out; 760 761 if (agp3) { 762 index += 2; 763 if (index == 5) 764 index = 0; 765 } 766 767 out: 768 return agp_speeds[index]; 769 } 770 771 static void pci_set_bus_speed(struct pci_bus *bus) 772 { 773 struct pci_dev *bridge = bus->self; 774 int pos; 775 776 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 777 if (!pos) 778 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 779 if (pos) { 780 u32 agpstat, agpcmd; 781 782 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 783 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 784 785 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 786 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 787 } 788 789 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 790 if (pos) { 791 u16 status; 792 enum pci_bus_speed max; 793 794 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 795 &status); 796 797 if (status & PCI_X_SSTATUS_533MHZ) { 798 max = PCI_SPEED_133MHz_PCIX_533; 799 } else if (status & PCI_X_SSTATUS_266MHZ) { 800 max = PCI_SPEED_133MHz_PCIX_266; 801 } else if (status & PCI_X_SSTATUS_133MHZ) { 802 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 803 max = PCI_SPEED_133MHz_PCIX_ECC; 804 else 805 max = PCI_SPEED_133MHz_PCIX; 806 } else { 807 max = PCI_SPEED_66MHz_PCIX; 808 } 809 810 bus->max_bus_speed = max; 811 bus->cur_bus_speed = pcix_bus_speed[ 812 (status & PCI_X_SSTATUS_FREQ) >> 6]; 813 814 return; 815 } 816 817 if (pci_is_pcie(bridge)) { 818 u32 linkcap; 819 u16 linksta; 820 821 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 822 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 823 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 824 825 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 826 pcie_update_link_speed(bus, linksta); 827 } 828 } 829 830 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 831 { 832 struct irq_domain *d; 833 834 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 835 d = dev_get_msi_domain(bus->bridge); 836 837 /* 838 * Any firmware interface that can resolve the msi_domain 839 * should be called from here. 840 */ 841 if (!d) 842 d = pci_host_bridge_of_msi_domain(bus); 843 if (!d) 844 d = pci_host_bridge_acpi_msi_domain(bus); 845 846 /* 847 * If no IRQ domain was found via the OF tree, try looking it up 848 * directly through the fwnode_handle. 849 */ 850 if (!d) { 851 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 852 853 if (fwnode) 854 d = irq_find_matching_fwnode(fwnode, 855 DOMAIN_BUS_PCI_MSI); 856 } 857 858 return d; 859 } 860 861 static void pci_set_bus_msi_domain(struct pci_bus *bus) 862 { 863 struct irq_domain *d; 864 struct pci_bus *b; 865 866 /* 867 * The bus can be a root bus, a subordinate bus, or a virtual bus 868 * created by an SR-IOV device. Walk up to the first bridge device 869 * found or derive the domain from the host bridge. 870 */ 871 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 872 if (b->self) 873 d = dev_get_msi_domain(&b->self->dev); 874 } 875 876 if (!d) 877 d = pci_host_bridge_msi_domain(b); 878 879 dev_set_msi_domain(&bus->dev, d); 880 } 881 882 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 883 { 884 struct device *parent = bridge->dev.parent; 885 struct resource_entry *window, *next, *n; 886 struct pci_bus *bus, *b; 887 resource_size_t offset, next_offset; 888 LIST_HEAD(resources); 889 struct resource *res, *next_res; 890 char addr[64], *fmt; 891 const char *name; 892 int err; 893 894 bus = pci_alloc_bus(NULL); 895 if (!bus) 896 return -ENOMEM; 897 898 bridge->bus = bus; 899 900 bus->sysdata = bridge->sysdata; 901 bus->ops = bridge->ops; 902 bus->number = bus->busn_res.start = bridge->busnr; 903 #ifdef CONFIG_PCI_DOMAINS_GENERIC 904 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 905 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 906 else 907 bus->domain_nr = bridge->domain_nr; 908 if (bus->domain_nr < 0) { 909 err = bus->domain_nr; 910 goto free; 911 } 912 #endif 913 914 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 915 if (b) { 916 /* Ignore it if we already got here via a different bridge */ 917 dev_dbg(&b->dev, "bus already known\n"); 918 err = -EEXIST; 919 goto free; 920 } 921 922 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 923 bridge->busnr); 924 925 err = pcibios_root_bridge_prepare(bridge); 926 if (err) 927 goto free; 928 929 /* Temporarily move resources off the list */ 930 list_splice_init(&bridge->windows, &resources); 931 err = device_add(&bridge->dev); 932 if (err) { 933 put_device(&bridge->dev); 934 goto free; 935 } 936 bus->bridge = get_device(&bridge->dev); 937 device_enable_async_suspend(bus->bridge); 938 pci_set_bus_of_node(bus); 939 pci_set_bus_msi_domain(bus); 940 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 941 !pci_host_of_has_msi_map(parent)) 942 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 943 944 if (!parent) 945 set_dev_node(bus->bridge, pcibus_to_node(bus)); 946 947 bus->dev.class = &pcibus_class; 948 bus->dev.parent = bus->bridge; 949 950 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 951 name = dev_name(&bus->dev); 952 953 err = device_register(&bus->dev); 954 if (err) 955 goto unregister; 956 957 pcibios_add_bus(bus); 958 959 if (bus->ops->add_bus) { 960 err = bus->ops->add_bus(bus); 961 if (WARN_ON(err < 0)) 962 dev_err(&bus->dev, "failed to add bus: %d\n", err); 963 } 964 965 /* Create legacy_io and legacy_mem files for this bus */ 966 pci_create_legacy_files(bus); 967 968 if (parent) 969 dev_info(parent, "PCI host bridge to bus %s\n", name); 970 else 971 pr_info("PCI host bridge to bus %s\n", name); 972 973 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 974 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 975 976 /* Coalesce contiguous windows */ 977 resource_list_for_each_entry_safe(window, n, &resources) { 978 if (list_is_last(&window->node, &resources)) 979 break; 980 981 next = list_next_entry(window, node); 982 offset = window->offset; 983 res = window->res; 984 next_offset = next->offset; 985 next_res = next->res; 986 987 if (res->flags != next_res->flags || offset != next_offset) 988 continue; 989 990 if (res->end + 1 == next_res->start) { 991 next_res->start = res->start; 992 res->flags = res->start = res->end = 0; 993 } 994 } 995 996 /* Add initial resources to the bus */ 997 resource_list_for_each_entry_safe(window, n, &resources) { 998 offset = window->offset; 999 res = window->res; 1000 if (!res->flags && !res->start && !res->end) 1001 continue; 1002 1003 list_move_tail(&window->node, &bridge->windows); 1004 1005 if (res->flags & IORESOURCE_BUS) 1006 pci_bus_insert_busn_res(bus, bus->number, res->end); 1007 else 1008 pci_bus_add_resource(bus, res, 0); 1009 1010 if (offset) { 1011 if (resource_type(res) == IORESOURCE_IO) 1012 fmt = " (bus address [%#06llx-%#06llx])"; 1013 else 1014 fmt = " (bus address [%#010llx-%#010llx])"; 1015 1016 snprintf(addr, sizeof(addr), fmt, 1017 (unsigned long long)(res->start - offset), 1018 (unsigned long long)(res->end - offset)); 1019 } else 1020 addr[0] = '\0'; 1021 1022 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1023 } 1024 1025 down_write(&pci_bus_sem); 1026 list_add_tail(&bus->node, &pci_root_buses); 1027 up_write(&pci_bus_sem); 1028 1029 return 0; 1030 1031 unregister: 1032 put_device(&bridge->dev); 1033 device_del(&bridge->dev); 1034 1035 free: 1036 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1037 pci_bus_release_domain_nr(bus, parent); 1038 #endif 1039 kfree(bus); 1040 return err; 1041 } 1042 1043 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1044 { 1045 int pos; 1046 u32 status; 1047 1048 /* 1049 * If extended config space isn't accessible on a bridge's primary 1050 * bus, we certainly can't access it on the secondary bus. 1051 */ 1052 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1053 return false; 1054 1055 /* 1056 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1057 * extended config space is accessible on the primary, it's also 1058 * accessible on the secondary. 1059 */ 1060 if (pci_is_pcie(bridge) && 1061 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1062 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1063 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1064 return true; 1065 1066 /* 1067 * For the other bridge types: 1068 * - PCI-to-PCI bridges 1069 * - PCIe-to-PCI/PCI-X forward bridges 1070 * - PCI/PCI-X-to-PCIe reverse bridges 1071 * extended config space on the secondary side is only accessible 1072 * if the bridge supports PCI-X Mode 2. 1073 */ 1074 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1075 if (!pos) 1076 return false; 1077 1078 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1079 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1080 } 1081 1082 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1083 struct pci_dev *bridge, int busnr) 1084 { 1085 struct pci_bus *child; 1086 struct pci_host_bridge *host; 1087 int i; 1088 int ret; 1089 1090 /* Allocate a new bus and inherit stuff from the parent */ 1091 child = pci_alloc_bus(parent); 1092 if (!child) 1093 return NULL; 1094 1095 child->parent = parent; 1096 child->sysdata = parent->sysdata; 1097 child->bus_flags = parent->bus_flags; 1098 1099 host = pci_find_host_bridge(parent); 1100 if (host->child_ops) 1101 child->ops = host->child_ops; 1102 else 1103 child->ops = parent->ops; 1104 1105 /* 1106 * Initialize some portions of the bus device, but don't register 1107 * it now as the parent is not properly set up yet. 1108 */ 1109 child->dev.class = &pcibus_class; 1110 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1111 1112 /* Set up the primary, secondary and subordinate bus numbers */ 1113 child->number = child->busn_res.start = busnr; 1114 child->primary = parent->busn_res.start; 1115 child->busn_res.end = 0xff; 1116 1117 if (!bridge) { 1118 child->dev.parent = parent->bridge; 1119 goto add_dev; 1120 } 1121 1122 child->self = bridge; 1123 child->bridge = get_device(&bridge->dev); 1124 child->dev.parent = child->bridge; 1125 pci_set_bus_of_node(child); 1126 pci_set_bus_speed(child); 1127 1128 /* 1129 * Check whether extended config space is accessible on the child 1130 * bus. Note that we currently assume it is always accessible on 1131 * the root bus. 1132 */ 1133 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1134 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1135 pci_info(child, "extended config space not accessible\n"); 1136 } 1137 1138 /* Set up default resource pointers and names */ 1139 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1140 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1141 child->resource[i]->name = child->name; 1142 } 1143 bridge->subordinate = child; 1144 1145 add_dev: 1146 pci_set_bus_msi_domain(child); 1147 ret = device_register(&child->dev); 1148 WARN_ON(ret < 0); 1149 1150 pcibios_add_bus(child); 1151 1152 if (child->ops->add_bus) { 1153 ret = child->ops->add_bus(child); 1154 if (WARN_ON(ret < 0)) 1155 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1156 } 1157 1158 /* Create legacy_io and legacy_mem files for this bus */ 1159 pci_create_legacy_files(child); 1160 1161 return child; 1162 } 1163 1164 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1165 int busnr) 1166 { 1167 struct pci_bus *child; 1168 1169 child = pci_alloc_child_bus(parent, dev, busnr); 1170 if (child) { 1171 down_write(&pci_bus_sem); 1172 list_add_tail(&child->node, &parent->children); 1173 up_write(&pci_bus_sem); 1174 } 1175 return child; 1176 } 1177 EXPORT_SYMBOL(pci_add_new_bus); 1178 1179 static void pci_enable_crs(struct pci_dev *pdev) 1180 { 1181 u16 root_cap = 0; 1182 1183 /* Enable CRS Software Visibility if supported */ 1184 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1185 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1186 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1187 PCI_EXP_RTCTL_CRSSVE); 1188 } 1189 1190 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1191 unsigned int available_buses); 1192 /** 1193 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1194 * numbers from EA capability. 1195 * @dev: Bridge 1196 * @sec: updated with secondary bus number from EA 1197 * @sub: updated with subordinate bus number from EA 1198 * 1199 * If @dev is a bridge with EA capability that specifies valid secondary 1200 * and subordinate bus numbers, return true with the bus numbers in @sec 1201 * and @sub. Otherwise return false. 1202 */ 1203 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1204 { 1205 int ea, offset; 1206 u32 dw; 1207 u8 ea_sec, ea_sub; 1208 1209 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1210 return false; 1211 1212 /* find PCI EA capability in list */ 1213 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1214 if (!ea) 1215 return false; 1216 1217 offset = ea + PCI_EA_FIRST_ENT; 1218 pci_read_config_dword(dev, offset, &dw); 1219 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1220 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1221 if (ea_sec == 0 || ea_sub < ea_sec) 1222 return false; 1223 1224 *sec = ea_sec; 1225 *sub = ea_sub; 1226 return true; 1227 } 1228 1229 /* 1230 * pci_scan_bridge_extend() - Scan buses behind a bridge 1231 * @bus: Parent bus the bridge is on 1232 * @dev: Bridge itself 1233 * @max: Starting subordinate number of buses behind this bridge 1234 * @available_buses: Total number of buses available for this bridge and 1235 * the devices below. After the minimal bus space has 1236 * been allocated the remaining buses will be 1237 * distributed equally between hotplug-capable bridges. 1238 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1239 * that need to be reconfigured. 1240 * 1241 * If it's a bridge, configure it and scan the bus behind it. 1242 * For CardBus bridges, we don't scan behind as the devices will 1243 * be handled by the bridge driver itself. 1244 * 1245 * We need to process bridges in two passes -- first we scan those 1246 * already configured by the BIOS and after we are done with all of 1247 * them, we proceed to assigning numbers to the remaining buses in 1248 * order to avoid overlaps between old and new bus numbers. 1249 * 1250 * Return: New subordinate number covering all buses behind this bridge. 1251 */ 1252 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1253 int max, unsigned int available_buses, 1254 int pass) 1255 { 1256 struct pci_bus *child; 1257 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1258 u32 buses, i, j = 0; 1259 u16 bctl; 1260 u8 primary, secondary, subordinate; 1261 int broken = 0; 1262 bool fixed_buses; 1263 u8 fixed_sec, fixed_sub; 1264 int next_busnr; 1265 1266 /* 1267 * Make sure the bridge is powered on to be able to access config 1268 * space of devices below it. 1269 */ 1270 pm_runtime_get_sync(&dev->dev); 1271 1272 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1273 primary = buses & 0xFF; 1274 secondary = (buses >> 8) & 0xFF; 1275 subordinate = (buses >> 16) & 0xFF; 1276 1277 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1278 secondary, subordinate, pass); 1279 1280 if (!primary && (primary != bus->number) && secondary && subordinate) { 1281 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1282 primary = bus->number; 1283 } 1284 1285 /* Check if setup is sensible at all */ 1286 if (!pass && 1287 (primary != bus->number || secondary <= bus->number || 1288 secondary > subordinate)) { 1289 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1290 secondary, subordinate); 1291 broken = 1; 1292 } 1293 1294 /* 1295 * Disable Master-Abort Mode during probing to avoid reporting of 1296 * bus errors in some architectures. 1297 */ 1298 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1299 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1300 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1301 1302 pci_enable_crs(dev); 1303 1304 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1305 !is_cardbus && !broken) { 1306 unsigned int cmax, buses; 1307 1308 /* 1309 * Bus already configured by firmware, process it in the 1310 * first pass and just note the configuration. 1311 */ 1312 if (pass) 1313 goto out; 1314 1315 /* 1316 * The bus might already exist for two reasons: Either we 1317 * are rescanning the bus or the bus is reachable through 1318 * more than one bridge. The second case can happen with 1319 * the i450NX chipset. 1320 */ 1321 child = pci_find_bus(pci_domain_nr(bus), secondary); 1322 if (!child) { 1323 child = pci_add_new_bus(bus, dev, secondary); 1324 if (!child) 1325 goto out; 1326 child->primary = primary; 1327 pci_bus_insert_busn_res(child, secondary, subordinate); 1328 child->bridge_ctl = bctl; 1329 } 1330 1331 buses = subordinate - secondary; 1332 cmax = pci_scan_child_bus_extend(child, buses); 1333 if (cmax > subordinate) 1334 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1335 subordinate, cmax); 1336 1337 /* Subordinate should equal child->busn_res.end */ 1338 if (subordinate > max) 1339 max = subordinate; 1340 } else { 1341 1342 /* 1343 * We need to assign a number to this bus which we always 1344 * do in the second pass. 1345 */ 1346 if (!pass) { 1347 if (pcibios_assign_all_busses() || broken || is_cardbus) 1348 1349 /* 1350 * Temporarily disable forwarding of the 1351 * configuration cycles on all bridges in 1352 * this bus segment to avoid possible 1353 * conflicts in the second pass between two 1354 * bridges programmed with overlapping bus 1355 * ranges. 1356 */ 1357 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1358 buses & ~0xffffff); 1359 goto out; 1360 } 1361 1362 /* Clear errors */ 1363 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1364 1365 /* Read bus numbers from EA Capability (if present) */ 1366 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1367 if (fixed_buses) 1368 next_busnr = fixed_sec; 1369 else 1370 next_busnr = max + 1; 1371 1372 /* 1373 * Prevent assigning a bus number that already exists. 1374 * This can happen when a bridge is hot-plugged, so in this 1375 * case we only re-scan this bus. 1376 */ 1377 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1378 if (!child) { 1379 child = pci_add_new_bus(bus, dev, next_busnr); 1380 if (!child) 1381 goto out; 1382 pci_bus_insert_busn_res(child, next_busnr, 1383 bus->busn_res.end); 1384 } 1385 max++; 1386 if (available_buses) 1387 available_buses--; 1388 1389 buses = (buses & 0xff000000) 1390 | ((unsigned int)(child->primary) << 0) 1391 | ((unsigned int)(child->busn_res.start) << 8) 1392 | ((unsigned int)(child->busn_res.end) << 16); 1393 1394 /* 1395 * yenta.c forces a secondary latency timer of 176. 1396 * Copy that behaviour here. 1397 */ 1398 if (is_cardbus) { 1399 buses &= ~0xff000000; 1400 buses |= CARDBUS_LATENCY_TIMER << 24; 1401 } 1402 1403 /* We need to blast all three values with a single write */ 1404 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1405 1406 if (!is_cardbus) { 1407 child->bridge_ctl = bctl; 1408 max = pci_scan_child_bus_extend(child, available_buses); 1409 } else { 1410 1411 /* 1412 * For CardBus bridges, we leave 4 bus numbers as 1413 * cards with a PCI-to-PCI bridge can be inserted 1414 * later. 1415 */ 1416 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1417 struct pci_bus *parent = bus; 1418 if (pci_find_bus(pci_domain_nr(bus), 1419 max+i+1)) 1420 break; 1421 while (parent->parent) { 1422 if ((!pcibios_assign_all_busses()) && 1423 (parent->busn_res.end > max) && 1424 (parent->busn_res.end <= max+i)) { 1425 j = 1; 1426 } 1427 parent = parent->parent; 1428 } 1429 if (j) { 1430 1431 /* 1432 * Often, there are two CardBus 1433 * bridges -- try to leave one 1434 * valid bus number for each one. 1435 */ 1436 i /= 2; 1437 break; 1438 } 1439 } 1440 max += i; 1441 } 1442 1443 /* 1444 * Set subordinate bus number to its real value. 1445 * If fixed subordinate bus number exists from EA 1446 * capability then use it. 1447 */ 1448 if (fixed_buses) 1449 max = fixed_sub; 1450 pci_bus_update_busn_res_end(child, max); 1451 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1452 } 1453 1454 sprintf(child->name, 1455 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1456 pci_domain_nr(bus), child->number); 1457 1458 /* Check that all devices are accessible */ 1459 while (bus->parent) { 1460 if ((child->busn_res.end > bus->busn_res.end) || 1461 (child->number > bus->busn_res.end) || 1462 (child->number < bus->number) || 1463 (child->busn_res.end < bus->number)) { 1464 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1465 &child->busn_res); 1466 break; 1467 } 1468 bus = bus->parent; 1469 } 1470 1471 out: 1472 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1473 1474 pm_runtime_put(&dev->dev); 1475 1476 return max; 1477 } 1478 1479 /* 1480 * pci_scan_bridge() - Scan buses behind a bridge 1481 * @bus: Parent bus the bridge is on 1482 * @dev: Bridge itself 1483 * @max: Starting subordinate number of buses behind this bridge 1484 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1485 * that need to be reconfigured. 1486 * 1487 * If it's a bridge, configure it and scan the bus behind it. 1488 * For CardBus bridges, we don't scan behind as the devices will 1489 * be handled by the bridge driver itself. 1490 * 1491 * We need to process bridges in two passes -- first we scan those 1492 * already configured by the BIOS and after we are done with all of 1493 * them, we proceed to assigning numbers to the remaining buses in 1494 * order to avoid overlaps between old and new bus numbers. 1495 * 1496 * Return: New subordinate number covering all buses behind this bridge. 1497 */ 1498 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1499 { 1500 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1501 } 1502 EXPORT_SYMBOL(pci_scan_bridge); 1503 1504 /* 1505 * Read interrupt line and base address registers. 1506 * The architecture-dependent code can tweak these, of course. 1507 */ 1508 static void pci_read_irq(struct pci_dev *dev) 1509 { 1510 unsigned char irq; 1511 1512 /* VFs are not allowed to use INTx, so skip the config reads */ 1513 if (dev->is_virtfn) { 1514 dev->pin = 0; 1515 dev->irq = 0; 1516 return; 1517 } 1518 1519 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1520 dev->pin = irq; 1521 if (irq) 1522 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1523 dev->irq = irq; 1524 } 1525 1526 void set_pcie_port_type(struct pci_dev *pdev) 1527 { 1528 int pos; 1529 u16 reg16; 1530 int type; 1531 struct pci_dev *parent; 1532 1533 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1534 if (!pos) 1535 return; 1536 1537 pdev->pcie_cap = pos; 1538 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1539 pdev->pcie_flags_reg = reg16; 1540 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1541 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1542 1543 parent = pci_upstream_bridge(pdev); 1544 if (!parent) 1545 return; 1546 1547 /* 1548 * Some systems do not identify their upstream/downstream ports 1549 * correctly so detect impossible configurations here and correct 1550 * the port type accordingly. 1551 */ 1552 type = pci_pcie_type(pdev); 1553 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1554 /* 1555 * If pdev claims to be downstream port but the parent 1556 * device is also downstream port assume pdev is actually 1557 * upstream port. 1558 */ 1559 if (pcie_downstream_port(parent)) { 1560 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1561 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1562 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1563 } 1564 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1565 /* 1566 * If pdev claims to be upstream port but the parent 1567 * device is also upstream port assume pdev is actually 1568 * downstream port. 1569 */ 1570 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1571 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1572 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1573 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1574 } 1575 } 1576 } 1577 1578 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1579 { 1580 u32 reg32; 1581 1582 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1583 if (reg32 & PCI_EXP_SLTCAP_HPC) 1584 pdev->is_hotplug_bridge = 1; 1585 } 1586 1587 static void set_pcie_thunderbolt(struct pci_dev *dev) 1588 { 1589 u16 vsec; 1590 1591 /* Is the device part of a Thunderbolt controller? */ 1592 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1593 if (vsec) 1594 dev->is_thunderbolt = 1; 1595 } 1596 1597 static void set_pcie_untrusted(struct pci_dev *dev) 1598 { 1599 struct pci_dev *parent; 1600 1601 /* 1602 * If the upstream bridge is untrusted we treat this device 1603 * untrusted as well. 1604 */ 1605 parent = pci_upstream_bridge(dev); 1606 if (parent && (parent->untrusted || parent->external_facing)) 1607 dev->untrusted = true; 1608 } 1609 1610 static void pci_set_removable(struct pci_dev *dev) 1611 { 1612 struct pci_dev *parent = pci_upstream_bridge(dev); 1613 1614 /* 1615 * We (only) consider everything downstream from an external_facing 1616 * device to be removable by the user. We're mainly concerned with 1617 * consumer platforms with user accessible thunderbolt ports that are 1618 * vulnerable to DMA attacks, and we expect those ports to be marked by 1619 * the firmware as external_facing. Devices in traditional hotplug 1620 * slots can technically be removed, but the expectation is that unless 1621 * the port is marked with external_facing, such devices are less 1622 * accessible to user / may not be removed by end user, and thus not 1623 * exposed as "removable" to userspace. 1624 */ 1625 if (parent && 1626 (parent->external_facing || dev_is_removable(&parent->dev))) 1627 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1628 } 1629 1630 /** 1631 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1632 * @dev: PCI device 1633 * 1634 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1635 * when forwarding a type1 configuration request the bridge must check that 1636 * the extended register address field is zero. The bridge is not permitted 1637 * to forward the transactions and must handle it as an Unsupported Request. 1638 * Some bridges do not follow this rule and simply drop the extended register 1639 * bits, resulting in the standard config space being aliased, every 256 1640 * bytes across the entire configuration space. Test for this condition by 1641 * comparing the first dword of each potential alias to the vendor/device ID. 1642 * Known offenders: 1643 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1644 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1645 */ 1646 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1647 { 1648 #ifdef CONFIG_PCI_QUIRKS 1649 int pos; 1650 u32 header, tmp; 1651 1652 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1653 1654 for (pos = PCI_CFG_SPACE_SIZE; 1655 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1656 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1657 || header != tmp) 1658 return false; 1659 } 1660 1661 return true; 1662 #else 1663 return false; 1664 #endif 1665 } 1666 1667 /** 1668 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1669 * @dev: PCI device 1670 * 1671 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1672 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1673 * access it. Maybe we don't have a way to generate extended config space 1674 * accesses, or the device is behind a reverse Express bridge. So we try 1675 * reading the dword at 0x100 which must either be 0 or a valid extended 1676 * capability header. 1677 */ 1678 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1679 { 1680 u32 status; 1681 int pos = PCI_CFG_SPACE_SIZE; 1682 1683 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1684 return PCI_CFG_SPACE_SIZE; 1685 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1686 return PCI_CFG_SPACE_SIZE; 1687 1688 return PCI_CFG_SPACE_EXP_SIZE; 1689 } 1690 1691 int pci_cfg_space_size(struct pci_dev *dev) 1692 { 1693 int pos; 1694 u32 status; 1695 u16 class; 1696 1697 #ifdef CONFIG_PCI_IOV 1698 /* 1699 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1700 * implement a PCIe capability and therefore must implement extended 1701 * config space. We can skip the NO_EXTCFG test below and the 1702 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1703 * the fact that the SR-IOV capability on the PF resides in extended 1704 * config space and must be accessible and non-aliased to have enabled 1705 * support for this VF. This is a micro performance optimization for 1706 * systems supporting many VFs. 1707 */ 1708 if (dev->is_virtfn) 1709 return PCI_CFG_SPACE_EXP_SIZE; 1710 #endif 1711 1712 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1713 return PCI_CFG_SPACE_SIZE; 1714 1715 class = dev->class >> 8; 1716 if (class == PCI_CLASS_BRIDGE_HOST) 1717 return pci_cfg_space_size_ext(dev); 1718 1719 if (pci_is_pcie(dev)) 1720 return pci_cfg_space_size_ext(dev); 1721 1722 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1723 if (!pos) 1724 return PCI_CFG_SPACE_SIZE; 1725 1726 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1727 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1728 return pci_cfg_space_size_ext(dev); 1729 1730 return PCI_CFG_SPACE_SIZE; 1731 } 1732 1733 static u32 pci_class(struct pci_dev *dev) 1734 { 1735 u32 class; 1736 1737 #ifdef CONFIG_PCI_IOV 1738 if (dev->is_virtfn) 1739 return dev->physfn->sriov->class; 1740 #endif 1741 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1742 return class; 1743 } 1744 1745 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1746 { 1747 #ifdef CONFIG_PCI_IOV 1748 if (dev->is_virtfn) { 1749 *vendor = dev->physfn->sriov->subsystem_vendor; 1750 *device = dev->physfn->sriov->subsystem_device; 1751 return; 1752 } 1753 #endif 1754 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1755 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1756 } 1757 1758 static u8 pci_hdr_type(struct pci_dev *dev) 1759 { 1760 u8 hdr_type; 1761 1762 #ifdef CONFIG_PCI_IOV 1763 if (dev->is_virtfn) 1764 return dev->physfn->sriov->hdr_type; 1765 #endif 1766 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1767 return hdr_type; 1768 } 1769 1770 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1771 1772 /** 1773 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1774 * @dev: PCI device 1775 * 1776 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1777 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1778 */ 1779 static int pci_intx_mask_broken(struct pci_dev *dev) 1780 { 1781 u16 orig, toggle, new; 1782 1783 pci_read_config_word(dev, PCI_COMMAND, &orig); 1784 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1785 pci_write_config_word(dev, PCI_COMMAND, toggle); 1786 pci_read_config_word(dev, PCI_COMMAND, &new); 1787 1788 pci_write_config_word(dev, PCI_COMMAND, orig); 1789 1790 /* 1791 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1792 * r2.3, so strictly speaking, a device is not *broken* if it's not 1793 * writable. But we'll live with the misnomer for now. 1794 */ 1795 if (new != toggle) 1796 return 1; 1797 return 0; 1798 } 1799 1800 static void early_dump_pci_device(struct pci_dev *pdev) 1801 { 1802 u32 value[256 / 4]; 1803 int i; 1804 1805 pci_info(pdev, "config space:\n"); 1806 1807 for (i = 0; i < 256; i += 4) 1808 pci_read_config_dword(pdev, i, &value[i / 4]); 1809 1810 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1811 value, 256, false); 1812 } 1813 1814 /** 1815 * pci_setup_device - Fill in class and map information of a device 1816 * @dev: the device structure to fill 1817 * 1818 * Initialize the device structure with information about the device's 1819 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1820 * Called at initialisation of the PCI subsystem and by CardBus services. 1821 * Returns 0 on success and negative if unknown type of device (not normal, 1822 * bridge or CardBus). 1823 */ 1824 int pci_setup_device(struct pci_dev *dev) 1825 { 1826 u32 class; 1827 u16 cmd; 1828 u8 hdr_type; 1829 int err, pos = 0; 1830 struct pci_bus_region region; 1831 struct resource *res; 1832 1833 hdr_type = pci_hdr_type(dev); 1834 1835 dev->sysdata = dev->bus->sysdata; 1836 dev->dev.parent = dev->bus->bridge; 1837 dev->dev.bus = &pci_bus_type; 1838 dev->hdr_type = hdr_type & 0x7f; 1839 dev->multifunction = !!(hdr_type & 0x80); 1840 dev->error_state = pci_channel_io_normal; 1841 set_pcie_port_type(dev); 1842 1843 err = pci_set_of_node(dev); 1844 if (err) 1845 return err; 1846 pci_set_acpi_fwnode(dev); 1847 1848 pci_dev_assign_slot(dev); 1849 1850 /* 1851 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1852 * set this higher, assuming the system even supports it. 1853 */ 1854 dev->dma_mask = 0xffffffff; 1855 1856 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1857 dev->bus->number, PCI_SLOT(dev->devfn), 1858 PCI_FUNC(dev->devfn)); 1859 1860 class = pci_class(dev); 1861 1862 dev->revision = class & 0xff; 1863 dev->class = class >> 8; /* upper 3 bytes */ 1864 1865 if (pci_early_dump) 1866 early_dump_pci_device(dev); 1867 1868 /* Need to have dev->class ready */ 1869 dev->cfg_size = pci_cfg_space_size(dev); 1870 1871 /* Need to have dev->cfg_size ready */ 1872 set_pcie_thunderbolt(dev); 1873 1874 set_pcie_untrusted(dev); 1875 1876 /* "Unknown power state" */ 1877 dev->current_state = PCI_UNKNOWN; 1878 1879 /* Early fixups, before probing the BARs */ 1880 pci_fixup_device(pci_fixup_early, dev); 1881 1882 pci_set_removable(dev); 1883 1884 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1885 dev->vendor, dev->device, dev->hdr_type, dev->class); 1886 1887 /* Device class may be changed after fixup */ 1888 class = dev->class >> 8; 1889 1890 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1891 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1892 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1893 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1894 cmd &= ~PCI_COMMAND_IO; 1895 cmd &= ~PCI_COMMAND_MEMORY; 1896 pci_write_config_word(dev, PCI_COMMAND, cmd); 1897 } 1898 } 1899 1900 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1901 1902 switch (dev->hdr_type) { /* header type */ 1903 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1904 if (class == PCI_CLASS_BRIDGE_PCI) 1905 goto bad; 1906 pci_read_irq(dev); 1907 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1908 1909 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1910 1911 /* 1912 * Do the ugly legacy mode stuff here rather than broken chip 1913 * quirk code. Legacy mode ATA controllers have fixed 1914 * addresses. These are not always echoed in BAR0-3, and 1915 * BAR0-3 in a few cases contain junk! 1916 */ 1917 if (class == PCI_CLASS_STORAGE_IDE) { 1918 u8 progif; 1919 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1920 if ((progif & 1) == 0) { 1921 region.start = 0x1F0; 1922 region.end = 0x1F7; 1923 res = &dev->resource[0]; 1924 res->flags = LEGACY_IO_RESOURCE; 1925 pcibios_bus_to_resource(dev->bus, res, ®ion); 1926 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1927 res); 1928 region.start = 0x3F6; 1929 region.end = 0x3F6; 1930 res = &dev->resource[1]; 1931 res->flags = LEGACY_IO_RESOURCE; 1932 pcibios_bus_to_resource(dev->bus, res, ®ion); 1933 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1934 res); 1935 } 1936 if ((progif & 4) == 0) { 1937 region.start = 0x170; 1938 region.end = 0x177; 1939 res = &dev->resource[2]; 1940 res->flags = LEGACY_IO_RESOURCE; 1941 pcibios_bus_to_resource(dev->bus, res, ®ion); 1942 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1943 res); 1944 region.start = 0x376; 1945 region.end = 0x376; 1946 res = &dev->resource[3]; 1947 res->flags = LEGACY_IO_RESOURCE; 1948 pcibios_bus_to_resource(dev->bus, res, ®ion); 1949 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1950 res); 1951 } 1952 } 1953 break; 1954 1955 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1956 /* 1957 * The PCI-to-PCI bridge spec requires that subtractive 1958 * decoding (i.e. transparent) bridge must have programming 1959 * interface code of 0x01. 1960 */ 1961 pci_read_irq(dev); 1962 dev->transparent = ((dev->class & 0xff) == 1); 1963 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1964 pci_read_bridge_windows(dev); 1965 set_pcie_hotplug_bridge(dev); 1966 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1967 if (pos) { 1968 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1969 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1970 } 1971 break; 1972 1973 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1974 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1975 goto bad; 1976 pci_read_irq(dev); 1977 pci_read_bases(dev, 1, 0); 1978 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1979 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1980 break; 1981 1982 default: /* unknown header */ 1983 pci_err(dev, "unknown header type %02x, ignoring device\n", 1984 dev->hdr_type); 1985 pci_release_of_node(dev); 1986 return -EIO; 1987 1988 bad: 1989 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1990 dev->class, dev->hdr_type); 1991 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1992 } 1993 1994 /* We found a fine healthy device, go go go... */ 1995 return 0; 1996 } 1997 1998 static void pci_configure_mps(struct pci_dev *dev) 1999 { 2000 struct pci_dev *bridge = pci_upstream_bridge(dev); 2001 int mps, mpss, p_mps, rc; 2002 2003 if (!pci_is_pcie(dev)) 2004 return; 2005 2006 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2007 if (dev->is_virtfn) 2008 return; 2009 2010 /* 2011 * For Root Complex Integrated Endpoints, program the maximum 2012 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2013 */ 2014 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2015 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2016 mps = 128; 2017 else 2018 mps = 128 << dev->pcie_mpss; 2019 rc = pcie_set_mps(dev, mps); 2020 if (rc) { 2021 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2022 mps); 2023 } 2024 return; 2025 } 2026 2027 if (!bridge || !pci_is_pcie(bridge)) 2028 return; 2029 2030 mps = pcie_get_mps(dev); 2031 p_mps = pcie_get_mps(bridge); 2032 2033 if (mps == p_mps) 2034 return; 2035 2036 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2037 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2038 mps, pci_name(bridge), p_mps); 2039 return; 2040 } 2041 2042 /* 2043 * Fancier MPS configuration is done later by 2044 * pcie_bus_configure_settings() 2045 */ 2046 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2047 return; 2048 2049 mpss = 128 << dev->pcie_mpss; 2050 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2051 pcie_set_mps(bridge, mpss); 2052 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2053 mpss, p_mps, 128 << bridge->pcie_mpss); 2054 p_mps = pcie_get_mps(bridge); 2055 } 2056 2057 rc = pcie_set_mps(dev, p_mps); 2058 if (rc) { 2059 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2060 p_mps); 2061 return; 2062 } 2063 2064 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2065 p_mps, mps, mpss); 2066 } 2067 2068 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2069 { 2070 struct pci_host_bridge *host; 2071 u32 cap; 2072 u16 ctl; 2073 int ret; 2074 2075 if (!pci_is_pcie(dev)) 2076 return 0; 2077 2078 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2079 if (ret) 2080 return 0; 2081 2082 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2083 return 0; 2084 2085 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2086 if (ret) 2087 return 0; 2088 2089 host = pci_find_host_bridge(dev->bus); 2090 if (!host) 2091 return 0; 2092 2093 /* 2094 * If some device in the hierarchy doesn't handle Extended Tags 2095 * correctly, make sure they're disabled. 2096 */ 2097 if (host->no_ext_tags) { 2098 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2099 pci_info(dev, "disabling Extended Tags\n"); 2100 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2101 PCI_EXP_DEVCTL_EXT_TAG); 2102 } 2103 return 0; 2104 } 2105 2106 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2107 pci_info(dev, "enabling Extended Tags\n"); 2108 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2109 PCI_EXP_DEVCTL_EXT_TAG); 2110 } 2111 return 0; 2112 } 2113 2114 /** 2115 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2116 * @dev: PCI device to query 2117 * 2118 * Returns true if the device has enabled relaxed ordering attribute. 2119 */ 2120 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2121 { 2122 u16 v; 2123 2124 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2125 2126 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2127 } 2128 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2129 2130 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2131 { 2132 struct pci_dev *root; 2133 2134 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2135 if (dev->is_virtfn) 2136 return; 2137 2138 if (!pcie_relaxed_ordering_enabled(dev)) 2139 return; 2140 2141 /* 2142 * For now, we only deal with Relaxed Ordering issues with Root 2143 * Ports. Peer-to-Peer DMA is another can of worms. 2144 */ 2145 root = pcie_find_root_port(dev); 2146 if (!root) 2147 return; 2148 2149 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2150 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2151 PCI_EXP_DEVCTL_RELAX_EN); 2152 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2153 } 2154 } 2155 2156 static void pci_configure_ltr(struct pci_dev *dev) 2157 { 2158 #ifdef CONFIG_PCIEASPM 2159 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2160 struct pci_dev *bridge; 2161 u32 cap, ctl; 2162 2163 if (!pci_is_pcie(dev)) 2164 return; 2165 2166 /* Read L1 PM substate capabilities */ 2167 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 2168 2169 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2170 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2171 return; 2172 2173 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2174 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2175 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2176 dev->ltr_path = 1; 2177 return; 2178 } 2179 2180 bridge = pci_upstream_bridge(dev); 2181 if (bridge && bridge->ltr_path) 2182 dev->ltr_path = 1; 2183 2184 return; 2185 } 2186 2187 if (!host->native_ltr) 2188 return; 2189 2190 /* 2191 * Software must not enable LTR in an Endpoint unless the Root 2192 * Complex and all intermediate Switches indicate support for LTR. 2193 * PCIe r4.0, sec 6.18. 2194 */ 2195 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2196 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2197 PCI_EXP_DEVCTL2_LTR_EN); 2198 dev->ltr_path = 1; 2199 return; 2200 } 2201 2202 /* 2203 * If we're configuring a hot-added device, LTR was likely 2204 * disabled in the upstream bridge, so re-enable it before enabling 2205 * it in the new device. 2206 */ 2207 bridge = pci_upstream_bridge(dev); 2208 if (bridge && bridge->ltr_path) { 2209 pci_bridge_reconfigure_ltr(dev); 2210 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2211 PCI_EXP_DEVCTL2_LTR_EN); 2212 dev->ltr_path = 1; 2213 } 2214 #endif 2215 } 2216 2217 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2218 { 2219 #ifdef CONFIG_PCI_PASID 2220 struct pci_dev *bridge; 2221 int pcie_type; 2222 u32 cap; 2223 2224 if (!pci_is_pcie(dev)) 2225 return; 2226 2227 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2228 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2229 return; 2230 2231 pcie_type = pci_pcie_type(dev); 2232 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2233 pcie_type == PCI_EXP_TYPE_RC_END) 2234 dev->eetlp_prefix_path = 1; 2235 else { 2236 bridge = pci_upstream_bridge(dev); 2237 if (bridge && bridge->eetlp_prefix_path) 2238 dev->eetlp_prefix_path = 1; 2239 } 2240 #endif 2241 } 2242 2243 static void pci_configure_serr(struct pci_dev *dev) 2244 { 2245 u16 control; 2246 2247 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2248 2249 /* 2250 * A bridge will not forward ERR_ messages coming from an 2251 * endpoint unless SERR# forwarding is enabled. 2252 */ 2253 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2254 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2255 control |= PCI_BRIDGE_CTL_SERR; 2256 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2257 } 2258 } 2259 } 2260 2261 static void pci_configure_device(struct pci_dev *dev) 2262 { 2263 pci_configure_mps(dev); 2264 pci_configure_extended_tags(dev, NULL); 2265 pci_configure_relaxed_ordering(dev); 2266 pci_configure_ltr(dev); 2267 pci_configure_eetlp_prefix(dev); 2268 pci_configure_serr(dev); 2269 2270 pci_acpi_program_hp_params(dev); 2271 } 2272 2273 static void pci_release_capabilities(struct pci_dev *dev) 2274 { 2275 pci_aer_exit(dev); 2276 pci_rcec_exit(dev); 2277 pci_iov_release(dev); 2278 pci_free_cap_save_buffers(dev); 2279 } 2280 2281 /** 2282 * pci_release_dev - Free a PCI device structure when all users of it are 2283 * finished 2284 * @dev: device that's been disconnected 2285 * 2286 * Will be called only by the device core when all users of this PCI device are 2287 * done. 2288 */ 2289 static void pci_release_dev(struct device *dev) 2290 { 2291 struct pci_dev *pci_dev; 2292 2293 pci_dev = to_pci_dev(dev); 2294 pci_release_capabilities(pci_dev); 2295 pci_release_of_node(pci_dev); 2296 pcibios_release_device(pci_dev); 2297 pci_bus_put(pci_dev->bus); 2298 kfree(pci_dev->driver_override); 2299 bitmap_free(pci_dev->dma_alias_mask); 2300 dev_dbg(dev, "device released\n"); 2301 kfree(pci_dev); 2302 } 2303 2304 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2305 { 2306 struct pci_dev *dev; 2307 2308 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2309 if (!dev) 2310 return NULL; 2311 2312 INIT_LIST_HEAD(&dev->bus_list); 2313 dev->dev.type = &pci_dev_type; 2314 dev->bus = pci_bus_get(bus); 2315 dev->driver_exclusive_resource = (struct resource) { 2316 .name = "PCI Exclusive", 2317 .start = 0, 2318 .end = -1, 2319 }; 2320 2321 #ifdef CONFIG_PCI_MSI 2322 raw_spin_lock_init(&dev->msi_lock); 2323 #endif 2324 return dev; 2325 } 2326 EXPORT_SYMBOL(pci_alloc_dev); 2327 2328 static bool pci_bus_crs_vendor_id(u32 l) 2329 { 2330 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 2331 } 2332 2333 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2334 int timeout) 2335 { 2336 int delay = 1; 2337 2338 if (!pci_bus_crs_vendor_id(*l)) 2339 return true; /* not a CRS completion */ 2340 2341 if (!timeout) 2342 return false; /* CRS, but caller doesn't want to wait */ 2343 2344 /* 2345 * We got the reserved Vendor ID that indicates a completion with 2346 * Configuration Request Retry Status (CRS). Retry until we get a 2347 * valid Vendor ID or we time out. 2348 */ 2349 while (pci_bus_crs_vendor_id(*l)) { 2350 if (delay > timeout) { 2351 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2352 pci_domain_nr(bus), bus->number, 2353 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2354 2355 return false; 2356 } 2357 if (delay >= 1000) 2358 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2359 pci_domain_nr(bus), bus->number, 2360 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2361 2362 msleep(delay); 2363 delay *= 2; 2364 2365 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2366 return false; 2367 } 2368 2369 if (delay >= 1000) 2370 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2371 pci_domain_nr(bus), bus->number, 2372 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2373 2374 return true; 2375 } 2376 2377 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2378 int timeout) 2379 { 2380 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2381 return false; 2382 2383 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2384 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2385 *l == 0x0000ffff || *l == 0xffff0000) 2386 return false; 2387 2388 if (pci_bus_crs_vendor_id(*l)) 2389 return pci_bus_wait_crs(bus, devfn, l, timeout); 2390 2391 return true; 2392 } 2393 2394 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2395 int timeout) 2396 { 2397 #ifdef CONFIG_PCI_QUIRKS 2398 struct pci_dev *bridge = bus->self; 2399 2400 /* 2401 * Certain IDT switches have an issue where they improperly trigger 2402 * ACS Source Validation errors on completions for config reads. 2403 */ 2404 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2405 bridge->device == 0x80b5) 2406 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2407 #endif 2408 2409 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2410 } 2411 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2412 2413 /* 2414 * Read the config data for a PCI device, sanity-check it, 2415 * and fill in the dev structure. 2416 */ 2417 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2418 { 2419 struct pci_dev *dev; 2420 u32 l; 2421 2422 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2423 return NULL; 2424 2425 dev = pci_alloc_dev(bus); 2426 if (!dev) 2427 return NULL; 2428 2429 dev->devfn = devfn; 2430 dev->vendor = l & 0xffff; 2431 dev->device = (l >> 16) & 0xffff; 2432 2433 if (pci_setup_device(dev)) { 2434 pci_bus_put(dev->bus); 2435 kfree(dev); 2436 return NULL; 2437 } 2438 2439 return dev; 2440 } 2441 2442 void pcie_report_downtraining(struct pci_dev *dev) 2443 { 2444 if (!pci_is_pcie(dev)) 2445 return; 2446 2447 /* Look from the device up to avoid downstream ports with no devices */ 2448 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2449 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2450 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2451 return; 2452 2453 /* Multi-function PCIe devices share the same link/status */ 2454 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2455 return; 2456 2457 /* Print link status only if the device is constrained by the fabric */ 2458 __pcie_print_link_status(dev, false); 2459 } 2460 2461 static void pci_init_capabilities(struct pci_dev *dev) 2462 { 2463 pci_ea_init(dev); /* Enhanced Allocation */ 2464 pci_msi_init(dev); /* Disable MSI */ 2465 pci_msix_init(dev); /* Disable MSI-X */ 2466 2467 /* Buffers for saving PCIe and PCI-X capabilities */ 2468 pci_allocate_cap_save_buffers(dev); 2469 2470 pci_pm_init(dev); /* Power Management */ 2471 pci_vpd_init(dev); /* Vital Product Data */ 2472 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2473 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2474 pci_ats_init(dev); /* Address Translation Services */ 2475 pci_pri_init(dev); /* Page Request Interface */ 2476 pci_pasid_init(dev); /* Process Address Space ID */ 2477 pci_acs_init(dev); /* Access Control Services */ 2478 pci_ptm_init(dev); /* Precision Time Measurement */ 2479 pci_aer_init(dev); /* Advanced Error Reporting */ 2480 pci_dpc_init(dev); /* Downstream Port Containment */ 2481 pci_rcec_init(dev); /* Root Complex Event Collector */ 2482 pci_doe_init(dev); /* Data Object Exchange */ 2483 2484 pcie_report_downtraining(dev); 2485 pci_init_reset_methods(dev); 2486 } 2487 2488 /* 2489 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2490 * devices. Firmware interfaces that can select the MSI domain on a 2491 * per-device basis should be called from here. 2492 */ 2493 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2494 { 2495 struct irq_domain *d; 2496 2497 /* 2498 * If a domain has been set through the pcibios_device_add() 2499 * callback, then this is the one (platform code knows best). 2500 */ 2501 d = dev_get_msi_domain(&dev->dev); 2502 if (d) 2503 return d; 2504 2505 /* 2506 * Let's see if we have a firmware interface able to provide 2507 * the domain. 2508 */ 2509 d = pci_msi_get_device_domain(dev); 2510 if (d) 2511 return d; 2512 2513 return NULL; 2514 } 2515 2516 static void pci_set_msi_domain(struct pci_dev *dev) 2517 { 2518 struct irq_domain *d; 2519 2520 /* 2521 * If the platform or firmware interfaces cannot supply a 2522 * device-specific MSI domain, then inherit the default domain 2523 * from the host bridge itself. 2524 */ 2525 d = pci_dev_msi_domain(dev); 2526 if (!d) 2527 d = dev_get_msi_domain(&dev->bus->dev); 2528 2529 dev_set_msi_domain(&dev->dev, d); 2530 } 2531 2532 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2533 { 2534 int ret; 2535 2536 pci_configure_device(dev); 2537 2538 device_initialize(&dev->dev); 2539 dev->dev.release = pci_release_dev; 2540 2541 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2542 dev->dev.dma_mask = &dev->dma_mask; 2543 dev->dev.dma_parms = &dev->dma_parms; 2544 dev->dev.coherent_dma_mask = 0xffffffffull; 2545 2546 dma_set_max_seg_size(&dev->dev, 65536); 2547 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2548 2549 /* Fix up broken headers */ 2550 pci_fixup_device(pci_fixup_header, dev); 2551 2552 pci_reassigndev_resource_alignment(dev); 2553 2554 dev->state_saved = false; 2555 2556 pci_init_capabilities(dev); 2557 2558 /* 2559 * Add the device to our list of discovered devices 2560 * and the bus list for fixup functions, etc. 2561 */ 2562 down_write(&pci_bus_sem); 2563 list_add_tail(&dev->bus_list, &bus->devices); 2564 up_write(&pci_bus_sem); 2565 2566 ret = pcibios_device_add(dev); 2567 WARN_ON(ret < 0); 2568 2569 /* Set up MSI IRQ domain */ 2570 pci_set_msi_domain(dev); 2571 2572 /* Notifier could use PCI capabilities */ 2573 dev->match_driver = false; 2574 ret = device_add(&dev->dev); 2575 WARN_ON(ret < 0); 2576 } 2577 2578 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2579 { 2580 struct pci_dev *dev; 2581 2582 dev = pci_get_slot(bus, devfn); 2583 if (dev) { 2584 pci_dev_put(dev); 2585 return dev; 2586 } 2587 2588 dev = pci_scan_device(bus, devfn); 2589 if (!dev) 2590 return NULL; 2591 2592 pci_device_add(dev, bus); 2593 2594 return dev; 2595 } 2596 EXPORT_SYMBOL(pci_scan_single_device); 2597 2598 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2599 { 2600 int pos; 2601 u16 cap = 0; 2602 unsigned int next_fn; 2603 2604 if (!dev) 2605 return -ENODEV; 2606 2607 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2608 if (!pos) 2609 return -ENODEV; 2610 2611 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2612 next_fn = PCI_ARI_CAP_NFN(cap); 2613 if (next_fn <= fn) 2614 return -ENODEV; /* protect against malformed list */ 2615 2616 return next_fn; 2617 } 2618 2619 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2620 { 2621 if (pci_ari_enabled(bus)) 2622 return next_ari_fn(bus, dev, fn); 2623 2624 if (fn >= 7) 2625 return -ENODEV; 2626 /* only multifunction devices may have more functions */ 2627 if (dev && !dev->multifunction) 2628 return -ENODEV; 2629 2630 return fn + 1; 2631 } 2632 2633 static int only_one_child(struct pci_bus *bus) 2634 { 2635 struct pci_dev *bridge = bus->self; 2636 2637 /* 2638 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2639 * we scan for all possible devices, not just Device 0. 2640 */ 2641 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2642 return 0; 2643 2644 /* 2645 * A PCIe Downstream Port normally leads to a Link with only Device 2646 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2647 * only for Device 0 in that situation. 2648 */ 2649 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2650 return 1; 2651 2652 return 0; 2653 } 2654 2655 /** 2656 * pci_scan_slot - Scan a PCI slot on a bus for devices 2657 * @bus: PCI bus to scan 2658 * @devfn: slot number to scan (must have zero function) 2659 * 2660 * Scan a PCI slot on the specified PCI bus for devices, adding 2661 * discovered devices to the @bus->devices list. New devices 2662 * will not have is_added set. 2663 * 2664 * Returns the number of new devices found. 2665 */ 2666 int pci_scan_slot(struct pci_bus *bus, int devfn) 2667 { 2668 struct pci_dev *dev; 2669 int fn = 0, nr = 0; 2670 2671 if (only_one_child(bus) && (devfn > 0)) 2672 return 0; /* Already scanned the entire slot */ 2673 2674 do { 2675 dev = pci_scan_single_device(bus, devfn + fn); 2676 if (dev) { 2677 if (!pci_dev_is_added(dev)) 2678 nr++; 2679 if (fn > 0) 2680 dev->multifunction = 1; 2681 } else if (fn == 0) { 2682 /* 2683 * Function 0 is required unless we are running on 2684 * a hypervisor that passes through individual PCI 2685 * functions. 2686 */ 2687 if (!hypervisor_isolated_pci_functions()) 2688 break; 2689 } 2690 fn = next_fn(bus, dev, fn); 2691 } while (fn >= 0); 2692 2693 /* Only one slot has PCIe device */ 2694 if (bus->self && nr) 2695 pcie_aspm_init_link_state(bus->self); 2696 2697 return nr; 2698 } 2699 EXPORT_SYMBOL(pci_scan_slot); 2700 2701 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2702 { 2703 u8 *smpss = data; 2704 2705 if (!pci_is_pcie(dev)) 2706 return 0; 2707 2708 /* 2709 * We don't have a way to change MPS settings on devices that have 2710 * drivers attached. A hot-added device might support only the minimum 2711 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2712 * where devices may be hot-added, we limit the fabric MPS to 128 so 2713 * hot-added devices will work correctly. 2714 * 2715 * However, if we hot-add a device to a slot directly below a Root 2716 * Port, it's impossible for there to be other existing devices below 2717 * the port. We don't limit the MPS in this case because we can 2718 * reconfigure MPS on both the Root Port and the hot-added device, 2719 * and there are no other devices involved. 2720 * 2721 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2722 */ 2723 if (dev->is_hotplug_bridge && 2724 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2725 *smpss = 0; 2726 2727 if (*smpss > dev->pcie_mpss) 2728 *smpss = dev->pcie_mpss; 2729 2730 return 0; 2731 } 2732 2733 static void pcie_write_mps(struct pci_dev *dev, int mps) 2734 { 2735 int rc; 2736 2737 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2738 mps = 128 << dev->pcie_mpss; 2739 2740 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2741 dev->bus->self) 2742 2743 /* 2744 * For "Performance", the assumption is made that 2745 * downstream communication will never be larger than 2746 * the MRRS. So, the MPS only needs to be configured 2747 * for the upstream communication. This being the case, 2748 * walk from the top down and set the MPS of the child 2749 * to that of the parent bus. 2750 * 2751 * Configure the device MPS with the smaller of the 2752 * device MPSS or the bridge MPS (which is assumed to be 2753 * properly configured at this point to the largest 2754 * allowable MPS based on its parent bus). 2755 */ 2756 mps = min(mps, pcie_get_mps(dev->bus->self)); 2757 } 2758 2759 rc = pcie_set_mps(dev, mps); 2760 if (rc) 2761 pci_err(dev, "Failed attempting to set the MPS\n"); 2762 } 2763 2764 static void pcie_write_mrrs(struct pci_dev *dev) 2765 { 2766 int rc, mrrs; 2767 2768 /* 2769 * In the "safe" case, do not configure the MRRS. There appear to be 2770 * issues with setting MRRS to 0 on a number of devices. 2771 */ 2772 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2773 return; 2774 2775 /* 2776 * For max performance, the MRRS must be set to the largest supported 2777 * value. However, it cannot be configured larger than the MPS the 2778 * device or the bus can support. This should already be properly 2779 * configured by a prior call to pcie_write_mps(). 2780 */ 2781 mrrs = pcie_get_mps(dev); 2782 2783 /* 2784 * MRRS is a R/W register. Invalid values can be written, but a 2785 * subsequent read will verify if the value is acceptable or not. 2786 * If the MRRS value provided is not acceptable (e.g., too large), 2787 * shrink the value until it is acceptable to the HW. 2788 */ 2789 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2790 rc = pcie_set_readrq(dev, mrrs); 2791 if (!rc) 2792 break; 2793 2794 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2795 mrrs /= 2; 2796 } 2797 2798 if (mrrs < 128) 2799 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2800 } 2801 2802 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2803 { 2804 int mps, orig_mps; 2805 2806 if (!pci_is_pcie(dev)) 2807 return 0; 2808 2809 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2810 pcie_bus_config == PCIE_BUS_DEFAULT) 2811 return 0; 2812 2813 mps = 128 << *(u8 *)data; 2814 orig_mps = pcie_get_mps(dev); 2815 2816 pcie_write_mps(dev, mps); 2817 pcie_write_mrrs(dev); 2818 2819 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2820 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2821 orig_mps, pcie_get_readrq(dev)); 2822 2823 return 0; 2824 } 2825 2826 /* 2827 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2828 * parents then children fashion. If this changes, then this code will not 2829 * work as designed. 2830 */ 2831 void pcie_bus_configure_settings(struct pci_bus *bus) 2832 { 2833 u8 smpss = 0; 2834 2835 if (!bus->self) 2836 return; 2837 2838 if (!pci_is_pcie(bus->self)) 2839 return; 2840 2841 /* 2842 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2843 * to be aware of the MPS of the destination. To work around this, 2844 * simply force the MPS of the entire system to the smallest possible. 2845 */ 2846 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2847 smpss = 0; 2848 2849 if (pcie_bus_config == PCIE_BUS_SAFE) { 2850 smpss = bus->self->pcie_mpss; 2851 2852 pcie_find_smpss(bus->self, &smpss); 2853 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2854 } 2855 2856 pcie_bus_configure_set(bus->self, &smpss); 2857 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2858 } 2859 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2860 2861 /* 2862 * Called after each bus is probed, but before its children are examined. This 2863 * is marked as __weak because multiple architectures define it. 2864 */ 2865 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2866 { 2867 /* nothing to do, expected to be removed in the future */ 2868 } 2869 2870 /** 2871 * pci_scan_child_bus_extend() - Scan devices below a bus 2872 * @bus: Bus to scan for devices 2873 * @available_buses: Total number of buses available (%0 does not try to 2874 * extend beyond the minimal) 2875 * 2876 * Scans devices below @bus including subordinate buses. Returns new 2877 * subordinate number including all the found devices. Passing 2878 * @available_buses causes the remaining bus space to be distributed 2879 * equally between hotplug-capable bridges to allow future extension of the 2880 * hierarchy. 2881 */ 2882 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2883 unsigned int available_buses) 2884 { 2885 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2886 unsigned int start = bus->busn_res.start; 2887 unsigned int devfn, cmax, max = start; 2888 struct pci_dev *dev; 2889 2890 dev_dbg(&bus->dev, "scanning bus\n"); 2891 2892 /* Go find them, Rover! */ 2893 for (devfn = 0; devfn < 256; devfn += 8) 2894 pci_scan_slot(bus, devfn); 2895 2896 /* Reserve buses for SR-IOV capability */ 2897 used_buses = pci_iov_bus_range(bus); 2898 max += used_buses; 2899 2900 /* 2901 * After performing arch-dependent fixup of the bus, look behind 2902 * all PCI-to-PCI bridges on this bus. 2903 */ 2904 if (!bus->is_added) { 2905 dev_dbg(&bus->dev, "fixups for bus\n"); 2906 pcibios_fixup_bus(bus); 2907 bus->is_added = 1; 2908 } 2909 2910 /* 2911 * Calculate how many hotplug bridges and normal bridges there 2912 * are on this bus. We will distribute the additional available 2913 * buses between hotplug bridges. 2914 */ 2915 for_each_pci_bridge(dev, bus) { 2916 if (dev->is_hotplug_bridge) 2917 hotplug_bridges++; 2918 else 2919 normal_bridges++; 2920 } 2921 2922 /* 2923 * Scan bridges that are already configured. We don't touch them 2924 * unless they are misconfigured (which will be done in the second 2925 * scan below). 2926 */ 2927 for_each_pci_bridge(dev, bus) { 2928 cmax = max; 2929 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2930 2931 /* 2932 * Reserve one bus for each bridge now to avoid extending 2933 * hotplug bridges too much during the second scan below. 2934 */ 2935 used_buses++; 2936 if (max - cmax > 1) 2937 used_buses += max - cmax - 1; 2938 } 2939 2940 /* Scan bridges that need to be reconfigured */ 2941 for_each_pci_bridge(dev, bus) { 2942 unsigned int buses = 0; 2943 2944 if (!hotplug_bridges && normal_bridges == 1) { 2945 /* 2946 * There is only one bridge on the bus (upstream 2947 * port) so it gets all available buses which it 2948 * can then distribute to the possible hotplug 2949 * bridges below. 2950 */ 2951 buses = available_buses; 2952 } else if (dev->is_hotplug_bridge) { 2953 /* 2954 * Distribute the extra buses between hotplug 2955 * bridges if any. 2956 */ 2957 buses = available_buses / hotplug_bridges; 2958 buses = min(buses, available_buses - used_buses + 1); 2959 } 2960 2961 cmax = max; 2962 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2963 /* One bus is already accounted so don't add it again */ 2964 if (max - cmax > 1) 2965 used_buses += max - cmax - 1; 2966 } 2967 2968 /* 2969 * Make sure a hotplug bridge has at least the minimum requested 2970 * number of buses but allow it to grow up to the maximum available 2971 * bus number if there is room. 2972 */ 2973 if (bus->self && bus->self->is_hotplug_bridge) { 2974 used_buses = max_t(unsigned int, available_buses, 2975 pci_hotplug_bus_size - 1); 2976 if (max - start < used_buses) { 2977 max = start + used_buses; 2978 2979 /* Do not allocate more buses than we have room left */ 2980 if (max > bus->busn_res.end) 2981 max = bus->busn_res.end; 2982 2983 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2984 &bus->busn_res, max - start); 2985 } 2986 } 2987 2988 /* 2989 * We've scanned the bus and so we know all about what's on 2990 * the other side of any bridges that may be on this bus plus 2991 * any devices. 2992 * 2993 * Return how far we've got finding sub-buses. 2994 */ 2995 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2996 return max; 2997 } 2998 2999 /** 3000 * pci_scan_child_bus() - Scan devices below a bus 3001 * @bus: Bus to scan for devices 3002 * 3003 * Scans devices below @bus including subordinate buses. Returns new 3004 * subordinate number including all the found devices. 3005 */ 3006 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3007 { 3008 return pci_scan_child_bus_extend(bus, 0); 3009 } 3010 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3011 3012 /** 3013 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3014 * @bridge: Host bridge to set up 3015 * 3016 * Default empty implementation. Replace with an architecture-specific setup 3017 * routine, if necessary. 3018 */ 3019 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3020 { 3021 return 0; 3022 } 3023 3024 void __weak pcibios_add_bus(struct pci_bus *bus) 3025 { 3026 } 3027 3028 void __weak pcibios_remove_bus(struct pci_bus *bus) 3029 { 3030 } 3031 3032 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3033 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3034 { 3035 int error; 3036 struct pci_host_bridge *bridge; 3037 3038 bridge = pci_alloc_host_bridge(0); 3039 if (!bridge) 3040 return NULL; 3041 3042 bridge->dev.parent = parent; 3043 3044 list_splice_init(resources, &bridge->windows); 3045 bridge->sysdata = sysdata; 3046 bridge->busnr = bus; 3047 bridge->ops = ops; 3048 3049 error = pci_register_host_bridge(bridge); 3050 if (error < 0) 3051 goto err_out; 3052 3053 return bridge->bus; 3054 3055 err_out: 3056 put_device(&bridge->dev); 3057 return NULL; 3058 } 3059 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3060 3061 int pci_host_probe(struct pci_host_bridge *bridge) 3062 { 3063 struct pci_bus *bus, *child; 3064 int ret; 3065 3066 ret = pci_scan_root_bus_bridge(bridge); 3067 if (ret < 0) { 3068 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3069 return ret; 3070 } 3071 3072 bus = bridge->bus; 3073 3074 /* 3075 * We insert PCI resources into the iomem_resource and 3076 * ioport_resource trees in either pci_bus_claim_resources() 3077 * or pci_bus_assign_resources(). 3078 */ 3079 if (pci_has_flag(PCI_PROBE_ONLY)) { 3080 pci_bus_claim_resources(bus); 3081 } else { 3082 pci_bus_size_bridges(bus); 3083 pci_bus_assign_resources(bus); 3084 3085 list_for_each_entry(child, &bus->children, node) 3086 pcie_bus_configure_settings(child); 3087 } 3088 3089 pci_bus_add_devices(bus); 3090 return 0; 3091 } 3092 EXPORT_SYMBOL_GPL(pci_host_probe); 3093 3094 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3095 { 3096 struct resource *res = &b->busn_res; 3097 struct resource *parent_res, *conflict; 3098 3099 res->start = bus; 3100 res->end = bus_max; 3101 res->flags = IORESOURCE_BUS; 3102 3103 if (!pci_is_root_bus(b)) 3104 parent_res = &b->parent->busn_res; 3105 else { 3106 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3107 res->flags |= IORESOURCE_PCI_FIXED; 3108 } 3109 3110 conflict = request_resource_conflict(parent_res, res); 3111 3112 if (conflict) 3113 dev_info(&b->dev, 3114 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3115 res, pci_is_root_bus(b) ? "domain " : "", 3116 parent_res, conflict->name, conflict); 3117 3118 return conflict == NULL; 3119 } 3120 3121 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3122 { 3123 struct resource *res = &b->busn_res; 3124 struct resource old_res = *res; 3125 resource_size_t size; 3126 int ret; 3127 3128 if (res->start > bus_max) 3129 return -EINVAL; 3130 3131 size = bus_max - res->start + 1; 3132 ret = adjust_resource(res, res->start, size); 3133 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3134 &old_res, ret ? "can not be" : "is", bus_max); 3135 3136 if (!ret && !res->parent) 3137 pci_bus_insert_busn_res(b, res->start, res->end); 3138 3139 return ret; 3140 } 3141 3142 void pci_bus_release_busn_res(struct pci_bus *b) 3143 { 3144 struct resource *res = &b->busn_res; 3145 int ret; 3146 3147 if (!res->flags || !res->parent) 3148 return; 3149 3150 ret = release_resource(res); 3151 dev_info(&b->dev, "busn_res: %pR %s released\n", 3152 res, ret ? "can not be" : "is"); 3153 } 3154 3155 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3156 { 3157 struct resource_entry *window; 3158 bool found = false; 3159 struct pci_bus *b; 3160 int max, bus, ret; 3161 3162 if (!bridge) 3163 return -EINVAL; 3164 3165 resource_list_for_each_entry(window, &bridge->windows) 3166 if (window->res->flags & IORESOURCE_BUS) { 3167 bridge->busnr = window->res->start; 3168 found = true; 3169 break; 3170 } 3171 3172 ret = pci_register_host_bridge(bridge); 3173 if (ret < 0) 3174 return ret; 3175 3176 b = bridge->bus; 3177 bus = bridge->busnr; 3178 3179 if (!found) { 3180 dev_info(&b->dev, 3181 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3182 bus); 3183 pci_bus_insert_busn_res(b, bus, 255); 3184 } 3185 3186 max = pci_scan_child_bus(b); 3187 3188 if (!found) 3189 pci_bus_update_busn_res_end(b, max); 3190 3191 return 0; 3192 } 3193 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3194 3195 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3196 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3197 { 3198 struct resource_entry *window; 3199 bool found = false; 3200 struct pci_bus *b; 3201 int max; 3202 3203 resource_list_for_each_entry(window, resources) 3204 if (window->res->flags & IORESOURCE_BUS) { 3205 found = true; 3206 break; 3207 } 3208 3209 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3210 if (!b) 3211 return NULL; 3212 3213 if (!found) { 3214 dev_info(&b->dev, 3215 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3216 bus); 3217 pci_bus_insert_busn_res(b, bus, 255); 3218 } 3219 3220 max = pci_scan_child_bus(b); 3221 3222 if (!found) 3223 pci_bus_update_busn_res_end(b, max); 3224 3225 return b; 3226 } 3227 EXPORT_SYMBOL(pci_scan_root_bus); 3228 3229 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3230 void *sysdata) 3231 { 3232 LIST_HEAD(resources); 3233 struct pci_bus *b; 3234 3235 pci_add_resource(&resources, &ioport_resource); 3236 pci_add_resource(&resources, &iomem_resource); 3237 pci_add_resource(&resources, &busn_resource); 3238 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3239 if (b) { 3240 pci_scan_child_bus(b); 3241 } else { 3242 pci_free_resource_list(&resources); 3243 } 3244 return b; 3245 } 3246 EXPORT_SYMBOL(pci_scan_bus); 3247 3248 /** 3249 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3250 * @bridge: PCI bridge for the bus to scan 3251 * 3252 * Scan a PCI bus and child buses for new devices, add them, 3253 * and enable them, resizing bridge mmio/io resource if necessary 3254 * and possible. The caller must ensure the child devices are already 3255 * removed for resizing to occur. 3256 * 3257 * Returns the max number of subordinate bus discovered. 3258 */ 3259 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3260 { 3261 unsigned int max; 3262 struct pci_bus *bus = bridge->subordinate; 3263 3264 max = pci_scan_child_bus(bus); 3265 3266 pci_assign_unassigned_bridge_resources(bridge); 3267 3268 pci_bus_add_devices(bus); 3269 3270 return max; 3271 } 3272 3273 /** 3274 * pci_rescan_bus - Scan a PCI bus for devices 3275 * @bus: PCI bus to scan 3276 * 3277 * Scan a PCI bus and child buses for new devices, add them, 3278 * and enable them. 3279 * 3280 * Returns the max number of subordinate bus discovered. 3281 */ 3282 unsigned int pci_rescan_bus(struct pci_bus *bus) 3283 { 3284 unsigned int max; 3285 3286 max = pci_scan_child_bus(bus); 3287 pci_assign_unassigned_bus_resources(bus); 3288 pci_bus_add_devices(bus); 3289 3290 return max; 3291 } 3292 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3293 3294 /* 3295 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3296 * routines should always be executed under this mutex. 3297 */ 3298 static DEFINE_MUTEX(pci_rescan_remove_lock); 3299 3300 void pci_lock_rescan_remove(void) 3301 { 3302 mutex_lock(&pci_rescan_remove_lock); 3303 } 3304 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3305 3306 void pci_unlock_rescan_remove(void) 3307 { 3308 mutex_unlock(&pci_rescan_remove_lock); 3309 } 3310 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3311 3312 static int __init pci_sort_bf_cmp(const struct device *d_a, 3313 const struct device *d_b) 3314 { 3315 const struct pci_dev *a = to_pci_dev(d_a); 3316 const struct pci_dev *b = to_pci_dev(d_b); 3317 3318 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3319 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3320 3321 if (a->bus->number < b->bus->number) return -1; 3322 else if (a->bus->number > b->bus->number) return 1; 3323 3324 if (a->devfn < b->devfn) return -1; 3325 else if (a->devfn > b->devfn) return 1; 3326 3327 return 0; 3328 } 3329 3330 void __init pci_sort_breadthfirst(void) 3331 { 3332 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3333 } 3334 3335 int pci_hp_add_bridge(struct pci_dev *dev) 3336 { 3337 struct pci_bus *parent = dev->bus; 3338 int busnr, start = parent->busn_res.start; 3339 unsigned int available_buses = 0; 3340 int end = parent->busn_res.end; 3341 3342 for (busnr = start; busnr <= end; busnr++) { 3343 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3344 break; 3345 } 3346 if (busnr-- > end) { 3347 pci_err(dev, "No bus number available for hot-added bridge\n"); 3348 return -1; 3349 } 3350 3351 /* Scan bridges that are already configured */ 3352 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3353 3354 /* 3355 * Distribute the available bus numbers between hotplug-capable 3356 * bridges to make extending the chain later possible. 3357 */ 3358 available_buses = end - busnr; 3359 3360 /* Scan bridges that need to be reconfigured */ 3361 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3362 3363 if (!dev->subordinate) 3364 return -1; 3365 3366 return 0; 3367 } 3368 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3369