1 /* 2 * probe.c - PCI detection and setup code 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/delay.h> 7 #include <linux/init.h> 8 #include <linux/pci.h> 9 #include <linux/slab.h> 10 #include <linux/module.h> 11 #include <linux/cpumask.h> 12 #include <linux/pci-aspm.h> 13 #include <acpi/acpi_hest.h> 14 #include "pci.h" 15 16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 17 #define CARDBUS_RESERVE_BUSNR 3 18 19 /* Ugh. Need to stop exporting this to modules. */ 20 LIST_HEAD(pci_root_buses); 21 EXPORT_SYMBOL(pci_root_buses); 22 23 24 static int find_anything(struct device *dev, void *data) 25 { 26 return 1; 27 } 28 29 /* 30 * Some device drivers need know if pci is initiated. 31 * Basically, we think pci is not initiated when there 32 * is no device to be found on the pci_bus_type. 33 */ 34 int no_pci_devices(void) 35 { 36 struct device *dev; 37 int no_devices; 38 39 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 40 no_devices = (dev == NULL); 41 put_device(dev); 42 return no_devices; 43 } 44 EXPORT_SYMBOL(no_pci_devices); 45 46 /* 47 * PCI Bus Class Devices 48 */ 49 static ssize_t pci_bus_show_cpuaffinity(struct device *dev, 50 int type, 51 struct device_attribute *attr, 52 char *buf) 53 { 54 int ret; 55 const struct cpumask *cpumask; 56 57 cpumask = cpumask_of_pcibus(to_pci_bus(dev)); 58 ret = type? 59 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : 60 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); 61 buf[ret++] = '\n'; 62 buf[ret] = '\0'; 63 return ret; 64 } 65 66 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, 67 struct device_attribute *attr, 68 char *buf) 69 { 70 return pci_bus_show_cpuaffinity(dev, 0, attr, buf); 71 } 72 73 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, 74 struct device_attribute *attr, 75 char *buf) 76 { 77 return pci_bus_show_cpuaffinity(dev, 1, attr, buf); 78 } 79 80 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); 81 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); 82 83 /* 84 * PCI Bus Class 85 */ 86 static void release_pcibus_dev(struct device *dev) 87 { 88 struct pci_bus *pci_bus = to_pci_bus(dev); 89 90 if (pci_bus->bridge) 91 put_device(pci_bus->bridge); 92 kfree(pci_bus); 93 } 94 95 static struct class pcibus_class = { 96 .name = "pci_bus", 97 .dev_release = &release_pcibus_dev, 98 }; 99 100 static int __init pcibus_class_init(void) 101 { 102 return class_register(&pcibus_class); 103 } 104 postcore_initcall(pcibus_class_init); 105 106 /* 107 * Translate the low bits of the PCI base 108 * to the resource type 109 */ 110 static inline unsigned int pci_calc_resource_flags(unsigned int flags) 111 { 112 if (flags & PCI_BASE_ADDRESS_SPACE_IO) 113 return IORESOURCE_IO; 114 115 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 116 return IORESOURCE_MEM | IORESOURCE_PREFETCH; 117 118 return IORESOURCE_MEM; 119 } 120 121 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 122 { 123 u64 size = mask & maxbase; /* Find the significant bits */ 124 if (!size) 125 return 0; 126 127 /* Get the lowest of them to find the decode size, and 128 from that the extent. */ 129 size = (size & ~(size-1)) - 1; 130 131 /* base == maxbase can be valid only if the BAR has 132 already been programmed with all 1s. */ 133 if (base == maxbase && ((base | size) & mask) != mask) 134 return 0; 135 136 return size; 137 } 138 139 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) 140 { 141 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 142 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 143 return pci_bar_io; 144 } 145 146 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 147 148 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) 149 return pci_bar_mem64; 150 return pci_bar_mem32; 151 } 152 153 /** 154 * pci_read_base - read a PCI BAR 155 * @dev: the PCI device 156 * @type: type of the BAR 157 * @res: resource buffer to be filled in 158 * @pos: BAR position in the config space 159 * 160 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 161 */ 162 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 163 struct resource *res, unsigned int pos) 164 { 165 u32 l, sz, mask; 166 167 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 168 169 res->name = pci_name(dev); 170 171 pci_read_config_dword(dev, pos, &l); 172 pci_write_config_dword(dev, pos, l | mask); 173 pci_read_config_dword(dev, pos, &sz); 174 pci_write_config_dword(dev, pos, l); 175 176 /* 177 * All bits set in sz means the device isn't working properly. 178 * If the BAR isn't implemented, all bits must be 0. If it's a 179 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 180 * 1 must be clear. 181 */ 182 if (!sz || sz == 0xffffffff) 183 goto fail; 184 185 /* 186 * I don't know how l can have all bits set. Copied from old code. 187 * Maybe it fixes a bug on some ancient platform. 188 */ 189 if (l == 0xffffffff) 190 l = 0; 191 192 if (type == pci_bar_unknown) { 193 type = decode_bar(res, l); 194 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 195 if (type == pci_bar_io) { 196 l &= PCI_BASE_ADDRESS_IO_MASK; 197 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; 198 } else { 199 l &= PCI_BASE_ADDRESS_MEM_MASK; 200 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 201 } 202 } else { 203 res->flags |= (l & IORESOURCE_ROM_ENABLE); 204 l &= PCI_ROM_ADDRESS_MASK; 205 mask = (u32)PCI_ROM_ADDRESS_MASK; 206 } 207 208 if (type == pci_bar_mem64) { 209 u64 l64 = l; 210 u64 sz64 = sz; 211 u64 mask64 = mask | (u64)~0 << 32; 212 213 pci_read_config_dword(dev, pos + 4, &l); 214 pci_write_config_dword(dev, pos + 4, ~0); 215 pci_read_config_dword(dev, pos + 4, &sz); 216 pci_write_config_dword(dev, pos + 4, l); 217 218 l64 |= ((u64)l << 32); 219 sz64 |= ((u64)sz << 32); 220 221 sz64 = pci_size(l64, sz64, mask64); 222 223 if (!sz64) 224 goto fail; 225 226 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 227 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", 228 pos); 229 goto fail; 230 } 231 232 res->flags |= IORESOURCE_MEM_64; 233 if ((sizeof(resource_size_t) < 8) && l) { 234 /* Address above 32-bit boundary; disable the BAR */ 235 pci_write_config_dword(dev, pos, 0); 236 pci_write_config_dword(dev, pos + 4, 0); 237 res->start = 0; 238 res->end = sz64; 239 } else { 240 res->start = l64; 241 res->end = l64 + sz64; 242 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", 243 pos, res); 244 } 245 } else { 246 sz = pci_size(l, sz, mask); 247 248 if (!sz) 249 goto fail; 250 251 res->start = l; 252 res->end = l + sz; 253 254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); 255 } 256 257 out: 258 return (type == pci_bar_mem64) ? 1 : 0; 259 fail: 260 res->flags = 0; 261 goto out; 262 } 263 264 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 265 { 266 unsigned int pos, reg; 267 268 for (pos = 0; pos < howmany; pos++) { 269 struct resource *res = &dev->resource[pos]; 270 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 271 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 272 } 273 274 if (rom) { 275 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 276 dev->rom_base_reg = rom; 277 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 278 IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 279 IORESOURCE_SIZEALIGN; 280 __pci_read_base(dev, pci_bar_mem32, res, rom); 281 } 282 } 283 284 void __devinit pci_read_bridge_bases(struct pci_bus *child) 285 { 286 struct pci_dev *dev = child->self; 287 u8 io_base_lo, io_limit_lo; 288 u16 mem_base_lo, mem_limit_lo; 289 unsigned long base, limit; 290 struct resource *res; 291 int i; 292 293 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 294 return; 295 296 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 297 child->secondary, child->subordinate, 298 dev->transparent ? " (subtractive decode)": ""); 299 300 if (dev->transparent) { 301 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) 302 child->resource[i] = child->parent->resource[i - 3]; 303 } 304 305 res = child->resource[0]; 306 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 307 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 308 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 309 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 310 311 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 312 u16 io_base_hi, io_limit_hi; 313 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 314 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 315 base |= (io_base_hi << 16); 316 limit |= (io_limit_hi << 16); 317 } 318 319 if (base <= limit) { 320 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 321 if (!res->start) 322 res->start = base; 323 if (!res->end) 324 res->end = limit + 0xfff; 325 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 326 } 327 328 res = child->resource[1]; 329 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 330 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 331 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 332 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 333 if (base <= limit) { 334 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 335 res->start = base; 336 res->end = limit + 0xfffff; 337 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 338 } 339 340 res = child->resource[2]; 341 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 342 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 343 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 344 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 345 346 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 347 u32 mem_base_hi, mem_limit_hi; 348 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 349 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 350 351 /* 352 * Some bridges set the base > limit by default, and some 353 * (broken) BIOSes do not initialize them. If we find 354 * this, just assume they are not being used. 355 */ 356 if (mem_base_hi <= mem_limit_hi) { 357 #if BITS_PER_LONG == 64 358 base |= ((long) mem_base_hi) << 32; 359 limit |= ((long) mem_limit_hi) << 32; 360 #else 361 if (mem_base_hi || mem_limit_hi) { 362 dev_err(&dev->dev, "can't handle 64-bit " 363 "address space for bridge\n"); 364 return; 365 } 366 #endif 367 } 368 } 369 if (base <= limit) { 370 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 371 IORESOURCE_MEM | IORESOURCE_PREFETCH; 372 if (res->flags & PCI_PREF_RANGE_TYPE_64) 373 res->flags |= IORESOURCE_MEM_64; 374 res->start = base; 375 res->end = limit + 0xfffff; 376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 377 } 378 } 379 380 static struct pci_bus * pci_alloc_bus(void) 381 { 382 struct pci_bus *b; 383 384 b = kzalloc(sizeof(*b), GFP_KERNEL); 385 if (b) { 386 INIT_LIST_HEAD(&b->node); 387 INIT_LIST_HEAD(&b->children); 388 INIT_LIST_HEAD(&b->devices); 389 INIT_LIST_HEAD(&b->slots); 390 } 391 return b; 392 } 393 394 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 395 struct pci_dev *bridge, int busnr) 396 { 397 struct pci_bus *child; 398 int i; 399 400 /* 401 * Allocate a new bus, and inherit stuff from the parent.. 402 */ 403 child = pci_alloc_bus(); 404 if (!child) 405 return NULL; 406 407 child->parent = parent; 408 child->ops = parent->ops; 409 child->sysdata = parent->sysdata; 410 child->bus_flags = parent->bus_flags; 411 412 /* initialize some portions of the bus device, but don't register it 413 * now as the parent is not properly set up yet. This device will get 414 * registered later in pci_bus_add_devices() 415 */ 416 child->dev.class = &pcibus_class; 417 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 418 419 /* 420 * Set up the primary, secondary and subordinate 421 * bus numbers. 422 */ 423 child->number = child->secondary = busnr; 424 child->primary = parent->secondary; 425 child->subordinate = 0xff; 426 427 if (!bridge) 428 return child; 429 430 child->self = bridge; 431 child->bridge = get_device(&bridge->dev); 432 433 /* Set up default resource pointers and names.. */ 434 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 435 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 436 child->resource[i]->name = child->name; 437 } 438 bridge->subordinate = child; 439 440 return child; 441 } 442 443 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 444 { 445 struct pci_bus *child; 446 447 child = pci_alloc_child_bus(parent, dev, busnr); 448 if (child) { 449 down_write(&pci_bus_sem); 450 list_add_tail(&child->node, &parent->children); 451 up_write(&pci_bus_sem); 452 } 453 return child; 454 } 455 456 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 457 { 458 struct pci_bus *parent = child->parent; 459 460 /* Attempts to fix that up are really dangerous unless 461 we're going to re-assign all bus numbers. */ 462 if (!pcibios_assign_all_busses()) 463 return; 464 465 while (parent->parent && parent->subordinate < max) { 466 parent->subordinate = max; 467 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 468 parent = parent->parent; 469 } 470 } 471 472 /* 473 * If it's a bridge, configure it and scan the bus behind it. 474 * For CardBus bridges, we don't scan behind as the devices will 475 * be handled by the bridge driver itself. 476 * 477 * We need to process bridges in two passes -- first we scan those 478 * already configured by the BIOS and after we are done with all of 479 * them, we proceed to assigning numbers to the remaining buses in 480 * order to avoid overlaps between old and new bus numbers. 481 */ 482 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 483 { 484 struct pci_bus *child; 485 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 486 u32 buses, i, j = 0; 487 u16 bctl; 488 int broken = 0; 489 490 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 491 492 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", 493 buses & 0xffffff, pass); 494 495 /* Check if setup is sensible at all */ 496 if (!pass && 497 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) { 498 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); 499 broken = 1; 500 } 501 502 /* Disable MasterAbortMode during probing to avoid reporting 503 of bus errors (in some architectures) */ 504 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 505 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 506 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 507 508 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { 509 unsigned int cmax, busnr; 510 /* 511 * Bus already configured by firmware, process it in the first 512 * pass and just note the configuration. 513 */ 514 if (pass) 515 goto out; 516 busnr = (buses >> 8) & 0xFF; 517 518 /* 519 * If we already got to this bus through a different bridge, 520 * don't re-add it. This can happen with the i450NX chipset. 521 * 522 * However, we continue to descend down the hierarchy and 523 * scan remaining child buses. 524 */ 525 child = pci_find_bus(pci_domain_nr(bus), busnr); 526 if (!child) { 527 child = pci_add_new_bus(bus, dev, busnr); 528 if (!child) 529 goto out; 530 child->primary = buses & 0xFF; 531 child->subordinate = (buses >> 16) & 0xFF; 532 child->bridge_ctl = bctl; 533 } 534 535 cmax = pci_scan_child_bus(child); 536 if (cmax > max) 537 max = cmax; 538 if (child->subordinate > max) 539 max = child->subordinate; 540 } else { 541 /* 542 * We need to assign a number to this bus which we always 543 * do in the second pass. 544 */ 545 if (!pass) { 546 if (pcibios_assign_all_busses() || broken) 547 /* Temporarily disable forwarding of the 548 configuration cycles on all bridges in 549 this bus segment to avoid possible 550 conflicts in the second pass between two 551 bridges programmed with overlapping 552 bus ranges. */ 553 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 554 buses & ~0xffffff); 555 goto out; 556 } 557 558 /* Clear errors */ 559 pci_write_config_word(dev, PCI_STATUS, 0xffff); 560 561 /* Prevent assigning a bus number that already exists. 562 * This can happen when a bridge is hot-plugged */ 563 if (pci_find_bus(pci_domain_nr(bus), max+1)) 564 goto out; 565 child = pci_add_new_bus(bus, dev, ++max); 566 buses = (buses & 0xff000000) 567 | ((unsigned int)(child->primary) << 0) 568 | ((unsigned int)(child->secondary) << 8) 569 | ((unsigned int)(child->subordinate) << 16); 570 571 /* 572 * yenta.c forces a secondary latency timer of 176. 573 * Copy that behaviour here. 574 */ 575 if (is_cardbus) { 576 buses &= ~0xff000000; 577 buses |= CARDBUS_LATENCY_TIMER << 24; 578 } 579 580 /* 581 * We need to blast all three values with a single write. 582 */ 583 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 584 585 if (!is_cardbus) { 586 child->bridge_ctl = bctl; 587 /* 588 * Adjust subordinate busnr in parent buses. 589 * We do this before scanning for children because 590 * some devices may not be detected if the bios 591 * was lazy. 592 */ 593 pci_fixup_parent_subordinate_busnr(child, max); 594 /* Now we can scan all subordinate buses... */ 595 max = pci_scan_child_bus(child); 596 /* 597 * now fix it up again since we have found 598 * the real value of max. 599 */ 600 pci_fixup_parent_subordinate_busnr(child, max); 601 } else { 602 /* 603 * For CardBus bridges, we leave 4 bus numbers 604 * as cards with a PCI-to-PCI bridge can be 605 * inserted later. 606 */ 607 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 608 struct pci_bus *parent = bus; 609 if (pci_find_bus(pci_domain_nr(bus), 610 max+i+1)) 611 break; 612 while (parent->parent) { 613 if ((!pcibios_assign_all_busses()) && 614 (parent->subordinate > max) && 615 (parent->subordinate <= max+i)) { 616 j = 1; 617 } 618 parent = parent->parent; 619 } 620 if (j) { 621 /* 622 * Often, there are two cardbus bridges 623 * -- try to leave one valid bus number 624 * for each one. 625 */ 626 i /= 2; 627 break; 628 } 629 } 630 max += i; 631 pci_fixup_parent_subordinate_busnr(child, max); 632 } 633 /* 634 * Set the subordinate bus number to its real value. 635 */ 636 child->subordinate = max; 637 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 638 } 639 640 sprintf(child->name, 641 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 642 pci_domain_nr(bus), child->number); 643 644 /* Has only triggered on CardBus, fixup is in yenta_socket */ 645 while (bus->parent) { 646 if ((child->subordinate > bus->subordinate) || 647 (child->number > bus->subordinate) || 648 (child->number < bus->number) || 649 (child->subordinate < bus->number)) { 650 dev_info(&child->dev, "[bus %02x-%02x] %s " 651 "hidden behind%s bridge %s [bus %02x-%02x]\n", 652 child->number, child->subordinate, 653 (bus->number > child->subordinate && 654 bus->subordinate < child->number) ? 655 "wholly" : "partially", 656 bus->self->transparent ? " transparent" : "", 657 dev_name(&bus->dev), 658 bus->number, bus->subordinate); 659 } 660 bus = bus->parent; 661 } 662 663 out: 664 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 665 666 return max; 667 } 668 669 /* 670 * Read interrupt line and base address registers. 671 * The architecture-dependent code can tweak these, of course. 672 */ 673 static void pci_read_irq(struct pci_dev *dev) 674 { 675 unsigned char irq; 676 677 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 678 dev->pin = irq; 679 if (irq) 680 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 681 dev->irq = irq; 682 } 683 684 static void set_pcie_port_type(struct pci_dev *pdev) 685 { 686 int pos; 687 u16 reg16; 688 689 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 690 if (!pos) 691 return; 692 pdev->is_pcie = 1; 693 pdev->pcie_cap = pos; 694 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 695 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 696 } 697 698 static void set_pcie_hotplug_bridge(struct pci_dev *pdev) 699 { 700 int pos; 701 u16 reg16; 702 u32 reg32; 703 704 pos = pci_pcie_cap(pdev); 705 if (!pos) 706 return; 707 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 708 if (!(reg16 & PCI_EXP_FLAGS_SLOT)) 709 return; 710 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); 711 if (reg32 & PCI_EXP_SLTCAP_HPC) 712 pdev->is_hotplug_bridge = 1; 713 } 714 715 static void set_pci_aer_firmware_first(struct pci_dev *pdev) 716 { 717 if (acpi_hest_firmware_first_pci(pdev)) 718 pdev->aer_firmware_first = 1; 719 } 720 721 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 722 723 /** 724 * pci_setup_device - fill in class and map information of a device 725 * @dev: the device structure to fill 726 * 727 * Initialize the device structure with information about the device's 728 * vendor,class,memory and IO-space addresses,IRQ lines etc. 729 * Called at initialisation of the PCI subsystem and by CardBus services. 730 * Returns 0 on success and negative if unknown type of device (not normal, 731 * bridge or CardBus). 732 */ 733 int pci_setup_device(struct pci_dev *dev) 734 { 735 u32 class; 736 u8 hdr_type; 737 struct pci_slot *slot; 738 int pos = 0; 739 740 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 741 return -EIO; 742 743 dev->sysdata = dev->bus->sysdata; 744 dev->dev.parent = dev->bus->bridge; 745 dev->dev.bus = &pci_bus_type; 746 dev->hdr_type = hdr_type & 0x7f; 747 dev->multifunction = !!(hdr_type & 0x80); 748 dev->error_state = pci_channel_io_normal; 749 set_pcie_port_type(dev); 750 set_pci_aer_firmware_first(dev); 751 752 list_for_each_entry(slot, &dev->bus->slots, list) 753 if (PCI_SLOT(dev->devfn) == slot->number) 754 dev->slot = slot; 755 756 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 757 set this higher, assuming the system even supports it. */ 758 dev->dma_mask = 0xffffffff; 759 760 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 761 dev->bus->number, PCI_SLOT(dev->devfn), 762 PCI_FUNC(dev->devfn)); 763 764 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 765 dev->revision = class & 0xff; 766 class >>= 8; /* upper 3 bytes */ 767 dev->class = class; 768 class >>= 8; 769 770 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", 771 dev->vendor, dev->device, class, dev->hdr_type); 772 773 /* need to have dev->class ready */ 774 dev->cfg_size = pci_cfg_space_size(dev); 775 776 /* "Unknown power state" */ 777 dev->current_state = PCI_UNKNOWN; 778 779 /* Early fixups, before probing the BARs */ 780 pci_fixup_device(pci_fixup_early, dev); 781 /* device class may be changed after fixup */ 782 class = dev->class >> 8; 783 784 switch (dev->hdr_type) { /* header type */ 785 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 786 if (class == PCI_CLASS_BRIDGE_PCI) 787 goto bad; 788 pci_read_irq(dev); 789 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 790 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 791 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 792 793 /* 794 * Do the ugly legacy mode stuff here rather than broken chip 795 * quirk code. Legacy mode ATA controllers have fixed 796 * addresses. These are not always echoed in BAR0-3, and 797 * BAR0-3 in a few cases contain junk! 798 */ 799 if (class == PCI_CLASS_STORAGE_IDE) { 800 u8 progif; 801 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 802 if ((progif & 1) == 0) { 803 dev->resource[0].start = 0x1F0; 804 dev->resource[0].end = 0x1F7; 805 dev->resource[0].flags = LEGACY_IO_RESOURCE; 806 dev->resource[1].start = 0x3F6; 807 dev->resource[1].end = 0x3F6; 808 dev->resource[1].flags = LEGACY_IO_RESOURCE; 809 } 810 if ((progif & 4) == 0) { 811 dev->resource[2].start = 0x170; 812 dev->resource[2].end = 0x177; 813 dev->resource[2].flags = LEGACY_IO_RESOURCE; 814 dev->resource[3].start = 0x376; 815 dev->resource[3].end = 0x376; 816 dev->resource[3].flags = LEGACY_IO_RESOURCE; 817 } 818 } 819 break; 820 821 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 822 if (class != PCI_CLASS_BRIDGE_PCI) 823 goto bad; 824 /* The PCI-to-PCI bridge spec requires that subtractive 825 decoding (i.e. transparent) bridge must have programming 826 interface code of 0x01. */ 827 pci_read_irq(dev); 828 dev->transparent = ((dev->class & 0xff) == 1); 829 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 830 set_pcie_hotplug_bridge(dev); 831 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 832 if (pos) { 833 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 834 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 835 } 836 break; 837 838 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 839 if (class != PCI_CLASS_BRIDGE_CARDBUS) 840 goto bad; 841 pci_read_irq(dev); 842 pci_read_bases(dev, 1, 0); 843 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 844 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 845 break; 846 847 default: /* unknown header */ 848 dev_err(&dev->dev, "unknown header type %02x, " 849 "ignoring device\n", dev->hdr_type); 850 return -EIO; 851 852 bad: 853 dev_err(&dev->dev, "ignoring class %02x (doesn't match header " 854 "type %02x)\n", class, dev->hdr_type); 855 dev->class = PCI_CLASS_NOT_DEFINED; 856 } 857 858 /* We found a fine healthy device, go go go... */ 859 return 0; 860 } 861 862 static void pci_release_capabilities(struct pci_dev *dev) 863 { 864 pci_vpd_release(dev); 865 pci_iov_release(dev); 866 } 867 868 /** 869 * pci_release_dev - free a pci device structure when all users of it are finished. 870 * @dev: device that's been disconnected 871 * 872 * Will be called only by the device core when all users of this pci device are 873 * done. 874 */ 875 static void pci_release_dev(struct device *dev) 876 { 877 struct pci_dev *pci_dev; 878 879 pci_dev = to_pci_dev(dev); 880 pci_release_capabilities(pci_dev); 881 kfree(pci_dev); 882 } 883 884 /** 885 * pci_cfg_space_size - get the configuration space size of the PCI device. 886 * @dev: PCI device 887 * 888 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 889 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 890 * access it. Maybe we don't have a way to generate extended config space 891 * accesses, or the device is behind a reverse Express bridge. So we try 892 * reading the dword at 0x100 which must either be 0 or a valid extended 893 * capability header. 894 */ 895 int pci_cfg_space_size_ext(struct pci_dev *dev) 896 { 897 u32 status; 898 int pos = PCI_CFG_SPACE_SIZE; 899 900 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 901 goto fail; 902 if (status == 0xffffffff) 903 goto fail; 904 905 return PCI_CFG_SPACE_EXP_SIZE; 906 907 fail: 908 return PCI_CFG_SPACE_SIZE; 909 } 910 911 int pci_cfg_space_size(struct pci_dev *dev) 912 { 913 int pos; 914 u32 status; 915 u16 class; 916 917 class = dev->class >> 8; 918 if (class == PCI_CLASS_BRIDGE_HOST) 919 return pci_cfg_space_size_ext(dev); 920 921 pos = pci_pcie_cap(dev); 922 if (!pos) { 923 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 924 if (!pos) 925 goto fail; 926 927 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 928 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 929 goto fail; 930 } 931 932 return pci_cfg_space_size_ext(dev); 933 934 fail: 935 return PCI_CFG_SPACE_SIZE; 936 } 937 938 static void pci_release_bus_bridge_dev(struct device *dev) 939 { 940 kfree(dev); 941 } 942 943 struct pci_dev *alloc_pci_dev(void) 944 { 945 struct pci_dev *dev; 946 947 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 948 if (!dev) 949 return NULL; 950 951 INIT_LIST_HEAD(&dev->bus_list); 952 953 return dev; 954 } 955 EXPORT_SYMBOL(alloc_pci_dev); 956 957 /* 958 * Read the config data for a PCI device, sanity-check it 959 * and fill in the dev structure... 960 */ 961 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 962 { 963 struct pci_dev *dev; 964 u32 l; 965 int delay = 1; 966 967 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 968 return NULL; 969 970 /* some broken boards return 0 or ~0 if a slot is empty: */ 971 if (l == 0xffffffff || l == 0x00000000 || 972 l == 0x0000ffff || l == 0xffff0000) 973 return NULL; 974 975 /* Configuration request Retry Status */ 976 while (l == 0xffff0001) { 977 msleep(delay); 978 delay *= 2; 979 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 980 return NULL; 981 /* Card hasn't responded in 60 seconds? Must be stuck. */ 982 if (delay > 60 * 1000) { 983 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " 984 "responding\n", pci_domain_nr(bus), 985 bus->number, PCI_SLOT(devfn), 986 PCI_FUNC(devfn)); 987 return NULL; 988 } 989 } 990 991 dev = alloc_pci_dev(); 992 if (!dev) 993 return NULL; 994 995 dev->bus = bus; 996 dev->devfn = devfn; 997 dev->vendor = l & 0xffff; 998 dev->device = (l >> 16) & 0xffff; 999 1000 if (pci_setup_device(dev)) { 1001 kfree(dev); 1002 return NULL; 1003 } 1004 1005 return dev; 1006 } 1007 1008 static void pci_init_capabilities(struct pci_dev *dev) 1009 { 1010 /* MSI/MSI-X list */ 1011 pci_msi_init_pci_dev(dev); 1012 1013 /* Buffers for saving PCIe and PCI-X capabilities */ 1014 pci_allocate_cap_save_buffers(dev); 1015 1016 /* Power Management */ 1017 pci_pm_init(dev); 1018 platform_pci_wakeup_init(dev); 1019 1020 /* Vital Product Data */ 1021 pci_vpd_pci22_init(dev); 1022 1023 /* Alternative Routing-ID Forwarding */ 1024 pci_enable_ari(dev); 1025 1026 /* Single Root I/O Virtualization */ 1027 pci_iov_init(dev); 1028 1029 /* Enable ACS P2P upstream forwarding */ 1030 pci_enable_acs(dev); 1031 } 1032 1033 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 1034 { 1035 device_initialize(&dev->dev); 1036 dev->dev.release = pci_release_dev; 1037 pci_dev_get(dev); 1038 1039 dev->dev.dma_mask = &dev->dma_mask; 1040 dev->dev.dma_parms = &dev->dma_parms; 1041 dev->dev.coherent_dma_mask = 0xffffffffull; 1042 1043 pci_set_dma_max_seg_size(dev, 65536); 1044 pci_set_dma_seg_boundary(dev, 0xffffffff); 1045 1046 /* Fix up broken headers */ 1047 pci_fixup_device(pci_fixup_header, dev); 1048 1049 /* Clear the state_saved flag. */ 1050 dev->state_saved = false; 1051 1052 /* Initialize various capabilities */ 1053 pci_init_capabilities(dev); 1054 1055 /* 1056 * Add the device to our list of discovered devices 1057 * and the bus list for fixup functions, etc. 1058 */ 1059 down_write(&pci_bus_sem); 1060 list_add_tail(&dev->bus_list, &bus->devices); 1061 up_write(&pci_bus_sem); 1062 } 1063 1064 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1065 { 1066 struct pci_dev *dev; 1067 1068 dev = pci_get_slot(bus, devfn); 1069 if (dev) { 1070 pci_dev_put(dev); 1071 return dev; 1072 } 1073 1074 dev = pci_scan_device(bus, devfn); 1075 if (!dev) 1076 return NULL; 1077 1078 pci_device_add(dev, bus); 1079 1080 return dev; 1081 } 1082 EXPORT_SYMBOL(pci_scan_single_device); 1083 1084 /** 1085 * pci_scan_slot - scan a PCI slot on a bus for devices. 1086 * @bus: PCI bus to scan 1087 * @devfn: slot number to scan (must have zero function.) 1088 * 1089 * Scan a PCI slot on the specified PCI bus for devices, adding 1090 * discovered devices to the @bus->devices list. New devices 1091 * will not have is_added set. 1092 * 1093 * Returns the number of new devices found. 1094 */ 1095 int pci_scan_slot(struct pci_bus *bus, int devfn) 1096 { 1097 int fn, nr = 0; 1098 struct pci_dev *dev; 1099 1100 dev = pci_scan_single_device(bus, devfn); 1101 if (dev && !dev->is_added) /* new device? */ 1102 nr++; 1103 1104 if (dev && dev->multifunction) { 1105 for (fn = 1; fn < 8; fn++) { 1106 dev = pci_scan_single_device(bus, devfn + fn); 1107 if (dev) { 1108 if (!dev->is_added) 1109 nr++; 1110 dev->multifunction = 1; 1111 } 1112 } 1113 } 1114 1115 /* only one slot has pcie device */ 1116 if (bus->self && nr) 1117 pcie_aspm_init_link_state(bus->self); 1118 1119 return nr; 1120 } 1121 1122 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1123 { 1124 unsigned int devfn, pass, max = bus->secondary; 1125 struct pci_dev *dev; 1126 1127 dev_dbg(&bus->dev, "scanning bus\n"); 1128 1129 /* Go find them, Rover! */ 1130 for (devfn = 0; devfn < 0x100; devfn += 8) 1131 pci_scan_slot(bus, devfn); 1132 1133 /* Reserve buses for SR-IOV capability. */ 1134 max += pci_iov_bus_range(bus); 1135 1136 /* 1137 * After performing arch-dependent fixup of the bus, look behind 1138 * all PCI-to-PCI bridges on this bus. 1139 */ 1140 if (!bus->is_added) { 1141 dev_dbg(&bus->dev, "fixups for bus\n"); 1142 pcibios_fixup_bus(bus); 1143 if (pci_is_root_bus(bus)) 1144 bus->is_added = 1; 1145 } 1146 1147 for (pass=0; pass < 2; pass++) 1148 list_for_each_entry(dev, &bus->devices, bus_list) { 1149 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1150 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1151 max = pci_scan_bridge(bus, dev, max, pass); 1152 } 1153 1154 /* 1155 * We've scanned the bus and so we know all about what's on 1156 * the other side of any bridges that may be on this bus plus 1157 * any devices. 1158 * 1159 * Return how far we've got finding sub-buses. 1160 */ 1161 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 1162 return max; 1163 } 1164 1165 struct pci_bus * pci_create_bus(struct device *parent, 1166 int bus, struct pci_ops *ops, void *sysdata) 1167 { 1168 int error; 1169 struct pci_bus *b, *b2; 1170 struct device *dev; 1171 1172 b = pci_alloc_bus(); 1173 if (!b) 1174 return NULL; 1175 1176 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1177 if (!dev){ 1178 kfree(b); 1179 return NULL; 1180 } 1181 1182 b->sysdata = sysdata; 1183 b->ops = ops; 1184 1185 b2 = pci_find_bus(pci_domain_nr(b), bus); 1186 if (b2) { 1187 /* If we already got to this bus through a different bridge, ignore it */ 1188 dev_dbg(&b2->dev, "bus already known\n"); 1189 goto err_out; 1190 } 1191 1192 down_write(&pci_bus_sem); 1193 list_add_tail(&b->node, &pci_root_buses); 1194 up_write(&pci_bus_sem); 1195 1196 dev->parent = parent; 1197 dev->release = pci_release_bus_bridge_dev; 1198 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); 1199 error = device_register(dev); 1200 if (error) 1201 goto dev_reg_err; 1202 b->bridge = get_device(dev); 1203 1204 if (!parent) 1205 set_dev_node(b->bridge, pcibus_to_node(b)); 1206 1207 b->dev.class = &pcibus_class; 1208 b->dev.parent = b->bridge; 1209 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); 1210 error = device_register(&b->dev); 1211 if (error) 1212 goto class_dev_reg_err; 1213 error = device_create_file(&b->dev, &dev_attr_cpuaffinity); 1214 if (error) 1215 goto dev_create_file_err; 1216 1217 /* Create legacy_io and legacy_mem files for this bus */ 1218 pci_create_legacy_files(b); 1219 1220 b->number = b->secondary = bus; 1221 b->resource[0] = &ioport_resource; 1222 b->resource[1] = &iomem_resource; 1223 1224 return b; 1225 1226 dev_create_file_err: 1227 device_unregister(&b->dev); 1228 class_dev_reg_err: 1229 device_unregister(dev); 1230 dev_reg_err: 1231 down_write(&pci_bus_sem); 1232 list_del(&b->node); 1233 up_write(&pci_bus_sem); 1234 err_out: 1235 kfree(dev); 1236 kfree(b); 1237 return NULL; 1238 } 1239 1240 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, 1241 int bus, struct pci_ops *ops, void *sysdata) 1242 { 1243 struct pci_bus *b; 1244 1245 b = pci_create_bus(parent, bus, ops, sysdata); 1246 if (b) 1247 b->subordinate = pci_scan_child_bus(b); 1248 return b; 1249 } 1250 EXPORT_SYMBOL(pci_scan_bus_parented); 1251 1252 #ifdef CONFIG_HOTPLUG 1253 /** 1254 * pci_rescan_bus - scan a PCI bus for devices. 1255 * @bus: PCI bus to scan 1256 * 1257 * Scan a PCI bus and child buses for new devices, adds them, 1258 * and enables them. 1259 * 1260 * Returns the max number of subordinate bus discovered. 1261 */ 1262 unsigned int __ref pci_rescan_bus(struct pci_bus *bus) 1263 { 1264 unsigned int max; 1265 struct pci_dev *dev; 1266 1267 max = pci_scan_child_bus(bus); 1268 1269 down_read(&pci_bus_sem); 1270 list_for_each_entry(dev, &bus->devices, bus_list) 1271 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1272 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1273 if (dev->subordinate) 1274 pci_bus_size_bridges(dev->subordinate); 1275 up_read(&pci_bus_sem); 1276 1277 pci_bus_assign_resources(bus); 1278 pci_enable_bridges(bus); 1279 pci_bus_add_devices(bus); 1280 1281 return max; 1282 } 1283 EXPORT_SYMBOL_GPL(pci_rescan_bus); 1284 1285 EXPORT_SYMBOL(pci_add_new_bus); 1286 EXPORT_SYMBOL(pci_scan_slot); 1287 EXPORT_SYMBOL(pci_scan_bridge); 1288 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1289 #endif 1290 1291 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) 1292 { 1293 const struct pci_dev *a = to_pci_dev(d_a); 1294 const struct pci_dev *b = to_pci_dev(d_b); 1295 1296 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1297 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1298 1299 if (a->bus->number < b->bus->number) return -1; 1300 else if (a->bus->number > b->bus->number) return 1; 1301 1302 if (a->devfn < b->devfn) return -1; 1303 else if (a->devfn > b->devfn) return 1; 1304 1305 return 0; 1306 } 1307 1308 void __init pci_sort_breadthfirst(void) 1309 { 1310 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 1311 } 1312