1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/of_device.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include "pci.h" 22 23 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 24 #define CARDBUS_RESERVE_BUSNR 3 25 26 static struct resource busn_resource = { 27 .name = "PCI busn", 28 .start = 0, 29 .end = 255, 30 .flags = IORESOURCE_BUS, 31 }; 32 33 /* Ugh. Need to stop exporting this to modules. */ 34 LIST_HEAD(pci_root_buses); 35 EXPORT_SYMBOL(pci_root_buses); 36 37 static LIST_HEAD(pci_domain_busn_res_list); 38 39 struct pci_domain_busn_res { 40 struct list_head list; 41 struct resource res; 42 int domain_nr; 43 }; 44 45 static struct resource *get_pci_domain_busn_res(int domain_nr) 46 { 47 struct pci_domain_busn_res *r; 48 49 list_for_each_entry(r, &pci_domain_busn_res_list, list) 50 if (r->domain_nr == domain_nr) 51 return &r->res; 52 53 r = kzalloc(sizeof(*r), GFP_KERNEL); 54 if (!r) 55 return NULL; 56 57 r->domain_nr = domain_nr; 58 r->res.start = 0; 59 r->res.end = 0xff; 60 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 61 62 list_add_tail(&r->list, &pci_domain_busn_res_list); 63 64 return &r->res; 65 } 66 67 /* 68 * Some device drivers need know if PCI is initiated. 69 * Basically, we think PCI is not initiated when there 70 * is no device to be found on the pci_bus_type. 71 */ 72 int no_pci_devices(void) 73 { 74 struct device *dev; 75 int no_devices; 76 77 dev = bus_find_next_device(&pci_bus_type, NULL); 78 no_devices = (dev == NULL); 79 put_device(dev); 80 return no_devices; 81 } 82 EXPORT_SYMBOL(no_pci_devices); 83 84 /* 85 * PCI Bus Class 86 */ 87 static void release_pcibus_dev(struct device *dev) 88 { 89 struct pci_bus *pci_bus = to_pci_bus(dev); 90 91 put_device(pci_bus->bridge); 92 pci_bus_remove_resources(pci_bus); 93 pci_release_bus_of_node(pci_bus); 94 kfree(pci_bus); 95 } 96 97 static struct class pcibus_class = { 98 .name = "pci_bus", 99 .dev_release = &release_pcibus_dev, 100 .dev_groups = pcibus_groups, 101 }; 102 103 static int __init pcibus_class_init(void) 104 { 105 return class_register(&pcibus_class); 106 } 107 postcore_initcall(pcibus_class_init); 108 109 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 110 { 111 u64 size = mask & maxbase; /* Find the significant bits */ 112 if (!size) 113 return 0; 114 115 /* 116 * Get the lowest of them to find the decode size, and from that 117 * the extent. 118 */ 119 size = size & ~(size-1); 120 121 /* 122 * base == maxbase can be valid only if the BAR has already been 123 * programmed with all 1s. 124 */ 125 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 126 return 0; 127 128 return size; 129 } 130 131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 132 { 133 u32 mem_type; 134 unsigned long flags; 135 136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 138 flags |= IORESOURCE_IO; 139 return flags; 140 } 141 142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 143 flags |= IORESOURCE_MEM; 144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 145 flags |= IORESOURCE_PREFETCH; 146 147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 148 switch (mem_type) { 149 case PCI_BASE_ADDRESS_MEM_TYPE_32: 150 break; 151 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 152 /* 1M mem BAR treated as 32-bit BAR */ 153 break; 154 case PCI_BASE_ADDRESS_MEM_TYPE_64: 155 flags |= IORESOURCE_MEM_64; 156 break; 157 default: 158 /* mem unknown type treated as 32-bit BAR */ 159 break; 160 } 161 return flags; 162 } 163 164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 165 166 /** 167 * pci_read_base - Read a PCI BAR 168 * @dev: the PCI device 169 * @type: type of the BAR 170 * @res: resource buffer to be filled in 171 * @pos: BAR position in the config space 172 * 173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 174 */ 175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 176 struct resource *res, unsigned int pos) 177 { 178 u32 l = 0, sz = 0, mask; 179 u64 l64, sz64, mask64; 180 u16 orig_cmd; 181 struct pci_bus_region region, inverted_region; 182 183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 184 185 /* No printks while decoding is disabled! */ 186 if (!dev->mmio_always_on) { 187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 189 pci_write_config_word(dev, PCI_COMMAND, 190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 191 } 192 } 193 194 res->name = pci_name(dev); 195 196 pci_read_config_dword(dev, pos, &l); 197 pci_write_config_dword(dev, pos, l | mask); 198 pci_read_config_dword(dev, pos, &sz); 199 pci_write_config_dword(dev, pos, l); 200 201 /* 202 * All bits set in sz means the device isn't working properly. 203 * If the BAR isn't implemented, all bits must be 0. If it's a 204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 205 * 1 must be clear. 206 */ 207 if (sz == 0xffffffff) 208 sz = 0; 209 210 /* 211 * I don't know how l can have all bits set. Copied from old code. 212 * Maybe it fixes a bug on some ancient platform. 213 */ 214 if (l == 0xffffffff) 215 l = 0; 216 217 if (type == pci_bar_unknown) { 218 res->flags = decode_bar(dev, l); 219 res->flags |= IORESOURCE_SIZEALIGN; 220 if (res->flags & IORESOURCE_IO) { 221 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 224 } else { 225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 228 } 229 } else { 230 if (l & PCI_ROM_ADDRESS_ENABLE) 231 res->flags |= IORESOURCE_ROM_ENABLE; 232 l64 = l & PCI_ROM_ADDRESS_MASK; 233 sz64 = sz & PCI_ROM_ADDRESS_MASK; 234 mask64 = PCI_ROM_ADDRESS_MASK; 235 } 236 237 if (res->flags & IORESOURCE_MEM_64) { 238 pci_read_config_dword(dev, pos + 4, &l); 239 pci_write_config_dword(dev, pos + 4, ~0); 240 pci_read_config_dword(dev, pos + 4, &sz); 241 pci_write_config_dword(dev, pos + 4, l); 242 243 l64 |= ((u64)l << 32); 244 sz64 |= ((u64)sz << 32); 245 mask64 |= ((u64)~0 << 32); 246 } 247 248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 250 251 if (!sz64) 252 goto fail; 253 254 sz64 = pci_size(l64, sz64, mask64); 255 if (!sz64) { 256 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 257 pos); 258 goto fail; 259 } 260 261 if (res->flags & IORESOURCE_MEM_64) { 262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 263 && sz64 > 0x100000000ULL) { 264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 265 res->start = 0; 266 res->end = 0; 267 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 268 pos, (unsigned long long)sz64); 269 goto out; 270 } 271 272 if ((sizeof(pci_bus_addr_t) < 8) && l) { 273 /* Above 32-bit boundary; try to reallocate */ 274 res->flags |= IORESOURCE_UNSET; 275 res->start = 0; 276 res->end = sz64 - 1; 277 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 278 pos, (unsigned long long)l64); 279 goto out; 280 } 281 } 282 283 region.start = l64; 284 region.end = l64 + sz64 - 1; 285 286 pcibios_bus_to_resource(dev->bus, res, ®ion); 287 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 288 289 /* 290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 291 * the corresponding resource address (the physical address used by 292 * the CPU. Converting that resource address back to a bus address 293 * should yield the original BAR value: 294 * 295 * resource_to_bus(bus_to_resource(A)) == A 296 * 297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 298 * be claimed by the device. 299 */ 300 if (inverted_region.start != region.start) { 301 res->flags |= IORESOURCE_UNSET; 302 res->start = 0; 303 res->end = region.end - region.start; 304 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 305 pos, (unsigned long long)region.start); 306 } 307 308 goto out; 309 310 311 fail: 312 res->flags = 0; 313 out: 314 if (res->flags) 315 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 316 317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 318 } 319 320 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 321 { 322 unsigned int pos, reg; 323 324 if (dev->non_compliant_bars) 325 return; 326 327 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 328 if (dev->is_virtfn) 329 return; 330 331 for (pos = 0; pos < howmany; pos++) { 332 struct resource *res = &dev->resource[pos]; 333 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 334 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 335 } 336 337 if (rom) { 338 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 339 dev->rom_base_reg = rom; 340 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 341 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 342 __pci_read_base(dev, pci_bar_mem32, res, rom); 343 } 344 } 345 346 static void pci_read_bridge_windows(struct pci_dev *bridge) 347 { 348 u16 io; 349 u32 pmem, tmp; 350 351 pci_read_config_word(bridge, PCI_IO_BASE, &io); 352 if (!io) { 353 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 354 pci_read_config_word(bridge, PCI_IO_BASE, &io); 355 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 356 } 357 if (io) 358 bridge->io_window = 1; 359 360 /* 361 * DECchip 21050 pass 2 errata: the bridge may miss an address 362 * disconnect boundary by one PCI data phase. Workaround: do not 363 * use prefetching on this device. 364 */ 365 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 366 return; 367 368 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 369 if (!pmem) { 370 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 371 0xffe0fff0); 372 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 373 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 374 } 375 if (!pmem) 376 return; 377 378 bridge->pref_window = 1; 379 380 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 381 382 /* 383 * Bridge claims to have a 64-bit prefetchable memory 384 * window; verify that the upper bits are actually 385 * writable. 386 */ 387 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 388 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 389 0xffffffff); 390 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 391 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 392 if (tmp) 393 bridge->pref_64_window = 1; 394 } 395 } 396 397 static void pci_read_bridge_io(struct pci_bus *child) 398 { 399 struct pci_dev *dev = child->self; 400 u8 io_base_lo, io_limit_lo; 401 unsigned long io_mask, io_granularity, base, limit; 402 struct pci_bus_region region; 403 struct resource *res; 404 405 io_mask = PCI_IO_RANGE_MASK; 406 io_granularity = 0x1000; 407 if (dev->io_window_1k) { 408 /* Support 1K I/O space granularity */ 409 io_mask = PCI_IO_1K_RANGE_MASK; 410 io_granularity = 0x400; 411 } 412 413 res = child->resource[0]; 414 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 415 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 416 base = (io_base_lo & io_mask) << 8; 417 limit = (io_limit_lo & io_mask) << 8; 418 419 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 420 u16 io_base_hi, io_limit_hi; 421 422 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 423 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 424 base |= ((unsigned long) io_base_hi << 16); 425 limit |= ((unsigned long) io_limit_hi << 16); 426 } 427 428 if (base <= limit) { 429 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 430 region.start = base; 431 region.end = limit + io_granularity - 1; 432 pcibios_bus_to_resource(dev->bus, res, ®ion); 433 pci_info(dev, " bridge window %pR\n", res); 434 } 435 } 436 437 static void pci_read_bridge_mmio(struct pci_bus *child) 438 { 439 struct pci_dev *dev = child->self; 440 u16 mem_base_lo, mem_limit_lo; 441 unsigned long base, limit; 442 struct pci_bus_region region; 443 struct resource *res; 444 445 res = child->resource[1]; 446 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 447 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 448 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 449 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 450 if (base <= limit) { 451 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 452 region.start = base; 453 region.end = limit + 0xfffff; 454 pcibios_bus_to_resource(dev->bus, res, ®ion); 455 pci_info(dev, " bridge window %pR\n", res); 456 } 457 } 458 459 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 460 { 461 struct pci_dev *dev = child->self; 462 u16 mem_base_lo, mem_limit_lo; 463 u64 base64, limit64; 464 pci_bus_addr_t base, limit; 465 struct pci_bus_region region; 466 struct resource *res; 467 468 res = child->resource[2]; 469 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 470 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 471 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 472 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 473 474 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 475 u32 mem_base_hi, mem_limit_hi; 476 477 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 478 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 479 480 /* 481 * Some bridges set the base > limit by default, and some 482 * (broken) BIOSes do not initialize them. If we find 483 * this, just assume they are not being used. 484 */ 485 if (mem_base_hi <= mem_limit_hi) { 486 base64 |= (u64) mem_base_hi << 32; 487 limit64 |= (u64) mem_limit_hi << 32; 488 } 489 } 490 491 base = (pci_bus_addr_t) base64; 492 limit = (pci_bus_addr_t) limit64; 493 494 if (base != base64) { 495 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 496 (unsigned long long) base64); 497 return; 498 } 499 500 if (base <= limit) { 501 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 502 IORESOURCE_MEM | IORESOURCE_PREFETCH; 503 if (res->flags & PCI_PREF_RANGE_TYPE_64) 504 res->flags |= IORESOURCE_MEM_64; 505 region.start = base; 506 region.end = limit + 0xfffff; 507 pcibios_bus_to_resource(dev->bus, res, ®ion); 508 pci_info(dev, " bridge window %pR\n", res); 509 } 510 } 511 512 void pci_read_bridge_bases(struct pci_bus *child) 513 { 514 struct pci_dev *dev = child->self; 515 struct resource *res; 516 int i; 517 518 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 519 return; 520 521 pci_info(dev, "PCI bridge to %pR%s\n", 522 &child->busn_res, 523 dev->transparent ? " (subtractive decode)" : ""); 524 525 pci_bus_remove_resources(child); 526 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 527 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 528 529 pci_read_bridge_io(child); 530 pci_read_bridge_mmio(child); 531 pci_read_bridge_mmio_pref(child); 532 533 if (dev->transparent) { 534 pci_bus_for_each_resource(child->parent, res, i) { 535 if (res && res->flags) { 536 pci_bus_add_resource(child, res, 537 PCI_SUBTRACTIVE_DECODE); 538 pci_info(dev, " bridge window %pR (subtractive decode)\n", 539 res); 540 } 541 } 542 } 543 } 544 545 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 546 { 547 struct pci_bus *b; 548 549 b = kzalloc(sizeof(*b), GFP_KERNEL); 550 if (!b) 551 return NULL; 552 553 INIT_LIST_HEAD(&b->node); 554 INIT_LIST_HEAD(&b->children); 555 INIT_LIST_HEAD(&b->devices); 556 INIT_LIST_HEAD(&b->slots); 557 INIT_LIST_HEAD(&b->resources); 558 b->max_bus_speed = PCI_SPEED_UNKNOWN; 559 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 560 #ifdef CONFIG_PCI_DOMAINS_GENERIC 561 if (parent) 562 b->domain_nr = parent->domain_nr; 563 #endif 564 return b; 565 } 566 567 static void devm_pci_release_host_bridge_dev(struct device *dev) 568 { 569 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 570 571 if (bridge->release_fn) 572 bridge->release_fn(bridge); 573 574 pci_free_resource_list(&bridge->windows); 575 } 576 577 static void pci_release_host_bridge_dev(struct device *dev) 578 { 579 devm_pci_release_host_bridge_dev(dev); 580 kfree(to_pci_host_bridge(dev)); 581 } 582 583 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 584 { 585 INIT_LIST_HEAD(&bridge->windows); 586 INIT_LIST_HEAD(&bridge->dma_ranges); 587 588 /* 589 * We assume we can manage these PCIe features. Some systems may 590 * reserve these for use by the platform itself, e.g., an ACPI BIOS 591 * may implement its own AER handling and use _OSC to prevent the 592 * OS from interfering. 593 */ 594 bridge->native_aer = 1; 595 bridge->native_pcie_hotplug = 1; 596 bridge->native_shpc_hotplug = 1; 597 bridge->native_pme = 1; 598 bridge->native_ltr = 1; 599 } 600 601 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 602 { 603 struct pci_host_bridge *bridge; 604 605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 606 if (!bridge) 607 return NULL; 608 609 pci_init_host_bridge(bridge); 610 bridge->dev.release = pci_release_host_bridge_dev; 611 612 return bridge; 613 } 614 EXPORT_SYMBOL(pci_alloc_host_bridge); 615 616 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 617 size_t priv) 618 { 619 struct pci_host_bridge *bridge; 620 621 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL); 622 if (!bridge) 623 return NULL; 624 625 pci_init_host_bridge(bridge); 626 bridge->dev.release = devm_pci_release_host_bridge_dev; 627 628 return bridge; 629 } 630 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 631 632 void pci_free_host_bridge(struct pci_host_bridge *bridge) 633 { 634 pci_free_resource_list(&bridge->windows); 635 pci_free_resource_list(&bridge->dma_ranges); 636 637 kfree(bridge); 638 } 639 EXPORT_SYMBOL(pci_free_host_bridge); 640 641 static const unsigned char pcix_bus_speed[] = { 642 PCI_SPEED_UNKNOWN, /* 0 */ 643 PCI_SPEED_66MHz_PCIX, /* 1 */ 644 PCI_SPEED_100MHz_PCIX, /* 2 */ 645 PCI_SPEED_133MHz_PCIX, /* 3 */ 646 PCI_SPEED_UNKNOWN, /* 4 */ 647 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 648 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 649 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 650 PCI_SPEED_UNKNOWN, /* 8 */ 651 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 652 PCI_SPEED_100MHz_PCIX_266, /* A */ 653 PCI_SPEED_133MHz_PCIX_266, /* B */ 654 PCI_SPEED_UNKNOWN, /* C */ 655 PCI_SPEED_66MHz_PCIX_533, /* D */ 656 PCI_SPEED_100MHz_PCIX_533, /* E */ 657 PCI_SPEED_133MHz_PCIX_533 /* F */ 658 }; 659 660 const unsigned char pcie_link_speed[] = { 661 PCI_SPEED_UNKNOWN, /* 0 */ 662 PCIE_SPEED_2_5GT, /* 1 */ 663 PCIE_SPEED_5_0GT, /* 2 */ 664 PCIE_SPEED_8_0GT, /* 3 */ 665 PCIE_SPEED_16_0GT, /* 4 */ 666 PCIE_SPEED_32_0GT, /* 5 */ 667 PCI_SPEED_UNKNOWN, /* 6 */ 668 PCI_SPEED_UNKNOWN, /* 7 */ 669 PCI_SPEED_UNKNOWN, /* 8 */ 670 PCI_SPEED_UNKNOWN, /* 9 */ 671 PCI_SPEED_UNKNOWN, /* A */ 672 PCI_SPEED_UNKNOWN, /* B */ 673 PCI_SPEED_UNKNOWN, /* C */ 674 PCI_SPEED_UNKNOWN, /* D */ 675 PCI_SPEED_UNKNOWN, /* E */ 676 PCI_SPEED_UNKNOWN /* F */ 677 }; 678 679 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 680 { 681 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 682 } 683 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 684 685 static unsigned char agp_speeds[] = { 686 AGP_UNKNOWN, 687 AGP_1X, 688 AGP_2X, 689 AGP_4X, 690 AGP_8X 691 }; 692 693 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 694 { 695 int index = 0; 696 697 if (agpstat & 4) 698 index = 3; 699 else if (agpstat & 2) 700 index = 2; 701 else if (agpstat & 1) 702 index = 1; 703 else 704 goto out; 705 706 if (agp3) { 707 index += 2; 708 if (index == 5) 709 index = 0; 710 } 711 712 out: 713 return agp_speeds[index]; 714 } 715 716 static void pci_set_bus_speed(struct pci_bus *bus) 717 { 718 struct pci_dev *bridge = bus->self; 719 int pos; 720 721 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 722 if (!pos) 723 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 724 if (pos) { 725 u32 agpstat, agpcmd; 726 727 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 728 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 729 730 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 731 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 732 } 733 734 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 735 if (pos) { 736 u16 status; 737 enum pci_bus_speed max; 738 739 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 740 &status); 741 742 if (status & PCI_X_SSTATUS_533MHZ) { 743 max = PCI_SPEED_133MHz_PCIX_533; 744 } else if (status & PCI_X_SSTATUS_266MHZ) { 745 max = PCI_SPEED_133MHz_PCIX_266; 746 } else if (status & PCI_X_SSTATUS_133MHZ) { 747 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 748 max = PCI_SPEED_133MHz_PCIX_ECC; 749 else 750 max = PCI_SPEED_133MHz_PCIX; 751 } else { 752 max = PCI_SPEED_66MHz_PCIX; 753 } 754 755 bus->max_bus_speed = max; 756 bus->cur_bus_speed = pcix_bus_speed[ 757 (status & PCI_X_SSTATUS_FREQ) >> 6]; 758 759 return; 760 } 761 762 if (pci_is_pcie(bridge)) { 763 u32 linkcap; 764 u16 linksta; 765 766 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 767 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 768 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 769 770 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 771 pcie_update_link_speed(bus, linksta); 772 } 773 } 774 775 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 776 { 777 struct irq_domain *d; 778 779 /* 780 * Any firmware interface that can resolve the msi_domain 781 * should be called from here. 782 */ 783 d = pci_host_bridge_of_msi_domain(bus); 784 if (!d) 785 d = pci_host_bridge_acpi_msi_domain(bus); 786 787 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 788 /* 789 * If no IRQ domain was found via the OF tree, try looking it up 790 * directly through the fwnode_handle. 791 */ 792 if (!d) { 793 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 794 795 if (fwnode) 796 d = irq_find_matching_fwnode(fwnode, 797 DOMAIN_BUS_PCI_MSI); 798 } 799 #endif 800 801 return d; 802 } 803 804 static void pci_set_bus_msi_domain(struct pci_bus *bus) 805 { 806 struct irq_domain *d; 807 struct pci_bus *b; 808 809 /* 810 * The bus can be a root bus, a subordinate bus, or a virtual bus 811 * created by an SR-IOV device. Walk up to the first bridge device 812 * found or derive the domain from the host bridge. 813 */ 814 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 815 if (b->self) 816 d = dev_get_msi_domain(&b->self->dev); 817 } 818 819 if (!d) 820 d = pci_host_bridge_msi_domain(b); 821 822 dev_set_msi_domain(&bus->dev, d); 823 } 824 825 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 826 { 827 struct device *parent = bridge->dev.parent; 828 struct resource_entry *window, *n; 829 struct pci_bus *bus, *b; 830 resource_size_t offset; 831 LIST_HEAD(resources); 832 struct resource *res; 833 char addr[64], *fmt; 834 const char *name; 835 int err; 836 837 bus = pci_alloc_bus(NULL); 838 if (!bus) 839 return -ENOMEM; 840 841 bridge->bus = bus; 842 843 /* Temporarily move resources off the list */ 844 list_splice_init(&bridge->windows, &resources); 845 bus->sysdata = bridge->sysdata; 846 bus->msi = bridge->msi; 847 bus->ops = bridge->ops; 848 bus->number = bus->busn_res.start = bridge->busnr; 849 #ifdef CONFIG_PCI_DOMAINS_GENERIC 850 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 851 #endif 852 853 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 854 if (b) { 855 /* Ignore it if we already got here via a different bridge */ 856 dev_dbg(&b->dev, "bus already known\n"); 857 err = -EEXIST; 858 goto free; 859 } 860 861 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 862 bridge->busnr); 863 864 err = pcibios_root_bridge_prepare(bridge); 865 if (err) 866 goto free; 867 868 err = device_register(&bridge->dev); 869 if (err) 870 put_device(&bridge->dev); 871 872 bus->bridge = get_device(&bridge->dev); 873 device_enable_async_suspend(bus->bridge); 874 pci_set_bus_of_node(bus); 875 pci_set_bus_msi_domain(bus); 876 877 if (!parent) 878 set_dev_node(bus->bridge, pcibus_to_node(bus)); 879 880 bus->dev.class = &pcibus_class; 881 bus->dev.parent = bus->bridge; 882 883 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 884 name = dev_name(&bus->dev); 885 886 err = device_register(&bus->dev); 887 if (err) 888 goto unregister; 889 890 pcibios_add_bus(bus); 891 892 /* Create legacy_io and legacy_mem files for this bus */ 893 pci_create_legacy_files(bus); 894 895 if (parent) 896 dev_info(parent, "PCI host bridge to bus %s\n", name); 897 else 898 pr_info("PCI host bridge to bus %s\n", name); 899 900 /* Add initial resources to the bus */ 901 resource_list_for_each_entry_safe(window, n, &resources) { 902 list_move_tail(&window->node, &bridge->windows); 903 offset = window->offset; 904 res = window->res; 905 906 if (res->flags & IORESOURCE_BUS) 907 pci_bus_insert_busn_res(bus, bus->number, res->end); 908 else 909 pci_bus_add_resource(bus, res, 0); 910 911 if (offset) { 912 if (resource_type(res) == IORESOURCE_IO) 913 fmt = " (bus address [%#06llx-%#06llx])"; 914 else 915 fmt = " (bus address [%#010llx-%#010llx])"; 916 917 snprintf(addr, sizeof(addr), fmt, 918 (unsigned long long)(res->start - offset), 919 (unsigned long long)(res->end - offset)); 920 } else 921 addr[0] = '\0'; 922 923 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 924 } 925 926 down_write(&pci_bus_sem); 927 list_add_tail(&bus->node, &pci_root_buses); 928 up_write(&pci_bus_sem); 929 930 return 0; 931 932 unregister: 933 put_device(&bridge->dev); 934 device_unregister(&bridge->dev); 935 936 free: 937 kfree(bus); 938 return err; 939 } 940 941 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 942 { 943 int pos; 944 u32 status; 945 946 /* 947 * If extended config space isn't accessible on a bridge's primary 948 * bus, we certainly can't access it on the secondary bus. 949 */ 950 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 951 return false; 952 953 /* 954 * PCIe Root Ports and switch ports are PCIe on both sides, so if 955 * extended config space is accessible on the primary, it's also 956 * accessible on the secondary. 957 */ 958 if (pci_is_pcie(bridge) && 959 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 960 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 961 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 962 return true; 963 964 /* 965 * For the other bridge types: 966 * - PCI-to-PCI bridges 967 * - PCIe-to-PCI/PCI-X forward bridges 968 * - PCI/PCI-X-to-PCIe reverse bridges 969 * extended config space on the secondary side is only accessible 970 * if the bridge supports PCI-X Mode 2. 971 */ 972 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 973 if (!pos) 974 return false; 975 976 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 977 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 978 } 979 980 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 981 struct pci_dev *bridge, int busnr) 982 { 983 struct pci_bus *child; 984 int i; 985 int ret; 986 987 /* Allocate a new bus and inherit stuff from the parent */ 988 child = pci_alloc_bus(parent); 989 if (!child) 990 return NULL; 991 992 child->parent = parent; 993 child->ops = parent->ops; 994 child->msi = parent->msi; 995 child->sysdata = parent->sysdata; 996 child->bus_flags = parent->bus_flags; 997 998 /* 999 * Initialize some portions of the bus device, but don't register 1000 * it now as the parent is not properly set up yet. 1001 */ 1002 child->dev.class = &pcibus_class; 1003 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1004 1005 /* Set up the primary, secondary and subordinate bus numbers */ 1006 child->number = child->busn_res.start = busnr; 1007 child->primary = parent->busn_res.start; 1008 child->busn_res.end = 0xff; 1009 1010 if (!bridge) { 1011 child->dev.parent = parent->bridge; 1012 goto add_dev; 1013 } 1014 1015 child->self = bridge; 1016 child->bridge = get_device(&bridge->dev); 1017 child->dev.parent = child->bridge; 1018 pci_set_bus_of_node(child); 1019 pci_set_bus_speed(child); 1020 1021 /* 1022 * Check whether extended config space is accessible on the child 1023 * bus. Note that we currently assume it is always accessible on 1024 * the root bus. 1025 */ 1026 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1027 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1028 pci_info(child, "extended config space not accessible\n"); 1029 } 1030 1031 /* Set up default resource pointers and names */ 1032 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1033 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1034 child->resource[i]->name = child->name; 1035 } 1036 bridge->subordinate = child; 1037 1038 add_dev: 1039 pci_set_bus_msi_domain(child); 1040 ret = device_register(&child->dev); 1041 WARN_ON(ret < 0); 1042 1043 pcibios_add_bus(child); 1044 1045 if (child->ops->add_bus) { 1046 ret = child->ops->add_bus(child); 1047 if (WARN_ON(ret < 0)) 1048 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1049 } 1050 1051 /* Create legacy_io and legacy_mem files for this bus */ 1052 pci_create_legacy_files(child); 1053 1054 return child; 1055 } 1056 1057 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1058 int busnr) 1059 { 1060 struct pci_bus *child; 1061 1062 child = pci_alloc_child_bus(parent, dev, busnr); 1063 if (child) { 1064 down_write(&pci_bus_sem); 1065 list_add_tail(&child->node, &parent->children); 1066 up_write(&pci_bus_sem); 1067 } 1068 return child; 1069 } 1070 EXPORT_SYMBOL(pci_add_new_bus); 1071 1072 static void pci_enable_crs(struct pci_dev *pdev) 1073 { 1074 u16 root_cap = 0; 1075 1076 /* Enable CRS Software Visibility if supported */ 1077 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1078 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1079 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1080 PCI_EXP_RTCTL_CRSSVE); 1081 } 1082 1083 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1084 unsigned int available_buses); 1085 /** 1086 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1087 * numbers from EA capability. 1088 * @dev: Bridge 1089 * @sec: updated with secondary bus number from EA 1090 * @sub: updated with subordinate bus number from EA 1091 * 1092 * If @dev is a bridge with EA capability, update @sec and @sub with 1093 * fixed bus numbers from the capability and return true. Otherwise, 1094 * return false. 1095 */ 1096 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1097 { 1098 int ea, offset; 1099 u32 dw; 1100 1101 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1102 return false; 1103 1104 /* find PCI EA capability in list */ 1105 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1106 if (!ea) 1107 return false; 1108 1109 offset = ea + PCI_EA_FIRST_ENT; 1110 pci_read_config_dword(dev, offset, &dw); 1111 *sec = dw & PCI_EA_SEC_BUS_MASK; 1112 *sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1113 return true; 1114 } 1115 1116 /* 1117 * pci_scan_bridge_extend() - Scan buses behind a bridge 1118 * @bus: Parent bus the bridge is on 1119 * @dev: Bridge itself 1120 * @max: Starting subordinate number of buses behind this bridge 1121 * @available_buses: Total number of buses available for this bridge and 1122 * the devices below. After the minimal bus space has 1123 * been allocated the remaining buses will be 1124 * distributed equally between hotplug-capable bridges. 1125 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1126 * that need to be reconfigured. 1127 * 1128 * If it's a bridge, configure it and scan the bus behind it. 1129 * For CardBus bridges, we don't scan behind as the devices will 1130 * be handled by the bridge driver itself. 1131 * 1132 * We need to process bridges in two passes -- first we scan those 1133 * already configured by the BIOS and after we are done with all of 1134 * them, we proceed to assigning numbers to the remaining buses in 1135 * order to avoid overlaps between old and new bus numbers. 1136 * 1137 * Return: New subordinate number covering all buses behind this bridge. 1138 */ 1139 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1140 int max, unsigned int available_buses, 1141 int pass) 1142 { 1143 struct pci_bus *child; 1144 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1145 u32 buses, i, j = 0; 1146 u16 bctl; 1147 u8 primary, secondary, subordinate; 1148 int broken = 0; 1149 bool fixed_buses; 1150 u8 fixed_sec, fixed_sub; 1151 int next_busnr; 1152 1153 /* 1154 * Make sure the bridge is powered on to be able to access config 1155 * space of devices below it. 1156 */ 1157 pm_runtime_get_sync(&dev->dev); 1158 1159 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1160 primary = buses & 0xFF; 1161 secondary = (buses >> 8) & 0xFF; 1162 subordinate = (buses >> 16) & 0xFF; 1163 1164 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1165 secondary, subordinate, pass); 1166 1167 if (!primary && (primary != bus->number) && secondary && subordinate) { 1168 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1169 primary = bus->number; 1170 } 1171 1172 /* Check if setup is sensible at all */ 1173 if (!pass && 1174 (primary != bus->number || secondary <= bus->number || 1175 secondary > subordinate)) { 1176 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1177 secondary, subordinate); 1178 broken = 1; 1179 } 1180 1181 /* 1182 * Disable Master-Abort Mode during probing to avoid reporting of 1183 * bus errors in some architectures. 1184 */ 1185 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1186 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1187 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1188 1189 pci_enable_crs(dev); 1190 1191 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1192 !is_cardbus && !broken) { 1193 unsigned int cmax; 1194 1195 /* 1196 * Bus already configured by firmware, process it in the 1197 * first pass and just note the configuration. 1198 */ 1199 if (pass) 1200 goto out; 1201 1202 /* 1203 * The bus might already exist for two reasons: Either we 1204 * are rescanning the bus or the bus is reachable through 1205 * more than one bridge. The second case can happen with 1206 * the i450NX chipset. 1207 */ 1208 child = pci_find_bus(pci_domain_nr(bus), secondary); 1209 if (!child) { 1210 child = pci_add_new_bus(bus, dev, secondary); 1211 if (!child) 1212 goto out; 1213 child->primary = primary; 1214 pci_bus_insert_busn_res(child, secondary, subordinate); 1215 child->bridge_ctl = bctl; 1216 } 1217 1218 cmax = pci_scan_child_bus(child); 1219 if (cmax > subordinate) 1220 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1221 subordinate, cmax); 1222 1223 /* Subordinate should equal child->busn_res.end */ 1224 if (subordinate > max) 1225 max = subordinate; 1226 } else { 1227 1228 /* 1229 * We need to assign a number to this bus which we always 1230 * do in the second pass. 1231 */ 1232 if (!pass) { 1233 if (pcibios_assign_all_busses() || broken || is_cardbus) 1234 1235 /* 1236 * Temporarily disable forwarding of the 1237 * configuration cycles on all bridges in 1238 * this bus segment to avoid possible 1239 * conflicts in the second pass between two 1240 * bridges programmed with overlapping bus 1241 * ranges. 1242 */ 1243 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1244 buses & ~0xffffff); 1245 goto out; 1246 } 1247 1248 /* Clear errors */ 1249 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1250 1251 /* Read bus numbers from EA Capability (if present) */ 1252 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1253 if (fixed_buses) 1254 next_busnr = fixed_sec; 1255 else 1256 next_busnr = max + 1; 1257 1258 /* 1259 * Prevent assigning a bus number that already exists. 1260 * This can happen when a bridge is hot-plugged, so in this 1261 * case we only re-scan this bus. 1262 */ 1263 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1264 if (!child) { 1265 child = pci_add_new_bus(bus, dev, next_busnr); 1266 if (!child) 1267 goto out; 1268 pci_bus_insert_busn_res(child, next_busnr, 1269 bus->busn_res.end); 1270 } 1271 max++; 1272 if (available_buses) 1273 available_buses--; 1274 1275 buses = (buses & 0xff000000) 1276 | ((unsigned int)(child->primary) << 0) 1277 | ((unsigned int)(child->busn_res.start) << 8) 1278 | ((unsigned int)(child->busn_res.end) << 16); 1279 1280 /* 1281 * yenta.c forces a secondary latency timer of 176. 1282 * Copy that behaviour here. 1283 */ 1284 if (is_cardbus) { 1285 buses &= ~0xff000000; 1286 buses |= CARDBUS_LATENCY_TIMER << 24; 1287 } 1288 1289 /* We need to blast all three values with a single write */ 1290 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1291 1292 if (!is_cardbus) { 1293 child->bridge_ctl = bctl; 1294 max = pci_scan_child_bus_extend(child, available_buses); 1295 } else { 1296 1297 /* 1298 * For CardBus bridges, we leave 4 bus numbers as 1299 * cards with a PCI-to-PCI bridge can be inserted 1300 * later. 1301 */ 1302 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1303 struct pci_bus *parent = bus; 1304 if (pci_find_bus(pci_domain_nr(bus), 1305 max+i+1)) 1306 break; 1307 while (parent->parent) { 1308 if ((!pcibios_assign_all_busses()) && 1309 (parent->busn_res.end > max) && 1310 (parent->busn_res.end <= max+i)) { 1311 j = 1; 1312 } 1313 parent = parent->parent; 1314 } 1315 if (j) { 1316 1317 /* 1318 * Often, there are two CardBus 1319 * bridges -- try to leave one 1320 * valid bus number for each one. 1321 */ 1322 i /= 2; 1323 break; 1324 } 1325 } 1326 max += i; 1327 } 1328 1329 /* 1330 * Set subordinate bus number to its real value. 1331 * If fixed subordinate bus number exists from EA 1332 * capability then use it. 1333 */ 1334 if (fixed_buses) 1335 max = fixed_sub; 1336 pci_bus_update_busn_res_end(child, max); 1337 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1338 } 1339 1340 sprintf(child->name, 1341 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1342 pci_domain_nr(bus), child->number); 1343 1344 /* Check that all devices are accessible */ 1345 while (bus->parent) { 1346 if ((child->busn_res.end > bus->busn_res.end) || 1347 (child->number > bus->busn_res.end) || 1348 (child->number < bus->number) || 1349 (child->busn_res.end < bus->number)) { 1350 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1351 &child->busn_res); 1352 break; 1353 } 1354 bus = bus->parent; 1355 } 1356 1357 out: 1358 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1359 1360 pm_runtime_put(&dev->dev); 1361 1362 return max; 1363 } 1364 1365 /* 1366 * pci_scan_bridge() - Scan buses behind a bridge 1367 * @bus: Parent bus the bridge is on 1368 * @dev: Bridge itself 1369 * @max: Starting subordinate number of buses behind this bridge 1370 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1371 * that need to be reconfigured. 1372 * 1373 * If it's a bridge, configure it and scan the bus behind it. 1374 * For CardBus bridges, we don't scan behind as the devices will 1375 * be handled by the bridge driver itself. 1376 * 1377 * We need to process bridges in two passes -- first we scan those 1378 * already configured by the BIOS and after we are done with all of 1379 * them, we proceed to assigning numbers to the remaining buses in 1380 * order to avoid overlaps between old and new bus numbers. 1381 * 1382 * Return: New subordinate number covering all buses behind this bridge. 1383 */ 1384 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1385 { 1386 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1387 } 1388 EXPORT_SYMBOL(pci_scan_bridge); 1389 1390 /* 1391 * Read interrupt line and base address registers. 1392 * The architecture-dependent code can tweak these, of course. 1393 */ 1394 static void pci_read_irq(struct pci_dev *dev) 1395 { 1396 unsigned char irq; 1397 1398 /* VFs are not allowed to use INTx, so skip the config reads */ 1399 if (dev->is_virtfn) { 1400 dev->pin = 0; 1401 dev->irq = 0; 1402 return; 1403 } 1404 1405 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1406 dev->pin = irq; 1407 if (irq) 1408 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1409 dev->irq = irq; 1410 } 1411 1412 void set_pcie_port_type(struct pci_dev *pdev) 1413 { 1414 int pos; 1415 u16 reg16; 1416 int type; 1417 struct pci_dev *parent; 1418 1419 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1420 if (!pos) 1421 return; 1422 1423 pdev->pcie_cap = pos; 1424 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1425 pdev->pcie_flags_reg = reg16; 1426 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 1427 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1428 1429 /* 1430 * A Root Port or a PCI-to-PCIe bridge is always the upstream end 1431 * of a Link. No PCIe component has two Links. Two Links are 1432 * connected by a Switch that has a Port on each Link and internal 1433 * logic to connect the two Ports. 1434 */ 1435 type = pci_pcie_type(pdev); 1436 if (type == PCI_EXP_TYPE_ROOT_PORT || 1437 type == PCI_EXP_TYPE_PCIE_BRIDGE) 1438 pdev->has_secondary_link = 1; 1439 else if (type == PCI_EXP_TYPE_UPSTREAM || 1440 type == PCI_EXP_TYPE_DOWNSTREAM) { 1441 parent = pci_upstream_bridge(pdev); 1442 1443 /* 1444 * Usually there's an upstream device (Root Port or Switch 1445 * Downstream Port), but we can't assume one exists. 1446 */ 1447 if (parent && !parent->has_secondary_link) 1448 pdev->has_secondary_link = 1; 1449 } 1450 } 1451 1452 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1453 { 1454 u32 reg32; 1455 1456 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1457 if (reg32 & PCI_EXP_SLTCAP_HPC) 1458 pdev->is_hotplug_bridge = 1; 1459 } 1460 1461 static void set_pcie_thunderbolt(struct pci_dev *dev) 1462 { 1463 int vsec = 0; 1464 u32 header; 1465 1466 while ((vsec = pci_find_next_ext_capability(dev, vsec, 1467 PCI_EXT_CAP_ID_VNDR))) { 1468 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); 1469 1470 /* Is the device part of a Thunderbolt controller? */ 1471 if (dev->vendor == PCI_VENDOR_ID_INTEL && 1472 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { 1473 dev->is_thunderbolt = 1; 1474 return; 1475 } 1476 } 1477 } 1478 1479 static void set_pcie_untrusted(struct pci_dev *dev) 1480 { 1481 struct pci_dev *parent; 1482 1483 /* 1484 * If the upstream bridge is untrusted we treat this device 1485 * untrusted as well. 1486 */ 1487 parent = pci_upstream_bridge(dev); 1488 if (parent && parent->untrusted) 1489 dev->untrusted = true; 1490 } 1491 1492 /** 1493 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1494 * @dev: PCI device 1495 * 1496 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1497 * when forwarding a type1 configuration request the bridge must check that 1498 * the extended register address field is zero. The bridge is not permitted 1499 * to forward the transactions and must handle it as an Unsupported Request. 1500 * Some bridges do not follow this rule and simply drop the extended register 1501 * bits, resulting in the standard config space being aliased, every 256 1502 * bytes across the entire configuration space. Test for this condition by 1503 * comparing the first dword of each potential alias to the vendor/device ID. 1504 * Known offenders: 1505 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1506 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1507 */ 1508 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1509 { 1510 #ifdef CONFIG_PCI_QUIRKS 1511 int pos; 1512 u32 header, tmp; 1513 1514 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1515 1516 for (pos = PCI_CFG_SPACE_SIZE; 1517 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1518 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1519 || header != tmp) 1520 return false; 1521 } 1522 1523 return true; 1524 #else 1525 return false; 1526 #endif 1527 } 1528 1529 /** 1530 * pci_cfg_space_size - Get the configuration space size of the PCI device 1531 * @dev: PCI device 1532 * 1533 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1534 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1535 * access it. Maybe we don't have a way to generate extended config space 1536 * accesses, or the device is behind a reverse Express bridge. So we try 1537 * reading the dword at 0x100 which must either be 0 or a valid extended 1538 * capability header. 1539 */ 1540 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1541 { 1542 u32 status; 1543 int pos = PCI_CFG_SPACE_SIZE; 1544 1545 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1546 return PCI_CFG_SPACE_SIZE; 1547 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) 1548 return PCI_CFG_SPACE_SIZE; 1549 1550 return PCI_CFG_SPACE_EXP_SIZE; 1551 } 1552 1553 int pci_cfg_space_size(struct pci_dev *dev) 1554 { 1555 int pos; 1556 u32 status; 1557 u16 class; 1558 1559 #ifdef CONFIG_PCI_IOV 1560 /* 1561 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1562 * implement a PCIe capability and therefore must implement extended 1563 * config space. We can skip the NO_EXTCFG test below and the 1564 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1565 * the fact that the SR-IOV capability on the PF resides in extended 1566 * config space and must be accessible and non-aliased to have enabled 1567 * support for this VF. This is a micro performance optimization for 1568 * systems supporting many VFs. 1569 */ 1570 if (dev->is_virtfn) 1571 return PCI_CFG_SPACE_EXP_SIZE; 1572 #endif 1573 1574 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1575 return PCI_CFG_SPACE_SIZE; 1576 1577 class = dev->class >> 8; 1578 if (class == PCI_CLASS_BRIDGE_HOST) 1579 return pci_cfg_space_size_ext(dev); 1580 1581 if (pci_is_pcie(dev)) 1582 return pci_cfg_space_size_ext(dev); 1583 1584 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1585 if (!pos) 1586 return PCI_CFG_SPACE_SIZE; 1587 1588 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1589 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1590 return pci_cfg_space_size_ext(dev); 1591 1592 return PCI_CFG_SPACE_SIZE; 1593 } 1594 1595 static u32 pci_class(struct pci_dev *dev) 1596 { 1597 u32 class; 1598 1599 #ifdef CONFIG_PCI_IOV 1600 if (dev->is_virtfn) 1601 return dev->physfn->sriov->class; 1602 #endif 1603 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1604 return class; 1605 } 1606 1607 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1608 { 1609 #ifdef CONFIG_PCI_IOV 1610 if (dev->is_virtfn) { 1611 *vendor = dev->physfn->sriov->subsystem_vendor; 1612 *device = dev->physfn->sriov->subsystem_device; 1613 return; 1614 } 1615 #endif 1616 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1617 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1618 } 1619 1620 static u8 pci_hdr_type(struct pci_dev *dev) 1621 { 1622 u8 hdr_type; 1623 1624 #ifdef CONFIG_PCI_IOV 1625 if (dev->is_virtfn) 1626 return dev->physfn->sriov->hdr_type; 1627 #endif 1628 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1629 return hdr_type; 1630 } 1631 1632 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1633 1634 static void pci_msi_setup_pci_dev(struct pci_dev *dev) 1635 { 1636 /* 1637 * Disable the MSI hardware to avoid screaming interrupts 1638 * during boot. This is the power on reset default so 1639 * usually this should be a noop. 1640 */ 1641 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); 1642 if (dev->msi_cap) 1643 pci_msi_set_enable(dev, 0); 1644 1645 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1646 if (dev->msix_cap) 1647 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); 1648 } 1649 1650 /** 1651 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1652 * @dev: PCI device 1653 * 1654 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1655 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1656 */ 1657 static int pci_intx_mask_broken(struct pci_dev *dev) 1658 { 1659 u16 orig, toggle, new; 1660 1661 pci_read_config_word(dev, PCI_COMMAND, &orig); 1662 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1663 pci_write_config_word(dev, PCI_COMMAND, toggle); 1664 pci_read_config_word(dev, PCI_COMMAND, &new); 1665 1666 pci_write_config_word(dev, PCI_COMMAND, orig); 1667 1668 /* 1669 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1670 * r2.3, so strictly speaking, a device is not *broken* if it's not 1671 * writable. But we'll live with the misnomer for now. 1672 */ 1673 if (new != toggle) 1674 return 1; 1675 return 0; 1676 } 1677 1678 static void early_dump_pci_device(struct pci_dev *pdev) 1679 { 1680 u32 value[256 / 4]; 1681 int i; 1682 1683 pci_info(pdev, "config space:\n"); 1684 1685 for (i = 0; i < 256; i += 4) 1686 pci_read_config_dword(pdev, i, &value[i / 4]); 1687 1688 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1689 value, 256, false); 1690 } 1691 1692 /** 1693 * pci_setup_device - Fill in class and map information of a device 1694 * @dev: the device structure to fill 1695 * 1696 * Initialize the device structure with information about the device's 1697 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1698 * Called at initialisation of the PCI subsystem and by CardBus services. 1699 * Returns 0 on success and negative if unknown type of device (not normal, 1700 * bridge or CardBus). 1701 */ 1702 int pci_setup_device(struct pci_dev *dev) 1703 { 1704 u32 class; 1705 u16 cmd; 1706 u8 hdr_type; 1707 int pos = 0; 1708 struct pci_bus_region region; 1709 struct resource *res; 1710 1711 hdr_type = pci_hdr_type(dev); 1712 1713 dev->sysdata = dev->bus->sysdata; 1714 dev->dev.parent = dev->bus->bridge; 1715 dev->dev.bus = &pci_bus_type; 1716 dev->hdr_type = hdr_type & 0x7f; 1717 dev->multifunction = !!(hdr_type & 0x80); 1718 dev->error_state = pci_channel_io_normal; 1719 set_pcie_port_type(dev); 1720 1721 pci_dev_assign_slot(dev); 1722 1723 /* 1724 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1725 * set this higher, assuming the system even supports it. 1726 */ 1727 dev->dma_mask = 0xffffffff; 1728 1729 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1730 dev->bus->number, PCI_SLOT(dev->devfn), 1731 PCI_FUNC(dev->devfn)); 1732 1733 class = pci_class(dev); 1734 1735 dev->revision = class & 0xff; 1736 dev->class = class >> 8; /* upper 3 bytes */ 1737 1738 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1739 dev->vendor, dev->device, dev->hdr_type, dev->class); 1740 1741 if (pci_early_dump) 1742 early_dump_pci_device(dev); 1743 1744 /* Need to have dev->class ready */ 1745 dev->cfg_size = pci_cfg_space_size(dev); 1746 1747 /* Need to have dev->cfg_size ready */ 1748 set_pcie_thunderbolt(dev); 1749 1750 set_pcie_untrusted(dev); 1751 1752 /* "Unknown power state" */ 1753 dev->current_state = PCI_UNKNOWN; 1754 1755 /* Early fixups, before probing the BARs */ 1756 pci_fixup_device(pci_fixup_early, dev); 1757 1758 /* Device class may be changed after fixup */ 1759 class = dev->class >> 8; 1760 1761 if (dev->non_compliant_bars) { 1762 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1763 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1764 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1765 cmd &= ~PCI_COMMAND_IO; 1766 cmd &= ~PCI_COMMAND_MEMORY; 1767 pci_write_config_word(dev, PCI_COMMAND, cmd); 1768 } 1769 } 1770 1771 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1772 1773 switch (dev->hdr_type) { /* header type */ 1774 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1775 if (class == PCI_CLASS_BRIDGE_PCI) 1776 goto bad; 1777 pci_read_irq(dev); 1778 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1779 1780 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1781 1782 /* 1783 * Do the ugly legacy mode stuff here rather than broken chip 1784 * quirk code. Legacy mode ATA controllers have fixed 1785 * addresses. These are not always echoed in BAR0-3, and 1786 * BAR0-3 in a few cases contain junk! 1787 */ 1788 if (class == PCI_CLASS_STORAGE_IDE) { 1789 u8 progif; 1790 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1791 if ((progif & 1) == 0) { 1792 region.start = 0x1F0; 1793 region.end = 0x1F7; 1794 res = &dev->resource[0]; 1795 res->flags = LEGACY_IO_RESOURCE; 1796 pcibios_bus_to_resource(dev->bus, res, ®ion); 1797 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1798 res); 1799 region.start = 0x3F6; 1800 region.end = 0x3F6; 1801 res = &dev->resource[1]; 1802 res->flags = LEGACY_IO_RESOURCE; 1803 pcibios_bus_to_resource(dev->bus, res, ®ion); 1804 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1805 res); 1806 } 1807 if ((progif & 4) == 0) { 1808 region.start = 0x170; 1809 region.end = 0x177; 1810 res = &dev->resource[2]; 1811 res->flags = LEGACY_IO_RESOURCE; 1812 pcibios_bus_to_resource(dev->bus, res, ®ion); 1813 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1814 res); 1815 region.start = 0x376; 1816 region.end = 0x376; 1817 res = &dev->resource[3]; 1818 res->flags = LEGACY_IO_RESOURCE; 1819 pcibios_bus_to_resource(dev->bus, res, ®ion); 1820 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1821 res); 1822 } 1823 } 1824 break; 1825 1826 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1827 /* 1828 * The PCI-to-PCI bridge spec requires that subtractive 1829 * decoding (i.e. transparent) bridge must have programming 1830 * interface code of 0x01. 1831 */ 1832 pci_read_irq(dev); 1833 dev->transparent = ((dev->class & 0xff) == 1); 1834 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1835 pci_read_bridge_windows(dev); 1836 set_pcie_hotplug_bridge(dev); 1837 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1838 if (pos) { 1839 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1840 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1841 } 1842 break; 1843 1844 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1845 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1846 goto bad; 1847 pci_read_irq(dev); 1848 pci_read_bases(dev, 1, 0); 1849 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1850 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1851 break; 1852 1853 default: /* unknown header */ 1854 pci_err(dev, "unknown header type %02x, ignoring device\n", 1855 dev->hdr_type); 1856 return -EIO; 1857 1858 bad: 1859 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1860 dev->class, dev->hdr_type); 1861 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1862 } 1863 1864 /* We found a fine healthy device, go go go... */ 1865 return 0; 1866 } 1867 1868 static void pci_configure_mps(struct pci_dev *dev) 1869 { 1870 struct pci_dev *bridge = pci_upstream_bridge(dev); 1871 int mps, mpss, p_mps, rc; 1872 1873 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) 1874 return; 1875 1876 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 1877 if (dev->is_virtfn) 1878 return; 1879 1880 mps = pcie_get_mps(dev); 1881 p_mps = pcie_get_mps(bridge); 1882 1883 if (mps == p_mps) 1884 return; 1885 1886 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 1887 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1888 mps, pci_name(bridge), p_mps); 1889 return; 1890 } 1891 1892 /* 1893 * Fancier MPS configuration is done later by 1894 * pcie_bus_configure_settings() 1895 */ 1896 if (pcie_bus_config != PCIE_BUS_DEFAULT) 1897 return; 1898 1899 mpss = 128 << dev->pcie_mpss; 1900 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 1901 pcie_set_mps(bridge, mpss); 1902 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 1903 mpss, p_mps, 128 << bridge->pcie_mpss); 1904 p_mps = pcie_get_mps(bridge); 1905 } 1906 1907 rc = pcie_set_mps(dev, p_mps); 1908 if (rc) { 1909 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1910 p_mps); 1911 return; 1912 } 1913 1914 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 1915 p_mps, mps, mpss); 1916 } 1917 1918 static struct hpp_type0 pci_default_type0 = { 1919 .revision = 1, 1920 .cache_line_size = 8, 1921 .latency_timer = 0x40, 1922 .enable_serr = 0, 1923 .enable_perr = 0, 1924 }; 1925 1926 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) 1927 { 1928 u16 pci_cmd, pci_bctl; 1929 1930 if (!hpp) 1931 hpp = &pci_default_type0; 1932 1933 if (hpp->revision > 1) { 1934 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n", 1935 hpp->revision); 1936 hpp = &pci_default_type0; 1937 } 1938 1939 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); 1940 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); 1941 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); 1942 if (hpp->enable_serr) 1943 pci_cmd |= PCI_COMMAND_SERR; 1944 if (hpp->enable_perr) 1945 pci_cmd |= PCI_COMMAND_PARITY; 1946 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); 1947 1948 /* Program bridge control value */ 1949 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 1950 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 1951 hpp->latency_timer); 1952 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); 1953 if (hpp->enable_perr) 1954 pci_bctl |= PCI_BRIDGE_CTL_PARITY; 1955 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); 1956 } 1957 } 1958 1959 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) 1960 { 1961 int pos; 1962 1963 if (!hpp) 1964 return; 1965 1966 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1967 if (!pos) 1968 return; 1969 1970 pci_warn(dev, "PCI-X settings not supported\n"); 1971 } 1972 1973 static bool pcie_root_rcb_set(struct pci_dev *dev) 1974 { 1975 struct pci_dev *rp = pcie_find_root_port(dev); 1976 u16 lnkctl; 1977 1978 if (!rp) 1979 return false; 1980 1981 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); 1982 if (lnkctl & PCI_EXP_LNKCTL_RCB) 1983 return true; 1984 1985 return false; 1986 } 1987 1988 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) 1989 { 1990 int pos; 1991 u32 reg32; 1992 1993 if (!hpp) 1994 return; 1995 1996 if (!pci_is_pcie(dev)) 1997 return; 1998 1999 if (hpp->revision > 1) { 2000 pci_warn(dev, "PCIe settings rev %d not supported\n", 2001 hpp->revision); 2002 return; 2003 } 2004 2005 /* 2006 * Don't allow _HPX to change MPS or MRRS settings. We manage 2007 * those to make sure they're consistent with the rest of the 2008 * platform. 2009 */ 2010 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | 2011 PCI_EXP_DEVCTL_READRQ; 2012 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | 2013 PCI_EXP_DEVCTL_READRQ); 2014 2015 /* Initialize Device Control Register */ 2016 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 2017 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); 2018 2019 /* Initialize Link Control Register */ 2020 if (pcie_cap_has_lnkctl(dev)) { 2021 2022 /* 2023 * If the Root Port supports Read Completion Boundary of 2024 * 128, set RCB to 128. Otherwise, clear it. 2025 */ 2026 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB; 2027 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB; 2028 if (pcie_root_rcb_set(dev)) 2029 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB; 2030 2031 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, 2032 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); 2033 } 2034 2035 /* Find Advanced Error Reporting Enhanced Capability */ 2036 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 2037 if (!pos) 2038 return; 2039 2040 /* Initialize Uncorrectable Error Mask Register */ 2041 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); 2042 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; 2043 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); 2044 2045 /* Initialize Uncorrectable Error Severity Register */ 2046 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); 2047 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; 2048 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); 2049 2050 /* Initialize Correctable Error Mask Register */ 2051 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); 2052 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; 2053 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); 2054 2055 /* Initialize Advanced Error Capabilities and Control Register */ 2056 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); 2057 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; 2058 2059 /* Don't enable ECRC generation or checking if unsupported */ 2060 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) 2061 reg32 &= ~PCI_ERR_CAP_ECRC_GENE; 2062 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC)) 2063 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE; 2064 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); 2065 2066 /* 2067 * FIXME: The following two registers are not supported yet. 2068 * 2069 * o Secondary Uncorrectable Error Severity Register 2070 * o Secondary Uncorrectable Error Mask Register 2071 */ 2072 } 2073 2074 static u16 hpx3_device_type(struct pci_dev *dev) 2075 { 2076 u16 pcie_type = pci_pcie_type(dev); 2077 const int pcie_to_hpx3_type[] = { 2078 [PCI_EXP_TYPE_ENDPOINT] = HPX_TYPE_ENDPOINT, 2079 [PCI_EXP_TYPE_LEG_END] = HPX_TYPE_LEG_END, 2080 [PCI_EXP_TYPE_RC_END] = HPX_TYPE_RC_END, 2081 [PCI_EXP_TYPE_RC_EC] = HPX_TYPE_RC_EC, 2082 [PCI_EXP_TYPE_ROOT_PORT] = HPX_TYPE_ROOT_PORT, 2083 [PCI_EXP_TYPE_UPSTREAM] = HPX_TYPE_UPSTREAM, 2084 [PCI_EXP_TYPE_DOWNSTREAM] = HPX_TYPE_DOWNSTREAM, 2085 [PCI_EXP_TYPE_PCI_BRIDGE] = HPX_TYPE_PCI_BRIDGE, 2086 [PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE, 2087 }; 2088 2089 if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type)) 2090 return 0; 2091 2092 return pcie_to_hpx3_type[pcie_type]; 2093 } 2094 2095 static u8 hpx3_function_type(struct pci_dev *dev) 2096 { 2097 if (dev->is_virtfn) 2098 return HPX_FN_SRIOV_VIRT; 2099 else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0) 2100 return HPX_FN_SRIOV_PHYS; 2101 else 2102 return HPX_FN_NORMAL; 2103 } 2104 2105 static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id) 2106 { 2107 u8 cap_ver = hpx3_cap_id & 0xf; 2108 2109 if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id) 2110 return true; 2111 else if (cap_ver == pcie_cap_id) 2112 return true; 2113 2114 return false; 2115 } 2116 2117 static void program_hpx_type3_register(struct pci_dev *dev, 2118 const struct hpx_type3 *reg) 2119 { 2120 u32 match_reg, write_reg, header, orig_value; 2121 u16 pos; 2122 2123 if (!(hpx3_device_type(dev) & reg->device_type)) 2124 return; 2125 2126 if (!(hpx3_function_type(dev) & reg->function_type)) 2127 return; 2128 2129 switch (reg->config_space_location) { 2130 case HPX_CFG_PCICFG: 2131 pos = 0; 2132 break; 2133 case HPX_CFG_PCIE_CAP: 2134 pos = pci_find_capability(dev, reg->pci_exp_cap_id); 2135 if (pos == 0) 2136 return; 2137 2138 break; 2139 case HPX_CFG_PCIE_CAP_EXT: 2140 pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id); 2141 if (pos == 0) 2142 return; 2143 2144 pci_read_config_dword(dev, pos, &header); 2145 if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header), 2146 reg->pci_exp_cap_ver)) 2147 return; 2148 2149 break; 2150 case HPX_CFG_VEND_CAP: /* Fall through */ 2151 case HPX_CFG_DVSEC: /* Fall through */ 2152 default: 2153 pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location"); 2154 return; 2155 } 2156 2157 pci_read_config_dword(dev, pos + reg->match_offset, &match_reg); 2158 2159 if ((match_reg & reg->match_mask_and) != reg->match_value) 2160 return; 2161 2162 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg); 2163 orig_value = write_reg; 2164 write_reg &= reg->reg_mask_and; 2165 write_reg |= reg->reg_mask_or; 2166 2167 if (orig_value == write_reg) 2168 return; 2169 2170 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg); 2171 2172 pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x", 2173 pos, orig_value, write_reg); 2174 } 2175 2176 static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx3) 2177 { 2178 if (!hpx3) 2179 return; 2180 2181 if (!pci_is_pcie(dev)) 2182 return; 2183 2184 program_hpx_type3_register(dev, hpx3); 2185 } 2186 2187 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2188 { 2189 struct pci_host_bridge *host; 2190 u32 cap; 2191 u16 ctl; 2192 int ret; 2193 2194 if (!pci_is_pcie(dev)) 2195 return 0; 2196 2197 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2198 if (ret) 2199 return 0; 2200 2201 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2202 return 0; 2203 2204 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2205 if (ret) 2206 return 0; 2207 2208 host = pci_find_host_bridge(dev->bus); 2209 if (!host) 2210 return 0; 2211 2212 /* 2213 * If some device in the hierarchy doesn't handle Extended Tags 2214 * correctly, make sure they're disabled. 2215 */ 2216 if (host->no_ext_tags) { 2217 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2218 pci_info(dev, "disabling Extended Tags\n"); 2219 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2220 PCI_EXP_DEVCTL_EXT_TAG); 2221 } 2222 return 0; 2223 } 2224 2225 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2226 pci_info(dev, "enabling Extended Tags\n"); 2227 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2228 PCI_EXP_DEVCTL_EXT_TAG); 2229 } 2230 return 0; 2231 } 2232 2233 /** 2234 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2235 * @dev: PCI device to query 2236 * 2237 * Returns true if the device has enabled relaxed ordering attribute. 2238 */ 2239 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2240 { 2241 u16 v; 2242 2243 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2244 2245 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2246 } 2247 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2248 2249 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2250 { 2251 struct pci_dev *root; 2252 2253 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2254 if (dev->is_virtfn) 2255 return; 2256 2257 if (!pcie_relaxed_ordering_enabled(dev)) 2258 return; 2259 2260 /* 2261 * For now, we only deal with Relaxed Ordering issues with Root 2262 * Ports. Peer-to-Peer DMA is another can of worms. 2263 */ 2264 root = pci_find_pcie_root_port(dev); 2265 if (!root) 2266 return; 2267 2268 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2269 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2270 PCI_EXP_DEVCTL_RELAX_EN); 2271 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2272 } 2273 } 2274 2275 static void pci_configure_ltr(struct pci_dev *dev) 2276 { 2277 #ifdef CONFIG_PCIEASPM 2278 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2279 struct pci_dev *bridge; 2280 u32 cap, ctl; 2281 2282 if (!pci_is_pcie(dev)) 2283 return; 2284 2285 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2286 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2287 return; 2288 2289 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2290 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2291 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2292 dev->ltr_path = 1; 2293 return; 2294 } 2295 2296 bridge = pci_upstream_bridge(dev); 2297 if (bridge && bridge->ltr_path) 2298 dev->ltr_path = 1; 2299 2300 return; 2301 } 2302 2303 if (!host->native_ltr) 2304 return; 2305 2306 /* 2307 * Software must not enable LTR in an Endpoint unless the Root 2308 * Complex and all intermediate Switches indicate support for LTR. 2309 * PCIe r4.0, sec 6.18. 2310 */ 2311 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 2312 ((bridge = pci_upstream_bridge(dev)) && 2313 bridge->ltr_path)) { 2314 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2315 PCI_EXP_DEVCTL2_LTR_EN); 2316 dev->ltr_path = 1; 2317 } 2318 #endif 2319 } 2320 2321 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2322 { 2323 #ifdef CONFIG_PCI_PASID 2324 struct pci_dev *bridge; 2325 int pcie_type; 2326 u32 cap; 2327 2328 if (!pci_is_pcie(dev)) 2329 return; 2330 2331 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2332 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2333 return; 2334 2335 pcie_type = pci_pcie_type(dev); 2336 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2337 pcie_type == PCI_EXP_TYPE_RC_END) 2338 dev->eetlp_prefix_path = 1; 2339 else { 2340 bridge = pci_upstream_bridge(dev); 2341 if (bridge && bridge->eetlp_prefix_path) 2342 dev->eetlp_prefix_path = 1; 2343 } 2344 #endif 2345 } 2346 2347 static void pci_configure_serr(struct pci_dev *dev) 2348 { 2349 u16 control; 2350 2351 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2352 2353 /* 2354 * A bridge will not forward ERR_ messages coming from an 2355 * endpoint unless SERR# forwarding is enabled. 2356 */ 2357 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2358 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2359 control |= PCI_BRIDGE_CTL_SERR; 2360 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2361 } 2362 } 2363 } 2364 2365 static void pci_configure_device(struct pci_dev *dev) 2366 { 2367 static const struct hotplug_program_ops hp_ops = { 2368 .program_type0 = program_hpp_type0, 2369 .program_type1 = program_hpp_type1, 2370 .program_type2 = program_hpp_type2, 2371 .program_type3 = program_hpx_type3, 2372 }; 2373 2374 pci_configure_mps(dev); 2375 pci_configure_extended_tags(dev, NULL); 2376 pci_configure_relaxed_ordering(dev); 2377 pci_configure_ltr(dev); 2378 pci_configure_eetlp_prefix(dev); 2379 pci_configure_serr(dev); 2380 2381 pci_acpi_program_hp_params(dev, &hp_ops); 2382 } 2383 2384 static void pci_release_capabilities(struct pci_dev *dev) 2385 { 2386 pci_aer_exit(dev); 2387 pci_vpd_release(dev); 2388 pci_iov_release(dev); 2389 pci_free_cap_save_buffers(dev); 2390 } 2391 2392 /** 2393 * pci_release_dev - Free a PCI device structure when all users of it are 2394 * finished 2395 * @dev: device that's been disconnected 2396 * 2397 * Will be called only by the device core when all users of this PCI device are 2398 * done. 2399 */ 2400 static void pci_release_dev(struct device *dev) 2401 { 2402 struct pci_dev *pci_dev; 2403 2404 pci_dev = to_pci_dev(dev); 2405 pci_release_capabilities(pci_dev); 2406 pci_release_of_node(pci_dev); 2407 pcibios_release_device(pci_dev); 2408 pci_bus_put(pci_dev->bus); 2409 kfree(pci_dev->driver_override); 2410 bitmap_free(pci_dev->dma_alias_mask); 2411 kfree(pci_dev); 2412 } 2413 2414 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2415 { 2416 struct pci_dev *dev; 2417 2418 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2419 if (!dev) 2420 return NULL; 2421 2422 INIT_LIST_HEAD(&dev->bus_list); 2423 dev->dev.type = &pci_dev_type; 2424 dev->bus = pci_bus_get(bus); 2425 2426 return dev; 2427 } 2428 EXPORT_SYMBOL(pci_alloc_dev); 2429 2430 static bool pci_bus_crs_vendor_id(u32 l) 2431 { 2432 return (l & 0xffff) == 0x0001; 2433 } 2434 2435 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2436 int timeout) 2437 { 2438 int delay = 1; 2439 2440 if (!pci_bus_crs_vendor_id(*l)) 2441 return true; /* not a CRS completion */ 2442 2443 if (!timeout) 2444 return false; /* CRS, but caller doesn't want to wait */ 2445 2446 /* 2447 * We got the reserved Vendor ID that indicates a completion with 2448 * Configuration Request Retry Status (CRS). Retry until we get a 2449 * valid Vendor ID or we time out. 2450 */ 2451 while (pci_bus_crs_vendor_id(*l)) { 2452 if (delay > timeout) { 2453 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2454 pci_domain_nr(bus), bus->number, 2455 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2456 2457 return false; 2458 } 2459 if (delay >= 1000) 2460 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2461 pci_domain_nr(bus), bus->number, 2462 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2463 2464 msleep(delay); 2465 delay *= 2; 2466 2467 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2468 return false; 2469 } 2470 2471 if (delay >= 1000) 2472 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2473 pci_domain_nr(bus), bus->number, 2474 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2475 2476 return true; 2477 } 2478 2479 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2480 int timeout) 2481 { 2482 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2483 return false; 2484 2485 /* Some broken boards return 0 or ~0 if a slot is empty: */ 2486 if (*l == 0xffffffff || *l == 0x00000000 || 2487 *l == 0x0000ffff || *l == 0xffff0000) 2488 return false; 2489 2490 if (pci_bus_crs_vendor_id(*l)) 2491 return pci_bus_wait_crs(bus, devfn, l, timeout); 2492 2493 return true; 2494 } 2495 2496 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2497 int timeout) 2498 { 2499 #ifdef CONFIG_PCI_QUIRKS 2500 struct pci_dev *bridge = bus->self; 2501 2502 /* 2503 * Certain IDT switches have an issue where they improperly trigger 2504 * ACS Source Validation errors on completions for config reads. 2505 */ 2506 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2507 bridge->device == 0x80b5) 2508 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2509 #endif 2510 2511 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2512 } 2513 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2514 2515 /* 2516 * Read the config data for a PCI device, sanity-check it, 2517 * and fill in the dev structure. 2518 */ 2519 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2520 { 2521 struct pci_dev *dev; 2522 u32 l; 2523 2524 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2525 return NULL; 2526 2527 dev = pci_alloc_dev(bus); 2528 if (!dev) 2529 return NULL; 2530 2531 dev->devfn = devfn; 2532 dev->vendor = l & 0xffff; 2533 dev->device = (l >> 16) & 0xffff; 2534 2535 pci_set_of_node(dev); 2536 2537 if (pci_setup_device(dev)) { 2538 pci_bus_put(dev->bus); 2539 kfree(dev); 2540 return NULL; 2541 } 2542 2543 return dev; 2544 } 2545 2546 void pcie_report_downtraining(struct pci_dev *dev) 2547 { 2548 if (!pci_is_pcie(dev)) 2549 return; 2550 2551 /* Look from the device up to avoid downstream ports with no devices */ 2552 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2553 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2554 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2555 return; 2556 2557 /* Multi-function PCIe devices share the same link/status */ 2558 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2559 return; 2560 2561 /* Print link status only if the device is constrained by the fabric */ 2562 __pcie_print_link_status(dev, false); 2563 } 2564 2565 static void pci_init_capabilities(struct pci_dev *dev) 2566 { 2567 /* Enhanced Allocation */ 2568 pci_ea_init(dev); 2569 2570 /* Setup MSI caps & disable MSI/MSI-X interrupts */ 2571 pci_msi_setup_pci_dev(dev); 2572 2573 /* Buffers for saving PCIe and PCI-X capabilities */ 2574 pci_allocate_cap_save_buffers(dev); 2575 2576 /* Power Management */ 2577 pci_pm_init(dev); 2578 2579 /* Vital Product Data */ 2580 pci_vpd_init(dev); 2581 2582 /* Alternative Routing-ID Forwarding */ 2583 pci_configure_ari(dev); 2584 2585 /* Single Root I/O Virtualization */ 2586 pci_iov_init(dev); 2587 2588 /* Address Translation Services */ 2589 pci_ats_init(dev); 2590 2591 /* Enable ACS P2P upstream forwarding */ 2592 pci_enable_acs(dev); 2593 2594 /* Precision Time Measurement */ 2595 pci_ptm_init(dev); 2596 2597 /* Advanced Error Reporting */ 2598 pci_aer_init(dev); 2599 2600 pcie_report_downtraining(dev); 2601 2602 if (pci_probe_reset_function(dev) == 0) 2603 dev->reset_fn = 1; 2604 } 2605 2606 /* 2607 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2608 * devices. Firmware interfaces that can select the MSI domain on a 2609 * per-device basis should be called from here. 2610 */ 2611 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2612 { 2613 struct irq_domain *d; 2614 2615 /* 2616 * If a domain has been set through the pcibios_add_device() 2617 * callback, then this is the one (platform code knows best). 2618 */ 2619 d = dev_get_msi_domain(&dev->dev); 2620 if (d) 2621 return d; 2622 2623 /* 2624 * Let's see if we have a firmware interface able to provide 2625 * the domain. 2626 */ 2627 d = pci_msi_get_device_domain(dev); 2628 if (d) 2629 return d; 2630 2631 return NULL; 2632 } 2633 2634 static void pci_set_msi_domain(struct pci_dev *dev) 2635 { 2636 struct irq_domain *d; 2637 2638 /* 2639 * If the platform or firmware interfaces cannot supply a 2640 * device-specific MSI domain, then inherit the default domain 2641 * from the host bridge itself. 2642 */ 2643 d = pci_dev_msi_domain(dev); 2644 if (!d) 2645 d = dev_get_msi_domain(&dev->bus->dev); 2646 2647 dev_set_msi_domain(&dev->dev, d); 2648 } 2649 2650 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2651 { 2652 int ret; 2653 2654 pci_configure_device(dev); 2655 2656 device_initialize(&dev->dev); 2657 dev->dev.release = pci_release_dev; 2658 2659 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2660 dev->dev.dma_mask = &dev->dma_mask; 2661 dev->dev.dma_parms = &dev->dma_parms; 2662 dev->dev.coherent_dma_mask = 0xffffffffull; 2663 2664 dma_set_max_seg_size(&dev->dev, 65536); 2665 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2666 2667 /* Fix up broken headers */ 2668 pci_fixup_device(pci_fixup_header, dev); 2669 2670 /* Moved out from quirk header fixup code */ 2671 pci_reassigndev_resource_alignment(dev); 2672 2673 /* Clear the state_saved flag */ 2674 dev->state_saved = false; 2675 2676 /* Initialize various capabilities */ 2677 pci_init_capabilities(dev); 2678 2679 /* 2680 * Add the device to our list of discovered devices 2681 * and the bus list for fixup functions, etc. 2682 */ 2683 down_write(&pci_bus_sem); 2684 list_add_tail(&dev->bus_list, &bus->devices); 2685 up_write(&pci_bus_sem); 2686 2687 ret = pcibios_add_device(dev); 2688 WARN_ON(ret < 0); 2689 2690 /* Set up MSI IRQ domain */ 2691 pci_set_msi_domain(dev); 2692 2693 /* Notifier could use PCI capabilities */ 2694 dev->match_driver = false; 2695 ret = device_add(&dev->dev); 2696 WARN_ON(ret < 0); 2697 } 2698 2699 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2700 { 2701 struct pci_dev *dev; 2702 2703 dev = pci_get_slot(bus, devfn); 2704 if (dev) { 2705 pci_dev_put(dev); 2706 return dev; 2707 } 2708 2709 dev = pci_scan_device(bus, devfn); 2710 if (!dev) 2711 return NULL; 2712 2713 pci_device_add(dev, bus); 2714 2715 return dev; 2716 } 2717 EXPORT_SYMBOL(pci_scan_single_device); 2718 2719 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) 2720 { 2721 int pos; 2722 u16 cap = 0; 2723 unsigned next_fn; 2724 2725 if (pci_ari_enabled(bus)) { 2726 if (!dev) 2727 return 0; 2728 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2729 if (!pos) 2730 return 0; 2731 2732 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2733 next_fn = PCI_ARI_CAP_NFN(cap); 2734 if (next_fn <= fn) 2735 return 0; /* protect against malformed list */ 2736 2737 return next_fn; 2738 } 2739 2740 /* dev may be NULL for non-contiguous multifunction devices */ 2741 if (!dev || dev->multifunction) 2742 return (fn + 1) % 8; 2743 2744 return 0; 2745 } 2746 2747 static int only_one_child(struct pci_bus *bus) 2748 { 2749 struct pci_dev *bridge = bus->self; 2750 2751 /* 2752 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2753 * we scan for all possible devices, not just Device 0. 2754 */ 2755 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2756 return 0; 2757 2758 /* 2759 * A PCIe Downstream Port normally leads to a Link with only Device 2760 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2761 * only for Device 0 in that situation. 2762 * 2763 * Checking has_secondary_link is a hack to identify Downstream 2764 * Ports because sometimes Switches are configured such that the 2765 * PCIe Port Type labels are backwards. 2766 */ 2767 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link) 2768 return 1; 2769 2770 return 0; 2771 } 2772 2773 /** 2774 * pci_scan_slot - Scan a PCI slot on a bus for devices 2775 * @bus: PCI bus to scan 2776 * @devfn: slot number to scan (must have zero function) 2777 * 2778 * Scan a PCI slot on the specified PCI bus for devices, adding 2779 * discovered devices to the @bus->devices list. New devices 2780 * will not have is_added set. 2781 * 2782 * Returns the number of new devices found. 2783 */ 2784 int pci_scan_slot(struct pci_bus *bus, int devfn) 2785 { 2786 unsigned fn, nr = 0; 2787 struct pci_dev *dev; 2788 2789 if (only_one_child(bus) && (devfn > 0)) 2790 return 0; /* Already scanned the entire slot */ 2791 2792 dev = pci_scan_single_device(bus, devfn); 2793 if (!dev) 2794 return 0; 2795 if (!pci_dev_is_added(dev)) 2796 nr++; 2797 2798 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { 2799 dev = pci_scan_single_device(bus, devfn + fn); 2800 if (dev) { 2801 if (!pci_dev_is_added(dev)) 2802 nr++; 2803 dev->multifunction = 1; 2804 } 2805 } 2806 2807 /* Only one slot has PCIe device */ 2808 if (bus->self && nr) 2809 pcie_aspm_init_link_state(bus->self); 2810 2811 return nr; 2812 } 2813 EXPORT_SYMBOL(pci_scan_slot); 2814 2815 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2816 { 2817 u8 *smpss = data; 2818 2819 if (!pci_is_pcie(dev)) 2820 return 0; 2821 2822 /* 2823 * We don't have a way to change MPS settings on devices that have 2824 * drivers attached. A hot-added device might support only the minimum 2825 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2826 * where devices may be hot-added, we limit the fabric MPS to 128 so 2827 * hot-added devices will work correctly. 2828 * 2829 * However, if we hot-add a device to a slot directly below a Root 2830 * Port, it's impossible for there to be other existing devices below 2831 * the port. We don't limit the MPS in this case because we can 2832 * reconfigure MPS on both the Root Port and the hot-added device, 2833 * and there are no other devices involved. 2834 * 2835 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2836 */ 2837 if (dev->is_hotplug_bridge && 2838 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2839 *smpss = 0; 2840 2841 if (*smpss > dev->pcie_mpss) 2842 *smpss = dev->pcie_mpss; 2843 2844 return 0; 2845 } 2846 2847 static void pcie_write_mps(struct pci_dev *dev, int mps) 2848 { 2849 int rc; 2850 2851 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2852 mps = 128 << dev->pcie_mpss; 2853 2854 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2855 dev->bus->self) 2856 2857 /* 2858 * For "Performance", the assumption is made that 2859 * downstream communication will never be larger than 2860 * the MRRS. So, the MPS only needs to be configured 2861 * for the upstream communication. This being the case, 2862 * walk from the top down and set the MPS of the child 2863 * to that of the parent bus. 2864 * 2865 * Configure the device MPS with the smaller of the 2866 * device MPSS or the bridge MPS (which is assumed to be 2867 * properly configured at this point to the largest 2868 * allowable MPS based on its parent bus). 2869 */ 2870 mps = min(mps, pcie_get_mps(dev->bus->self)); 2871 } 2872 2873 rc = pcie_set_mps(dev, mps); 2874 if (rc) 2875 pci_err(dev, "Failed attempting to set the MPS\n"); 2876 } 2877 2878 static void pcie_write_mrrs(struct pci_dev *dev) 2879 { 2880 int rc, mrrs; 2881 2882 /* 2883 * In the "safe" case, do not configure the MRRS. There appear to be 2884 * issues with setting MRRS to 0 on a number of devices. 2885 */ 2886 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2887 return; 2888 2889 /* 2890 * For max performance, the MRRS must be set to the largest supported 2891 * value. However, it cannot be configured larger than the MPS the 2892 * device or the bus can support. This should already be properly 2893 * configured by a prior call to pcie_write_mps(). 2894 */ 2895 mrrs = pcie_get_mps(dev); 2896 2897 /* 2898 * MRRS is a R/W register. Invalid values can be written, but a 2899 * subsequent read will verify if the value is acceptable or not. 2900 * If the MRRS value provided is not acceptable (e.g., too large), 2901 * shrink the value until it is acceptable to the HW. 2902 */ 2903 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2904 rc = pcie_set_readrq(dev, mrrs); 2905 if (!rc) 2906 break; 2907 2908 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2909 mrrs /= 2; 2910 } 2911 2912 if (mrrs < 128) 2913 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2914 } 2915 2916 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2917 { 2918 int mps, orig_mps; 2919 2920 if (!pci_is_pcie(dev)) 2921 return 0; 2922 2923 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2924 pcie_bus_config == PCIE_BUS_DEFAULT) 2925 return 0; 2926 2927 mps = 128 << *(u8 *)data; 2928 orig_mps = pcie_get_mps(dev); 2929 2930 pcie_write_mps(dev, mps); 2931 pcie_write_mrrs(dev); 2932 2933 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2934 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2935 orig_mps, pcie_get_readrq(dev)); 2936 2937 return 0; 2938 } 2939 2940 /* 2941 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2942 * parents then children fashion. If this changes, then this code will not 2943 * work as designed. 2944 */ 2945 void pcie_bus_configure_settings(struct pci_bus *bus) 2946 { 2947 u8 smpss = 0; 2948 2949 if (!bus->self) 2950 return; 2951 2952 if (!pci_is_pcie(bus->self)) 2953 return; 2954 2955 /* 2956 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2957 * to be aware of the MPS of the destination. To work around this, 2958 * simply force the MPS of the entire system to the smallest possible. 2959 */ 2960 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2961 smpss = 0; 2962 2963 if (pcie_bus_config == PCIE_BUS_SAFE) { 2964 smpss = bus->self->pcie_mpss; 2965 2966 pcie_find_smpss(bus->self, &smpss); 2967 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2968 } 2969 2970 pcie_bus_configure_set(bus->self, &smpss); 2971 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2972 } 2973 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2974 2975 /* 2976 * Called after each bus is probed, but before its children are examined. This 2977 * is marked as __weak because multiple architectures define it. 2978 */ 2979 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2980 { 2981 /* nothing to do, expected to be removed in the future */ 2982 } 2983 2984 /** 2985 * pci_scan_child_bus_extend() - Scan devices below a bus 2986 * @bus: Bus to scan for devices 2987 * @available_buses: Total number of buses available (%0 does not try to 2988 * extend beyond the minimal) 2989 * 2990 * Scans devices below @bus including subordinate buses. Returns new 2991 * subordinate number including all the found devices. Passing 2992 * @available_buses causes the remaining bus space to be distributed 2993 * equally between hotplug-capable bridges to allow future extension of the 2994 * hierarchy. 2995 */ 2996 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2997 unsigned int available_buses) 2998 { 2999 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 3000 unsigned int start = bus->busn_res.start; 3001 unsigned int devfn, fn, cmax, max = start; 3002 struct pci_dev *dev; 3003 int nr_devs; 3004 3005 dev_dbg(&bus->dev, "scanning bus\n"); 3006 3007 /* Go find them, Rover! */ 3008 for (devfn = 0; devfn < 256; devfn += 8) { 3009 nr_devs = pci_scan_slot(bus, devfn); 3010 3011 /* 3012 * The Jailhouse hypervisor may pass individual functions of a 3013 * multi-function device to a guest without passing function 0. 3014 * Look for them as well. 3015 */ 3016 if (jailhouse_paravirt() && nr_devs == 0) { 3017 for (fn = 1; fn < 8; fn++) { 3018 dev = pci_scan_single_device(bus, devfn + fn); 3019 if (dev) 3020 dev->multifunction = 1; 3021 } 3022 } 3023 } 3024 3025 /* Reserve buses for SR-IOV capability */ 3026 used_buses = pci_iov_bus_range(bus); 3027 max += used_buses; 3028 3029 /* 3030 * After performing arch-dependent fixup of the bus, look behind 3031 * all PCI-to-PCI bridges on this bus. 3032 */ 3033 if (!bus->is_added) { 3034 dev_dbg(&bus->dev, "fixups for bus\n"); 3035 pcibios_fixup_bus(bus); 3036 bus->is_added = 1; 3037 } 3038 3039 /* 3040 * Calculate how many hotplug bridges and normal bridges there 3041 * are on this bus. We will distribute the additional available 3042 * buses between hotplug bridges. 3043 */ 3044 for_each_pci_bridge(dev, bus) { 3045 if (dev->is_hotplug_bridge) 3046 hotplug_bridges++; 3047 else 3048 normal_bridges++; 3049 } 3050 3051 /* 3052 * Scan bridges that are already configured. We don't touch them 3053 * unless they are misconfigured (which will be done in the second 3054 * scan below). 3055 */ 3056 for_each_pci_bridge(dev, bus) { 3057 cmax = max; 3058 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 3059 3060 /* 3061 * Reserve one bus for each bridge now to avoid extending 3062 * hotplug bridges too much during the second scan below. 3063 */ 3064 used_buses++; 3065 if (cmax - max > 1) 3066 used_buses += cmax - max - 1; 3067 } 3068 3069 /* Scan bridges that need to be reconfigured */ 3070 for_each_pci_bridge(dev, bus) { 3071 unsigned int buses = 0; 3072 3073 if (!hotplug_bridges && normal_bridges == 1) { 3074 3075 /* 3076 * There is only one bridge on the bus (upstream 3077 * port) so it gets all available buses which it 3078 * can then distribute to the possible hotplug 3079 * bridges below. 3080 */ 3081 buses = available_buses; 3082 } else if (dev->is_hotplug_bridge) { 3083 3084 /* 3085 * Distribute the extra buses between hotplug 3086 * bridges if any. 3087 */ 3088 buses = available_buses / hotplug_bridges; 3089 buses = min(buses, available_buses - used_buses + 1); 3090 } 3091 3092 cmax = max; 3093 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 3094 /* One bus is already accounted so don't add it again */ 3095 if (max - cmax > 1) 3096 used_buses += max - cmax - 1; 3097 } 3098 3099 /* 3100 * Make sure a hotplug bridge has at least the minimum requested 3101 * number of buses but allow it to grow up to the maximum available 3102 * bus number of there is room. 3103 */ 3104 if (bus->self && bus->self->is_hotplug_bridge) { 3105 used_buses = max_t(unsigned int, available_buses, 3106 pci_hotplug_bus_size - 1); 3107 if (max - start < used_buses) { 3108 max = start + used_buses; 3109 3110 /* Do not allocate more buses than we have room left */ 3111 if (max > bus->busn_res.end) 3112 max = bus->busn_res.end; 3113 3114 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 3115 &bus->busn_res, max - start); 3116 } 3117 } 3118 3119 /* 3120 * We've scanned the bus and so we know all about what's on 3121 * the other side of any bridges that may be on this bus plus 3122 * any devices. 3123 * 3124 * Return how far we've got finding sub-buses. 3125 */ 3126 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3127 return max; 3128 } 3129 3130 /** 3131 * pci_scan_child_bus() - Scan devices below a bus 3132 * @bus: Bus to scan for devices 3133 * 3134 * Scans devices below @bus including subordinate buses. Returns new 3135 * subordinate number including all the found devices. 3136 */ 3137 unsigned int pci_scan_child_bus(struct pci_bus *bus) 3138 { 3139 return pci_scan_child_bus_extend(bus, 0); 3140 } 3141 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3142 3143 /** 3144 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3145 * @bridge: Host bridge to set up 3146 * 3147 * Default empty implementation. Replace with an architecture-specific setup 3148 * routine, if necessary. 3149 */ 3150 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3151 { 3152 return 0; 3153 } 3154 3155 void __weak pcibios_add_bus(struct pci_bus *bus) 3156 { 3157 } 3158 3159 void __weak pcibios_remove_bus(struct pci_bus *bus) 3160 { 3161 } 3162 3163 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3164 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3165 { 3166 int error; 3167 struct pci_host_bridge *bridge; 3168 3169 bridge = pci_alloc_host_bridge(0); 3170 if (!bridge) 3171 return NULL; 3172 3173 bridge->dev.parent = parent; 3174 3175 list_splice_init(resources, &bridge->windows); 3176 bridge->sysdata = sysdata; 3177 bridge->busnr = bus; 3178 bridge->ops = ops; 3179 3180 error = pci_register_host_bridge(bridge); 3181 if (error < 0) 3182 goto err_out; 3183 3184 return bridge->bus; 3185 3186 err_out: 3187 kfree(bridge); 3188 return NULL; 3189 } 3190 EXPORT_SYMBOL_GPL(pci_create_root_bus); 3191 3192 int pci_host_probe(struct pci_host_bridge *bridge) 3193 { 3194 struct pci_bus *bus, *child; 3195 int ret; 3196 3197 ret = pci_scan_root_bus_bridge(bridge); 3198 if (ret < 0) { 3199 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3200 return ret; 3201 } 3202 3203 bus = bridge->bus; 3204 3205 /* 3206 * We insert PCI resources into the iomem_resource and 3207 * ioport_resource trees in either pci_bus_claim_resources() 3208 * or pci_bus_assign_resources(). 3209 */ 3210 if (pci_has_flag(PCI_PROBE_ONLY)) { 3211 pci_bus_claim_resources(bus); 3212 } else { 3213 pci_bus_size_bridges(bus); 3214 pci_bus_assign_resources(bus); 3215 3216 list_for_each_entry(child, &bus->children, node) 3217 pcie_bus_configure_settings(child); 3218 } 3219 3220 pci_bus_add_devices(bus); 3221 return 0; 3222 } 3223 EXPORT_SYMBOL_GPL(pci_host_probe); 3224 3225 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3226 { 3227 struct resource *res = &b->busn_res; 3228 struct resource *parent_res, *conflict; 3229 3230 res->start = bus; 3231 res->end = bus_max; 3232 res->flags = IORESOURCE_BUS; 3233 3234 if (!pci_is_root_bus(b)) 3235 parent_res = &b->parent->busn_res; 3236 else { 3237 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3238 res->flags |= IORESOURCE_PCI_FIXED; 3239 } 3240 3241 conflict = request_resource_conflict(parent_res, res); 3242 3243 if (conflict) 3244 dev_info(&b->dev, 3245 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3246 res, pci_is_root_bus(b) ? "domain " : "", 3247 parent_res, conflict->name, conflict); 3248 3249 return conflict == NULL; 3250 } 3251 3252 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3253 { 3254 struct resource *res = &b->busn_res; 3255 struct resource old_res = *res; 3256 resource_size_t size; 3257 int ret; 3258 3259 if (res->start > bus_max) 3260 return -EINVAL; 3261 3262 size = bus_max - res->start + 1; 3263 ret = adjust_resource(res, res->start, size); 3264 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3265 &old_res, ret ? "can not be" : "is", bus_max); 3266 3267 if (!ret && !res->parent) 3268 pci_bus_insert_busn_res(b, res->start, res->end); 3269 3270 return ret; 3271 } 3272 3273 void pci_bus_release_busn_res(struct pci_bus *b) 3274 { 3275 struct resource *res = &b->busn_res; 3276 int ret; 3277 3278 if (!res->flags || !res->parent) 3279 return; 3280 3281 ret = release_resource(res); 3282 dev_info(&b->dev, "busn_res: %pR %s released\n", 3283 res, ret ? "can not be" : "is"); 3284 } 3285 3286 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3287 { 3288 struct resource_entry *window; 3289 bool found = false; 3290 struct pci_bus *b; 3291 int max, bus, ret; 3292 3293 if (!bridge) 3294 return -EINVAL; 3295 3296 resource_list_for_each_entry(window, &bridge->windows) 3297 if (window->res->flags & IORESOURCE_BUS) { 3298 found = true; 3299 break; 3300 } 3301 3302 ret = pci_register_host_bridge(bridge); 3303 if (ret < 0) 3304 return ret; 3305 3306 b = bridge->bus; 3307 bus = bridge->busnr; 3308 3309 if (!found) { 3310 dev_info(&b->dev, 3311 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3312 bus); 3313 pci_bus_insert_busn_res(b, bus, 255); 3314 } 3315 3316 max = pci_scan_child_bus(b); 3317 3318 if (!found) 3319 pci_bus_update_busn_res_end(b, max); 3320 3321 return 0; 3322 } 3323 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3324 3325 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3326 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3327 { 3328 struct resource_entry *window; 3329 bool found = false; 3330 struct pci_bus *b; 3331 int max; 3332 3333 resource_list_for_each_entry(window, resources) 3334 if (window->res->flags & IORESOURCE_BUS) { 3335 found = true; 3336 break; 3337 } 3338 3339 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3340 if (!b) 3341 return NULL; 3342 3343 if (!found) { 3344 dev_info(&b->dev, 3345 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3346 bus); 3347 pci_bus_insert_busn_res(b, bus, 255); 3348 } 3349 3350 max = pci_scan_child_bus(b); 3351 3352 if (!found) 3353 pci_bus_update_busn_res_end(b, max); 3354 3355 return b; 3356 } 3357 EXPORT_SYMBOL(pci_scan_root_bus); 3358 3359 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3360 void *sysdata) 3361 { 3362 LIST_HEAD(resources); 3363 struct pci_bus *b; 3364 3365 pci_add_resource(&resources, &ioport_resource); 3366 pci_add_resource(&resources, &iomem_resource); 3367 pci_add_resource(&resources, &busn_resource); 3368 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3369 if (b) { 3370 pci_scan_child_bus(b); 3371 } else { 3372 pci_free_resource_list(&resources); 3373 } 3374 return b; 3375 } 3376 EXPORT_SYMBOL(pci_scan_bus); 3377 3378 /** 3379 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3380 * @bridge: PCI bridge for the bus to scan 3381 * 3382 * Scan a PCI bus and child buses for new devices, add them, 3383 * and enable them, resizing bridge mmio/io resource if necessary 3384 * and possible. The caller must ensure the child devices are already 3385 * removed for resizing to occur. 3386 * 3387 * Returns the max number of subordinate bus discovered. 3388 */ 3389 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3390 { 3391 unsigned int max; 3392 struct pci_bus *bus = bridge->subordinate; 3393 3394 max = pci_scan_child_bus(bus); 3395 3396 pci_assign_unassigned_bridge_resources(bridge); 3397 3398 pci_bus_add_devices(bus); 3399 3400 return max; 3401 } 3402 3403 /** 3404 * pci_rescan_bus - Scan a PCI bus for devices 3405 * @bus: PCI bus to scan 3406 * 3407 * Scan a PCI bus and child buses for new devices, add them, 3408 * and enable them. 3409 * 3410 * Returns the max number of subordinate bus discovered. 3411 */ 3412 unsigned int pci_rescan_bus(struct pci_bus *bus) 3413 { 3414 unsigned int max; 3415 3416 max = pci_scan_child_bus(bus); 3417 pci_assign_unassigned_bus_resources(bus); 3418 pci_bus_add_devices(bus); 3419 3420 return max; 3421 } 3422 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3423 3424 /* 3425 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3426 * routines should always be executed under this mutex. 3427 */ 3428 static DEFINE_MUTEX(pci_rescan_remove_lock); 3429 3430 void pci_lock_rescan_remove(void) 3431 { 3432 mutex_lock(&pci_rescan_remove_lock); 3433 } 3434 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3435 3436 void pci_unlock_rescan_remove(void) 3437 { 3438 mutex_unlock(&pci_rescan_remove_lock); 3439 } 3440 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3441 3442 static int __init pci_sort_bf_cmp(const struct device *d_a, 3443 const struct device *d_b) 3444 { 3445 const struct pci_dev *a = to_pci_dev(d_a); 3446 const struct pci_dev *b = to_pci_dev(d_b); 3447 3448 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3449 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3450 3451 if (a->bus->number < b->bus->number) return -1; 3452 else if (a->bus->number > b->bus->number) return 1; 3453 3454 if (a->devfn < b->devfn) return -1; 3455 else if (a->devfn > b->devfn) return 1; 3456 3457 return 0; 3458 } 3459 3460 void __init pci_sort_breadthfirst(void) 3461 { 3462 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3463 } 3464 3465 int pci_hp_add_bridge(struct pci_dev *dev) 3466 { 3467 struct pci_bus *parent = dev->bus; 3468 int busnr, start = parent->busn_res.start; 3469 unsigned int available_buses = 0; 3470 int end = parent->busn_res.end; 3471 3472 for (busnr = start; busnr <= end; busnr++) { 3473 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3474 break; 3475 } 3476 if (busnr-- > end) { 3477 pci_err(dev, "No bus number available for hot-added bridge\n"); 3478 return -1; 3479 } 3480 3481 /* Scan bridges that are already configured */ 3482 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3483 3484 /* 3485 * Distribute the available bus numbers between hotplug-capable 3486 * bridges to make extending the chain later possible. 3487 */ 3488 available_buses = end - busnr; 3489 3490 /* Scan bridges that need to be reconfigured */ 3491 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3492 3493 if (!dev->subordinate) 3494 return -1; 3495 3496 return 0; 3497 } 3498 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3499