1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_device.h> 12 #include <linux/of_pci.h> 13 #include <linux/pci_hotplug.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/cpumask.h> 17 #include <linux/aer.h> 18 #include <linux/acpi.h> 19 #include <linux/hypervisor.h> 20 #include <linux/irqdomain.h> 21 #include <linux/pm_runtime.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * __pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 185 186 /* No printks while decoding is disabled! */ 187 if (!dev->mmio_always_on) { 188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 190 pci_write_config_word(dev, PCI_COMMAND, 191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 192 } 193 } 194 195 res->name = pci_name(dev); 196 197 pci_read_config_dword(dev, pos, &l); 198 pci_write_config_dword(dev, pos, l | mask); 199 pci_read_config_dword(dev, pos, &sz); 200 pci_write_config_dword(dev, pos, l); 201 202 /* 203 * All bits set in sz means the device isn't working properly. 204 * If the BAR isn't implemented, all bits must be 0. If it's a 205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 206 * 1 must be clear. 207 */ 208 if (sz == 0xffffffff) 209 sz = 0; 210 211 /* 212 * I don't know how l can have all bits set. Copied from old code. 213 * Maybe it fixes a bug on some ancient platform. 214 */ 215 if (l == 0xffffffff) 216 l = 0; 217 218 if (type == pci_bar_unknown) { 219 res->flags = decode_bar(dev, l); 220 res->flags |= IORESOURCE_SIZEALIGN; 221 if (res->flags & IORESOURCE_IO) { 222 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 225 } else { 226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 229 } 230 } else { 231 if (l & PCI_ROM_ADDRESS_ENABLE) 232 res->flags |= IORESOURCE_ROM_ENABLE; 233 l64 = l & PCI_ROM_ADDRESS_MASK; 234 sz64 = sz & PCI_ROM_ADDRESS_MASK; 235 mask64 = PCI_ROM_ADDRESS_MASK; 236 } 237 238 if (res->flags & IORESOURCE_MEM_64) { 239 pci_read_config_dword(dev, pos + 4, &l); 240 pci_write_config_dword(dev, pos + 4, ~0); 241 pci_read_config_dword(dev, pos + 4, &sz); 242 pci_write_config_dword(dev, pos + 4, l); 243 244 l64 |= ((u64)l << 32); 245 sz64 |= ((u64)sz << 32); 246 mask64 |= ((u64)~0 << 32); 247 } 248 249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 251 252 if (!sz64) 253 goto fail; 254 255 sz64 = pci_size(l64, sz64, mask64); 256 if (!sz64) { 257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 258 pos); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 269 pos, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 279 pos, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 306 pos, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_windows(struct pci_dev *bridge) 348 { 349 u16 io; 350 u32 pmem, tmp; 351 352 pci_read_config_word(bridge, PCI_IO_BASE, &io); 353 if (!io) { 354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 355 pci_read_config_word(bridge, PCI_IO_BASE, &io); 356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 357 } 358 if (io) 359 bridge->io_window = 1; 360 361 /* 362 * DECchip 21050 pass 2 errata: the bridge may miss an address 363 * disconnect boundary by one PCI data phase. Workaround: do not 364 * use prefetching on this device. 365 */ 366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 367 return; 368 369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 370 if (!pmem) { 371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 372 0xffe0fff0); 373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 375 } 376 if (!pmem) 377 return; 378 379 bridge->pref_window = 1; 380 381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 382 383 /* 384 * Bridge claims to have a 64-bit prefetchable memory 385 * window; verify that the upper bits are actually 386 * writable. 387 */ 388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 390 0xffffffff); 391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 393 if (tmp) 394 bridge->pref_64_window = 1; 395 } 396 } 397 398 static void pci_read_bridge_io(struct pci_bus *child) 399 { 400 struct pci_dev *dev = child->self; 401 u8 io_base_lo, io_limit_lo; 402 unsigned long io_mask, io_granularity, base, limit; 403 struct pci_bus_region region; 404 struct resource *res; 405 406 io_mask = PCI_IO_RANGE_MASK; 407 io_granularity = 0x1000; 408 if (dev->io_window_1k) { 409 /* Support 1K I/O space granularity */ 410 io_mask = PCI_IO_1K_RANGE_MASK; 411 io_granularity = 0x400; 412 } 413 414 res = child->resource[0]; 415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 417 base = (io_base_lo & io_mask) << 8; 418 limit = (io_limit_lo & io_mask) << 8; 419 420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 421 u16 io_base_hi, io_limit_hi; 422 423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 425 base |= ((unsigned long) io_base_hi << 16); 426 limit |= ((unsigned long) io_limit_hi << 16); 427 } 428 429 if (base <= limit) { 430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 431 region.start = base; 432 region.end = limit + io_granularity - 1; 433 pcibios_bus_to_resource(dev->bus, res, ®ion); 434 pci_info(dev, " bridge window %pR\n", res); 435 } 436 } 437 438 static void pci_read_bridge_mmio(struct pci_bus *child) 439 { 440 struct pci_dev *dev = child->self; 441 u16 mem_base_lo, mem_limit_lo; 442 unsigned long base, limit; 443 struct pci_bus_region region; 444 struct resource *res; 445 446 res = child->resource[1]; 447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 if (base <= limit) { 452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 453 region.start = base; 454 region.end = limit + 0xfffff; 455 pcibios_bus_to_resource(dev->bus, res, ®ion); 456 pci_info(dev, " bridge window %pR\n", res); 457 } 458 } 459 460 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 461 { 462 struct pci_dev *dev = child->self; 463 u16 mem_base_lo, mem_limit_lo; 464 u64 base64, limit64; 465 pci_bus_addr_t base, limit; 466 struct pci_bus_region region; 467 struct resource *res; 468 469 res = child->resource[2]; 470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 474 475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 476 u32 mem_base_hi, mem_limit_hi; 477 478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 480 481 /* 482 * Some bridges set the base > limit by default, and some 483 * (broken) BIOSes do not initialize them. If we find 484 * this, just assume they are not being used. 485 */ 486 if (mem_base_hi <= mem_limit_hi) { 487 base64 |= (u64) mem_base_hi << 32; 488 limit64 |= (u64) mem_limit_hi << 32; 489 } 490 } 491 492 base = (pci_bus_addr_t) base64; 493 limit = (pci_bus_addr_t) limit64; 494 495 if (base != base64) { 496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 497 (unsigned long long) base64); 498 return; 499 } 500 501 if (base <= limit) { 502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 503 IORESOURCE_MEM | IORESOURCE_PREFETCH; 504 if (res->flags & PCI_PREF_RANGE_TYPE_64) 505 res->flags |= IORESOURCE_MEM_64; 506 region.start = base; 507 region.end = limit + 0xfffff; 508 pcibios_bus_to_resource(dev->bus, res, ®ion); 509 pci_info(dev, " bridge window %pR\n", res); 510 } 511 } 512 513 void pci_read_bridge_bases(struct pci_bus *child) 514 { 515 struct pci_dev *dev = child->self; 516 struct resource *res; 517 int i; 518 519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 520 return; 521 522 pci_info(dev, "PCI bridge to %pR%s\n", 523 &child->busn_res, 524 dev->transparent ? " (subtractive decode)" : ""); 525 526 pci_bus_remove_resources(child); 527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 529 530 pci_read_bridge_io(child); 531 pci_read_bridge_mmio(child); 532 pci_read_bridge_mmio_pref(child); 533 534 if (dev->transparent) { 535 pci_bus_for_each_resource(child->parent, res, i) { 536 if (res && res->flags) { 537 pci_bus_add_resource(child, res, 538 PCI_SUBTRACTIVE_DECODE); 539 pci_info(dev, " bridge window %pR (subtractive decode)\n", 540 res); 541 } 542 } 543 } 544 } 545 546 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 547 { 548 struct pci_bus *b; 549 550 b = kzalloc(sizeof(*b), GFP_KERNEL); 551 if (!b) 552 return NULL; 553 554 INIT_LIST_HEAD(&b->node); 555 INIT_LIST_HEAD(&b->children); 556 INIT_LIST_HEAD(&b->devices); 557 INIT_LIST_HEAD(&b->slots); 558 INIT_LIST_HEAD(&b->resources); 559 b->max_bus_speed = PCI_SPEED_UNKNOWN; 560 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 561 #ifdef CONFIG_PCI_DOMAINS_GENERIC 562 if (parent) 563 b->domain_nr = parent->domain_nr; 564 #endif 565 return b; 566 } 567 568 static void pci_release_host_bridge_dev(struct device *dev) 569 { 570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 571 572 if (bridge->release_fn) 573 bridge->release_fn(bridge); 574 575 pci_free_resource_list(&bridge->windows); 576 pci_free_resource_list(&bridge->dma_ranges); 577 kfree(bridge); 578 } 579 580 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 581 { 582 INIT_LIST_HEAD(&bridge->windows); 583 INIT_LIST_HEAD(&bridge->dma_ranges); 584 585 /* 586 * We assume we can manage these PCIe features. Some systems may 587 * reserve these for use by the platform itself, e.g., an ACPI BIOS 588 * may implement its own AER handling and use _OSC to prevent the 589 * OS from interfering. 590 */ 591 bridge->native_aer = 1; 592 bridge->native_pcie_hotplug = 1; 593 bridge->native_shpc_hotplug = 1; 594 bridge->native_pme = 1; 595 bridge->native_ltr = 1; 596 bridge->native_dpc = 1; 597 598 device_initialize(&bridge->dev); 599 } 600 601 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 602 { 603 struct pci_host_bridge *bridge; 604 605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 606 if (!bridge) 607 return NULL; 608 609 pci_init_host_bridge(bridge); 610 bridge->dev.release = pci_release_host_bridge_dev; 611 612 return bridge; 613 } 614 EXPORT_SYMBOL(pci_alloc_host_bridge); 615 616 static void devm_pci_alloc_host_bridge_release(void *data) 617 { 618 pci_free_host_bridge(data); 619 } 620 621 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 622 size_t priv) 623 { 624 int ret; 625 struct pci_host_bridge *bridge; 626 627 bridge = pci_alloc_host_bridge(priv); 628 if (!bridge) 629 return NULL; 630 631 bridge->dev.parent = dev; 632 633 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 634 bridge); 635 if (ret) 636 return NULL; 637 638 ret = devm_of_pci_bridge_init(dev, bridge); 639 if (ret) 640 return NULL; 641 642 return bridge; 643 } 644 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 645 646 void pci_free_host_bridge(struct pci_host_bridge *bridge) 647 { 648 put_device(&bridge->dev); 649 } 650 EXPORT_SYMBOL(pci_free_host_bridge); 651 652 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 653 static const unsigned char pcix_bus_speed[] = { 654 PCI_SPEED_UNKNOWN, /* 0 */ 655 PCI_SPEED_66MHz_PCIX, /* 1 */ 656 PCI_SPEED_100MHz_PCIX, /* 2 */ 657 PCI_SPEED_133MHz_PCIX, /* 3 */ 658 PCI_SPEED_UNKNOWN, /* 4 */ 659 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 660 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 661 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 662 PCI_SPEED_UNKNOWN, /* 8 */ 663 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 664 PCI_SPEED_100MHz_PCIX_266, /* A */ 665 PCI_SPEED_133MHz_PCIX_266, /* B */ 666 PCI_SPEED_UNKNOWN, /* C */ 667 PCI_SPEED_66MHz_PCIX_533, /* D */ 668 PCI_SPEED_100MHz_PCIX_533, /* E */ 669 PCI_SPEED_133MHz_PCIX_533 /* F */ 670 }; 671 672 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 673 const unsigned char pcie_link_speed[] = { 674 PCI_SPEED_UNKNOWN, /* 0 */ 675 PCIE_SPEED_2_5GT, /* 1 */ 676 PCIE_SPEED_5_0GT, /* 2 */ 677 PCIE_SPEED_8_0GT, /* 3 */ 678 PCIE_SPEED_16_0GT, /* 4 */ 679 PCIE_SPEED_32_0GT, /* 5 */ 680 PCIE_SPEED_64_0GT, /* 6 */ 681 PCI_SPEED_UNKNOWN, /* 7 */ 682 PCI_SPEED_UNKNOWN, /* 8 */ 683 PCI_SPEED_UNKNOWN, /* 9 */ 684 PCI_SPEED_UNKNOWN, /* A */ 685 PCI_SPEED_UNKNOWN, /* B */ 686 PCI_SPEED_UNKNOWN, /* C */ 687 PCI_SPEED_UNKNOWN, /* D */ 688 PCI_SPEED_UNKNOWN, /* E */ 689 PCI_SPEED_UNKNOWN /* F */ 690 }; 691 EXPORT_SYMBOL_GPL(pcie_link_speed); 692 693 const char *pci_speed_string(enum pci_bus_speed speed) 694 { 695 /* Indexed by the pci_bus_speed enum */ 696 static const char *speed_strings[] = { 697 "33 MHz PCI", /* 0x00 */ 698 "66 MHz PCI", /* 0x01 */ 699 "66 MHz PCI-X", /* 0x02 */ 700 "100 MHz PCI-X", /* 0x03 */ 701 "133 MHz PCI-X", /* 0x04 */ 702 NULL, /* 0x05 */ 703 NULL, /* 0x06 */ 704 NULL, /* 0x07 */ 705 NULL, /* 0x08 */ 706 "66 MHz PCI-X 266", /* 0x09 */ 707 "100 MHz PCI-X 266", /* 0x0a */ 708 "133 MHz PCI-X 266", /* 0x0b */ 709 "Unknown AGP", /* 0x0c */ 710 "1x AGP", /* 0x0d */ 711 "2x AGP", /* 0x0e */ 712 "4x AGP", /* 0x0f */ 713 "8x AGP", /* 0x10 */ 714 "66 MHz PCI-X 533", /* 0x11 */ 715 "100 MHz PCI-X 533", /* 0x12 */ 716 "133 MHz PCI-X 533", /* 0x13 */ 717 "2.5 GT/s PCIe", /* 0x14 */ 718 "5.0 GT/s PCIe", /* 0x15 */ 719 "8.0 GT/s PCIe", /* 0x16 */ 720 "16.0 GT/s PCIe", /* 0x17 */ 721 "32.0 GT/s PCIe", /* 0x18 */ 722 "64.0 GT/s PCIe", /* 0x19 */ 723 }; 724 725 if (speed < ARRAY_SIZE(speed_strings)) 726 return speed_strings[speed]; 727 return "Unknown"; 728 } 729 EXPORT_SYMBOL_GPL(pci_speed_string); 730 731 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 732 { 733 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 734 } 735 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 736 737 static unsigned char agp_speeds[] = { 738 AGP_UNKNOWN, 739 AGP_1X, 740 AGP_2X, 741 AGP_4X, 742 AGP_8X 743 }; 744 745 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 746 { 747 int index = 0; 748 749 if (agpstat & 4) 750 index = 3; 751 else if (agpstat & 2) 752 index = 2; 753 else if (agpstat & 1) 754 index = 1; 755 else 756 goto out; 757 758 if (agp3) { 759 index += 2; 760 if (index == 5) 761 index = 0; 762 } 763 764 out: 765 return agp_speeds[index]; 766 } 767 768 static void pci_set_bus_speed(struct pci_bus *bus) 769 { 770 struct pci_dev *bridge = bus->self; 771 int pos; 772 773 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 774 if (!pos) 775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 776 if (pos) { 777 u32 agpstat, agpcmd; 778 779 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 780 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 781 782 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 783 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 784 } 785 786 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 787 if (pos) { 788 u16 status; 789 enum pci_bus_speed max; 790 791 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 792 &status); 793 794 if (status & PCI_X_SSTATUS_533MHZ) { 795 max = PCI_SPEED_133MHz_PCIX_533; 796 } else if (status & PCI_X_SSTATUS_266MHZ) { 797 max = PCI_SPEED_133MHz_PCIX_266; 798 } else if (status & PCI_X_SSTATUS_133MHZ) { 799 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 800 max = PCI_SPEED_133MHz_PCIX_ECC; 801 else 802 max = PCI_SPEED_133MHz_PCIX; 803 } else { 804 max = PCI_SPEED_66MHz_PCIX; 805 } 806 807 bus->max_bus_speed = max; 808 bus->cur_bus_speed = pcix_bus_speed[ 809 (status & PCI_X_SSTATUS_FREQ) >> 6]; 810 811 return; 812 } 813 814 if (pci_is_pcie(bridge)) { 815 u32 linkcap; 816 u16 linksta; 817 818 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 819 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 820 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 821 822 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 823 pcie_update_link_speed(bus, linksta); 824 } 825 } 826 827 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 828 { 829 struct irq_domain *d; 830 831 /* 832 * Any firmware interface that can resolve the msi_domain 833 * should be called from here. 834 */ 835 d = pci_host_bridge_of_msi_domain(bus); 836 if (!d) 837 d = pci_host_bridge_acpi_msi_domain(bus); 838 839 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 840 /* 841 * If no IRQ domain was found via the OF tree, try looking it up 842 * directly through the fwnode_handle. 843 */ 844 if (!d) { 845 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 846 847 if (fwnode) 848 d = irq_find_matching_fwnode(fwnode, 849 DOMAIN_BUS_PCI_MSI); 850 } 851 #endif 852 853 return d; 854 } 855 856 static void pci_set_bus_msi_domain(struct pci_bus *bus) 857 { 858 struct irq_domain *d; 859 struct pci_bus *b; 860 861 /* 862 * The bus can be a root bus, a subordinate bus, or a virtual bus 863 * created by an SR-IOV device. Walk up to the first bridge device 864 * found or derive the domain from the host bridge. 865 */ 866 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 867 if (b->self) 868 d = dev_get_msi_domain(&b->self->dev); 869 } 870 871 if (!d) 872 d = pci_host_bridge_msi_domain(b); 873 874 dev_set_msi_domain(&bus->dev, d); 875 } 876 877 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 878 { 879 struct device *parent = bridge->dev.parent; 880 struct resource_entry *window, *n; 881 struct pci_bus *bus, *b; 882 resource_size_t offset; 883 LIST_HEAD(resources); 884 struct resource *res; 885 char addr[64], *fmt; 886 const char *name; 887 int err; 888 889 bus = pci_alloc_bus(NULL); 890 if (!bus) 891 return -ENOMEM; 892 893 bridge->bus = bus; 894 895 /* Temporarily move resources off the list */ 896 list_splice_init(&bridge->windows, &resources); 897 bus->sysdata = bridge->sysdata; 898 bus->ops = bridge->ops; 899 bus->number = bus->busn_res.start = bridge->busnr; 900 #ifdef CONFIG_PCI_DOMAINS_GENERIC 901 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 902 #endif 903 904 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 905 if (b) { 906 /* Ignore it if we already got here via a different bridge */ 907 dev_dbg(&b->dev, "bus already known\n"); 908 err = -EEXIST; 909 goto free; 910 } 911 912 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 913 bridge->busnr); 914 915 err = pcibios_root_bridge_prepare(bridge); 916 if (err) 917 goto free; 918 919 err = device_add(&bridge->dev); 920 if (err) { 921 put_device(&bridge->dev); 922 goto free; 923 } 924 bus->bridge = get_device(&bridge->dev); 925 device_enable_async_suspend(bus->bridge); 926 pci_set_bus_of_node(bus); 927 pci_set_bus_msi_domain(bus); 928 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev)) 929 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 930 931 if (!parent) 932 set_dev_node(bus->bridge, pcibus_to_node(bus)); 933 934 bus->dev.class = &pcibus_class; 935 bus->dev.parent = bus->bridge; 936 937 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 938 name = dev_name(&bus->dev); 939 940 err = device_register(&bus->dev); 941 if (err) 942 goto unregister; 943 944 pcibios_add_bus(bus); 945 946 if (bus->ops->add_bus) { 947 err = bus->ops->add_bus(bus); 948 if (WARN_ON(err < 0)) 949 dev_err(&bus->dev, "failed to add bus: %d\n", err); 950 } 951 952 /* Create legacy_io and legacy_mem files for this bus */ 953 pci_create_legacy_files(bus); 954 955 if (parent) 956 dev_info(parent, "PCI host bridge to bus %s\n", name); 957 else 958 pr_info("PCI host bridge to bus %s\n", name); 959 960 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 961 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 962 963 /* Add initial resources to the bus */ 964 resource_list_for_each_entry_safe(window, n, &resources) { 965 list_move_tail(&window->node, &bridge->windows); 966 offset = window->offset; 967 res = window->res; 968 969 if (res->flags & IORESOURCE_BUS) 970 pci_bus_insert_busn_res(bus, bus->number, res->end); 971 else 972 pci_bus_add_resource(bus, res, 0); 973 974 if (offset) { 975 if (resource_type(res) == IORESOURCE_IO) 976 fmt = " (bus address [%#06llx-%#06llx])"; 977 else 978 fmt = " (bus address [%#010llx-%#010llx])"; 979 980 snprintf(addr, sizeof(addr), fmt, 981 (unsigned long long)(res->start - offset), 982 (unsigned long long)(res->end - offset)); 983 } else 984 addr[0] = '\0'; 985 986 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 987 } 988 989 down_write(&pci_bus_sem); 990 list_add_tail(&bus->node, &pci_root_buses); 991 up_write(&pci_bus_sem); 992 993 return 0; 994 995 unregister: 996 put_device(&bridge->dev); 997 device_del(&bridge->dev); 998 999 free: 1000 kfree(bus); 1001 return err; 1002 } 1003 1004 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1005 { 1006 int pos; 1007 u32 status; 1008 1009 /* 1010 * If extended config space isn't accessible on a bridge's primary 1011 * bus, we certainly can't access it on the secondary bus. 1012 */ 1013 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1014 return false; 1015 1016 /* 1017 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1018 * extended config space is accessible on the primary, it's also 1019 * accessible on the secondary. 1020 */ 1021 if (pci_is_pcie(bridge) && 1022 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1023 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1024 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1025 return true; 1026 1027 /* 1028 * For the other bridge types: 1029 * - PCI-to-PCI bridges 1030 * - PCIe-to-PCI/PCI-X forward bridges 1031 * - PCI/PCI-X-to-PCIe reverse bridges 1032 * extended config space on the secondary side is only accessible 1033 * if the bridge supports PCI-X Mode 2. 1034 */ 1035 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1036 if (!pos) 1037 return false; 1038 1039 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1040 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1041 } 1042 1043 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1044 struct pci_dev *bridge, int busnr) 1045 { 1046 struct pci_bus *child; 1047 struct pci_host_bridge *host; 1048 int i; 1049 int ret; 1050 1051 /* Allocate a new bus and inherit stuff from the parent */ 1052 child = pci_alloc_bus(parent); 1053 if (!child) 1054 return NULL; 1055 1056 child->parent = parent; 1057 child->sysdata = parent->sysdata; 1058 child->bus_flags = parent->bus_flags; 1059 1060 host = pci_find_host_bridge(parent); 1061 if (host->child_ops) 1062 child->ops = host->child_ops; 1063 else 1064 child->ops = parent->ops; 1065 1066 /* 1067 * Initialize some portions of the bus device, but don't register 1068 * it now as the parent is not properly set up yet. 1069 */ 1070 child->dev.class = &pcibus_class; 1071 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1072 1073 /* Set up the primary, secondary and subordinate bus numbers */ 1074 child->number = child->busn_res.start = busnr; 1075 child->primary = parent->busn_res.start; 1076 child->busn_res.end = 0xff; 1077 1078 if (!bridge) { 1079 child->dev.parent = parent->bridge; 1080 goto add_dev; 1081 } 1082 1083 child->self = bridge; 1084 child->bridge = get_device(&bridge->dev); 1085 child->dev.parent = child->bridge; 1086 pci_set_bus_of_node(child); 1087 pci_set_bus_speed(child); 1088 1089 /* 1090 * Check whether extended config space is accessible on the child 1091 * bus. Note that we currently assume it is always accessible on 1092 * the root bus. 1093 */ 1094 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1095 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1096 pci_info(child, "extended config space not accessible\n"); 1097 } 1098 1099 /* Set up default resource pointers and names */ 1100 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1101 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1102 child->resource[i]->name = child->name; 1103 } 1104 bridge->subordinate = child; 1105 1106 add_dev: 1107 pci_set_bus_msi_domain(child); 1108 ret = device_register(&child->dev); 1109 WARN_ON(ret < 0); 1110 1111 pcibios_add_bus(child); 1112 1113 if (child->ops->add_bus) { 1114 ret = child->ops->add_bus(child); 1115 if (WARN_ON(ret < 0)) 1116 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1117 } 1118 1119 /* Create legacy_io and legacy_mem files for this bus */ 1120 pci_create_legacy_files(child); 1121 1122 return child; 1123 } 1124 1125 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1126 int busnr) 1127 { 1128 struct pci_bus *child; 1129 1130 child = pci_alloc_child_bus(parent, dev, busnr); 1131 if (child) { 1132 down_write(&pci_bus_sem); 1133 list_add_tail(&child->node, &parent->children); 1134 up_write(&pci_bus_sem); 1135 } 1136 return child; 1137 } 1138 EXPORT_SYMBOL(pci_add_new_bus); 1139 1140 static void pci_enable_crs(struct pci_dev *pdev) 1141 { 1142 u16 root_cap = 0; 1143 1144 /* Enable CRS Software Visibility if supported */ 1145 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1146 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1147 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1148 PCI_EXP_RTCTL_CRSSVE); 1149 } 1150 1151 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1152 unsigned int available_buses); 1153 /** 1154 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1155 * numbers from EA capability. 1156 * @dev: Bridge 1157 * @sec: updated with secondary bus number from EA 1158 * @sub: updated with subordinate bus number from EA 1159 * 1160 * If @dev is a bridge with EA capability that specifies valid secondary 1161 * and subordinate bus numbers, return true with the bus numbers in @sec 1162 * and @sub. Otherwise return false. 1163 */ 1164 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1165 { 1166 int ea, offset; 1167 u32 dw; 1168 u8 ea_sec, ea_sub; 1169 1170 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1171 return false; 1172 1173 /* find PCI EA capability in list */ 1174 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1175 if (!ea) 1176 return false; 1177 1178 offset = ea + PCI_EA_FIRST_ENT; 1179 pci_read_config_dword(dev, offset, &dw); 1180 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1181 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1182 if (ea_sec == 0 || ea_sub < ea_sec) 1183 return false; 1184 1185 *sec = ea_sec; 1186 *sub = ea_sub; 1187 return true; 1188 } 1189 1190 /* 1191 * pci_scan_bridge_extend() - Scan buses behind a bridge 1192 * @bus: Parent bus the bridge is on 1193 * @dev: Bridge itself 1194 * @max: Starting subordinate number of buses behind this bridge 1195 * @available_buses: Total number of buses available for this bridge and 1196 * the devices below. After the minimal bus space has 1197 * been allocated the remaining buses will be 1198 * distributed equally between hotplug-capable bridges. 1199 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1200 * that need to be reconfigured. 1201 * 1202 * If it's a bridge, configure it and scan the bus behind it. 1203 * For CardBus bridges, we don't scan behind as the devices will 1204 * be handled by the bridge driver itself. 1205 * 1206 * We need to process bridges in two passes -- first we scan those 1207 * already configured by the BIOS and after we are done with all of 1208 * them, we proceed to assigning numbers to the remaining buses in 1209 * order to avoid overlaps between old and new bus numbers. 1210 * 1211 * Return: New subordinate number covering all buses behind this bridge. 1212 */ 1213 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1214 int max, unsigned int available_buses, 1215 int pass) 1216 { 1217 struct pci_bus *child; 1218 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1219 u32 buses, i, j = 0; 1220 u16 bctl; 1221 u8 primary, secondary, subordinate; 1222 int broken = 0; 1223 bool fixed_buses; 1224 u8 fixed_sec, fixed_sub; 1225 int next_busnr; 1226 1227 /* 1228 * Make sure the bridge is powered on to be able to access config 1229 * space of devices below it. 1230 */ 1231 pm_runtime_get_sync(&dev->dev); 1232 1233 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1234 primary = buses & 0xFF; 1235 secondary = (buses >> 8) & 0xFF; 1236 subordinate = (buses >> 16) & 0xFF; 1237 1238 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1239 secondary, subordinate, pass); 1240 1241 if (!primary && (primary != bus->number) && secondary && subordinate) { 1242 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1243 primary = bus->number; 1244 } 1245 1246 /* Check if setup is sensible at all */ 1247 if (!pass && 1248 (primary != bus->number || secondary <= bus->number || 1249 secondary > subordinate)) { 1250 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1251 secondary, subordinate); 1252 broken = 1; 1253 } 1254 1255 /* 1256 * Disable Master-Abort Mode during probing to avoid reporting of 1257 * bus errors in some architectures. 1258 */ 1259 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1260 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1261 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1262 1263 pci_enable_crs(dev); 1264 1265 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1266 !is_cardbus && !broken) { 1267 unsigned int cmax; 1268 1269 /* 1270 * Bus already configured by firmware, process it in the 1271 * first pass and just note the configuration. 1272 */ 1273 if (pass) 1274 goto out; 1275 1276 /* 1277 * The bus might already exist for two reasons: Either we 1278 * are rescanning the bus or the bus is reachable through 1279 * more than one bridge. The second case can happen with 1280 * the i450NX chipset. 1281 */ 1282 child = pci_find_bus(pci_domain_nr(bus), secondary); 1283 if (!child) { 1284 child = pci_add_new_bus(bus, dev, secondary); 1285 if (!child) 1286 goto out; 1287 child->primary = primary; 1288 pci_bus_insert_busn_res(child, secondary, subordinate); 1289 child->bridge_ctl = bctl; 1290 } 1291 1292 cmax = pci_scan_child_bus(child); 1293 if (cmax > subordinate) 1294 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1295 subordinate, cmax); 1296 1297 /* Subordinate should equal child->busn_res.end */ 1298 if (subordinate > max) 1299 max = subordinate; 1300 } else { 1301 1302 /* 1303 * We need to assign a number to this bus which we always 1304 * do in the second pass. 1305 */ 1306 if (!pass) { 1307 if (pcibios_assign_all_busses() || broken || is_cardbus) 1308 1309 /* 1310 * Temporarily disable forwarding of the 1311 * configuration cycles on all bridges in 1312 * this bus segment to avoid possible 1313 * conflicts in the second pass between two 1314 * bridges programmed with overlapping bus 1315 * ranges. 1316 */ 1317 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1318 buses & ~0xffffff); 1319 goto out; 1320 } 1321 1322 /* Clear errors */ 1323 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1324 1325 /* Read bus numbers from EA Capability (if present) */ 1326 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1327 if (fixed_buses) 1328 next_busnr = fixed_sec; 1329 else 1330 next_busnr = max + 1; 1331 1332 /* 1333 * Prevent assigning a bus number that already exists. 1334 * This can happen when a bridge is hot-plugged, so in this 1335 * case we only re-scan this bus. 1336 */ 1337 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1338 if (!child) { 1339 child = pci_add_new_bus(bus, dev, next_busnr); 1340 if (!child) 1341 goto out; 1342 pci_bus_insert_busn_res(child, next_busnr, 1343 bus->busn_res.end); 1344 } 1345 max++; 1346 if (available_buses) 1347 available_buses--; 1348 1349 buses = (buses & 0xff000000) 1350 | ((unsigned int)(child->primary) << 0) 1351 | ((unsigned int)(child->busn_res.start) << 8) 1352 | ((unsigned int)(child->busn_res.end) << 16); 1353 1354 /* 1355 * yenta.c forces a secondary latency timer of 176. 1356 * Copy that behaviour here. 1357 */ 1358 if (is_cardbus) { 1359 buses &= ~0xff000000; 1360 buses |= CARDBUS_LATENCY_TIMER << 24; 1361 } 1362 1363 /* We need to blast all three values with a single write */ 1364 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1365 1366 if (!is_cardbus) { 1367 child->bridge_ctl = bctl; 1368 max = pci_scan_child_bus_extend(child, available_buses); 1369 } else { 1370 1371 /* 1372 * For CardBus bridges, we leave 4 bus numbers as 1373 * cards with a PCI-to-PCI bridge can be inserted 1374 * later. 1375 */ 1376 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1377 struct pci_bus *parent = bus; 1378 if (pci_find_bus(pci_domain_nr(bus), 1379 max+i+1)) 1380 break; 1381 while (parent->parent) { 1382 if ((!pcibios_assign_all_busses()) && 1383 (parent->busn_res.end > max) && 1384 (parent->busn_res.end <= max+i)) { 1385 j = 1; 1386 } 1387 parent = parent->parent; 1388 } 1389 if (j) { 1390 1391 /* 1392 * Often, there are two CardBus 1393 * bridges -- try to leave one 1394 * valid bus number for each one. 1395 */ 1396 i /= 2; 1397 break; 1398 } 1399 } 1400 max += i; 1401 } 1402 1403 /* 1404 * Set subordinate bus number to its real value. 1405 * If fixed subordinate bus number exists from EA 1406 * capability then use it. 1407 */ 1408 if (fixed_buses) 1409 max = fixed_sub; 1410 pci_bus_update_busn_res_end(child, max); 1411 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1412 } 1413 1414 sprintf(child->name, 1415 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1416 pci_domain_nr(bus), child->number); 1417 1418 /* Check that all devices are accessible */ 1419 while (bus->parent) { 1420 if ((child->busn_res.end > bus->busn_res.end) || 1421 (child->number > bus->busn_res.end) || 1422 (child->number < bus->number) || 1423 (child->busn_res.end < bus->number)) { 1424 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1425 &child->busn_res); 1426 break; 1427 } 1428 bus = bus->parent; 1429 } 1430 1431 out: 1432 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1433 1434 pm_runtime_put(&dev->dev); 1435 1436 return max; 1437 } 1438 1439 /* 1440 * pci_scan_bridge() - Scan buses behind a bridge 1441 * @bus: Parent bus the bridge is on 1442 * @dev: Bridge itself 1443 * @max: Starting subordinate number of buses behind this bridge 1444 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1445 * that need to be reconfigured. 1446 * 1447 * If it's a bridge, configure it and scan the bus behind it. 1448 * For CardBus bridges, we don't scan behind as the devices will 1449 * be handled by the bridge driver itself. 1450 * 1451 * We need to process bridges in two passes -- first we scan those 1452 * already configured by the BIOS and after we are done with all of 1453 * them, we proceed to assigning numbers to the remaining buses in 1454 * order to avoid overlaps between old and new bus numbers. 1455 * 1456 * Return: New subordinate number covering all buses behind this bridge. 1457 */ 1458 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1459 { 1460 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1461 } 1462 EXPORT_SYMBOL(pci_scan_bridge); 1463 1464 /* 1465 * Read interrupt line and base address registers. 1466 * The architecture-dependent code can tweak these, of course. 1467 */ 1468 static void pci_read_irq(struct pci_dev *dev) 1469 { 1470 unsigned char irq; 1471 1472 /* VFs are not allowed to use INTx, so skip the config reads */ 1473 if (dev->is_virtfn) { 1474 dev->pin = 0; 1475 dev->irq = 0; 1476 return; 1477 } 1478 1479 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1480 dev->pin = irq; 1481 if (irq) 1482 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1483 dev->irq = irq; 1484 } 1485 1486 void set_pcie_port_type(struct pci_dev *pdev) 1487 { 1488 int pos; 1489 u16 reg16; 1490 int type; 1491 struct pci_dev *parent; 1492 1493 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1494 if (!pos) 1495 return; 1496 1497 pdev->pcie_cap = pos; 1498 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1499 pdev->pcie_flags_reg = reg16; 1500 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 1501 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1502 1503 parent = pci_upstream_bridge(pdev); 1504 if (!parent) 1505 return; 1506 1507 /* 1508 * Some systems do not identify their upstream/downstream ports 1509 * correctly so detect impossible configurations here and correct 1510 * the port type accordingly. 1511 */ 1512 type = pci_pcie_type(pdev); 1513 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1514 /* 1515 * If pdev claims to be downstream port but the parent 1516 * device is also downstream port assume pdev is actually 1517 * upstream port. 1518 */ 1519 if (pcie_downstream_port(parent)) { 1520 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1521 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1522 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1523 } 1524 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1525 /* 1526 * If pdev claims to be upstream port but the parent 1527 * device is also upstream port assume pdev is actually 1528 * downstream port. 1529 */ 1530 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1531 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1532 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1533 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1534 } 1535 } 1536 } 1537 1538 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1539 { 1540 u32 reg32; 1541 1542 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1543 if (reg32 & PCI_EXP_SLTCAP_HPC) 1544 pdev->is_hotplug_bridge = 1; 1545 } 1546 1547 static void set_pcie_thunderbolt(struct pci_dev *dev) 1548 { 1549 int vsec = 0; 1550 u32 header; 1551 1552 while ((vsec = pci_find_next_ext_capability(dev, vsec, 1553 PCI_EXT_CAP_ID_VNDR))) { 1554 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); 1555 1556 /* Is the device part of a Thunderbolt controller? */ 1557 if (dev->vendor == PCI_VENDOR_ID_INTEL && 1558 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { 1559 dev->is_thunderbolt = 1; 1560 return; 1561 } 1562 } 1563 } 1564 1565 static void set_pcie_untrusted(struct pci_dev *dev) 1566 { 1567 struct pci_dev *parent; 1568 1569 /* 1570 * If the upstream bridge is untrusted we treat this device 1571 * untrusted as well. 1572 */ 1573 parent = pci_upstream_bridge(dev); 1574 if (parent && (parent->untrusted || parent->external_facing)) 1575 dev->untrusted = true; 1576 } 1577 1578 /** 1579 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1580 * @dev: PCI device 1581 * 1582 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1583 * when forwarding a type1 configuration request the bridge must check that 1584 * the extended register address field is zero. The bridge is not permitted 1585 * to forward the transactions and must handle it as an Unsupported Request. 1586 * Some bridges do not follow this rule and simply drop the extended register 1587 * bits, resulting in the standard config space being aliased, every 256 1588 * bytes across the entire configuration space. Test for this condition by 1589 * comparing the first dword of each potential alias to the vendor/device ID. 1590 * Known offenders: 1591 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1592 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1593 */ 1594 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1595 { 1596 #ifdef CONFIG_PCI_QUIRKS 1597 int pos; 1598 u32 header, tmp; 1599 1600 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1601 1602 for (pos = PCI_CFG_SPACE_SIZE; 1603 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1604 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1605 || header != tmp) 1606 return false; 1607 } 1608 1609 return true; 1610 #else 1611 return false; 1612 #endif 1613 } 1614 1615 /** 1616 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1617 * @dev: PCI device 1618 * 1619 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1620 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1621 * access it. Maybe we don't have a way to generate extended config space 1622 * accesses, or the device is behind a reverse Express bridge. So we try 1623 * reading the dword at 0x100 which must either be 0 or a valid extended 1624 * capability header. 1625 */ 1626 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1627 { 1628 u32 status; 1629 int pos = PCI_CFG_SPACE_SIZE; 1630 1631 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1632 return PCI_CFG_SPACE_SIZE; 1633 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) 1634 return PCI_CFG_SPACE_SIZE; 1635 1636 return PCI_CFG_SPACE_EXP_SIZE; 1637 } 1638 1639 int pci_cfg_space_size(struct pci_dev *dev) 1640 { 1641 int pos; 1642 u32 status; 1643 u16 class; 1644 1645 #ifdef CONFIG_PCI_IOV 1646 /* 1647 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1648 * implement a PCIe capability and therefore must implement extended 1649 * config space. We can skip the NO_EXTCFG test below and the 1650 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1651 * the fact that the SR-IOV capability on the PF resides in extended 1652 * config space and must be accessible and non-aliased to have enabled 1653 * support for this VF. This is a micro performance optimization for 1654 * systems supporting many VFs. 1655 */ 1656 if (dev->is_virtfn) 1657 return PCI_CFG_SPACE_EXP_SIZE; 1658 #endif 1659 1660 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1661 return PCI_CFG_SPACE_SIZE; 1662 1663 class = dev->class >> 8; 1664 if (class == PCI_CLASS_BRIDGE_HOST) 1665 return pci_cfg_space_size_ext(dev); 1666 1667 if (pci_is_pcie(dev)) 1668 return pci_cfg_space_size_ext(dev); 1669 1670 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1671 if (!pos) 1672 return PCI_CFG_SPACE_SIZE; 1673 1674 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1675 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1676 return pci_cfg_space_size_ext(dev); 1677 1678 return PCI_CFG_SPACE_SIZE; 1679 } 1680 1681 static u32 pci_class(struct pci_dev *dev) 1682 { 1683 u32 class; 1684 1685 #ifdef CONFIG_PCI_IOV 1686 if (dev->is_virtfn) 1687 return dev->physfn->sriov->class; 1688 #endif 1689 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1690 return class; 1691 } 1692 1693 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1694 { 1695 #ifdef CONFIG_PCI_IOV 1696 if (dev->is_virtfn) { 1697 *vendor = dev->physfn->sriov->subsystem_vendor; 1698 *device = dev->physfn->sriov->subsystem_device; 1699 return; 1700 } 1701 #endif 1702 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1703 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1704 } 1705 1706 static u8 pci_hdr_type(struct pci_dev *dev) 1707 { 1708 u8 hdr_type; 1709 1710 #ifdef CONFIG_PCI_IOV 1711 if (dev->is_virtfn) 1712 return dev->physfn->sriov->hdr_type; 1713 #endif 1714 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1715 return hdr_type; 1716 } 1717 1718 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1719 1720 /** 1721 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1722 * @dev: PCI device 1723 * 1724 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1725 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1726 */ 1727 static int pci_intx_mask_broken(struct pci_dev *dev) 1728 { 1729 u16 orig, toggle, new; 1730 1731 pci_read_config_word(dev, PCI_COMMAND, &orig); 1732 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1733 pci_write_config_word(dev, PCI_COMMAND, toggle); 1734 pci_read_config_word(dev, PCI_COMMAND, &new); 1735 1736 pci_write_config_word(dev, PCI_COMMAND, orig); 1737 1738 /* 1739 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1740 * r2.3, so strictly speaking, a device is not *broken* if it's not 1741 * writable. But we'll live with the misnomer for now. 1742 */ 1743 if (new != toggle) 1744 return 1; 1745 return 0; 1746 } 1747 1748 static void early_dump_pci_device(struct pci_dev *pdev) 1749 { 1750 u32 value[256 / 4]; 1751 int i; 1752 1753 pci_info(pdev, "config space:\n"); 1754 1755 for (i = 0; i < 256; i += 4) 1756 pci_read_config_dword(pdev, i, &value[i / 4]); 1757 1758 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1759 value, 256, false); 1760 } 1761 1762 /** 1763 * pci_setup_device - Fill in class and map information of a device 1764 * @dev: the device structure to fill 1765 * 1766 * Initialize the device structure with information about the device's 1767 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1768 * Called at initialisation of the PCI subsystem and by CardBus services. 1769 * Returns 0 on success and negative if unknown type of device (not normal, 1770 * bridge or CardBus). 1771 */ 1772 int pci_setup_device(struct pci_dev *dev) 1773 { 1774 u32 class; 1775 u16 cmd; 1776 u8 hdr_type; 1777 int pos = 0; 1778 struct pci_bus_region region; 1779 struct resource *res; 1780 1781 hdr_type = pci_hdr_type(dev); 1782 1783 dev->sysdata = dev->bus->sysdata; 1784 dev->dev.parent = dev->bus->bridge; 1785 dev->dev.bus = &pci_bus_type; 1786 dev->hdr_type = hdr_type & 0x7f; 1787 dev->multifunction = !!(hdr_type & 0x80); 1788 dev->error_state = pci_channel_io_normal; 1789 set_pcie_port_type(dev); 1790 1791 pci_dev_assign_slot(dev); 1792 1793 /* 1794 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1795 * set this higher, assuming the system even supports it. 1796 */ 1797 dev->dma_mask = 0xffffffff; 1798 1799 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1800 dev->bus->number, PCI_SLOT(dev->devfn), 1801 PCI_FUNC(dev->devfn)); 1802 1803 class = pci_class(dev); 1804 1805 dev->revision = class & 0xff; 1806 dev->class = class >> 8; /* upper 3 bytes */ 1807 1808 if (pci_early_dump) 1809 early_dump_pci_device(dev); 1810 1811 /* Need to have dev->class ready */ 1812 dev->cfg_size = pci_cfg_space_size(dev); 1813 1814 /* Need to have dev->cfg_size ready */ 1815 set_pcie_thunderbolt(dev); 1816 1817 set_pcie_untrusted(dev); 1818 1819 /* "Unknown power state" */ 1820 dev->current_state = PCI_UNKNOWN; 1821 1822 /* Early fixups, before probing the BARs */ 1823 pci_fixup_device(pci_fixup_early, dev); 1824 1825 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1826 dev->vendor, dev->device, dev->hdr_type, dev->class); 1827 1828 /* Device class may be changed after fixup */ 1829 class = dev->class >> 8; 1830 1831 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1832 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1833 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1834 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1835 cmd &= ~PCI_COMMAND_IO; 1836 cmd &= ~PCI_COMMAND_MEMORY; 1837 pci_write_config_word(dev, PCI_COMMAND, cmd); 1838 } 1839 } 1840 1841 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1842 1843 switch (dev->hdr_type) { /* header type */ 1844 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1845 if (class == PCI_CLASS_BRIDGE_PCI) 1846 goto bad; 1847 pci_read_irq(dev); 1848 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1849 1850 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1851 1852 /* 1853 * Do the ugly legacy mode stuff here rather than broken chip 1854 * quirk code. Legacy mode ATA controllers have fixed 1855 * addresses. These are not always echoed in BAR0-3, and 1856 * BAR0-3 in a few cases contain junk! 1857 */ 1858 if (class == PCI_CLASS_STORAGE_IDE) { 1859 u8 progif; 1860 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1861 if ((progif & 1) == 0) { 1862 region.start = 0x1F0; 1863 region.end = 0x1F7; 1864 res = &dev->resource[0]; 1865 res->flags = LEGACY_IO_RESOURCE; 1866 pcibios_bus_to_resource(dev->bus, res, ®ion); 1867 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1868 res); 1869 region.start = 0x3F6; 1870 region.end = 0x3F6; 1871 res = &dev->resource[1]; 1872 res->flags = LEGACY_IO_RESOURCE; 1873 pcibios_bus_to_resource(dev->bus, res, ®ion); 1874 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1875 res); 1876 } 1877 if ((progif & 4) == 0) { 1878 region.start = 0x170; 1879 region.end = 0x177; 1880 res = &dev->resource[2]; 1881 res->flags = LEGACY_IO_RESOURCE; 1882 pcibios_bus_to_resource(dev->bus, res, ®ion); 1883 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1884 res); 1885 region.start = 0x376; 1886 region.end = 0x376; 1887 res = &dev->resource[3]; 1888 res->flags = LEGACY_IO_RESOURCE; 1889 pcibios_bus_to_resource(dev->bus, res, ®ion); 1890 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1891 res); 1892 } 1893 } 1894 break; 1895 1896 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1897 /* 1898 * The PCI-to-PCI bridge spec requires that subtractive 1899 * decoding (i.e. transparent) bridge must have programming 1900 * interface code of 0x01. 1901 */ 1902 pci_read_irq(dev); 1903 dev->transparent = ((dev->class & 0xff) == 1); 1904 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1905 pci_read_bridge_windows(dev); 1906 set_pcie_hotplug_bridge(dev); 1907 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1908 if (pos) { 1909 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1910 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1911 } 1912 break; 1913 1914 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1915 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1916 goto bad; 1917 pci_read_irq(dev); 1918 pci_read_bases(dev, 1, 0); 1919 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1920 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1921 break; 1922 1923 default: /* unknown header */ 1924 pci_err(dev, "unknown header type %02x, ignoring device\n", 1925 dev->hdr_type); 1926 return -EIO; 1927 1928 bad: 1929 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1930 dev->class, dev->hdr_type); 1931 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1932 } 1933 1934 /* We found a fine healthy device, go go go... */ 1935 return 0; 1936 } 1937 1938 static void pci_configure_mps(struct pci_dev *dev) 1939 { 1940 struct pci_dev *bridge = pci_upstream_bridge(dev); 1941 int mps, mpss, p_mps, rc; 1942 1943 if (!pci_is_pcie(dev)) 1944 return; 1945 1946 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 1947 if (dev->is_virtfn) 1948 return; 1949 1950 /* 1951 * For Root Complex Integrated Endpoints, program the maximum 1952 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 1953 */ 1954 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 1955 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 1956 mps = 128; 1957 else 1958 mps = 128 << dev->pcie_mpss; 1959 rc = pcie_set_mps(dev, mps); 1960 if (rc) { 1961 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1962 mps); 1963 } 1964 return; 1965 } 1966 1967 if (!bridge || !pci_is_pcie(bridge)) 1968 return; 1969 1970 mps = pcie_get_mps(dev); 1971 p_mps = pcie_get_mps(bridge); 1972 1973 if (mps == p_mps) 1974 return; 1975 1976 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 1977 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1978 mps, pci_name(bridge), p_mps); 1979 return; 1980 } 1981 1982 /* 1983 * Fancier MPS configuration is done later by 1984 * pcie_bus_configure_settings() 1985 */ 1986 if (pcie_bus_config != PCIE_BUS_DEFAULT) 1987 return; 1988 1989 mpss = 128 << dev->pcie_mpss; 1990 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 1991 pcie_set_mps(bridge, mpss); 1992 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 1993 mpss, p_mps, 128 << bridge->pcie_mpss); 1994 p_mps = pcie_get_mps(bridge); 1995 } 1996 1997 rc = pcie_set_mps(dev, p_mps); 1998 if (rc) { 1999 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2000 p_mps); 2001 return; 2002 } 2003 2004 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2005 p_mps, mps, mpss); 2006 } 2007 2008 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2009 { 2010 struct pci_host_bridge *host; 2011 u32 cap; 2012 u16 ctl; 2013 int ret; 2014 2015 if (!pci_is_pcie(dev)) 2016 return 0; 2017 2018 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2019 if (ret) 2020 return 0; 2021 2022 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2023 return 0; 2024 2025 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2026 if (ret) 2027 return 0; 2028 2029 host = pci_find_host_bridge(dev->bus); 2030 if (!host) 2031 return 0; 2032 2033 /* 2034 * If some device in the hierarchy doesn't handle Extended Tags 2035 * correctly, make sure they're disabled. 2036 */ 2037 if (host->no_ext_tags) { 2038 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2039 pci_info(dev, "disabling Extended Tags\n"); 2040 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2041 PCI_EXP_DEVCTL_EXT_TAG); 2042 } 2043 return 0; 2044 } 2045 2046 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2047 pci_info(dev, "enabling Extended Tags\n"); 2048 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2049 PCI_EXP_DEVCTL_EXT_TAG); 2050 } 2051 return 0; 2052 } 2053 2054 /** 2055 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2056 * @dev: PCI device to query 2057 * 2058 * Returns true if the device has enabled relaxed ordering attribute. 2059 */ 2060 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2061 { 2062 u16 v; 2063 2064 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2065 2066 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2067 } 2068 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2069 2070 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2071 { 2072 struct pci_dev *root; 2073 2074 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2075 if (dev->is_virtfn) 2076 return; 2077 2078 if (!pcie_relaxed_ordering_enabled(dev)) 2079 return; 2080 2081 /* 2082 * For now, we only deal with Relaxed Ordering issues with Root 2083 * Ports. Peer-to-Peer DMA is another can of worms. 2084 */ 2085 root = pcie_find_root_port(dev); 2086 if (!root) 2087 return; 2088 2089 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2090 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2091 PCI_EXP_DEVCTL_RELAX_EN); 2092 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2093 } 2094 } 2095 2096 static void pci_configure_ltr(struct pci_dev *dev) 2097 { 2098 #ifdef CONFIG_PCIEASPM 2099 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2100 struct pci_dev *bridge; 2101 u32 cap, ctl; 2102 2103 if (!pci_is_pcie(dev)) 2104 return; 2105 2106 /* Read L1 PM substate capabilities */ 2107 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 2108 2109 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2110 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2111 return; 2112 2113 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2114 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2115 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2116 dev->ltr_path = 1; 2117 return; 2118 } 2119 2120 bridge = pci_upstream_bridge(dev); 2121 if (bridge && bridge->ltr_path) 2122 dev->ltr_path = 1; 2123 2124 return; 2125 } 2126 2127 if (!host->native_ltr) 2128 return; 2129 2130 /* 2131 * Software must not enable LTR in an Endpoint unless the Root 2132 * Complex and all intermediate Switches indicate support for LTR. 2133 * PCIe r4.0, sec 6.18. 2134 */ 2135 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 2136 ((bridge = pci_upstream_bridge(dev)) && 2137 bridge->ltr_path)) { 2138 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2139 PCI_EXP_DEVCTL2_LTR_EN); 2140 dev->ltr_path = 1; 2141 } 2142 #endif 2143 } 2144 2145 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2146 { 2147 #ifdef CONFIG_PCI_PASID 2148 struct pci_dev *bridge; 2149 int pcie_type; 2150 u32 cap; 2151 2152 if (!pci_is_pcie(dev)) 2153 return; 2154 2155 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2156 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2157 return; 2158 2159 pcie_type = pci_pcie_type(dev); 2160 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2161 pcie_type == PCI_EXP_TYPE_RC_END) 2162 dev->eetlp_prefix_path = 1; 2163 else { 2164 bridge = pci_upstream_bridge(dev); 2165 if (bridge && bridge->eetlp_prefix_path) 2166 dev->eetlp_prefix_path = 1; 2167 } 2168 #endif 2169 } 2170 2171 static void pci_configure_serr(struct pci_dev *dev) 2172 { 2173 u16 control; 2174 2175 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2176 2177 /* 2178 * A bridge will not forward ERR_ messages coming from an 2179 * endpoint unless SERR# forwarding is enabled. 2180 */ 2181 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2182 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2183 control |= PCI_BRIDGE_CTL_SERR; 2184 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2185 } 2186 } 2187 } 2188 2189 static void pci_configure_device(struct pci_dev *dev) 2190 { 2191 pci_configure_mps(dev); 2192 pci_configure_extended_tags(dev, NULL); 2193 pci_configure_relaxed_ordering(dev); 2194 pci_configure_ltr(dev); 2195 pci_configure_eetlp_prefix(dev); 2196 pci_configure_serr(dev); 2197 2198 pci_acpi_program_hp_params(dev); 2199 } 2200 2201 static void pci_release_capabilities(struct pci_dev *dev) 2202 { 2203 pci_aer_exit(dev); 2204 pci_rcec_exit(dev); 2205 pci_vpd_release(dev); 2206 pci_iov_release(dev); 2207 pci_free_cap_save_buffers(dev); 2208 } 2209 2210 /** 2211 * pci_release_dev - Free a PCI device structure when all users of it are 2212 * finished 2213 * @dev: device that's been disconnected 2214 * 2215 * Will be called only by the device core when all users of this PCI device are 2216 * done. 2217 */ 2218 static void pci_release_dev(struct device *dev) 2219 { 2220 struct pci_dev *pci_dev; 2221 2222 pci_dev = to_pci_dev(dev); 2223 pci_release_capabilities(pci_dev); 2224 pci_release_of_node(pci_dev); 2225 pcibios_release_device(pci_dev); 2226 pci_bus_put(pci_dev->bus); 2227 kfree(pci_dev->driver_override); 2228 bitmap_free(pci_dev->dma_alias_mask); 2229 kfree(pci_dev); 2230 } 2231 2232 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2233 { 2234 struct pci_dev *dev; 2235 2236 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2237 if (!dev) 2238 return NULL; 2239 2240 INIT_LIST_HEAD(&dev->bus_list); 2241 dev->dev.type = &pci_dev_type; 2242 dev->bus = pci_bus_get(bus); 2243 2244 return dev; 2245 } 2246 EXPORT_SYMBOL(pci_alloc_dev); 2247 2248 static bool pci_bus_crs_vendor_id(u32 l) 2249 { 2250 return (l & 0xffff) == 0x0001; 2251 } 2252 2253 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2254 int timeout) 2255 { 2256 int delay = 1; 2257 2258 if (!pci_bus_crs_vendor_id(*l)) 2259 return true; /* not a CRS completion */ 2260 2261 if (!timeout) 2262 return false; /* CRS, but caller doesn't want to wait */ 2263 2264 /* 2265 * We got the reserved Vendor ID that indicates a completion with 2266 * Configuration Request Retry Status (CRS). Retry until we get a 2267 * valid Vendor ID or we time out. 2268 */ 2269 while (pci_bus_crs_vendor_id(*l)) { 2270 if (delay > timeout) { 2271 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2272 pci_domain_nr(bus), bus->number, 2273 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2274 2275 return false; 2276 } 2277 if (delay >= 1000) 2278 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2279 pci_domain_nr(bus), bus->number, 2280 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2281 2282 msleep(delay); 2283 delay *= 2; 2284 2285 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2286 return false; 2287 } 2288 2289 if (delay >= 1000) 2290 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2291 pci_domain_nr(bus), bus->number, 2292 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2293 2294 return true; 2295 } 2296 2297 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2298 int timeout) 2299 { 2300 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2301 return false; 2302 2303 /* Some broken boards return 0 or ~0 if a slot is empty: */ 2304 if (*l == 0xffffffff || *l == 0x00000000 || 2305 *l == 0x0000ffff || *l == 0xffff0000) 2306 return false; 2307 2308 if (pci_bus_crs_vendor_id(*l)) 2309 return pci_bus_wait_crs(bus, devfn, l, timeout); 2310 2311 return true; 2312 } 2313 2314 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2315 int timeout) 2316 { 2317 #ifdef CONFIG_PCI_QUIRKS 2318 struct pci_dev *bridge = bus->self; 2319 2320 /* 2321 * Certain IDT switches have an issue where they improperly trigger 2322 * ACS Source Validation errors on completions for config reads. 2323 */ 2324 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2325 bridge->device == 0x80b5) 2326 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2327 #endif 2328 2329 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2330 } 2331 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2332 2333 /* 2334 * Read the config data for a PCI device, sanity-check it, 2335 * and fill in the dev structure. 2336 */ 2337 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2338 { 2339 struct pci_dev *dev; 2340 u32 l; 2341 2342 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2343 return NULL; 2344 2345 dev = pci_alloc_dev(bus); 2346 if (!dev) 2347 return NULL; 2348 2349 dev->devfn = devfn; 2350 dev->vendor = l & 0xffff; 2351 dev->device = (l >> 16) & 0xffff; 2352 2353 pci_set_of_node(dev); 2354 2355 if (pci_setup_device(dev)) { 2356 pci_release_of_node(dev); 2357 pci_bus_put(dev->bus); 2358 kfree(dev); 2359 return NULL; 2360 } 2361 2362 return dev; 2363 } 2364 2365 void pcie_report_downtraining(struct pci_dev *dev) 2366 { 2367 if (!pci_is_pcie(dev)) 2368 return; 2369 2370 /* Look from the device up to avoid downstream ports with no devices */ 2371 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2372 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2373 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2374 return; 2375 2376 /* Multi-function PCIe devices share the same link/status */ 2377 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2378 return; 2379 2380 /* Print link status only if the device is constrained by the fabric */ 2381 __pcie_print_link_status(dev, false); 2382 } 2383 2384 static void pci_init_capabilities(struct pci_dev *dev) 2385 { 2386 pci_ea_init(dev); /* Enhanced Allocation */ 2387 pci_msi_init(dev); /* Disable MSI */ 2388 pci_msix_init(dev); /* Disable MSI-X */ 2389 2390 /* Buffers for saving PCIe and PCI-X capabilities */ 2391 pci_allocate_cap_save_buffers(dev); 2392 2393 pci_pm_init(dev); /* Power Management */ 2394 pci_vpd_init(dev); /* Vital Product Data */ 2395 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2396 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2397 pci_ats_init(dev); /* Address Translation Services */ 2398 pci_pri_init(dev); /* Page Request Interface */ 2399 pci_pasid_init(dev); /* Process Address Space ID */ 2400 pci_acs_init(dev); /* Access Control Services */ 2401 pci_ptm_init(dev); /* Precision Time Measurement */ 2402 pci_aer_init(dev); /* Advanced Error Reporting */ 2403 pci_dpc_init(dev); /* Downstream Port Containment */ 2404 pci_rcec_init(dev); /* Root Complex Event Collector */ 2405 2406 pcie_report_downtraining(dev); 2407 2408 if (pci_probe_reset_function(dev) == 0) 2409 dev->reset_fn = 1; 2410 } 2411 2412 /* 2413 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2414 * devices. Firmware interfaces that can select the MSI domain on a 2415 * per-device basis should be called from here. 2416 */ 2417 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2418 { 2419 struct irq_domain *d; 2420 2421 /* 2422 * If a domain has been set through the pcibios_add_device() 2423 * callback, then this is the one (platform code knows best). 2424 */ 2425 d = dev_get_msi_domain(&dev->dev); 2426 if (d) 2427 return d; 2428 2429 /* 2430 * Let's see if we have a firmware interface able to provide 2431 * the domain. 2432 */ 2433 d = pci_msi_get_device_domain(dev); 2434 if (d) 2435 return d; 2436 2437 return NULL; 2438 } 2439 2440 static void pci_set_msi_domain(struct pci_dev *dev) 2441 { 2442 struct irq_domain *d; 2443 2444 /* 2445 * If the platform or firmware interfaces cannot supply a 2446 * device-specific MSI domain, then inherit the default domain 2447 * from the host bridge itself. 2448 */ 2449 d = pci_dev_msi_domain(dev); 2450 if (!d) 2451 d = dev_get_msi_domain(&dev->bus->dev); 2452 2453 dev_set_msi_domain(&dev->dev, d); 2454 } 2455 2456 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2457 { 2458 int ret; 2459 2460 pci_configure_device(dev); 2461 2462 device_initialize(&dev->dev); 2463 dev->dev.release = pci_release_dev; 2464 2465 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2466 dev->dev.dma_mask = &dev->dma_mask; 2467 dev->dev.dma_parms = &dev->dma_parms; 2468 dev->dev.coherent_dma_mask = 0xffffffffull; 2469 2470 dma_set_max_seg_size(&dev->dev, 65536); 2471 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2472 2473 /* Fix up broken headers */ 2474 pci_fixup_device(pci_fixup_header, dev); 2475 2476 pci_reassigndev_resource_alignment(dev); 2477 2478 dev->state_saved = false; 2479 2480 pci_init_capabilities(dev); 2481 2482 /* 2483 * Add the device to our list of discovered devices 2484 * and the bus list for fixup functions, etc. 2485 */ 2486 down_write(&pci_bus_sem); 2487 list_add_tail(&dev->bus_list, &bus->devices); 2488 up_write(&pci_bus_sem); 2489 2490 ret = pcibios_add_device(dev); 2491 WARN_ON(ret < 0); 2492 2493 /* Set up MSI IRQ domain */ 2494 pci_set_msi_domain(dev); 2495 2496 /* Notifier could use PCI capabilities */ 2497 dev->match_driver = false; 2498 ret = device_add(&dev->dev); 2499 WARN_ON(ret < 0); 2500 } 2501 2502 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2503 { 2504 struct pci_dev *dev; 2505 2506 dev = pci_get_slot(bus, devfn); 2507 if (dev) { 2508 pci_dev_put(dev); 2509 return dev; 2510 } 2511 2512 dev = pci_scan_device(bus, devfn); 2513 if (!dev) 2514 return NULL; 2515 2516 pci_device_add(dev, bus); 2517 2518 return dev; 2519 } 2520 EXPORT_SYMBOL(pci_scan_single_device); 2521 2522 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) 2523 { 2524 int pos; 2525 u16 cap = 0; 2526 unsigned next_fn; 2527 2528 if (pci_ari_enabled(bus)) { 2529 if (!dev) 2530 return 0; 2531 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2532 if (!pos) 2533 return 0; 2534 2535 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2536 next_fn = PCI_ARI_CAP_NFN(cap); 2537 if (next_fn <= fn) 2538 return 0; /* protect against malformed list */ 2539 2540 return next_fn; 2541 } 2542 2543 /* dev may be NULL for non-contiguous multifunction devices */ 2544 if (!dev || dev->multifunction) 2545 return (fn + 1) % 8; 2546 2547 return 0; 2548 } 2549 2550 static int only_one_child(struct pci_bus *bus) 2551 { 2552 struct pci_dev *bridge = bus->self; 2553 2554 /* 2555 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2556 * we scan for all possible devices, not just Device 0. 2557 */ 2558 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2559 return 0; 2560 2561 /* 2562 * A PCIe Downstream Port normally leads to a Link with only Device 2563 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2564 * only for Device 0 in that situation. 2565 */ 2566 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2567 return 1; 2568 2569 return 0; 2570 } 2571 2572 /** 2573 * pci_scan_slot - Scan a PCI slot on a bus for devices 2574 * @bus: PCI bus to scan 2575 * @devfn: slot number to scan (must have zero function) 2576 * 2577 * Scan a PCI slot on the specified PCI bus for devices, adding 2578 * discovered devices to the @bus->devices list. New devices 2579 * will not have is_added set. 2580 * 2581 * Returns the number of new devices found. 2582 */ 2583 int pci_scan_slot(struct pci_bus *bus, int devfn) 2584 { 2585 unsigned fn, nr = 0; 2586 struct pci_dev *dev; 2587 2588 if (only_one_child(bus) && (devfn > 0)) 2589 return 0; /* Already scanned the entire slot */ 2590 2591 dev = pci_scan_single_device(bus, devfn); 2592 if (!dev) 2593 return 0; 2594 if (!pci_dev_is_added(dev)) 2595 nr++; 2596 2597 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { 2598 dev = pci_scan_single_device(bus, devfn + fn); 2599 if (dev) { 2600 if (!pci_dev_is_added(dev)) 2601 nr++; 2602 dev->multifunction = 1; 2603 } 2604 } 2605 2606 /* Only one slot has PCIe device */ 2607 if (bus->self && nr) 2608 pcie_aspm_init_link_state(bus->self); 2609 2610 return nr; 2611 } 2612 EXPORT_SYMBOL(pci_scan_slot); 2613 2614 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2615 { 2616 u8 *smpss = data; 2617 2618 if (!pci_is_pcie(dev)) 2619 return 0; 2620 2621 /* 2622 * We don't have a way to change MPS settings on devices that have 2623 * drivers attached. A hot-added device might support only the minimum 2624 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2625 * where devices may be hot-added, we limit the fabric MPS to 128 so 2626 * hot-added devices will work correctly. 2627 * 2628 * However, if we hot-add a device to a slot directly below a Root 2629 * Port, it's impossible for there to be other existing devices below 2630 * the port. We don't limit the MPS in this case because we can 2631 * reconfigure MPS on both the Root Port and the hot-added device, 2632 * and there are no other devices involved. 2633 * 2634 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2635 */ 2636 if (dev->is_hotplug_bridge && 2637 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2638 *smpss = 0; 2639 2640 if (*smpss > dev->pcie_mpss) 2641 *smpss = dev->pcie_mpss; 2642 2643 return 0; 2644 } 2645 2646 static void pcie_write_mps(struct pci_dev *dev, int mps) 2647 { 2648 int rc; 2649 2650 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2651 mps = 128 << dev->pcie_mpss; 2652 2653 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2654 dev->bus->self) 2655 2656 /* 2657 * For "Performance", the assumption is made that 2658 * downstream communication will never be larger than 2659 * the MRRS. So, the MPS only needs to be configured 2660 * for the upstream communication. This being the case, 2661 * walk from the top down and set the MPS of the child 2662 * to that of the parent bus. 2663 * 2664 * Configure the device MPS with the smaller of the 2665 * device MPSS or the bridge MPS (which is assumed to be 2666 * properly configured at this point to the largest 2667 * allowable MPS based on its parent bus). 2668 */ 2669 mps = min(mps, pcie_get_mps(dev->bus->self)); 2670 } 2671 2672 rc = pcie_set_mps(dev, mps); 2673 if (rc) 2674 pci_err(dev, "Failed attempting to set the MPS\n"); 2675 } 2676 2677 static void pcie_write_mrrs(struct pci_dev *dev) 2678 { 2679 int rc, mrrs; 2680 2681 /* 2682 * In the "safe" case, do not configure the MRRS. There appear to be 2683 * issues with setting MRRS to 0 on a number of devices. 2684 */ 2685 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2686 return; 2687 2688 /* 2689 * For max performance, the MRRS must be set to the largest supported 2690 * value. However, it cannot be configured larger than the MPS the 2691 * device or the bus can support. This should already be properly 2692 * configured by a prior call to pcie_write_mps(). 2693 */ 2694 mrrs = pcie_get_mps(dev); 2695 2696 /* 2697 * MRRS is a R/W register. Invalid values can be written, but a 2698 * subsequent read will verify if the value is acceptable or not. 2699 * If the MRRS value provided is not acceptable (e.g., too large), 2700 * shrink the value until it is acceptable to the HW. 2701 */ 2702 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2703 rc = pcie_set_readrq(dev, mrrs); 2704 if (!rc) 2705 break; 2706 2707 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2708 mrrs /= 2; 2709 } 2710 2711 if (mrrs < 128) 2712 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2713 } 2714 2715 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2716 { 2717 int mps, orig_mps; 2718 2719 if (!pci_is_pcie(dev)) 2720 return 0; 2721 2722 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2723 pcie_bus_config == PCIE_BUS_DEFAULT) 2724 return 0; 2725 2726 mps = 128 << *(u8 *)data; 2727 orig_mps = pcie_get_mps(dev); 2728 2729 pcie_write_mps(dev, mps); 2730 pcie_write_mrrs(dev); 2731 2732 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2733 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2734 orig_mps, pcie_get_readrq(dev)); 2735 2736 return 0; 2737 } 2738 2739 /* 2740 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2741 * parents then children fashion. If this changes, then this code will not 2742 * work as designed. 2743 */ 2744 void pcie_bus_configure_settings(struct pci_bus *bus) 2745 { 2746 u8 smpss = 0; 2747 2748 if (!bus->self) 2749 return; 2750 2751 if (!pci_is_pcie(bus->self)) 2752 return; 2753 2754 /* 2755 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2756 * to be aware of the MPS of the destination. To work around this, 2757 * simply force the MPS of the entire system to the smallest possible. 2758 */ 2759 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2760 smpss = 0; 2761 2762 if (pcie_bus_config == PCIE_BUS_SAFE) { 2763 smpss = bus->self->pcie_mpss; 2764 2765 pcie_find_smpss(bus->self, &smpss); 2766 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2767 } 2768 2769 pcie_bus_configure_set(bus->self, &smpss); 2770 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2771 } 2772 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2773 2774 /* 2775 * Called after each bus is probed, but before its children are examined. This 2776 * is marked as __weak because multiple architectures define it. 2777 */ 2778 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2779 { 2780 /* nothing to do, expected to be removed in the future */ 2781 } 2782 2783 /** 2784 * pci_scan_child_bus_extend() - Scan devices below a bus 2785 * @bus: Bus to scan for devices 2786 * @available_buses: Total number of buses available (%0 does not try to 2787 * extend beyond the minimal) 2788 * 2789 * Scans devices below @bus including subordinate buses. Returns new 2790 * subordinate number including all the found devices. Passing 2791 * @available_buses causes the remaining bus space to be distributed 2792 * equally between hotplug-capable bridges to allow future extension of the 2793 * hierarchy. 2794 */ 2795 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2796 unsigned int available_buses) 2797 { 2798 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2799 unsigned int start = bus->busn_res.start; 2800 unsigned int devfn, fn, cmax, max = start; 2801 struct pci_dev *dev; 2802 int nr_devs; 2803 2804 dev_dbg(&bus->dev, "scanning bus\n"); 2805 2806 /* Go find them, Rover! */ 2807 for (devfn = 0; devfn < 256; devfn += 8) { 2808 nr_devs = pci_scan_slot(bus, devfn); 2809 2810 /* 2811 * The Jailhouse hypervisor may pass individual functions of a 2812 * multi-function device to a guest without passing function 0. 2813 * Look for them as well. 2814 */ 2815 if (jailhouse_paravirt() && nr_devs == 0) { 2816 for (fn = 1; fn < 8; fn++) { 2817 dev = pci_scan_single_device(bus, devfn + fn); 2818 if (dev) 2819 dev->multifunction = 1; 2820 } 2821 } 2822 } 2823 2824 /* Reserve buses for SR-IOV capability */ 2825 used_buses = pci_iov_bus_range(bus); 2826 max += used_buses; 2827 2828 /* 2829 * After performing arch-dependent fixup of the bus, look behind 2830 * all PCI-to-PCI bridges on this bus. 2831 */ 2832 if (!bus->is_added) { 2833 dev_dbg(&bus->dev, "fixups for bus\n"); 2834 pcibios_fixup_bus(bus); 2835 bus->is_added = 1; 2836 } 2837 2838 /* 2839 * Calculate how many hotplug bridges and normal bridges there 2840 * are on this bus. We will distribute the additional available 2841 * buses between hotplug bridges. 2842 */ 2843 for_each_pci_bridge(dev, bus) { 2844 if (dev->is_hotplug_bridge) 2845 hotplug_bridges++; 2846 else 2847 normal_bridges++; 2848 } 2849 2850 /* 2851 * Scan bridges that are already configured. We don't touch them 2852 * unless they are misconfigured (which will be done in the second 2853 * scan below). 2854 */ 2855 for_each_pci_bridge(dev, bus) { 2856 cmax = max; 2857 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2858 2859 /* 2860 * Reserve one bus for each bridge now to avoid extending 2861 * hotplug bridges too much during the second scan below. 2862 */ 2863 used_buses++; 2864 if (cmax - max > 1) 2865 used_buses += cmax - max - 1; 2866 } 2867 2868 /* Scan bridges that need to be reconfigured */ 2869 for_each_pci_bridge(dev, bus) { 2870 unsigned int buses = 0; 2871 2872 if (!hotplug_bridges && normal_bridges == 1) { 2873 2874 /* 2875 * There is only one bridge on the bus (upstream 2876 * port) so it gets all available buses which it 2877 * can then distribute to the possible hotplug 2878 * bridges below. 2879 */ 2880 buses = available_buses; 2881 } else if (dev->is_hotplug_bridge) { 2882 2883 /* 2884 * Distribute the extra buses between hotplug 2885 * bridges if any. 2886 */ 2887 buses = available_buses / hotplug_bridges; 2888 buses = min(buses, available_buses - used_buses + 1); 2889 } 2890 2891 cmax = max; 2892 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2893 /* One bus is already accounted so don't add it again */ 2894 if (max - cmax > 1) 2895 used_buses += max - cmax - 1; 2896 } 2897 2898 /* 2899 * Make sure a hotplug bridge has at least the minimum requested 2900 * number of buses but allow it to grow up to the maximum available 2901 * bus number of there is room. 2902 */ 2903 if (bus->self && bus->self->is_hotplug_bridge) { 2904 used_buses = max_t(unsigned int, available_buses, 2905 pci_hotplug_bus_size - 1); 2906 if (max - start < used_buses) { 2907 max = start + used_buses; 2908 2909 /* Do not allocate more buses than we have room left */ 2910 if (max > bus->busn_res.end) 2911 max = bus->busn_res.end; 2912 2913 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2914 &bus->busn_res, max - start); 2915 } 2916 } 2917 2918 /* 2919 * We've scanned the bus and so we know all about what's on 2920 * the other side of any bridges that may be on this bus plus 2921 * any devices. 2922 * 2923 * Return how far we've got finding sub-buses. 2924 */ 2925 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2926 return max; 2927 } 2928 2929 /** 2930 * pci_scan_child_bus() - Scan devices below a bus 2931 * @bus: Bus to scan for devices 2932 * 2933 * Scans devices below @bus including subordinate buses. Returns new 2934 * subordinate number including all the found devices. 2935 */ 2936 unsigned int pci_scan_child_bus(struct pci_bus *bus) 2937 { 2938 return pci_scan_child_bus_extend(bus, 0); 2939 } 2940 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 2941 2942 /** 2943 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 2944 * @bridge: Host bridge to set up 2945 * 2946 * Default empty implementation. Replace with an architecture-specific setup 2947 * routine, if necessary. 2948 */ 2949 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 2950 { 2951 return 0; 2952 } 2953 2954 void __weak pcibios_add_bus(struct pci_bus *bus) 2955 { 2956 } 2957 2958 void __weak pcibios_remove_bus(struct pci_bus *bus) 2959 { 2960 } 2961 2962 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 2963 struct pci_ops *ops, void *sysdata, struct list_head *resources) 2964 { 2965 int error; 2966 struct pci_host_bridge *bridge; 2967 2968 bridge = pci_alloc_host_bridge(0); 2969 if (!bridge) 2970 return NULL; 2971 2972 bridge->dev.parent = parent; 2973 2974 list_splice_init(resources, &bridge->windows); 2975 bridge->sysdata = sysdata; 2976 bridge->busnr = bus; 2977 bridge->ops = ops; 2978 2979 error = pci_register_host_bridge(bridge); 2980 if (error < 0) 2981 goto err_out; 2982 2983 return bridge->bus; 2984 2985 err_out: 2986 put_device(&bridge->dev); 2987 return NULL; 2988 } 2989 EXPORT_SYMBOL_GPL(pci_create_root_bus); 2990 2991 int pci_host_probe(struct pci_host_bridge *bridge) 2992 { 2993 struct pci_bus *bus, *child; 2994 int ret; 2995 2996 ret = pci_scan_root_bus_bridge(bridge); 2997 if (ret < 0) { 2998 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 2999 return ret; 3000 } 3001 3002 bus = bridge->bus; 3003 3004 /* 3005 * We insert PCI resources into the iomem_resource and 3006 * ioport_resource trees in either pci_bus_claim_resources() 3007 * or pci_bus_assign_resources(). 3008 */ 3009 if (pci_has_flag(PCI_PROBE_ONLY)) { 3010 pci_bus_claim_resources(bus); 3011 } else { 3012 pci_bus_size_bridges(bus); 3013 pci_bus_assign_resources(bus); 3014 3015 list_for_each_entry(child, &bus->children, node) 3016 pcie_bus_configure_settings(child); 3017 } 3018 3019 pci_bus_add_devices(bus); 3020 return 0; 3021 } 3022 EXPORT_SYMBOL_GPL(pci_host_probe); 3023 3024 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3025 { 3026 struct resource *res = &b->busn_res; 3027 struct resource *parent_res, *conflict; 3028 3029 res->start = bus; 3030 res->end = bus_max; 3031 res->flags = IORESOURCE_BUS; 3032 3033 if (!pci_is_root_bus(b)) 3034 parent_res = &b->parent->busn_res; 3035 else { 3036 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3037 res->flags |= IORESOURCE_PCI_FIXED; 3038 } 3039 3040 conflict = request_resource_conflict(parent_res, res); 3041 3042 if (conflict) 3043 dev_info(&b->dev, 3044 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3045 res, pci_is_root_bus(b) ? "domain " : "", 3046 parent_res, conflict->name, conflict); 3047 3048 return conflict == NULL; 3049 } 3050 3051 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3052 { 3053 struct resource *res = &b->busn_res; 3054 struct resource old_res = *res; 3055 resource_size_t size; 3056 int ret; 3057 3058 if (res->start > bus_max) 3059 return -EINVAL; 3060 3061 size = bus_max - res->start + 1; 3062 ret = adjust_resource(res, res->start, size); 3063 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3064 &old_res, ret ? "can not be" : "is", bus_max); 3065 3066 if (!ret && !res->parent) 3067 pci_bus_insert_busn_res(b, res->start, res->end); 3068 3069 return ret; 3070 } 3071 3072 void pci_bus_release_busn_res(struct pci_bus *b) 3073 { 3074 struct resource *res = &b->busn_res; 3075 int ret; 3076 3077 if (!res->flags || !res->parent) 3078 return; 3079 3080 ret = release_resource(res); 3081 dev_info(&b->dev, "busn_res: %pR %s released\n", 3082 res, ret ? "can not be" : "is"); 3083 } 3084 3085 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3086 { 3087 struct resource_entry *window; 3088 bool found = false; 3089 struct pci_bus *b; 3090 int max, bus, ret; 3091 3092 if (!bridge) 3093 return -EINVAL; 3094 3095 resource_list_for_each_entry(window, &bridge->windows) 3096 if (window->res->flags & IORESOURCE_BUS) { 3097 bridge->busnr = window->res->start; 3098 found = true; 3099 break; 3100 } 3101 3102 ret = pci_register_host_bridge(bridge); 3103 if (ret < 0) 3104 return ret; 3105 3106 b = bridge->bus; 3107 bus = bridge->busnr; 3108 3109 if (!found) { 3110 dev_info(&b->dev, 3111 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3112 bus); 3113 pci_bus_insert_busn_res(b, bus, 255); 3114 } 3115 3116 max = pci_scan_child_bus(b); 3117 3118 if (!found) 3119 pci_bus_update_busn_res_end(b, max); 3120 3121 return 0; 3122 } 3123 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3124 3125 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3126 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3127 { 3128 struct resource_entry *window; 3129 bool found = false; 3130 struct pci_bus *b; 3131 int max; 3132 3133 resource_list_for_each_entry(window, resources) 3134 if (window->res->flags & IORESOURCE_BUS) { 3135 found = true; 3136 break; 3137 } 3138 3139 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3140 if (!b) 3141 return NULL; 3142 3143 if (!found) { 3144 dev_info(&b->dev, 3145 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3146 bus); 3147 pci_bus_insert_busn_res(b, bus, 255); 3148 } 3149 3150 max = pci_scan_child_bus(b); 3151 3152 if (!found) 3153 pci_bus_update_busn_res_end(b, max); 3154 3155 return b; 3156 } 3157 EXPORT_SYMBOL(pci_scan_root_bus); 3158 3159 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3160 void *sysdata) 3161 { 3162 LIST_HEAD(resources); 3163 struct pci_bus *b; 3164 3165 pci_add_resource(&resources, &ioport_resource); 3166 pci_add_resource(&resources, &iomem_resource); 3167 pci_add_resource(&resources, &busn_resource); 3168 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3169 if (b) { 3170 pci_scan_child_bus(b); 3171 } else { 3172 pci_free_resource_list(&resources); 3173 } 3174 return b; 3175 } 3176 EXPORT_SYMBOL(pci_scan_bus); 3177 3178 /** 3179 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3180 * @bridge: PCI bridge for the bus to scan 3181 * 3182 * Scan a PCI bus and child buses for new devices, add them, 3183 * and enable them, resizing bridge mmio/io resource if necessary 3184 * and possible. The caller must ensure the child devices are already 3185 * removed for resizing to occur. 3186 * 3187 * Returns the max number of subordinate bus discovered. 3188 */ 3189 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3190 { 3191 unsigned int max; 3192 struct pci_bus *bus = bridge->subordinate; 3193 3194 max = pci_scan_child_bus(bus); 3195 3196 pci_assign_unassigned_bridge_resources(bridge); 3197 3198 pci_bus_add_devices(bus); 3199 3200 return max; 3201 } 3202 3203 /** 3204 * pci_rescan_bus - Scan a PCI bus for devices 3205 * @bus: PCI bus to scan 3206 * 3207 * Scan a PCI bus and child buses for new devices, add them, 3208 * and enable them. 3209 * 3210 * Returns the max number of subordinate bus discovered. 3211 */ 3212 unsigned int pci_rescan_bus(struct pci_bus *bus) 3213 { 3214 unsigned int max; 3215 3216 max = pci_scan_child_bus(bus); 3217 pci_assign_unassigned_bus_resources(bus); 3218 pci_bus_add_devices(bus); 3219 3220 return max; 3221 } 3222 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3223 3224 /* 3225 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3226 * routines should always be executed under this mutex. 3227 */ 3228 static DEFINE_MUTEX(pci_rescan_remove_lock); 3229 3230 void pci_lock_rescan_remove(void) 3231 { 3232 mutex_lock(&pci_rescan_remove_lock); 3233 } 3234 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3235 3236 void pci_unlock_rescan_remove(void) 3237 { 3238 mutex_unlock(&pci_rescan_remove_lock); 3239 } 3240 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3241 3242 static int __init pci_sort_bf_cmp(const struct device *d_a, 3243 const struct device *d_b) 3244 { 3245 const struct pci_dev *a = to_pci_dev(d_a); 3246 const struct pci_dev *b = to_pci_dev(d_b); 3247 3248 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3249 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3250 3251 if (a->bus->number < b->bus->number) return -1; 3252 else if (a->bus->number > b->bus->number) return 1; 3253 3254 if (a->devfn < b->devfn) return -1; 3255 else if (a->devfn > b->devfn) return 1; 3256 3257 return 0; 3258 } 3259 3260 void __init pci_sort_breadthfirst(void) 3261 { 3262 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3263 } 3264 3265 int pci_hp_add_bridge(struct pci_dev *dev) 3266 { 3267 struct pci_bus *parent = dev->bus; 3268 int busnr, start = parent->busn_res.start; 3269 unsigned int available_buses = 0; 3270 int end = parent->busn_res.end; 3271 3272 for (busnr = start; busnr <= end; busnr++) { 3273 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3274 break; 3275 } 3276 if (busnr-- > end) { 3277 pci_err(dev, "No bus number available for hot-added bridge\n"); 3278 return -1; 3279 } 3280 3281 /* Scan bridges that are already configured */ 3282 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3283 3284 /* 3285 * Distribute the available bus numbers between hotplug-capable 3286 * bridges to make extending the chain later possible. 3287 */ 3288 available_buses = end - busnr; 3289 3290 /* Scan bridges that need to be reconfigured */ 3291 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3292 3293 if (!dev->subordinate) 3294 return -1; 3295 3296 return 0; 3297 } 3298 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3299