xref: /openbmc/linux/drivers/pci/probe.c (revision 13e7accb81d6c07993385af8342238ff22b41ac8)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * PCI detection and setup code
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/msi.h>
11 #include <linux/of_device.h>
12 #include <linux/of_pci.h>
13 #include <linux/pci_hotplug.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/cpumask.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/bitfield.h>
23 #include "pci.h"
24 
25 #define CARDBUS_LATENCY_TIMER	176	/* secondary latency timer */
26 #define CARDBUS_RESERVE_BUSNR	3
27 
28 static struct resource busn_resource = {
29 	.name	= "PCI busn",
30 	.start	= 0,
31 	.end	= 255,
32 	.flags	= IORESOURCE_BUS,
33 };
34 
35 /* Ugh.  Need to stop exporting this to modules. */
36 LIST_HEAD(pci_root_buses);
37 EXPORT_SYMBOL(pci_root_buses);
38 
39 static LIST_HEAD(pci_domain_busn_res_list);
40 
41 struct pci_domain_busn_res {
42 	struct list_head list;
43 	struct resource res;
44 	int domain_nr;
45 };
46 
47 static struct resource *get_pci_domain_busn_res(int domain_nr)
48 {
49 	struct pci_domain_busn_res *r;
50 
51 	list_for_each_entry(r, &pci_domain_busn_res_list, list)
52 		if (r->domain_nr == domain_nr)
53 			return &r->res;
54 
55 	r = kzalloc(sizeof(*r), GFP_KERNEL);
56 	if (!r)
57 		return NULL;
58 
59 	r->domain_nr = domain_nr;
60 	r->res.start = 0;
61 	r->res.end = 0xff;
62 	r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 
64 	list_add_tail(&r->list, &pci_domain_busn_res_list);
65 
66 	return &r->res;
67 }
68 
69 /*
70  * Some device drivers need know if PCI is initiated.
71  * Basically, we think PCI is not initiated when there
72  * is no device to be found on the pci_bus_type.
73  */
74 int no_pci_devices(void)
75 {
76 	struct device *dev;
77 	int no_devices;
78 
79 	dev = bus_find_next_device(&pci_bus_type, NULL);
80 	no_devices = (dev == NULL);
81 	put_device(dev);
82 	return no_devices;
83 }
84 EXPORT_SYMBOL(no_pci_devices);
85 
86 /*
87  * PCI Bus Class
88  */
89 static void release_pcibus_dev(struct device *dev)
90 {
91 	struct pci_bus *pci_bus = to_pci_bus(dev);
92 
93 	put_device(pci_bus->bridge);
94 	pci_bus_remove_resources(pci_bus);
95 	pci_release_bus_of_node(pci_bus);
96 	kfree(pci_bus);
97 }
98 
99 static struct class pcibus_class = {
100 	.name		= "pci_bus",
101 	.dev_release	= &release_pcibus_dev,
102 	.dev_groups	= pcibus_groups,
103 };
104 
105 static int __init pcibus_class_init(void)
106 {
107 	return class_register(&pcibus_class);
108 }
109 postcore_initcall(pcibus_class_init);
110 
111 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112 {
113 	u64 size = mask & maxbase;	/* Find the significant bits */
114 	if (!size)
115 		return 0;
116 
117 	/*
118 	 * Get the lowest of them to find the decode size, and from that
119 	 * the extent.
120 	 */
121 	size = size & ~(size-1);
122 
123 	/*
124 	 * base == maxbase can be valid only if the BAR has already been
125 	 * programmed with all 1s.
126 	 */
127 	if (base == maxbase && ((base | (size - 1)) & mask) != mask)
128 		return 0;
129 
130 	return size;
131 }
132 
133 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134 {
135 	u32 mem_type;
136 	unsigned long flags;
137 
138 	if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
139 		flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
140 		flags |= IORESOURCE_IO;
141 		return flags;
142 	}
143 
144 	flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
145 	flags |= IORESOURCE_MEM;
146 	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
147 		flags |= IORESOURCE_PREFETCH;
148 
149 	mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
150 	switch (mem_type) {
151 	case PCI_BASE_ADDRESS_MEM_TYPE_32:
152 		break;
153 	case PCI_BASE_ADDRESS_MEM_TYPE_1M:
154 		/* 1M mem BAR treated as 32-bit BAR */
155 		break;
156 	case PCI_BASE_ADDRESS_MEM_TYPE_64:
157 		flags |= IORESOURCE_MEM_64;
158 		break;
159 	default:
160 		/* mem unknown type treated as 32-bit BAR */
161 		break;
162 	}
163 	return flags;
164 }
165 
166 #define PCI_COMMAND_DECODE_ENABLE	(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 
168 /**
169  * __pci_read_base - Read a PCI BAR
170  * @dev: the PCI device
171  * @type: type of the BAR
172  * @res: resource buffer to be filled in
173  * @pos: BAR position in the config space
174  *
175  * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176  */
177 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 		    struct resource *res, unsigned int pos)
179 {
180 	u32 l = 0, sz = 0, mask;
181 	u64 l64, sz64, mask64;
182 	u16 orig_cmd;
183 	struct pci_bus_region region, inverted_region;
184 
185 	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186 
187 	/* No printks while decoding is disabled! */
188 	if (!dev->mmio_always_on) {
189 		pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 		if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 			pci_write_config_word(dev, PCI_COMMAND,
192 				orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 		}
194 	}
195 
196 	res->name = pci_name(dev);
197 
198 	pci_read_config_dword(dev, pos, &l);
199 	pci_write_config_dword(dev, pos, l | mask);
200 	pci_read_config_dword(dev, pos, &sz);
201 	pci_write_config_dword(dev, pos, l);
202 
203 	/*
204 	 * All bits set in sz means the device isn't working properly.
205 	 * If the BAR isn't implemented, all bits must be 0.  If it's a
206 	 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 	 * 1 must be clear.
208 	 */
209 	if (PCI_POSSIBLE_ERROR(sz))
210 		sz = 0;
211 
212 	/*
213 	 * I don't know how l can have all bits set.  Copied from old code.
214 	 * Maybe it fixes a bug on some ancient platform.
215 	 */
216 	if (PCI_POSSIBLE_ERROR(l))
217 		l = 0;
218 
219 	if (type == pci_bar_unknown) {
220 		res->flags = decode_bar(dev, l);
221 		res->flags |= IORESOURCE_SIZEALIGN;
222 		if (res->flags & IORESOURCE_IO) {
223 			l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 			sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 			mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 		} else {
227 			l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 			sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 			mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 		}
231 	} else {
232 		if (l & PCI_ROM_ADDRESS_ENABLE)
233 			res->flags |= IORESOURCE_ROM_ENABLE;
234 		l64 = l & PCI_ROM_ADDRESS_MASK;
235 		sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 		mask64 = PCI_ROM_ADDRESS_MASK;
237 	}
238 
239 	if (res->flags & IORESOURCE_MEM_64) {
240 		pci_read_config_dword(dev, pos + 4, &l);
241 		pci_write_config_dword(dev, pos + 4, ~0);
242 		pci_read_config_dword(dev, pos + 4, &sz);
243 		pci_write_config_dword(dev, pos + 4, l);
244 
245 		l64 |= ((u64)l << 32);
246 		sz64 |= ((u64)sz << 32);
247 		mask64 |= ((u64)~0 << 32);
248 	}
249 
250 	if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 		pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252 
253 	if (!sz64)
254 		goto fail;
255 
256 	sz64 = pci_size(l64, sz64, mask64);
257 	if (!sz64) {
258 		pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 			 pos);
260 		goto fail;
261 	}
262 
263 	if (res->flags & IORESOURCE_MEM_64) {
264 		if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
265 		    && sz64 > 0x100000000ULL) {
266 			res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 			res->start = 0;
268 			res->end = 0;
269 			pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 				pos, (unsigned long long)sz64);
271 			goto out;
272 		}
273 
274 		if ((sizeof(pci_bus_addr_t) < 8) && l) {
275 			/* Above 32-bit boundary; try to reallocate */
276 			res->flags |= IORESOURCE_UNSET;
277 			res->start = 0;
278 			res->end = sz64 - 1;
279 			pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 				 pos, (unsigned long long)l64);
281 			goto out;
282 		}
283 	}
284 
285 	region.start = l64;
286 	region.end = l64 + sz64 - 1;
287 
288 	pcibios_bus_to_resource(dev->bus, res, &region);
289 	pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290 
291 	/*
292 	 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 	 * the corresponding resource address (the physical address used by
294 	 * the CPU.  Converting that resource address back to a bus address
295 	 * should yield the original BAR value:
296 	 *
297 	 *     resource_to_bus(bus_to_resource(A)) == A
298 	 *
299 	 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 	 * be claimed by the device.
301 	 */
302 	if (inverted_region.start != region.start) {
303 		res->flags |= IORESOURCE_UNSET;
304 		res->start = 0;
305 		res->end = region.end - region.start;
306 		pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 			 pos, (unsigned long long)region.start);
308 	}
309 
310 	goto out;
311 
312 
313 fail:
314 	res->flags = 0;
315 out:
316 	if (res->flags)
317 		pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318 
319 	return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320 }
321 
322 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323 {
324 	unsigned int pos, reg;
325 
326 	if (dev->non_compliant_bars)
327 		return;
328 
329 	/* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
330 	if (dev->is_virtfn)
331 		return;
332 
333 	for (pos = 0; pos < howmany; pos++) {
334 		struct resource *res = &dev->resource[pos];
335 		reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 		pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
337 	}
338 
339 	if (rom) {
340 		struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 		dev->rom_base_reg = rom;
342 		res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 				IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 		__pci_read_base(dev, pci_bar_mem32, res, rom);
345 	}
346 }
347 
348 static void pci_read_bridge_windows(struct pci_dev *bridge)
349 {
350 	u16 io;
351 	u32 pmem, tmp;
352 
353 	pci_read_config_word(bridge, PCI_IO_BASE, &io);
354 	if (!io) {
355 		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
356 		pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 	}
359 	if (io)
360 		bridge->io_window = 1;
361 
362 	/*
363 	 * DECchip 21050 pass 2 errata: the bridge may miss an address
364 	 * disconnect boundary by one PCI data phase.  Workaround: do not
365 	 * use prefetching on this device.
366 	 */
367 	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
368 		return;
369 
370 	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
371 	if (!pmem) {
372 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
373 					       0xffe0fff0);
374 		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
375 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
376 	}
377 	if (!pmem)
378 		return;
379 
380 	bridge->pref_window = 1;
381 
382 	if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
383 
384 		/*
385 		 * Bridge claims to have a 64-bit prefetchable memory
386 		 * window; verify that the upper bits are actually
387 		 * writable.
388 		 */
389 		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
390 		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
391 				       0xffffffff);
392 		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
393 		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
394 		if (tmp)
395 			bridge->pref_64_window = 1;
396 	}
397 }
398 
399 static void pci_read_bridge_io(struct pci_bus *child)
400 {
401 	struct pci_dev *dev = child->self;
402 	u8 io_base_lo, io_limit_lo;
403 	unsigned long io_mask, io_granularity, base, limit;
404 	struct pci_bus_region region;
405 	struct resource *res;
406 
407 	io_mask = PCI_IO_RANGE_MASK;
408 	io_granularity = 0x1000;
409 	if (dev->io_window_1k) {
410 		/* Support 1K I/O space granularity */
411 		io_mask = PCI_IO_1K_RANGE_MASK;
412 		io_granularity = 0x400;
413 	}
414 
415 	res = child->resource[0];
416 	pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
417 	pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
418 	base = (io_base_lo & io_mask) << 8;
419 	limit = (io_limit_lo & io_mask) << 8;
420 
421 	if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
422 		u16 io_base_hi, io_limit_hi;
423 
424 		pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
425 		pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
426 		base |= ((unsigned long) io_base_hi << 16);
427 		limit |= ((unsigned long) io_limit_hi << 16);
428 	}
429 
430 	if (base <= limit) {
431 		res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
432 		region.start = base;
433 		region.end = limit + io_granularity - 1;
434 		pcibios_bus_to_resource(dev->bus, res, &region);
435 		pci_info(dev, "  bridge window %pR\n", res);
436 	}
437 }
438 
439 static void pci_read_bridge_mmio(struct pci_bus *child)
440 {
441 	struct pci_dev *dev = child->self;
442 	u16 mem_base_lo, mem_limit_lo;
443 	unsigned long base, limit;
444 	struct pci_bus_region region;
445 	struct resource *res;
446 
447 	res = child->resource[1];
448 	pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
449 	pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
450 	base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 	limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
452 	if (base <= limit) {
453 		res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
454 		region.start = base;
455 		region.end = limit + 0xfffff;
456 		pcibios_bus_to_resource(dev->bus, res, &region);
457 		pci_info(dev, "  bridge window %pR\n", res);
458 	}
459 }
460 
461 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462 {
463 	struct pci_dev *dev = child->self;
464 	u16 mem_base_lo, mem_limit_lo;
465 	u64 base64, limit64;
466 	pci_bus_addr_t base, limit;
467 	struct pci_bus_region region;
468 	struct resource *res;
469 
470 	res = child->resource[2];
471 	pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
472 	pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
473 	base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
474 	limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475 
476 	if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
477 		u32 mem_base_hi, mem_limit_hi;
478 
479 		pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
480 		pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
481 
482 		/*
483 		 * Some bridges set the base > limit by default, and some
484 		 * (broken) BIOSes do not initialize them.  If we find
485 		 * this, just assume they are not being used.
486 		 */
487 		if (mem_base_hi <= mem_limit_hi) {
488 			base64 |= (u64) mem_base_hi << 32;
489 			limit64 |= (u64) mem_limit_hi << 32;
490 		}
491 	}
492 
493 	base = (pci_bus_addr_t) base64;
494 	limit = (pci_bus_addr_t) limit64;
495 
496 	if (base != base64) {
497 		pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 			(unsigned long long) base64);
499 		return;
500 	}
501 
502 	if (base <= limit) {
503 		res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
504 					 IORESOURCE_MEM | IORESOURCE_PREFETCH;
505 		if (res->flags & PCI_PREF_RANGE_TYPE_64)
506 			res->flags |= IORESOURCE_MEM_64;
507 		region.start = base;
508 		region.end = limit + 0xfffff;
509 		pcibios_bus_to_resource(dev->bus, res, &region);
510 		pci_info(dev, "  bridge window %pR\n", res);
511 	}
512 }
513 
514 void pci_read_bridge_bases(struct pci_bus *child)
515 {
516 	struct pci_dev *dev = child->self;
517 	struct resource *res;
518 	int i;
519 
520 	if (pci_is_root_bus(child))	/* It's a host bus, nothing to read */
521 		return;
522 
523 	pci_info(dev, "PCI bridge to %pR%s\n",
524 		 &child->busn_res,
525 		 dev->transparent ? " (subtractive decode)" : "");
526 
527 	pci_bus_remove_resources(child);
528 	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
529 		child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530 
531 	pci_read_bridge_io(child);
532 	pci_read_bridge_mmio(child);
533 	pci_read_bridge_mmio_pref(child);
534 
535 	if (dev->transparent) {
536 		pci_bus_for_each_resource(child->parent, res, i) {
537 			if (res && res->flags) {
538 				pci_bus_add_resource(child, res,
539 						     PCI_SUBTRACTIVE_DECODE);
540 				pci_info(dev, "  bridge window %pR (subtractive decode)\n",
541 					   res);
542 			}
543 		}
544 	}
545 }
546 
547 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
548 {
549 	struct pci_bus *b;
550 
551 	b = kzalloc(sizeof(*b), GFP_KERNEL);
552 	if (!b)
553 		return NULL;
554 
555 	INIT_LIST_HEAD(&b->node);
556 	INIT_LIST_HEAD(&b->children);
557 	INIT_LIST_HEAD(&b->devices);
558 	INIT_LIST_HEAD(&b->slots);
559 	INIT_LIST_HEAD(&b->resources);
560 	b->max_bus_speed = PCI_SPEED_UNKNOWN;
561 	b->cur_bus_speed = PCI_SPEED_UNKNOWN;
562 #ifdef CONFIG_PCI_DOMAINS_GENERIC
563 	if (parent)
564 		b->domain_nr = parent->domain_nr;
565 #endif
566 	return b;
567 }
568 
569 static void pci_release_host_bridge_dev(struct device *dev)
570 {
571 	struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572 
573 	if (bridge->release_fn)
574 		bridge->release_fn(bridge);
575 
576 	pci_free_resource_list(&bridge->windows);
577 	pci_free_resource_list(&bridge->dma_ranges);
578 	kfree(bridge);
579 }
580 
581 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
582 {
583 	INIT_LIST_HEAD(&bridge->windows);
584 	INIT_LIST_HEAD(&bridge->dma_ranges);
585 
586 	/*
587 	 * We assume we can manage these PCIe features.  Some systems may
588 	 * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 	 * may implement its own AER handling and use _OSC to prevent the
590 	 * OS from interfering.
591 	 */
592 	bridge->native_aer = 1;
593 	bridge->native_pcie_hotplug = 1;
594 	bridge->native_shpc_hotplug = 1;
595 	bridge->native_pme = 1;
596 	bridge->native_ltr = 1;
597 	bridge->native_dpc = 1;
598 	bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
599 
600 	device_initialize(&bridge->dev);
601 }
602 
603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
604 {
605 	struct pci_host_bridge *bridge;
606 
607 	bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
608 	if (!bridge)
609 		return NULL;
610 
611 	pci_init_host_bridge(bridge);
612 	bridge->dev.release = pci_release_host_bridge_dev;
613 
614 	return bridge;
615 }
616 EXPORT_SYMBOL(pci_alloc_host_bridge);
617 
618 static void devm_pci_alloc_host_bridge_release(void *data)
619 {
620 	pci_free_host_bridge(data);
621 }
622 
623 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
624 						   size_t priv)
625 {
626 	int ret;
627 	struct pci_host_bridge *bridge;
628 
629 	bridge = pci_alloc_host_bridge(priv);
630 	if (!bridge)
631 		return NULL;
632 
633 	bridge->dev.parent = dev;
634 
635 	ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
636 				       bridge);
637 	if (ret)
638 		return NULL;
639 
640 	ret = devm_of_pci_bridge_init(dev, bridge);
641 	if (ret)
642 		return NULL;
643 
644 	return bridge;
645 }
646 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
647 
648 void pci_free_host_bridge(struct pci_host_bridge *bridge)
649 {
650 	put_device(&bridge->dev);
651 }
652 EXPORT_SYMBOL(pci_free_host_bridge);
653 
654 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
655 static const unsigned char pcix_bus_speed[] = {
656 	PCI_SPEED_UNKNOWN,		/* 0 */
657 	PCI_SPEED_66MHz_PCIX,		/* 1 */
658 	PCI_SPEED_100MHz_PCIX,		/* 2 */
659 	PCI_SPEED_133MHz_PCIX,		/* 3 */
660 	PCI_SPEED_UNKNOWN,		/* 4 */
661 	PCI_SPEED_66MHz_PCIX_ECC,	/* 5 */
662 	PCI_SPEED_100MHz_PCIX_ECC,	/* 6 */
663 	PCI_SPEED_133MHz_PCIX_ECC,	/* 7 */
664 	PCI_SPEED_UNKNOWN,		/* 8 */
665 	PCI_SPEED_66MHz_PCIX_266,	/* 9 */
666 	PCI_SPEED_100MHz_PCIX_266,	/* A */
667 	PCI_SPEED_133MHz_PCIX_266,	/* B */
668 	PCI_SPEED_UNKNOWN,		/* C */
669 	PCI_SPEED_66MHz_PCIX_533,	/* D */
670 	PCI_SPEED_100MHz_PCIX_533,	/* E */
671 	PCI_SPEED_133MHz_PCIX_533	/* F */
672 };
673 
674 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
675 const unsigned char pcie_link_speed[] = {
676 	PCI_SPEED_UNKNOWN,		/* 0 */
677 	PCIE_SPEED_2_5GT,		/* 1 */
678 	PCIE_SPEED_5_0GT,		/* 2 */
679 	PCIE_SPEED_8_0GT,		/* 3 */
680 	PCIE_SPEED_16_0GT,		/* 4 */
681 	PCIE_SPEED_32_0GT,		/* 5 */
682 	PCIE_SPEED_64_0GT,		/* 6 */
683 	PCI_SPEED_UNKNOWN,		/* 7 */
684 	PCI_SPEED_UNKNOWN,		/* 8 */
685 	PCI_SPEED_UNKNOWN,		/* 9 */
686 	PCI_SPEED_UNKNOWN,		/* A */
687 	PCI_SPEED_UNKNOWN,		/* B */
688 	PCI_SPEED_UNKNOWN,		/* C */
689 	PCI_SPEED_UNKNOWN,		/* D */
690 	PCI_SPEED_UNKNOWN,		/* E */
691 	PCI_SPEED_UNKNOWN		/* F */
692 };
693 EXPORT_SYMBOL_GPL(pcie_link_speed);
694 
695 const char *pci_speed_string(enum pci_bus_speed speed)
696 {
697 	/* Indexed by the pci_bus_speed enum */
698 	static const char *speed_strings[] = {
699 	    "33 MHz PCI",		/* 0x00 */
700 	    "66 MHz PCI",		/* 0x01 */
701 	    "66 MHz PCI-X",		/* 0x02 */
702 	    "100 MHz PCI-X",		/* 0x03 */
703 	    "133 MHz PCI-X",		/* 0x04 */
704 	    NULL,			/* 0x05 */
705 	    NULL,			/* 0x06 */
706 	    NULL,			/* 0x07 */
707 	    NULL,			/* 0x08 */
708 	    "66 MHz PCI-X 266",		/* 0x09 */
709 	    "100 MHz PCI-X 266",	/* 0x0a */
710 	    "133 MHz PCI-X 266",	/* 0x0b */
711 	    "Unknown AGP",		/* 0x0c */
712 	    "1x AGP",			/* 0x0d */
713 	    "2x AGP",			/* 0x0e */
714 	    "4x AGP",			/* 0x0f */
715 	    "8x AGP",			/* 0x10 */
716 	    "66 MHz PCI-X 533",		/* 0x11 */
717 	    "100 MHz PCI-X 533",	/* 0x12 */
718 	    "133 MHz PCI-X 533",	/* 0x13 */
719 	    "2.5 GT/s PCIe",		/* 0x14 */
720 	    "5.0 GT/s PCIe",		/* 0x15 */
721 	    "8.0 GT/s PCIe",		/* 0x16 */
722 	    "16.0 GT/s PCIe",		/* 0x17 */
723 	    "32.0 GT/s PCIe",		/* 0x18 */
724 	    "64.0 GT/s PCIe",		/* 0x19 */
725 	};
726 
727 	if (speed < ARRAY_SIZE(speed_strings))
728 		return speed_strings[speed];
729 	return "Unknown";
730 }
731 EXPORT_SYMBOL_GPL(pci_speed_string);
732 
733 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
734 {
735 	bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
736 }
737 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
738 
739 static unsigned char agp_speeds[] = {
740 	AGP_UNKNOWN,
741 	AGP_1X,
742 	AGP_2X,
743 	AGP_4X,
744 	AGP_8X
745 };
746 
747 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
748 {
749 	int index = 0;
750 
751 	if (agpstat & 4)
752 		index = 3;
753 	else if (agpstat & 2)
754 		index = 2;
755 	else if (agpstat & 1)
756 		index = 1;
757 	else
758 		goto out;
759 
760 	if (agp3) {
761 		index += 2;
762 		if (index == 5)
763 			index = 0;
764 	}
765 
766  out:
767 	return agp_speeds[index];
768 }
769 
770 static void pci_set_bus_speed(struct pci_bus *bus)
771 {
772 	struct pci_dev *bridge = bus->self;
773 	int pos;
774 
775 	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
776 	if (!pos)
777 		pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
778 	if (pos) {
779 		u32 agpstat, agpcmd;
780 
781 		pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
782 		bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
783 
784 		pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
785 		bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
786 	}
787 
788 	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
789 	if (pos) {
790 		u16 status;
791 		enum pci_bus_speed max;
792 
793 		pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
794 				     &status);
795 
796 		if (status & PCI_X_SSTATUS_533MHZ) {
797 			max = PCI_SPEED_133MHz_PCIX_533;
798 		} else if (status & PCI_X_SSTATUS_266MHZ) {
799 			max = PCI_SPEED_133MHz_PCIX_266;
800 		} else if (status & PCI_X_SSTATUS_133MHZ) {
801 			if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
802 				max = PCI_SPEED_133MHz_PCIX_ECC;
803 			else
804 				max = PCI_SPEED_133MHz_PCIX;
805 		} else {
806 			max = PCI_SPEED_66MHz_PCIX;
807 		}
808 
809 		bus->max_bus_speed = max;
810 		bus->cur_bus_speed = pcix_bus_speed[
811 			(status & PCI_X_SSTATUS_FREQ) >> 6];
812 
813 		return;
814 	}
815 
816 	if (pci_is_pcie(bridge)) {
817 		u32 linkcap;
818 		u16 linksta;
819 
820 		pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
821 		bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
822 		bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
823 
824 		pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
825 		pcie_update_link_speed(bus, linksta);
826 	}
827 }
828 
829 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
830 {
831 	struct irq_domain *d;
832 
833 	/* If the host bridge driver sets a MSI domain of the bridge, use it */
834 	d = dev_get_msi_domain(bus->bridge);
835 
836 	/*
837 	 * Any firmware interface that can resolve the msi_domain
838 	 * should be called from here.
839 	 */
840 	if (!d)
841 		d = pci_host_bridge_of_msi_domain(bus);
842 	if (!d)
843 		d = pci_host_bridge_acpi_msi_domain(bus);
844 
845 	/*
846 	 * If no IRQ domain was found via the OF tree, try looking it up
847 	 * directly through the fwnode_handle.
848 	 */
849 	if (!d) {
850 		struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
851 
852 		if (fwnode)
853 			d = irq_find_matching_fwnode(fwnode,
854 						     DOMAIN_BUS_PCI_MSI);
855 	}
856 
857 	return d;
858 }
859 
860 static void pci_set_bus_msi_domain(struct pci_bus *bus)
861 {
862 	struct irq_domain *d;
863 	struct pci_bus *b;
864 
865 	/*
866 	 * The bus can be a root bus, a subordinate bus, or a virtual bus
867 	 * created by an SR-IOV device.  Walk up to the first bridge device
868 	 * found or derive the domain from the host bridge.
869 	 */
870 	for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
871 		if (b->self)
872 			d = dev_get_msi_domain(&b->self->dev);
873 	}
874 
875 	if (!d)
876 		d = pci_host_bridge_msi_domain(b);
877 
878 	dev_set_msi_domain(&bus->dev, d);
879 }
880 
881 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
882 {
883 	struct device *parent = bridge->dev.parent;
884 	struct resource_entry *window, *next, *n;
885 	struct pci_bus *bus, *b;
886 	resource_size_t offset, next_offset;
887 	LIST_HEAD(resources);
888 	struct resource *res, *next_res;
889 	char addr[64], *fmt;
890 	const char *name;
891 	int err;
892 
893 	bus = pci_alloc_bus(NULL);
894 	if (!bus)
895 		return -ENOMEM;
896 
897 	bridge->bus = bus;
898 
899 	bus->sysdata = bridge->sysdata;
900 	bus->ops = bridge->ops;
901 	bus->number = bus->busn_res.start = bridge->busnr;
902 #ifdef CONFIG_PCI_DOMAINS_GENERIC
903 	if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
904 		bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
905 	else
906 		bus->domain_nr = bridge->domain_nr;
907 #endif
908 
909 	b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
910 	if (b) {
911 		/* Ignore it if we already got here via a different bridge */
912 		dev_dbg(&b->dev, "bus already known\n");
913 		err = -EEXIST;
914 		goto free;
915 	}
916 
917 	dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
918 		     bridge->busnr);
919 
920 	err = pcibios_root_bridge_prepare(bridge);
921 	if (err)
922 		goto free;
923 
924 	/* Temporarily move resources off the list */
925 	list_splice_init(&bridge->windows, &resources);
926 	err = device_add(&bridge->dev);
927 	if (err) {
928 		put_device(&bridge->dev);
929 		goto free;
930 	}
931 	bus->bridge = get_device(&bridge->dev);
932 	device_enable_async_suspend(bus->bridge);
933 	pci_set_bus_of_node(bus);
934 	pci_set_bus_msi_domain(bus);
935 	if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
936 	    !pci_host_of_has_msi_map(parent))
937 		bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
938 
939 	if (!parent)
940 		set_dev_node(bus->bridge, pcibus_to_node(bus));
941 
942 	bus->dev.class = &pcibus_class;
943 	bus->dev.parent = bus->bridge;
944 
945 	dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
946 	name = dev_name(&bus->dev);
947 
948 	err = device_register(&bus->dev);
949 	if (err)
950 		goto unregister;
951 
952 	pcibios_add_bus(bus);
953 
954 	if (bus->ops->add_bus) {
955 		err = bus->ops->add_bus(bus);
956 		if (WARN_ON(err < 0))
957 			dev_err(&bus->dev, "failed to add bus: %d\n", err);
958 	}
959 
960 	/* Create legacy_io and legacy_mem files for this bus */
961 	pci_create_legacy_files(bus);
962 
963 	if (parent)
964 		dev_info(parent, "PCI host bridge to bus %s\n", name);
965 	else
966 		pr_info("PCI host bridge to bus %s\n", name);
967 
968 	if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
969 		dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
970 
971 	/* Coalesce contiguous windows */
972 	resource_list_for_each_entry_safe(window, n, &resources) {
973 		if (list_is_last(&window->node, &resources))
974 			break;
975 
976 		next = list_next_entry(window, node);
977 		offset = window->offset;
978 		res = window->res;
979 		next_offset = next->offset;
980 		next_res = next->res;
981 
982 		if (res->flags != next_res->flags || offset != next_offset)
983 			continue;
984 
985 		if (res->end + 1 == next_res->start) {
986 			next_res->start = res->start;
987 			res->flags = res->start = res->end = 0;
988 		}
989 	}
990 
991 	/* Add initial resources to the bus */
992 	resource_list_for_each_entry_safe(window, n, &resources) {
993 		offset = window->offset;
994 		res = window->res;
995 		if (!res->end)
996 			continue;
997 
998 		list_move_tail(&window->node, &bridge->windows);
999 
1000 		if (res->flags & IORESOURCE_BUS)
1001 			pci_bus_insert_busn_res(bus, bus->number, res->end);
1002 		else
1003 			pci_bus_add_resource(bus, res, 0);
1004 
1005 		if (offset) {
1006 			if (resource_type(res) == IORESOURCE_IO)
1007 				fmt = " (bus address [%#06llx-%#06llx])";
1008 			else
1009 				fmt = " (bus address [%#010llx-%#010llx])";
1010 
1011 			snprintf(addr, sizeof(addr), fmt,
1012 				 (unsigned long long)(res->start - offset),
1013 				 (unsigned long long)(res->end - offset));
1014 		} else
1015 			addr[0] = '\0';
1016 
1017 		dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1018 	}
1019 
1020 	down_write(&pci_bus_sem);
1021 	list_add_tail(&bus->node, &pci_root_buses);
1022 	up_write(&pci_bus_sem);
1023 
1024 	return 0;
1025 
1026 unregister:
1027 	put_device(&bridge->dev);
1028 	device_del(&bridge->dev);
1029 
1030 free:
1031 	kfree(bus);
1032 	return err;
1033 }
1034 
1035 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1036 {
1037 	int pos;
1038 	u32 status;
1039 
1040 	/*
1041 	 * If extended config space isn't accessible on a bridge's primary
1042 	 * bus, we certainly can't access it on the secondary bus.
1043 	 */
1044 	if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1045 		return false;
1046 
1047 	/*
1048 	 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1049 	 * extended config space is accessible on the primary, it's also
1050 	 * accessible on the secondary.
1051 	 */
1052 	if (pci_is_pcie(bridge) &&
1053 	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1054 	     pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1055 	     pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1056 		return true;
1057 
1058 	/*
1059 	 * For the other bridge types:
1060 	 *   - PCI-to-PCI bridges
1061 	 *   - PCIe-to-PCI/PCI-X forward bridges
1062 	 *   - PCI/PCI-X-to-PCIe reverse bridges
1063 	 * extended config space on the secondary side is only accessible
1064 	 * if the bridge supports PCI-X Mode 2.
1065 	 */
1066 	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1067 	if (!pos)
1068 		return false;
1069 
1070 	pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1071 	return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1072 }
1073 
1074 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1075 					   struct pci_dev *bridge, int busnr)
1076 {
1077 	struct pci_bus *child;
1078 	struct pci_host_bridge *host;
1079 	int i;
1080 	int ret;
1081 
1082 	/* Allocate a new bus and inherit stuff from the parent */
1083 	child = pci_alloc_bus(parent);
1084 	if (!child)
1085 		return NULL;
1086 
1087 	child->parent = parent;
1088 	child->sysdata = parent->sysdata;
1089 	child->bus_flags = parent->bus_flags;
1090 
1091 	host = pci_find_host_bridge(parent);
1092 	if (host->child_ops)
1093 		child->ops = host->child_ops;
1094 	else
1095 		child->ops = parent->ops;
1096 
1097 	/*
1098 	 * Initialize some portions of the bus device, but don't register
1099 	 * it now as the parent is not properly set up yet.
1100 	 */
1101 	child->dev.class = &pcibus_class;
1102 	dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1103 
1104 	/* Set up the primary, secondary and subordinate bus numbers */
1105 	child->number = child->busn_res.start = busnr;
1106 	child->primary = parent->busn_res.start;
1107 	child->busn_res.end = 0xff;
1108 
1109 	if (!bridge) {
1110 		child->dev.parent = parent->bridge;
1111 		goto add_dev;
1112 	}
1113 
1114 	child->self = bridge;
1115 	child->bridge = get_device(&bridge->dev);
1116 	child->dev.parent = child->bridge;
1117 	pci_set_bus_of_node(child);
1118 	pci_set_bus_speed(child);
1119 
1120 	/*
1121 	 * Check whether extended config space is accessible on the child
1122 	 * bus.  Note that we currently assume it is always accessible on
1123 	 * the root bus.
1124 	 */
1125 	if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1126 		child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1127 		pci_info(child, "extended config space not accessible\n");
1128 	}
1129 
1130 	/* Set up default resource pointers and names */
1131 	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1132 		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1133 		child->resource[i]->name = child->name;
1134 	}
1135 	bridge->subordinate = child;
1136 
1137 add_dev:
1138 	pci_set_bus_msi_domain(child);
1139 	ret = device_register(&child->dev);
1140 	WARN_ON(ret < 0);
1141 
1142 	pcibios_add_bus(child);
1143 
1144 	if (child->ops->add_bus) {
1145 		ret = child->ops->add_bus(child);
1146 		if (WARN_ON(ret < 0))
1147 			dev_err(&child->dev, "failed to add bus: %d\n", ret);
1148 	}
1149 
1150 	/* Create legacy_io and legacy_mem files for this bus */
1151 	pci_create_legacy_files(child);
1152 
1153 	return child;
1154 }
1155 
1156 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1157 				int busnr)
1158 {
1159 	struct pci_bus *child;
1160 
1161 	child = pci_alloc_child_bus(parent, dev, busnr);
1162 	if (child) {
1163 		down_write(&pci_bus_sem);
1164 		list_add_tail(&child->node, &parent->children);
1165 		up_write(&pci_bus_sem);
1166 	}
1167 	return child;
1168 }
1169 EXPORT_SYMBOL(pci_add_new_bus);
1170 
1171 static void pci_enable_crs(struct pci_dev *pdev)
1172 {
1173 	u16 root_cap = 0;
1174 
1175 	/* Enable CRS Software Visibility if supported */
1176 	pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1177 	if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1178 		pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1179 					 PCI_EXP_RTCTL_CRSSVE);
1180 }
1181 
1182 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1183 					      unsigned int available_buses);
1184 /**
1185  * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1186  * numbers from EA capability.
1187  * @dev: Bridge
1188  * @sec: updated with secondary bus number from EA
1189  * @sub: updated with subordinate bus number from EA
1190  *
1191  * If @dev is a bridge with EA capability that specifies valid secondary
1192  * and subordinate bus numbers, return true with the bus numbers in @sec
1193  * and @sub.  Otherwise return false.
1194  */
1195 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1196 {
1197 	int ea, offset;
1198 	u32 dw;
1199 	u8 ea_sec, ea_sub;
1200 
1201 	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1202 		return false;
1203 
1204 	/* find PCI EA capability in list */
1205 	ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1206 	if (!ea)
1207 		return false;
1208 
1209 	offset = ea + PCI_EA_FIRST_ENT;
1210 	pci_read_config_dword(dev, offset, &dw);
1211 	ea_sec =  dw & PCI_EA_SEC_BUS_MASK;
1212 	ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1213 	if (ea_sec  == 0 || ea_sub < ea_sec)
1214 		return false;
1215 
1216 	*sec = ea_sec;
1217 	*sub = ea_sub;
1218 	return true;
1219 }
1220 
1221 /*
1222  * pci_scan_bridge_extend() - Scan buses behind a bridge
1223  * @bus: Parent bus the bridge is on
1224  * @dev: Bridge itself
1225  * @max: Starting subordinate number of buses behind this bridge
1226  * @available_buses: Total number of buses available for this bridge and
1227  *		     the devices below. After the minimal bus space has
1228  *		     been allocated the remaining buses will be
1229  *		     distributed equally between hotplug-capable bridges.
1230  * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1231  *        that need to be reconfigured.
1232  *
1233  * If it's a bridge, configure it and scan the bus behind it.
1234  * For CardBus bridges, we don't scan behind as the devices will
1235  * be handled by the bridge driver itself.
1236  *
1237  * We need to process bridges in two passes -- first we scan those
1238  * already configured by the BIOS and after we are done with all of
1239  * them, we proceed to assigning numbers to the remaining buses in
1240  * order to avoid overlaps between old and new bus numbers.
1241  *
1242  * Return: New subordinate number covering all buses behind this bridge.
1243  */
1244 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1245 				  int max, unsigned int available_buses,
1246 				  int pass)
1247 {
1248 	struct pci_bus *child;
1249 	int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1250 	u32 buses, i, j = 0;
1251 	u16 bctl;
1252 	u8 primary, secondary, subordinate;
1253 	int broken = 0;
1254 	bool fixed_buses;
1255 	u8 fixed_sec, fixed_sub;
1256 	int next_busnr;
1257 
1258 	/*
1259 	 * Make sure the bridge is powered on to be able to access config
1260 	 * space of devices below it.
1261 	 */
1262 	pm_runtime_get_sync(&dev->dev);
1263 
1264 	pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1265 	primary = buses & 0xFF;
1266 	secondary = (buses >> 8) & 0xFF;
1267 	subordinate = (buses >> 16) & 0xFF;
1268 
1269 	pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1270 		secondary, subordinate, pass);
1271 
1272 	if (!primary && (primary != bus->number) && secondary && subordinate) {
1273 		pci_warn(dev, "Primary bus is hard wired to 0\n");
1274 		primary = bus->number;
1275 	}
1276 
1277 	/* Check if setup is sensible at all */
1278 	if (!pass &&
1279 	    (primary != bus->number || secondary <= bus->number ||
1280 	     secondary > subordinate)) {
1281 		pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1282 			 secondary, subordinate);
1283 		broken = 1;
1284 	}
1285 
1286 	/*
1287 	 * Disable Master-Abort Mode during probing to avoid reporting of
1288 	 * bus errors in some architectures.
1289 	 */
1290 	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1291 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1292 			      bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1293 
1294 	pci_enable_crs(dev);
1295 
1296 	if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1297 	    !is_cardbus && !broken) {
1298 		unsigned int cmax, buses;
1299 
1300 		/*
1301 		 * Bus already configured by firmware, process it in the
1302 		 * first pass and just note the configuration.
1303 		 */
1304 		if (pass)
1305 			goto out;
1306 
1307 		/*
1308 		 * The bus might already exist for two reasons: Either we
1309 		 * are rescanning the bus or the bus is reachable through
1310 		 * more than one bridge. The second case can happen with
1311 		 * the i450NX chipset.
1312 		 */
1313 		child = pci_find_bus(pci_domain_nr(bus), secondary);
1314 		if (!child) {
1315 			child = pci_add_new_bus(bus, dev, secondary);
1316 			if (!child)
1317 				goto out;
1318 			child->primary = primary;
1319 			pci_bus_insert_busn_res(child, secondary, subordinate);
1320 			child->bridge_ctl = bctl;
1321 		}
1322 
1323 		buses = subordinate - secondary;
1324 		cmax = pci_scan_child_bus_extend(child, buses);
1325 		if (cmax > subordinate)
1326 			pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1327 				 subordinate, cmax);
1328 
1329 		/* Subordinate should equal child->busn_res.end */
1330 		if (subordinate > max)
1331 			max = subordinate;
1332 	} else {
1333 
1334 		/*
1335 		 * We need to assign a number to this bus which we always
1336 		 * do in the second pass.
1337 		 */
1338 		if (!pass) {
1339 			if (pcibios_assign_all_busses() || broken || is_cardbus)
1340 
1341 				/*
1342 				 * Temporarily disable forwarding of the
1343 				 * configuration cycles on all bridges in
1344 				 * this bus segment to avoid possible
1345 				 * conflicts in the second pass between two
1346 				 * bridges programmed with overlapping bus
1347 				 * ranges.
1348 				 */
1349 				pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1350 						       buses & ~0xffffff);
1351 			goto out;
1352 		}
1353 
1354 		/* Clear errors */
1355 		pci_write_config_word(dev, PCI_STATUS, 0xffff);
1356 
1357 		/* Read bus numbers from EA Capability (if present) */
1358 		fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1359 		if (fixed_buses)
1360 			next_busnr = fixed_sec;
1361 		else
1362 			next_busnr = max + 1;
1363 
1364 		/*
1365 		 * Prevent assigning a bus number that already exists.
1366 		 * This can happen when a bridge is hot-plugged, so in this
1367 		 * case we only re-scan this bus.
1368 		 */
1369 		child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1370 		if (!child) {
1371 			child = pci_add_new_bus(bus, dev, next_busnr);
1372 			if (!child)
1373 				goto out;
1374 			pci_bus_insert_busn_res(child, next_busnr,
1375 						bus->busn_res.end);
1376 		}
1377 		max++;
1378 		if (available_buses)
1379 			available_buses--;
1380 
1381 		buses = (buses & 0xff000000)
1382 		      | ((unsigned int)(child->primary)     <<  0)
1383 		      | ((unsigned int)(child->busn_res.start)   <<  8)
1384 		      | ((unsigned int)(child->busn_res.end) << 16);
1385 
1386 		/*
1387 		 * yenta.c forces a secondary latency timer of 176.
1388 		 * Copy that behaviour here.
1389 		 */
1390 		if (is_cardbus) {
1391 			buses &= ~0xff000000;
1392 			buses |= CARDBUS_LATENCY_TIMER << 24;
1393 		}
1394 
1395 		/* We need to blast all three values with a single write */
1396 		pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1397 
1398 		if (!is_cardbus) {
1399 			child->bridge_ctl = bctl;
1400 			max = pci_scan_child_bus_extend(child, available_buses);
1401 		} else {
1402 
1403 			/*
1404 			 * For CardBus bridges, we leave 4 bus numbers as
1405 			 * cards with a PCI-to-PCI bridge can be inserted
1406 			 * later.
1407 			 */
1408 			for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1409 				struct pci_bus *parent = bus;
1410 				if (pci_find_bus(pci_domain_nr(bus),
1411 							max+i+1))
1412 					break;
1413 				while (parent->parent) {
1414 					if ((!pcibios_assign_all_busses()) &&
1415 					    (parent->busn_res.end > max) &&
1416 					    (parent->busn_res.end <= max+i)) {
1417 						j = 1;
1418 					}
1419 					parent = parent->parent;
1420 				}
1421 				if (j) {
1422 
1423 					/*
1424 					 * Often, there are two CardBus
1425 					 * bridges -- try to leave one
1426 					 * valid bus number for each one.
1427 					 */
1428 					i /= 2;
1429 					break;
1430 				}
1431 			}
1432 			max += i;
1433 		}
1434 
1435 		/*
1436 		 * Set subordinate bus number to its real value.
1437 		 * If fixed subordinate bus number exists from EA
1438 		 * capability then use it.
1439 		 */
1440 		if (fixed_buses)
1441 			max = fixed_sub;
1442 		pci_bus_update_busn_res_end(child, max);
1443 		pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1444 	}
1445 
1446 	sprintf(child->name,
1447 		(is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1448 		pci_domain_nr(bus), child->number);
1449 
1450 	/* Check that all devices are accessible */
1451 	while (bus->parent) {
1452 		if ((child->busn_res.end > bus->busn_res.end) ||
1453 		    (child->number > bus->busn_res.end) ||
1454 		    (child->number < bus->number) ||
1455 		    (child->busn_res.end < bus->number)) {
1456 			dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1457 				 &child->busn_res);
1458 			break;
1459 		}
1460 		bus = bus->parent;
1461 	}
1462 
1463 out:
1464 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1465 
1466 	pm_runtime_put(&dev->dev);
1467 
1468 	return max;
1469 }
1470 
1471 /*
1472  * pci_scan_bridge() - Scan buses behind a bridge
1473  * @bus: Parent bus the bridge is on
1474  * @dev: Bridge itself
1475  * @max: Starting subordinate number of buses behind this bridge
1476  * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1477  *        that need to be reconfigured.
1478  *
1479  * If it's a bridge, configure it and scan the bus behind it.
1480  * For CardBus bridges, we don't scan behind as the devices will
1481  * be handled by the bridge driver itself.
1482  *
1483  * We need to process bridges in two passes -- first we scan those
1484  * already configured by the BIOS and after we are done with all of
1485  * them, we proceed to assigning numbers to the remaining buses in
1486  * order to avoid overlaps between old and new bus numbers.
1487  *
1488  * Return: New subordinate number covering all buses behind this bridge.
1489  */
1490 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1491 {
1492 	return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1493 }
1494 EXPORT_SYMBOL(pci_scan_bridge);
1495 
1496 /*
1497  * Read interrupt line and base address registers.
1498  * The architecture-dependent code can tweak these, of course.
1499  */
1500 static void pci_read_irq(struct pci_dev *dev)
1501 {
1502 	unsigned char irq;
1503 
1504 	/* VFs are not allowed to use INTx, so skip the config reads */
1505 	if (dev->is_virtfn) {
1506 		dev->pin = 0;
1507 		dev->irq = 0;
1508 		return;
1509 	}
1510 
1511 	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1512 	dev->pin = irq;
1513 	if (irq)
1514 		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1515 	dev->irq = irq;
1516 }
1517 
1518 void set_pcie_port_type(struct pci_dev *pdev)
1519 {
1520 	int pos;
1521 	u16 reg16;
1522 	int type;
1523 	struct pci_dev *parent;
1524 
1525 	pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1526 	if (!pos)
1527 		return;
1528 
1529 	pdev->pcie_cap = pos;
1530 	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1531 	pdev->pcie_flags_reg = reg16;
1532 	pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1533 	pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1534 
1535 	parent = pci_upstream_bridge(pdev);
1536 	if (!parent)
1537 		return;
1538 
1539 	/*
1540 	 * Some systems do not identify their upstream/downstream ports
1541 	 * correctly so detect impossible configurations here and correct
1542 	 * the port type accordingly.
1543 	 */
1544 	type = pci_pcie_type(pdev);
1545 	if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1546 		/*
1547 		 * If pdev claims to be downstream port but the parent
1548 		 * device is also downstream port assume pdev is actually
1549 		 * upstream port.
1550 		 */
1551 		if (pcie_downstream_port(parent)) {
1552 			pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1553 			pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1554 			pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1555 		}
1556 	} else if (type == PCI_EXP_TYPE_UPSTREAM) {
1557 		/*
1558 		 * If pdev claims to be upstream port but the parent
1559 		 * device is also upstream port assume pdev is actually
1560 		 * downstream port.
1561 		 */
1562 		if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1563 			pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1564 			pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1565 			pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1566 		}
1567 	}
1568 }
1569 
1570 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1571 {
1572 	u32 reg32;
1573 
1574 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1575 	if (reg32 & PCI_EXP_SLTCAP_HPC)
1576 		pdev->is_hotplug_bridge = 1;
1577 }
1578 
1579 static void set_pcie_thunderbolt(struct pci_dev *dev)
1580 {
1581 	u16 vsec;
1582 
1583 	/* Is the device part of a Thunderbolt controller? */
1584 	vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1585 	if (vsec)
1586 		dev->is_thunderbolt = 1;
1587 }
1588 
1589 static void set_pcie_untrusted(struct pci_dev *dev)
1590 {
1591 	struct pci_dev *parent;
1592 
1593 	/*
1594 	 * If the upstream bridge is untrusted we treat this device
1595 	 * untrusted as well.
1596 	 */
1597 	parent = pci_upstream_bridge(dev);
1598 	if (parent && (parent->untrusted || parent->external_facing))
1599 		dev->untrusted = true;
1600 }
1601 
1602 static void pci_set_removable(struct pci_dev *dev)
1603 {
1604 	struct pci_dev *parent = pci_upstream_bridge(dev);
1605 
1606 	/*
1607 	 * We (only) consider everything downstream from an external_facing
1608 	 * device to be removable by the user. We're mainly concerned with
1609 	 * consumer platforms with user accessible thunderbolt ports that are
1610 	 * vulnerable to DMA attacks, and we expect those ports to be marked by
1611 	 * the firmware as external_facing. Devices in traditional hotplug
1612 	 * slots can technically be removed, but the expectation is that unless
1613 	 * the port is marked with external_facing, such devices are less
1614 	 * accessible to user / may not be removed by end user, and thus not
1615 	 * exposed as "removable" to userspace.
1616 	 */
1617 	if (parent &&
1618 	    (parent->external_facing || dev_is_removable(&parent->dev)))
1619 		dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1620 }
1621 
1622 /**
1623  * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1624  * @dev: PCI device
1625  *
1626  * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1627  * when forwarding a type1 configuration request the bridge must check that
1628  * the extended register address field is zero.  The bridge is not permitted
1629  * to forward the transactions and must handle it as an Unsupported Request.
1630  * Some bridges do not follow this rule and simply drop the extended register
1631  * bits, resulting in the standard config space being aliased, every 256
1632  * bytes across the entire configuration space.  Test for this condition by
1633  * comparing the first dword of each potential alias to the vendor/device ID.
1634  * Known offenders:
1635  *   ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1636  *   AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1637  */
1638 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1639 {
1640 #ifdef CONFIG_PCI_QUIRKS
1641 	int pos;
1642 	u32 header, tmp;
1643 
1644 	pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1645 
1646 	for (pos = PCI_CFG_SPACE_SIZE;
1647 	     pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1648 		if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1649 		    || header != tmp)
1650 			return false;
1651 	}
1652 
1653 	return true;
1654 #else
1655 	return false;
1656 #endif
1657 }
1658 
1659 /**
1660  * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1661  * @dev: PCI device
1662  *
1663  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1664  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
1665  * access it.  Maybe we don't have a way to generate extended config space
1666  * accesses, or the device is behind a reverse Express bridge.  So we try
1667  * reading the dword at 0x100 which must either be 0 or a valid extended
1668  * capability header.
1669  */
1670 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1671 {
1672 	u32 status;
1673 	int pos = PCI_CFG_SPACE_SIZE;
1674 
1675 	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1676 		return PCI_CFG_SPACE_SIZE;
1677 	if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1678 		return PCI_CFG_SPACE_SIZE;
1679 
1680 	return PCI_CFG_SPACE_EXP_SIZE;
1681 }
1682 
1683 int pci_cfg_space_size(struct pci_dev *dev)
1684 {
1685 	int pos;
1686 	u32 status;
1687 	u16 class;
1688 
1689 #ifdef CONFIG_PCI_IOV
1690 	/*
1691 	 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1692 	 * implement a PCIe capability and therefore must implement extended
1693 	 * config space.  We can skip the NO_EXTCFG test below and the
1694 	 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1695 	 * the fact that the SR-IOV capability on the PF resides in extended
1696 	 * config space and must be accessible and non-aliased to have enabled
1697 	 * support for this VF.  This is a micro performance optimization for
1698 	 * systems supporting many VFs.
1699 	 */
1700 	if (dev->is_virtfn)
1701 		return PCI_CFG_SPACE_EXP_SIZE;
1702 #endif
1703 
1704 	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1705 		return PCI_CFG_SPACE_SIZE;
1706 
1707 	class = dev->class >> 8;
1708 	if (class == PCI_CLASS_BRIDGE_HOST)
1709 		return pci_cfg_space_size_ext(dev);
1710 
1711 	if (pci_is_pcie(dev))
1712 		return pci_cfg_space_size_ext(dev);
1713 
1714 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1715 	if (!pos)
1716 		return PCI_CFG_SPACE_SIZE;
1717 
1718 	pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1719 	if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1720 		return pci_cfg_space_size_ext(dev);
1721 
1722 	return PCI_CFG_SPACE_SIZE;
1723 }
1724 
1725 static u32 pci_class(struct pci_dev *dev)
1726 {
1727 	u32 class;
1728 
1729 #ifdef CONFIG_PCI_IOV
1730 	if (dev->is_virtfn)
1731 		return dev->physfn->sriov->class;
1732 #endif
1733 	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1734 	return class;
1735 }
1736 
1737 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1738 {
1739 #ifdef CONFIG_PCI_IOV
1740 	if (dev->is_virtfn) {
1741 		*vendor = dev->physfn->sriov->subsystem_vendor;
1742 		*device = dev->physfn->sriov->subsystem_device;
1743 		return;
1744 	}
1745 #endif
1746 	pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1747 	pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1748 }
1749 
1750 static u8 pci_hdr_type(struct pci_dev *dev)
1751 {
1752 	u8 hdr_type;
1753 
1754 #ifdef CONFIG_PCI_IOV
1755 	if (dev->is_virtfn)
1756 		return dev->physfn->sriov->hdr_type;
1757 #endif
1758 	pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1759 	return hdr_type;
1760 }
1761 
1762 #define LEGACY_IO_RESOURCE	(IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1763 
1764 /**
1765  * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1766  * @dev: PCI device
1767  *
1768  * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev.  Check this
1769  * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1770  */
1771 static int pci_intx_mask_broken(struct pci_dev *dev)
1772 {
1773 	u16 orig, toggle, new;
1774 
1775 	pci_read_config_word(dev, PCI_COMMAND, &orig);
1776 	toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1777 	pci_write_config_word(dev, PCI_COMMAND, toggle);
1778 	pci_read_config_word(dev, PCI_COMMAND, &new);
1779 
1780 	pci_write_config_word(dev, PCI_COMMAND, orig);
1781 
1782 	/*
1783 	 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1784 	 * r2.3, so strictly speaking, a device is not *broken* if it's not
1785 	 * writable.  But we'll live with the misnomer for now.
1786 	 */
1787 	if (new != toggle)
1788 		return 1;
1789 	return 0;
1790 }
1791 
1792 static void early_dump_pci_device(struct pci_dev *pdev)
1793 {
1794 	u32 value[256 / 4];
1795 	int i;
1796 
1797 	pci_info(pdev, "config space:\n");
1798 
1799 	for (i = 0; i < 256; i += 4)
1800 		pci_read_config_dword(pdev, i, &value[i / 4]);
1801 
1802 	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1803 		       value, 256, false);
1804 }
1805 
1806 /**
1807  * pci_setup_device - Fill in class and map information of a device
1808  * @dev: the device structure to fill
1809  *
1810  * Initialize the device structure with information about the device's
1811  * vendor,class,memory and IO-space addresses, IRQ lines etc.
1812  * Called at initialisation of the PCI subsystem and by CardBus services.
1813  * Returns 0 on success and negative if unknown type of device (not normal,
1814  * bridge or CardBus).
1815  */
1816 int pci_setup_device(struct pci_dev *dev)
1817 {
1818 	u32 class;
1819 	u16 cmd;
1820 	u8 hdr_type;
1821 	int pos = 0;
1822 	struct pci_bus_region region;
1823 	struct resource *res;
1824 
1825 	hdr_type = pci_hdr_type(dev);
1826 
1827 	dev->sysdata = dev->bus->sysdata;
1828 	dev->dev.parent = dev->bus->bridge;
1829 	dev->dev.bus = &pci_bus_type;
1830 	dev->hdr_type = hdr_type & 0x7f;
1831 	dev->multifunction = !!(hdr_type & 0x80);
1832 	dev->error_state = pci_channel_io_normal;
1833 	set_pcie_port_type(dev);
1834 
1835 	pci_set_of_node(dev);
1836 	pci_set_acpi_fwnode(dev);
1837 
1838 	pci_dev_assign_slot(dev);
1839 
1840 	/*
1841 	 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1842 	 * set this higher, assuming the system even supports it.
1843 	 */
1844 	dev->dma_mask = 0xffffffff;
1845 
1846 	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1847 		     dev->bus->number, PCI_SLOT(dev->devfn),
1848 		     PCI_FUNC(dev->devfn));
1849 
1850 	class = pci_class(dev);
1851 
1852 	dev->revision = class & 0xff;
1853 	dev->class = class >> 8;		    /* upper 3 bytes */
1854 
1855 	if (pci_early_dump)
1856 		early_dump_pci_device(dev);
1857 
1858 	/* Need to have dev->class ready */
1859 	dev->cfg_size = pci_cfg_space_size(dev);
1860 
1861 	/* Need to have dev->cfg_size ready */
1862 	set_pcie_thunderbolt(dev);
1863 
1864 	set_pcie_untrusted(dev);
1865 
1866 	/* "Unknown power state" */
1867 	dev->current_state = PCI_UNKNOWN;
1868 
1869 	/* Early fixups, before probing the BARs */
1870 	pci_fixup_device(pci_fixup_early, dev);
1871 
1872 	pci_set_removable(dev);
1873 
1874 	pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1875 		 dev->vendor, dev->device, dev->hdr_type, dev->class);
1876 
1877 	/* Device class may be changed after fixup */
1878 	class = dev->class >> 8;
1879 
1880 	if (dev->non_compliant_bars && !dev->mmio_always_on) {
1881 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
1882 		if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1883 			pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1884 			cmd &= ~PCI_COMMAND_IO;
1885 			cmd &= ~PCI_COMMAND_MEMORY;
1886 			pci_write_config_word(dev, PCI_COMMAND, cmd);
1887 		}
1888 	}
1889 
1890 	dev->broken_intx_masking = pci_intx_mask_broken(dev);
1891 
1892 	/* Clear errors left from system firmware */
1893 	pci_write_config_word(dev, PCI_STATUS, 0xffff);
1894 
1895 	switch (dev->hdr_type) {		    /* header type */
1896 	case PCI_HEADER_TYPE_NORMAL:		    /* standard header */
1897 		if (class == PCI_CLASS_BRIDGE_PCI)
1898 			goto bad;
1899 		pci_read_irq(dev);
1900 		pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1901 
1902 		pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1903 
1904 		/*
1905 		 * Do the ugly legacy mode stuff here rather than broken chip
1906 		 * quirk code. Legacy mode ATA controllers have fixed
1907 		 * addresses. These are not always echoed in BAR0-3, and
1908 		 * BAR0-3 in a few cases contain junk!
1909 		 */
1910 		if (class == PCI_CLASS_STORAGE_IDE) {
1911 			u8 progif;
1912 			pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1913 			if ((progif & 1) == 0) {
1914 				region.start = 0x1F0;
1915 				region.end = 0x1F7;
1916 				res = &dev->resource[0];
1917 				res->flags = LEGACY_IO_RESOURCE;
1918 				pcibios_bus_to_resource(dev->bus, res, &region);
1919 				pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1920 					 res);
1921 				region.start = 0x3F6;
1922 				region.end = 0x3F6;
1923 				res = &dev->resource[1];
1924 				res->flags = LEGACY_IO_RESOURCE;
1925 				pcibios_bus_to_resource(dev->bus, res, &region);
1926 				pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1927 					 res);
1928 			}
1929 			if ((progif & 4) == 0) {
1930 				region.start = 0x170;
1931 				region.end = 0x177;
1932 				res = &dev->resource[2];
1933 				res->flags = LEGACY_IO_RESOURCE;
1934 				pcibios_bus_to_resource(dev->bus, res, &region);
1935 				pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1936 					 res);
1937 				region.start = 0x376;
1938 				region.end = 0x376;
1939 				res = &dev->resource[3];
1940 				res->flags = LEGACY_IO_RESOURCE;
1941 				pcibios_bus_to_resource(dev->bus, res, &region);
1942 				pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1943 					 res);
1944 			}
1945 		}
1946 		break;
1947 
1948 	case PCI_HEADER_TYPE_BRIDGE:		    /* bridge header */
1949 		/*
1950 		 * The PCI-to-PCI bridge spec requires that subtractive
1951 		 * decoding (i.e. transparent) bridge must have programming
1952 		 * interface code of 0x01.
1953 		 */
1954 		pci_read_irq(dev);
1955 		dev->transparent = ((dev->class & 0xff) == 1);
1956 		pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1957 		pci_read_bridge_windows(dev);
1958 		set_pcie_hotplug_bridge(dev);
1959 		pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1960 		if (pos) {
1961 			pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1962 			pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1963 		}
1964 		break;
1965 
1966 	case PCI_HEADER_TYPE_CARDBUS:		    /* CardBus bridge header */
1967 		if (class != PCI_CLASS_BRIDGE_CARDBUS)
1968 			goto bad;
1969 		pci_read_irq(dev);
1970 		pci_read_bases(dev, 1, 0);
1971 		pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1972 		pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1973 		break;
1974 
1975 	default:				    /* unknown header */
1976 		pci_err(dev, "unknown header type %02x, ignoring device\n",
1977 			dev->hdr_type);
1978 		pci_release_of_node(dev);
1979 		return -EIO;
1980 
1981 	bad:
1982 		pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1983 			dev->class, dev->hdr_type);
1984 		dev->class = PCI_CLASS_NOT_DEFINED << 8;
1985 	}
1986 
1987 	/* We found a fine healthy device, go go go... */
1988 	return 0;
1989 }
1990 
1991 static void pci_configure_mps(struct pci_dev *dev)
1992 {
1993 	struct pci_dev *bridge = pci_upstream_bridge(dev);
1994 	int mps, mpss, p_mps, rc;
1995 
1996 	if (!pci_is_pcie(dev))
1997 		return;
1998 
1999 	/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2000 	if (dev->is_virtfn)
2001 		return;
2002 
2003 	/*
2004 	 * For Root Complex Integrated Endpoints, program the maximum
2005 	 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2006 	 */
2007 	if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2008 		if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2009 			mps = 128;
2010 		else
2011 			mps = 128 << dev->pcie_mpss;
2012 		rc = pcie_set_mps(dev, mps);
2013 		if (rc) {
2014 			pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2015 				 mps);
2016 		}
2017 		return;
2018 	}
2019 
2020 	if (!bridge || !pci_is_pcie(bridge))
2021 		return;
2022 
2023 	mps = pcie_get_mps(dev);
2024 	p_mps = pcie_get_mps(bridge);
2025 
2026 	if (mps == p_mps)
2027 		return;
2028 
2029 	if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2030 		pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2031 			 mps, pci_name(bridge), p_mps);
2032 		return;
2033 	}
2034 
2035 	/*
2036 	 * Fancier MPS configuration is done later by
2037 	 * pcie_bus_configure_settings()
2038 	 */
2039 	if (pcie_bus_config != PCIE_BUS_DEFAULT)
2040 		return;
2041 
2042 	mpss = 128 << dev->pcie_mpss;
2043 	if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2044 		pcie_set_mps(bridge, mpss);
2045 		pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2046 			 mpss, p_mps, 128 << bridge->pcie_mpss);
2047 		p_mps = pcie_get_mps(bridge);
2048 	}
2049 
2050 	rc = pcie_set_mps(dev, p_mps);
2051 	if (rc) {
2052 		pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2053 			 p_mps);
2054 		return;
2055 	}
2056 
2057 	pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2058 		 p_mps, mps, mpss);
2059 }
2060 
2061 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2062 {
2063 	struct pci_host_bridge *host;
2064 	u32 cap;
2065 	u16 ctl;
2066 	int ret;
2067 
2068 	if (!pci_is_pcie(dev))
2069 		return 0;
2070 
2071 	ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2072 	if (ret)
2073 		return 0;
2074 
2075 	if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2076 		return 0;
2077 
2078 	ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2079 	if (ret)
2080 		return 0;
2081 
2082 	host = pci_find_host_bridge(dev->bus);
2083 	if (!host)
2084 		return 0;
2085 
2086 	/*
2087 	 * If some device in the hierarchy doesn't handle Extended Tags
2088 	 * correctly, make sure they're disabled.
2089 	 */
2090 	if (host->no_ext_tags) {
2091 		if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2092 			pci_info(dev, "disabling Extended Tags\n");
2093 			pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2094 						   PCI_EXP_DEVCTL_EXT_TAG);
2095 		}
2096 		return 0;
2097 	}
2098 
2099 	if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2100 		pci_info(dev, "enabling Extended Tags\n");
2101 		pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2102 					 PCI_EXP_DEVCTL_EXT_TAG);
2103 	}
2104 	return 0;
2105 }
2106 
2107 /**
2108  * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2109  * @dev: PCI device to query
2110  *
2111  * Returns true if the device has enabled relaxed ordering attribute.
2112  */
2113 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2114 {
2115 	u16 v;
2116 
2117 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2118 
2119 	return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2120 }
2121 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2122 
2123 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2124 {
2125 	struct pci_dev *root;
2126 
2127 	/* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2128 	if (dev->is_virtfn)
2129 		return;
2130 
2131 	if (!pcie_relaxed_ordering_enabled(dev))
2132 		return;
2133 
2134 	/*
2135 	 * For now, we only deal with Relaxed Ordering issues with Root
2136 	 * Ports. Peer-to-Peer DMA is another can of worms.
2137 	 */
2138 	root = pcie_find_root_port(dev);
2139 	if (!root)
2140 		return;
2141 
2142 	if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2143 		pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2144 					   PCI_EXP_DEVCTL_RELAX_EN);
2145 		pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2146 	}
2147 }
2148 
2149 static void pci_configure_ltr(struct pci_dev *dev)
2150 {
2151 #ifdef CONFIG_PCIEASPM
2152 	struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2153 	struct pci_dev *bridge;
2154 	u32 cap, ctl;
2155 
2156 	if (!pci_is_pcie(dev))
2157 		return;
2158 
2159 	/* Read L1 PM substate capabilities */
2160 	dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2161 
2162 	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2163 	if (!(cap & PCI_EXP_DEVCAP2_LTR))
2164 		return;
2165 
2166 	pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2167 	if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2168 		if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2169 			dev->ltr_path = 1;
2170 			return;
2171 		}
2172 
2173 		bridge = pci_upstream_bridge(dev);
2174 		if (bridge && bridge->ltr_path)
2175 			dev->ltr_path = 1;
2176 
2177 		return;
2178 	}
2179 
2180 	if (!host->native_ltr)
2181 		return;
2182 
2183 	/*
2184 	 * Software must not enable LTR in an Endpoint unless the Root
2185 	 * Complex and all intermediate Switches indicate support for LTR.
2186 	 * PCIe r4.0, sec 6.18.
2187 	 */
2188 	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2189 		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2190 					 PCI_EXP_DEVCTL2_LTR_EN);
2191 		dev->ltr_path = 1;
2192 		return;
2193 	}
2194 
2195 	/*
2196 	 * If we're configuring a hot-added device, LTR was likely
2197 	 * disabled in the upstream bridge, so re-enable it before enabling
2198 	 * it in the new device.
2199 	 */
2200 	bridge = pci_upstream_bridge(dev);
2201 	if (bridge && bridge->ltr_path) {
2202 		pci_bridge_reconfigure_ltr(dev);
2203 		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2204 					 PCI_EXP_DEVCTL2_LTR_EN);
2205 		dev->ltr_path = 1;
2206 	}
2207 #endif
2208 }
2209 
2210 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2211 {
2212 #ifdef CONFIG_PCI_PASID
2213 	struct pci_dev *bridge;
2214 	int pcie_type;
2215 	u32 cap;
2216 
2217 	if (!pci_is_pcie(dev))
2218 		return;
2219 
2220 	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2221 	if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2222 		return;
2223 
2224 	pcie_type = pci_pcie_type(dev);
2225 	if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2226 	    pcie_type == PCI_EXP_TYPE_RC_END)
2227 		dev->eetlp_prefix_path = 1;
2228 	else {
2229 		bridge = pci_upstream_bridge(dev);
2230 		if (bridge && bridge->eetlp_prefix_path)
2231 			dev->eetlp_prefix_path = 1;
2232 	}
2233 #endif
2234 }
2235 
2236 static void pci_configure_serr(struct pci_dev *dev)
2237 {
2238 	u16 control;
2239 
2240 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2241 
2242 		/*
2243 		 * A bridge will not forward ERR_ messages coming from an
2244 		 * endpoint unless SERR# forwarding is enabled.
2245 		 */
2246 		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2247 		if (!(control & PCI_BRIDGE_CTL_SERR)) {
2248 			control |= PCI_BRIDGE_CTL_SERR;
2249 			pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2250 		}
2251 	}
2252 }
2253 
2254 static void pci_configure_device(struct pci_dev *dev)
2255 {
2256 	pci_configure_mps(dev);
2257 	pci_configure_extended_tags(dev, NULL);
2258 	pci_configure_relaxed_ordering(dev);
2259 	pci_configure_ltr(dev);
2260 	pci_configure_eetlp_prefix(dev);
2261 	pci_configure_serr(dev);
2262 
2263 	pci_acpi_program_hp_params(dev);
2264 }
2265 
2266 static void pci_release_capabilities(struct pci_dev *dev)
2267 {
2268 	pci_aer_exit(dev);
2269 	pci_rcec_exit(dev);
2270 	pci_iov_release(dev);
2271 	pci_free_cap_save_buffers(dev);
2272 }
2273 
2274 /**
2275  * pci_release_dev - Free a PCI device structure when all users of it are
2276  *		     finished
2277  * @dev: device that's been disconnected
2278  *
2279  * Will be called only by the device core when all users of this PCI device are
2280  * done.
2281  */
2282 static void pci_release_dev(struct device *dev)
2283 {
2284 	struct pci_dev *pci_dev;
2285 
2286 	pci_dev = to_pci_dev(dev);
2287 	pci_release_capabilities(pci_dev);
2288 	pci_release_of_node(pci_dev);
2289 	pcibios_release_device(pci_dev);
2290 	pci_bus_put(pci_dev->bus);
2291 	kfree(pci_dev->driver_override);
2292 	bitmap_free(pci_dev->dma_alias_mask);
2293 	dev_dbg(dev, "device released\n");
2294 	kfree(pci_dev);
2295 }
2296 
2297 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2298 {
2299 	struct pci_dev *dev;
2300 
2301 	dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2302 	if (!dev)
2303 		return NULL;
2304 
2305 	INIT_LIST_HEAD(&dev->bus_list);
2306 	dev->dev.type = &pci_dev_type;
2307 	dev->bus = pci_bus_get(bus);
2308 #ifdef CONFIG_PCI_MSI
2309 	raw_spin_lock_init(&dev->msi_lock);
2310 #endif
2311 	return dev;
2312 }
2313 EXPORT_SYMBOL(pci_alloc_dev);
2314 
2315 static bool pci_bus_crs_vendor_id(u32 l)
2316 {
2317 	return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
2318 }
2319 
2320 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2321 			     int timeout)
2322 {
2323 	int delay = 1;
2324 
2325 	if (!pci_bus_crs_vendor_id(*l))
2326 		return true;	/* not a CRS completion */
2327 
2328 	if (!timeout)
2329 		return false;	/* CRS, but caller doesn't want to wait */
2330 
2331 	/*
2332 	 * We got the reserved Vendor ID that indicates a completion with
2333 	 * Configuration Request Retry Status (CRS).  Retry until we get a
2334 	 * valid Vendor ID or we time out.
2335 	 */
2336 	while (pci_bus_crs_vendor_id(*l)) {
2337 		if (delay > timeout) {
2338 			pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2339 				pci_domain_nr(bus), bus->number,
2340 				PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2341 
2342 			return false;
2343 		}
2344 		if (delay >= 1000)
2345 			pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2346 				pci_domain_nr(bus), bus->number,
2347 				PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2348 
2349 		msleep(delay);
2350 		delay *= 2;
2351 
2352 		if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2353 			return false;
2354 	}
2355 
2356 	if (delay >= 1000)
2357 		pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2358 			pci_domain_nr(bus), bus->number,
2359 			PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2360 
2361 	return true;
2362 }
2363 
2364 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2365 					int timeout)
2366 {
2367 	if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2368 		return false;
2369 
2370 	/* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2371 	if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2372 	    *l == 0x0000ffff || *l == 0xffff0000)
2373 		return false;
2374 
2375 	if (pci_bus_crs_vendor_id(*l))
2376 		return pci_bus_wait_crs(bus, devfn, l, timeout);
2377 
2378 	return true;
2379 }
2380 
2381 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2382 				int timeout)
2383 {
2384 #ifdef CONFIG_PCI_QUIRKS
2385 	struct pci_dev *bridge = bus->self;
2386 
2387 	/*
2388 	 * Certain IDT switches have an issue where they improperly trigger
2389 	 * ACS Source Validation errors on completions for config reads.
2390 	 */
2391 	if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2392 	    bridge->device == 0x80b5)
2393 		return pci_idt_bus_quirk(bus, devfn, l, timeout);
2394 #endif
2395 
2396 	return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2397 }
2398 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2399 
2400 /*
2401  * Read the config data for a PCI device, sanity-check it,
2402  * and fill in the dev structure.
2403  */
2404 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2405 {
2406 	struct pci_dev *dev;
2407 	u32 l;
2408 
2409 	if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2410 		return NULL;
2411 
2412 	dev = pci_alloc_dev(bus);
2413 	if (!dev)
2414 		return NULL;
2415 
2416 	dev->devfn = devfn;
2417 	dev->vendor = l & 0xffff;
2418 	dev->device = (l >> 16) & 0xffff;
2419 
2420 	if (pci_setup_device(dev)) {
2421 		pci_bus_put(dev->bus);
2422 		kfree(dev);
2423 		return NULL;
2424 	}
2425 
2426 	return dev;
2427 }
2428 
2429 void pcie_report_downtraining(struct pci_dev *dev)
2430 {
2431 	if (!pci_is_pcie(dev))
2432 		return;
2433 
2434 	/* Look from the device up to avoid downstream ports with no devices */
2435 	if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2436 	    (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2437 	    (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2438 		return;
2439 
2440 	/* Multi-function PCIe devices share the same link/status */
2441 	if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2442 		return;
2443 
2444 	/* Print link status only if the device is constrained by the fabric */
2445 	__pcie_print_link_status(dev, false);
2446 }
2447 
2448 static void pci_init_capabilities(struct pci_dev *dev)
2449 {
2450 	pci_ea_init(dev);		/* Enhanced Allocation */
2451 	pci_msi_init(dev);		/* Disable MSI */
2452 	pci_msix_init(dev);		/* Disable MSI-X */
2453 
2454 	/* Buffers for saving PCIe and PCI-X capabilities */
2455 	pci_allocate_cap_save_buffers(dev);
2456 
2457 	pci_pm_init(dev);		/* Power Management */
2458 	pci_vpd_init(dev);		/* Vital Product Data */
2459 	pci_configure_ari(dev);		/* Alternative Routing-ID Forwarding */
2460 	pci_iov_init(dev);		/* Single Root I/O Virtualization */
2461 	pci_ats_init(dev);		/* Address Translation Services */
2462 	pci_pri_init(dev);		/* Page Request Interface */
2463 	pci_pasid_init(dev);		/* Process Address Space ID */
2464 	pci_acs_init(dev);		/* Access Control Services */
2465 	pci_ptm_init(dev);		/* Precision Time Measurement */
2466 	pci_aer_init(dev);		/* Advanced Error Reporting */
2467 	pci_dpc_init(dev);		/* Downstream Port Containment */
2468 	pci_rcec_init(dev);		/* Root Complex Event Collector */
2469 
2470 	pcie_report_downtraining(dev);
2471 	pci_init_reset_methods(dev);
2472 }
2473 
2474 /*
2475  * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2476  * devices. Firmware interfaces that can select the MSI domain on a
2477  * per-device basis should be called from here.
2478  */
2479 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2480 {
2481 	struct irq_domain *d;
2482 
2483 	/*
2484 	 * If a domain has been set through the pcibios_device_add()
2485 	 * callback, then this is the one (platform code knows best).
2486 	 */
2487 	d = dev_get_msi_domain(&dev->dev);
2488 	if (d)
2489 		return d;
2490 
2491 	/*
2492 	 * Let's see if we have a firmware interface able to provide
2493 	 * the domain.
2494 	 */
2495 	d = pci_msi_get_device_domain(dev);
2496 	if (d)
2497 		return d;
2498 
2499 	return NULL;
2500 }
2501 
2502 static void pci_set_msi_domain(struct pci_dev *dev)
2503 {
2504 	struct irq_domain *d;
2505 
2506 	/*
2507 	 * If the platform or firmware interfaces cannot supply a
2508 	 * device-specific MSI domain, then inherit the default domain
2509 	 * from the host bridge itself.
2510 	 */
2511 	d = pci_dev_msi_domain(dev);
2512 	if (!d)
2513 		d = dev_get_msi_domain(&dev->bus->dev);
2514 
2515 	dev_set_msi_domain(&dev->dev, d);
2516 }
2517 
2518 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2519 {
2520 	int ret;
2521 
2522 	pci_configure_device(dev);
2523 
2524 	device_initialize(&dev->dev);
2525 	dev->dev.release = pci_release_dev;
2526 
2527 	set_dev_node(&dev->dev, pcibus_to_node(bus));
2528 	dev->dev.dma_mask = &dev->dma_mask;
2529 	dev->dev.dma_parms = &dev->dma_parms;
2530 	dev->dev.coherent_dma_mask = 0xffffffffull;
2531 
2532 	dma_set_max_seg_size(&dev->dev, 65536);
2533 	dma_set_seg_boundary(&dev->dev, 0xffffffff);
2534 
2535 	/* Fix up broken headers */
2536 	pci_fixup_device(pci_fixup_header, dev);
2537 
2538 	pci_reassigndev_resource_alignment(dev);
2539 
2540 	dev->state_saved = false;
2541 
2542 	pci_init_capabilities(dev);
2543 
2544 	/*
2545 	 * Add the device to our list of discovered devices
2546 	 * and the bus list for fixup functions, etc.
2547 	 */
2548 	down_write(&pci_bus_sem);
2549 	list_add_tail(&dev->bus_list, &bus->devices);
2550 	up_write(&pci_bus_sem);
2551 
2552 	ret = pcibios_device_add(dev);
2553 	WARN_ON(ret < 0);
2554 
2555 	/* Set up MSI IRQ domain */
2556 	pci_set_msi_domain(dev);
2557 
2558 	/* Notifier could use PCI capabilities */
2559 	dev->match_driver = false;
2560 	ret = device_add(&dev->dev);
2561 	WARN_ON(ret < 0);
2562 }
2563 
2564 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2565 {
2566 	struct pci_dev *dev;
2567 
2568 	dev = pci_get_slot(bus, devfn);
2569 	if (dev) {
2570 		pci_dev_put(dev);
2571 		return dev;
2572 	}
2573 
2574 	dev = pci_scan_device(bus, devfn);
2575 	if (!dev)
2576 		return NULL;
2577 
2578 	pci_device_add(dev, bus);
2579 
2580 	return dev;
2581 }
2582 EXPORT_SYMBOL(pci_scan_single_device);
2583 
2584 static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2585 {
2586 	int pos;
2587 	u16 cap = 0;
2588 	unsigned int next_fn;
2589 
2590 	if (!dev)
2591 		return -ENODEV;
2592 
2593 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2594 	if (!pos)
2595 		return -ENODEV;
2596 
2597 	pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2598 	next_fn = PCI_ARI_CAP_NFN(cap);
2599 	if (next_fn <= fn)
2600 		return -ENODEV;	/* protect against malformed list */
2601 
2602 	return next_fn;
2603 }
2604 
2605 static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2606 {
2607 	if (pci_ari_enabled(bus))
2608 		return next_ari_fn(bus, dev, fn);
2609 
2610 	if (fn >= 7)
2611 		return -ENODEV;
2612 	/* only multifunction devices may have more functions */
2613 	if (dev && !dev->multifunction)
2614 		return -ENODEV;
2615 
2616 	return fn + 1;
2617 }
2618 
2619 static int only_one_child(struct pci_bus *bus)
2620 {
2621 	struct pci_dev *bridge = bus->self;
2622 
2623 	/*
2624 	 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2625 	 * we scan for all possible devices, not just Device 0.
2626 	 */
2627 	if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2628 		return 0;
2629 
2630 	/*
2631 	 * A PCIe Downstream Port normally leads to a Link with only Device
2632 	 * 0 on it (PCIe spec r3.1, sec 7.3.1).  As an optimization, scan
2633 	 * only for Device 0 in that situation.
2634 	 */
2635 	if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2636 		return 1;
2637 
2638 	return 0;
2639 }
2640 
2641 /**
2642  * pci_scan_slot - Scan a PCI slot on a bus for devices
2643  * @bus: PCI bus to scan
2644  * @devfn: slot number to scan (must have zero function)
2645  *
2646  * Scan a PCI slot on the specified PCI bus for devices, adding
2647  * discovered devices to the @bus->devices list.  New devices
2648  * will not have is_added set.
2649  *
2650  * Returns the number of new devices found.
2651  */
2652 int pci_scan_slot(struct pci_bus *bus, int devfn)
2653 {
2654 	struct pci_dev *dev;
2655 	int fn = 0, nr = 0;
2656 
2657 	if (only_one_child(bus) && (devfn > 0))
2658 		return 0; /* Already scanned the entire slot */
2659 
2660 	do {
2661 		dev = pci_scan_single_device(bus, devfn + fn);
2662 		if (dev) {
2663 			if (!pci_dev_is_added(dev))
2664 				nr++;
2665 			if (fn > 0)
2666 				dev->multifunction = 1;
2667 		} else if (fn == 0) {
2668 			/*
2669 			 * Function 0 is required unless we are running on
2670 			 * a hypervisor that passes through individual PCI
2671 			 * functions.
2672 			 */
2673 			if (!hypervisor_isolated_pci_functions())
2674 				break;
2675 		}
2676 		fn = next_fn(bus, dev, fn);
2677 	} while (fn >= 0);
2678 
2679 	/* Only one slot has PCIe device */
2680 	if (bus->self && nr)
2681 		pcie_aspm_init_link_state(bus->self);
2682 
2683 	return nr;
2684 }
2685 EXPORT_SYMBOL(pci_scan_slot);
2686 
2687 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2688 {
2689 	u8 *smpss = data;
2690 
2691 	if (!pci_is_pcie(dev))
2692 		return 0;
2693 
2694 	/*
2695 	 * We don't have a way to change MPS settings on devices that have
2696 	 * drivers attached.  A hot-added device might support only the minimum
2697 	 * MPS setting (MPS=128).  Therefore, if the fabric contains a bridge
2698 	 * where devices may be hot-added, we limit the fabric MPS to 128 so
2699 	 * hot-added devices will work correctly.
2700 	 *
2701 	 * However, if we hot-add a device to a slot directly below a Root
2702 	 * Port, it's impossible for there to be other existing devices below
2703 	 * the port.  We don't limit the MPS in this case because we can
2704 	 * reconfigure MPS on both the Root Port and the hot-added device,
2705 	 * and there are no other devices involved.
2706 	 *
2707 	 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2708 	 */
2709 	if (dev->is_hotplug_bridge &&
2710 	    pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2711 		*smpss = 0;
2712 
2713 	if (*smpss > dev->pcie_mpss)
2714 		*smpss = dev->pcie_mpss;
2715 
2716 	return 0;
2717 }
2718 
2719 static void pcie_write_mps(struct pci_dev *dev, int mps)
2720 {
2721 	int rc;
2722 
2723 	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2724 		mps = 128 << dev->pcie_mpss;
2725 
2726 		if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2727 		    dev->bus->self)
2728 
2729 			/*
2730 			 * For "Performance", the assumption is made that
2731 			 * downstream communication will never be larger than
2732 			 * the MRRS.  So, the MPS only needs to be configured
2733 			 * for the upstream communication.  This being the case,
2734 			 * walk from the top down and set the MPS of the child
2735 			 * to that of the parent bus.
2736 			 *
2737 			 * Configure the device MPS with the smaller of the
2738 			 * device MPSS or the bridge MPS (which is assumed to be
2739 			 * properly configured at this point to the largest
2740 			 * allowable MPS based on its parent bus).
2741 			 */
2742 			mps = min(mps, pcie_get_mps(dev->bus->self));
2743 	}
2744 
2745 	rc = pcie_set_mps(dev, mps);
2746 	if (rc)
2747 		pci_err(dev, "Failed attempting to set the MPS\n");
2748 }
2749 
2750 static void pcie_write_mrrs(struct pci_dev *dev)
2751 {
2752 	int rc, mrrs;
2753 
2754 	/*
2755 	 * In the "safe" case, do not configure the MRRS.  There appear to be
2756 	 * issues with setting MRRS to 0 on a number of devices.
2757 	 */
2758 	if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2759 		return;
2760 
2761 	/*
2762 	 * For max performance, the MRRS must be set to the largest supported
2763 	 * value.  However, it cannot be configured larger than the MPS the
2764 	 * device or the bus can support.  This should already be properly
2765 	 * configured by a prior call to pcie_write_mps().
2766 	 */
2767 	mrrs = pcie_get_mps(dev);
2768 
2769 	/*
2770 	 * MRRS is a R/W register.  Invalid values can be written, but a
2771 	 * subsequent read will verify if the value is acceptable or not.
2772 	 * If the MRRS value provided is not acceptable (e.g., too large),
2773 	 * shrink the value until it is acceptable to the HW.
2774 	 */
2775 	while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2776 		rc = pcie_set_readrq(dev, mrrs);
2777 		if (!rc)
2778 			break;
2779 
2780 		pci_warn(dev, "Failed attempting to set the MRRS\n");
2781 		mrrs /= 2;
2782 	}
2783 
2784 	if (mrrs < 128)
2785 		pci_err(dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
2786 }
2787 
2788 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2789 {
2790 	int mps, orig_mps;
2791 
2792 	if (!pci_is_pcie(dev))
2793 		return 0;
2794 
2795 	if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2796 	    pcie_bus_config == PCIE_BUS_DEFAULT)
2797 		return 0;
2798 
2799 	mps = 128 << *(u8 *)data;
2800 	orig_mps = pcie_get_mps(dev);
2801 
2802 	pcie_write_mps(dev, mps);
2803 	pcie_write_mrrs(dev);
2804 
2805 	pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2806 		 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2807 		 orig_mps, pcie_get_readrq(dev));
2808 
2809 	return 0;
2810 }
2811 
2812 /*
2813  * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2814  * parents then children fashion.  If this changes, then this code will not
2815  * work as designed.
2816  */
2817 void pcie_bus_configure_settings(struct pci_bus *bus)
2818 {
2819 	u8 smpss = 0;
2820 
2821 	if (!bus->self)
2822 		return;
2823 
2824 	if (!pci_is_pcie(bus->self))
2825 		return;
2826 
2827 	/*
2828 	 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2829 	 * to be aware of the MPS of the destination.  To work around this,
2830 	 * simply force the MPS of the entire system to the smallest possible.
2831 	 */
2832 	if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2833 		smpss = 0;
2834 
2835 	if (pcie_bus_config == PCIE_BUS_SAFE) {
2836 		smpss = bus->self->pcie_mpss;
2837 
2838 		pcie_find_smpss(bus->self, &smpss);
2839 		pci_walk_bus(bus, pcie_find_smpss, &smpss);
2840 	}
2841 
2842 	pcie_bus_configure_set(bus->self, &smpss);
2843 	pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2844 }
2845 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2846 
2847 /*
2848  * Called after each bus is probed, but before its children are examined.  This
2849  * is marked as __weak because multiple architectures define it.
2850  */
2851 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2852 {
2853        /* nothing to do, expected to be removed in the future */
2854 }
2855 
2856 /**
2857  * pci_scan_child_bus_extend() - Scan devices below a bus
2858  * @bus: Bus to scan for devices
2859  * @available_buses: Total number of buses available (%0 does not try to
2860  *		     extend beyond the minimal)
2861  *
2862  * Scans devices below @bus including subordinate buses. Returns new
2863  * subordinate number including all the found devices. Passing
2864  * @available_buses causes the remaining bus space to be distributed
2865  * equally between hotplug-capable bridges to allow future extension of the
2866  * hierarchy.
2867  */
2868 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2869 					      unsigned int available_buses)
2870 {
2871 	unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2872 	unsigned int start = bus->busn_res.start;
2873 	unsigned int devfn, cmax, max = start;
2874 	struct pci_dev *dev;
2875 
2876 	dev_dbg(&bus->dev, "scanning bus\n");
2877 
2878 	/* Go find them, Rover! */
2879 	for (devfn = 0; devfn < 256; devfn += 8)
2880 		pci_scan_slot(bus, devfn);
2881 
2882 	/* Reserve buses for SR-IOV capability */
2883 	used_buses = pci_iov_bus_range(bus);
2884 	max += used_buses;
2885 
2886 	/*
2887 	 * After performing arch-dependent fixup of the bus, look behind
2888 	 * all PCI-to-PCI bridges on this bus.
2889 	 */
2890 	if (!bus->is_added) {
2891 		dev_dbg(&bus->dev, "fixups for bus\n");
2892 		pcibios_fixup_bus(bus);
2893 		bus->is_added = 1;
2894 	}
2895 
2896 	/*
2897 	 * Calculate how many hotplug bridges and normal bridges there
2898 	 * are on this bus. We will distribute the additional available
2899 	 * buses between hotplug bridges.
2900 	 */
2901 	for_each_pci_bridge(dev, bus) {
2902 		if (dev->is_hotplug_bridge)
2903 			hotplug_bridges++;
2904 		else
2905 			normal_bridges++;
2906 	}
2907 
2908 	/*
2909 	 * Scan bridges that are already configured. We don't touch them
2910 	 * unless they are misconfigured (which will be done in the second
2911 	 * scan below).
2912 	 */
2913 	for_each_pci_bridge(dev, bus) {
2914 		cmax = max;
2915 		max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2916 
2917 		/*
2918 		 * Reserve one bus for each bridge now to avoid extending
2919 		 * hotplug bridges too much during the second scan below.
2920 		 */
2921 		used_buses++;
2922 		if (max - cmax > 1)
2923 			used_buses += max - cmax - 1;
2924 	}
2925 
2926 	/* Scan bridges that need to be reconfigured */
2927 	for_each_pci_bridge(dev, bus) {
2928 		unsigned int buses = 0;
2929 
2930 		if (!hotplug_bridges && normal_bridges == 1) {
2931 			/*
2932 			 * There is only one bridge on the bus (upstream
2933 			 * port) so it gets all available buses which it
2934 			 * can then distribute to the possible hotplug
2935 			 * bridges below.
2936 			 */
2937 			buses = available_buses;
2938 		} else if (dev->is_hotplug_bridge) {
2939 			/*
2940 			 * Distribute the extra buses between hotplug
2941 			 * bridges if any.
2942 			 */
2943 			buses = available_buses / hotplug_bridges;
2944 			buses = min(buses, available_buses - used_buses + 1);
2945 		}
2946 
2947 		cmax = max;
2948 		max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2949 		/* One bus is already accounted so don't add it again */
2950 		if (max - cmax > 1)
2951 			used_buses += max - cmax - 1;
2952 	}
2953 
2954 	/*
2955 	 * Make sure a hotplug bridge has at least the minimum requested
2956 	 * number of buses but allow it to grow up to the maximum available
2957 	 * bus number if there is room.
2958 	 */
2959 	if (bus->self && bus->self->is_hotplug_bridge) {
2960 		used_buses = max_t(unsigned int, available_buses,
2961 				   pci_hotplug_bus_size - 1);
2962 		if (max - start < used_buses) {
2963 			max = start + used_buses;
2964 
2965 			/* Do not allocate more buses than we have room left */
2966 			if (max > bus->busn_res.end)
2967 				max = bus->busn_res.end;
2968 
2969 			dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2970 				&bus->busn_res, max - start);
2971 		}
2972 	}
2973 
2974 	/*
2975 	 * We've scanned the bus and so we know all about what's on
2976 	 * the other side of any bridges that may be on this bus plus
2977 	 * any devices.
2978 	 *
2979 	 * Return how far we've got finding sub-buses.
2980 	 */
2981 	dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2982 	return max;
2983 }
2984 
2985 /**
2986  * pci_scan_child_bus() - Scan devices below a bus
2987  * @bus: Bus to scan for devices
2988  *
2989  * Scans devices below @bus including subordinate buses. Returns new
2990  * subordinate number including all the found devices.
2991  */
2992 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2993 {
2994 	return pci_scan_child_bus_extend(bus, 0);
2995 }
2996 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2997 
2998 /**
2999  * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3000  * @bridge: Host bridge to set up
3001  *
3002  * Default empty implementation.  Replace with an architecture-specific setup
3003  * routine, if necessary.
3004  */
3005 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3006 {
3007 	return 0;
3008 }
3009 
3010 void __weak pcibios_add_bus(struct pci_bus *bus)
3011 {
3012 }
3013 
3014 void __weak pcibios_remove_bus(struct pci_bus *bus)
3015 {
3016 }
3017 
3018 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3019 		struct pci_ops *ops, void *sysdata, struct list_head *resources)
3020 {
3021 	int error;
3022 	struct pci_host_bridge *bridge;
3023 
3024 	bridge = pci_alloc_host_bridge(0);
3025 	if (!bridge)
3026 		return NULL;
3027 
3028 	bridge->dev.parent = parent;
3029 
3030 	list_splice_init(resources, &bridge->windows);
3031 	bridge->sysdata = sysdata;
3032 	bridge->busnr = bus;
3033 	bridge->ops = ops;
3034 
3035 	error = pci_register_host_bridge(bridge);
3036 	if (error < 0)
3037 		goto err_out;
3038 
3039 	return bridge->bus;
3040 
3041 err_out:
3042 	put_device(&bridge->dev);
3043 	return NULL;
3044 }
3045 EXPORT_SYMBOL_GPL(pci_create_root_bus);
3046 
3047 int pci_host_probe(struct pci_host_bridge *bridge)
3048 {
3049 	struct pci_bus *bus, *child;
3050 	int ret;
3051 
3052 	ret = pci_scan_root_bus_bridge(bridge);
3053 	if (ret < 0) {
3054 		dev_err(bridge->dev.parent, "Scanning root bridge failed");
3055 		return ret;
3056 	}
3057 
3058 	bus = bridge->bus;
3059 
3060 	/*
3061 	 * We insert PCI resources into the iomem_resource and
3062 	 * ioport_resource trees in either pci_bus_claim_resources()
3063 	 * or pci_bus_assign_resources().
3064 	 */
3065 	if (pci_has_flag(PCI_PROBE_ONLY)) {
3066 		pci_bus_claim_resources(bus);
3067 	} else {
3068 		pci_bus_size_bridges(bus);
3069 		pci_bus_assign_resources(bus);
3070 
3071 		list_for_each_entry(child, &bus->children, node)
3072 			pcie_bus_configure_settings(child);
3073 	}
3074 
3075 	pci_bus_add_devices(bus);
3076 	return 0;
3077 }
3078 EXPORT_SYMBOL_GPL(pci_host_probe);
3079 
3080 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3081 {
3082 	struct resource *res = &b->busn_res;
3083 	struct resource *parent_res, *conflict;
3084 
3085 	res->start = bus;
3086 	res->end = bus_max;
3087 	res->flags = IORESOURCE_BUS;
3088 
3089 	if (!pci_is_root_bus(b))
3090 		parent_res = &b->parent->busn_res;
3091 	else {
3092 		parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3093 		res->flags |= IORESOURCE_PCI_FIXED;
3094 	}
3095 
3096 	conflict = request_resource_conflict(parent_res, res);
3097 
3098 	if (conflict)
3099 		dev_info(&b->dev,
3100 			   "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3101 			    res, pci_is_root_bus(b) ? "domain " : "",
3102 			    parent_res, conflict->name, conflict);
3103 
3104 	return conflict == NULL;
3105 }
3106 
3107 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3108 {
3109 	struct resource *res = &b->busn_res;
3110 	struct resource old_res = *res;
3111 	resource_size_t size;
3112 	int ret;
3113 
3114 	if (res->start > bus_max)
3115 		return -EINVAL;
3116 
3117 	size = bus_max - res->start + 1;
3118 	ret = adjust_resource(res, res->start, size);
3119 	dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3120 			&old_res, ret ? "can not be" : "is", bus_max);
3121 
3122 	if (!ret && !res->parent)
3123 		pci_bus_insert_busn_res(b, res->start, res->end);
3124 
3125 	return ret;
3126 }
3127 
3128 void pci_bus_release_busn_res(struct pci_bus *b)
3129 {
3130 	struct resource *res = &b->busn_res;
3131 	int ret;
3132 
3133 	if (!res->flags || !res->parent)
3134 		return;
3135 
3136 	ret = release_resource(res);
3137 	dev_info(&b->dev, "busn_res: %pR %s released\n",
3138 			res, ret ? "can not be" : "is");
3139 }
3140 
3141 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3142 {
3143 	struct resource_entry *window;
3144 	bool found = false;
3145 	struct pci_bus *b;
3146 	int max, bus, ret;
3147 
3148 	if (!bridge)
3149 		return -EINVAL;
3150 
3151 	resource_list_for_each_entry(window, &bridge->windows)
3152 		if (window->res->flags & IORESOURCE_BUS) {
3153 			bridge->busnr = window->res->start;
3154 			found = true;
3155 			break;
3156 		}
3157 
3158 	ret = pci_register_host_bridge(bridge);
3159 	if (ret < 0)
3160 		return ret;
3161 
3162 	b = bridge->bus;
3163 	bus = bridge->busnr;
3164 
3165 	if (!found) {
3166 		dev_info(&b->dev,
3167 		 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3168 			bus);
3169 		pci_bus_insert_busn_res(b, bus, 255);
3170 	}
3171 
3172 	max = pci_scan_child_bus(b);
3173 
3174 	if (!found)
3175 		pci_bus_update_busn_res_end(b, max);
3176 
3177 	return 0;
3178 }
3179 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3180 
3181 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3182 		struct pci_ops *ops, void *sysdata, struct list_head *resources)
3183 {
3184 	struct resource_entry *window;
3185 	bool found = false;
3186 	struct pci_bus *b;
3187 	int max;
3188 
3189 	resource_list_for_each_entry(window, resources)
3190 		if (window->res->flags & IORESOURCE_BUS) {
3191 			found = true;
3192 			break;
3193 		}
3194 
3195 	b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3196 	if (!b)
3197 		return NULL;
3198 
3199 	if (!found) {
3200 		dev_info(&b->dev,
3201 		 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3202 			bus);
3203 		pci_bus_insert_busn_res(b, bus, 255);
3204 	}
3205 
3206 	max = pci_scan_child_bus(b);
3207 
3208 	if (!found)
3209 		pci_bus_update_busn_res_end(b, max);
3210 
3211 	return b;
3212 }
3213 EXPORT_SYMBOL(pci_scan_root_bus);
3214 
3215 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3216 					void *sysdata)
3217 {
3218 	LIST_HEAD(resources);
3219 	struct pci_bus *b;
3220 
3221 	pci_add_resource(&resources, &ioport_resource);
3222 	pci_add_resource(&resources, &iomem_resource);
3223 	pci_add_resource(&resources, &busn_resource);
3224 	b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3225 	if (b) {
3226 		pci_scan_child_bus(b);
3227 	} else {
3228 		pci_free_resource_list(&resources);
3229 	}
3230 	return b;
3231 }
3232 EXPORT_SYMBOL(pci_scan_bus);
3233 
3234 /**
3235  * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3236  * @bridge: PCI bridge for the bus to scan
3237  *
3238  * Scan a PCI bus and child buses for new devices, add them,
3239  * and enable them, resizing bridge mmio/io resource if necessary
3240  * and possible.  The caller must ensure the child devices are already
3241  * removed for resizing to occur.
3242  *
3243  * Returns the max number of subordinate bus discovered.
3244  */
3245 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3246 {
3247 	unsigned int max;
3248 	struct pci_bus *bus = bridge->subordinate;
3249 
3250 	max = pci_scan_child_bus(bus);
3251 
3252 	pci_assign_unassigned_bridge_resources(bridge);
3253 
3254 	pci_bus_add_devices(bus);
3255 
3256 	return max;
3257 }
3258 
3259 /**
3260  * pci_rescan_bus - Scan a PCI bus for devices
3261  * @bus: PCI bus to scan
3262  *
3263  * Scan a PCI bus and child buses for new devices, add them,
3264  * and enable them.
3265  *
3266  * Returns the max number of subordinate bus discovered.
3267  */
3268 unsigned int pci_rescan_bus(struct pci_bus *bus)
3269 {
3270 	unsigned int max;
3271 
3272 	max = pci_scan_child_bus(bus);
3273 	pci_assign_unassigned_bus_resources(bus);
3274 	pci_bus_add_devices(bus);
3275 
3276 	return max;
3277 }
3278 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3279 
3280 /*
3281  * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3282  * routines should always be executed under this mutex.
3283  */
3284 static DEFINE_MUTEX(pci_rescan_remove_lock);
3285 
3286 void pci_lock_rescan_remove(void)
3287 {
3288 	mutex_lock(&pci_rescan_remove_lock);
3289 }
3290 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3291 
3292 void pci_unlock_rescan_remove(void)
3293 {
3294 	mutex_unlock(&pci_rescan_remove_lock);
3295 }
3296 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3297 
3298 static int __init pci_sort_bf_cmp(const struct device *d_a,
3299 				  const struct device *d_b)
3300 {
3301 	const struct pci_dev *a = to_pci_dev(d_a);
3302 	const struct pci_dev *b = to_pci_dev(d_b);
3303 
3304 	if      (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3305 	else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return  1;
3306 
3307 	if      (a->bus->number < b->bus->number) return -1;
3308 	else if (a->bus->number > b->bus->number) return  1;
3309 
3310 	if      (a->devfn < b->devfn) return -1;
3311 	else if (a->devfn > b->devfn) return  1;
3312 
3313 	return 0;
3314 }
3315 
3316 void __init pci_sort_breadthfirst(void)
3317 {
3318 	bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3319 }
3320 
3321 int pci_hp_add_bridge(struct pci_dev *dev)
3322 {
3323 	struct pci_bus *parent = dev->bus;
3324 	int busnr, start = parent->busn_res.start;
3325 	unsigned int available_buses = 0;
3326 	int end = parent->busn_res.end;
3327 
3328 	for (busnr = start; busnr <= end; busnr++) {
3329 		if (!pci_find_bus(pci_domain_nr(parent), busnr))
3330 			break;
3331 	}
3332 	if (busnr-- > end) {
3333 		pci_err(dev, "No bus number available for hot-added bridge\n");
3334 		return -1;
3335 	}
3336 
3337 	/* Scan bridges that are already configured */
3338 	busnr = pci_scan_bridge(parent, dev, busnr, 0);
3339 
3340 	/*
3341 	 * Distribute the available bus numbers between hotplug-capable
3342 	 * bridges to make extending the chain later possible.
3343 	 */
3344 	available_buses = end - busnr;
3345 
3346 	/* Scan bridges that need to be reconfigured */
3347 	pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3348 
3349 	if (!dev->subordinate)
3350 		return -1;
3351 
3352 	return 0;
3353 }
3354 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
3355