1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/msi.h> 11 #include <linux/of_device.h> 12 #include <linux/of_pci.h> 13 #include <linux/pci_hotplug.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/cpumask.h> 17 #include <linux/aer.h> 18 #include <linux/acpi.h> 19 #include <linux/hypervisor.h> 20 #include <linux/irqdomain.h> 21 #include <linux/pm_runtime.h> 22 #include "pci.h" 23 24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 25 #define CARDBUS_RESERVE_BUSNR 3 26 27 static struct resource busn_resource = { 28 .name = "PCI busn", 29 .start = 0, 30 .end = 255, 31 .flags = IORESOURCE_BUS, 32 }; 33 34 /* Ugh. Need to stop exporting this to modules. */ 35 LIST_HEAD(pci_root_buses); 36 EXPORT_SYMBOL(pci_root_buses); 37 38 static LIST_HEAD(pci_domain_busn_res_list); 39 40 struct pci_domain_busn_res { 41 struct list_head list; 42 struct resource res; 43 int domain_nr; 44 }; 45 46 static struct resource *get_pci_domain_busn_res(int domain_nr) 47 { 48 struct pci_domain_busn_res *r; 49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list) 51 if (r->domain_nr == domain_nr) 52 return &r->res; 53 54 r = kzalloc(sizeof(*r), GFP_KERNEL); 55 if (!r) 56 return NULL; 57 58 r->domain_nr = domain_nr; 59 r->res.start = 0; 60 r->res.end = 0xff; 61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 62 63 list_add_tail(&r->list, &pci_domain_busn_res_list); 64 65 return &r->res; 66 } 67 68 /* 69 * Some device drivers need know if PCI is initiated. 70 * Basically, we think PCI is not initiated when there 71 * is no device to be found on the pci_bus_type. 72 */ 73 int no_pci_devices(void) 74 { 75 struct device *dev; 76 int no_devices; 77 78 dev = bus_find_next_device(&pci_bus_type, NULL); 79 no_devices = (dev == NULL); 80 put_device(dev); 81 return no_devices; 82 } 83 EXPORT_SYMBOL(no_pci_devices); 84 85 /* 86 * PCI Bus Class 87 */ 88 static void release_pcibus_dev(struct device *dev) 89 { 90 struct pci_bus *pci_bus = to_pci_bus(dev); 91 92 put_device(pci_bus->bridge); 93 pci_bus_remove_resources(pci_bus); 94 pci_release_bus_of_node(pci_bus); 95 kfree(pci_bus); 96 } 97 98 static struct class pcibus_class = { 99 .name = "pci_bus", 100 .dev_release = &release_pcibus_dev, 101 .dev_groups = pcibus_groups, 102 }; 103 104 static int __init pcibus_class_init(void) 105 { 106 return class_register(&pcibus_class); 107 } 108 postcore_initcall(pcibus_class_init); 109 110 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 111 { 112 u64 size = mask & maxbase; /* Find the significant bits */ 113 if (!size) 114 return 0; 115 116 /* 117 * Get the lowest of them to find the decode size, and from that 118 * the extent. 119 */ 120 size = size & ~(size-1); 121 122 /* 123 * base == maxbase can be valid only if the BAR has already been 124 * programmed with all 1s. 125 */ 126 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 127 return 0; 128 129 return size; 130 } 131 132 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 133 { 134 u32 mem_type; 135 unsigned long flags; 136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 139 flags |= IORESOURCE_IO; 140 return flags; 141 } 142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 144 flags |= IORESOURCE_MEM; 145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 146 flags |= IORESOURCE_PREFETCH; 147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 149 switch (mem_type) { 150 case PCI_BASE_ADDRESS_MEM_TYPE_32: 151 break; 152 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 153 /* 1M mem BAR treated as 32-bit BAR */ 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_64: 156 flags |= IORESOURCE_MEM_64; 157 break; 158 default: 159 /* mem unknown type treated as 32-bit BAR */ 160 break; 161 } 162 return flags; 163 } 164 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 167 /** 168 * pci_read_base - Read a PCI BAR 169 * @dev: the PCI device 170 * @type: type of the BAR 171 * @res: resource buffer to be filled in 172 * @pos: BAR position in the config space 173 * 174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 175 */ 176 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 177 struct resource *res, unsigned int pos) 178 { 179 u32 l = 0, sz = 0, mask; 180 u64 l64, sz64, mask64; 181 u16 orig_cmd; 182 struct pci_bus_region region, inverted_region; 183 184 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 185 186 /* No printks while decoding is disabled! */ 187 if (!dev->mmio_always_on) { 188 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 189 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 190 pci_write_config_word(dev, PCI_COMMAND, 191 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 192 } 193 } 194 195 res->name = pci_name(dev); 196 197 pci_read_config_dword(dev, pos, &l); 198 pci_write_config_dword(dev, pos, l | mask); 199 pci_read_config_dword(dev, pos, &sz); 200 pci_write_config_dword(dev, pos, l); 201 202 /* 203 * All bits set in sz means the device isn't working properly. 204 * If the BAR isn't implemented, all bits must be 0. If it's a 205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 206 * 1 must be clear. 207 */ 208 if (sz == 0xffffffff) 209 sz = 0; 210 211 /* 212 * I don't know how l can have all bits set. Copied from old code. 213 * Maybe it fixes a bug on some ancient platform. 214 */ 215 if (l == 0xffffffff) 216 l = 0; 217 218 if (type == pci_bar_unknown) { 219 res->flags = decode_bar(dev, l); 220 res->flags |= IORESOURCE_SIZEALIGN; 221 if (res->flags & IORESOURCE_IO) { 222 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 223 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 224 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 225 } else { 226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 229 } 230 } else { 231 if (l & PCI_ROM_ADDRESS_ENABLE) 232 res->flags |= IORESOURCE_ROM_ENABLE; 233 l64 = l & PCI_ROM_ADDRESS_MASK; 234 sz64 = sz & PCI_ROM_ADDRESS_MASK; 235 mask64 = PCI_ROM_ADDRESS_MASK; 236 } 237 238 if (res->flags & IORESOURCE_MEM_64) { 239 pci_read_config_dword(dev, pos + 4, &l); 240 pci_write_config_dword(dev, pos + 4, ~0); 241 pci_read_config_dword(dev, pos + 4, &sz); 242 pci_write_config_dword(dev, pos + 4, l); 243 244 l64 |= ((u64)l << 32); 245 sz64 |= ((u64)sz << 32); 246 mask64 |= ((u64)~0 << 32); 247 } 248 249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 251 252 if (!sz64) 253 goto fail; 254 255 sz64 = pci_size(l64, sz64, mask64); 256 if (!sz64) { 257 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 258 pos); 259 goto fail; 260 } 261 262 if (res->flags & IORESOURCE_MEM_64) { 263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 264 && sz64 > 0x100000000ULL) { 265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 266 res->start = 0; 267 res->end = 0; 268 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 269 pos, (unsigned long long)sz64); 270 goto out; 271 } 272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) { 274 /* Above 32-bit boundary; try to reallocate */ 275 res->flags |= IORESOURCE_UNSET; 276 res->start = 0; 277 res->end = sz64 - 1; 278 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 279 pos, (unsigned long long)l64); 280 goto out; 281 } 282 } 283 284 region.start = l64; 285 region.end = l64 + sz64 - 1; 286 287 pcibios_bus_to_resource(dev->bus, res, ®ion); 288 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 289 290 /* 291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 292 * the corresponding resource address (the physical address used by 293 * the CPU. Converting that resource address back to a bus address 294 * should yield the original BAR value: 295 * 296 * resource_to_bus(bus_to_resource(A)) == A 297 * 298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 299 * be claimed by the device. 300 */ 301 if (inverted_region.start != region.start) { 302 res->flags |= IORESOURCE_UNSET; 303 res->start = 0; 304 res->end = region.end - region.start; 305 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 306 pos, (unsigned long long)region.start); 307 } 308 309 goto out; 310 311 312 fail: 313 res->flags = 0; 314 out: 315 if (res->flags) 316 pci_info(dev, "reg 0x%x: %pR\n", pos, res); 317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 319 } 320 321 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 322 { 323 unsigned int pos, reg; 324 325 if (dev->non_compliant_bars) 326 return; 327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 329 if (dev->is_virtfn) 330 return; 331 332 for (pos = 0; pos < howmany; pos++) { 333 struct resource *res = &dev->resource[pos]; 334 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 336 } 337 338 if (rom) { 339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 340 dev->rom_base_reg = rom; 341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 343 __pci_read_base(dev, pci_bar_mem32, res, rom); 344 } 345 } 346 347 static void pci_read_bridge_windows(struct pci_dev *bridge) 348 { 349 u16 io; 350 u32 pmem, tmp; 351 352 pci_read_config_word(bridge, PCI_IO_BASE, &io); 353 if (!io) { 354 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 355 pci_read_config_word(bridge, PCI_IO_BASE, &io); 356 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 357 } 358 if (io) 359 bridge->io_window = 1; 360 361 /* 362 * DECchip 21050 pass 2 errata: the bridge may miss an address 363 * disconnect boundary by one PCI data phase. Workaround: do not 364 * use prefetching on this device. 365 */ 366 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 367 return; 368 369 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 370 if (!pmem) { 371 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 372 0xffe0fff0); 373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 374 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 375 } 376 if (!pmem) 377 return; 378 379 bridge->pref_window = 1; 380 381 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 382 383 /* 384 * Bridge claims to have a 64-bit prefetchable memory 385 * window; verify that the upper bits are actually 386 * writable. 387 */ 388 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 389 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 390 0xffffffff); 391 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 392 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 393 if (tmp) 394 bridge->pref_64_window = 1; 395 } 396 } 397 398 static void pci_read_bridge_io(struct pci_bus *child) 399 { 400 struct pci_dev *dev = child->self; 401 u8 io_base_lo, io_limit_lo; 402 unsigned long io_mask, io_granularity, base, limit; 403 struct pci_bus_region region; 404 struct resource *res; 405 406 io_mask = PCI_IO_RANGE_MASK; 407 io_granularity = 0x1000; 408 if (dev->io_window_1k) { 409 /* Support 1K I/O space granularity */ 410 io_mask = PCI_IO_1K_RANGE_MASK; 411 io_granularity = 0x400; 412 } 413 414 res = child->resource[0]; 415 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 416 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 417 base = (io_base_lo & io_mask) << 8; 418 limit = (io_limit_lo & io_mask) << 8; 419 420 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 421 u16 io_base_hi, io_limit_hi; 422 423 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 424 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 425 base |= ((unsigned long) io_base_hi << 16); 426 limit |= ((unsigned long) io_limit_hi << 16); 427 } 428 429 if (base <= limit) { 430 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 431 region.start = base; 432 region.end = limit + io_granularity - 1; 433 pcibios_bus_to_resource(dev->bus, res, ®ion); 434 pci_info(dev, " bridge window %pR\n", res); 435 } 436 } 437 438 static void pci_read_bridge_mmio(struct pci_bus *child) 439 { 440 struct pci_dev *dev = child->self; 441 u16 mem_base_lo, mem_limit_lo; 442 unsigned long base, limit; 443 struct pci_bus_region region; 444 struct resource *res; 445 446 res = child->resource[1]; 447 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 448 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 449 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 450 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 451 if (base <= limit) { 452 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 453 region.start = base; 454 region.end = limit + 0xfffff; 455 pcibios_bus_to_resource(dev->bus, res, ®ion); 456 pci_info(dev, " bridge window %pR\n", res); 457 } 458 } 459 460 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 461 { 462 struct pci_dev *dev = child->self; 463 u16 mem_base_lo, mem_limit_lo; 464 u64 base64, limit64; 465 pci_bus_addr_t base, limit; 466 struct pci_bus_region region; 467 struct resource *res; 468 469 res = child->resource[2]; 470 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 471 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 472 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 473 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 474 475 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 476 u32 mem_base_hi, mem_limit_hi; 477 478 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 479 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 480 481 /* 482 * Some bridges set the base > limit by default, and some 483 * (broken) BIOSes do not initialize them. If we find 484 * this, just assume they are not being used. 485 */ 486 if (mem_base_hi <= mem_limit_hi) { 487 base64 |= (u64) mem_base_hi << 32; 488 limit64 |= (u64) mem_limit_hi << 32; 489 } 490 } 491 492 base = (pci_bus_addr_t) base64; 493 limit = (pci_bus_addr_t) limit64; 494 495 if (base != base64) { 496 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 497 (unsigned long long) base64); 498 return; 499 } 500 501 if (base <= limit) { 502 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 503 IORESOURCE_MEM | IORESOURCE_PREFETCH; 504 if (res->flags & PCI_PREF_RANGE_TYPE_64) 505 res->flags |= IORESOURCE_MEM_64; 506 region.start = base; 507 region.end = limit + 0xfffff; 508 pcibios_bus_to_resource(dev->bus, res, ®ion); 509 pci_info(dev, " bridge window %pR\n", res); 510 } 511 } 512 513 void pci_read_bridge_bases(struct pci_bus *child) 514 { 515 struct pci_dev *dev = child->self; 516 struct resource *res; 517 int i; 518 519 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 520 return; 521 522 pci_info(dev, "PCI bridge to %pR%s\n", 523 &child->busn_res, 524 dev->transparent ? " (subtractive decode)" : ""); 525 526 pci_bus_remove_resources(child); 527 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 528 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 529 530 pci_read_bridge_io(child); 531 pci_read_bridge_mmio(child); 532 pci_read_bridge_mmio_pref(child); 533 534 if (dev->transparent) { 535 pci_bus_for_each_resource(child->parent, res, i) { 536 if (res && res->flags) { 537 pci_bus_add_resource(child, res, 538 PCI_SUBTRACTIVE_DECODE); 539 pci_info(dev, " bridge window %pR (subtractive decode)\n", 540 res); 541 } 542 } 543 } 544 } 545 546 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 547 { 548 struct pci_bus *b; 549 550 b = kzalloc(sizeof(*b), GFP_KERNEL); 551 if (!b) 552 return NULL; 553 554 INIT_LIST_HEAD(&b->node); 555 INIT_LIST_HEAD(&b->children); 556 INIT_LIST_HEAD(&b->devices); 557 INIT_LIST_HEAD(&b->slots); 558 INIT_LIST_HEAD(&b->resources); 559 b->max_bus_speed = PCI_SPEED_UNKNOWN; 560 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 561 #ifdef CONFIG_PCI_DOMAINS_GENERIC 562 if (parent) 563 b->domain_nr = parent->domain_nr; 564 #endif 565 return b; 566 } 567 568 static void pci_release_host_bridge_dev(struct device *dev) 569 { 570 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 571 572 if (bridge->release_fn) 573 bridge->release_fn(bridge); 574 575 pci_free_resource_list(&bridge->windows); 576 pci_free_resource_list(&bridge->dma_ranges); 577 kfree(bridge); 578 } 579 580 static void pci_init_host_bridge(struct pci_host_bridge *bridge) 581 { 582 INIT_LIST_HEAD(&bridge->windows); 583 INIT_LIST_HEAD(&bridge->dma_ranges); 584 585 /* 586 * We assume we can manage these PCIe features. Some systems may 587 * reserve these for use by the platform itself, e.g., an ACPI BIOS 588 * may implement its own AER handling and use _OSC to prevent the 589 * OS from interfering. 590 */ 591 bridge->native_aer = 1; 592 bridge->native_pcie_hotplug = 1; 593 bridge->native_shpc_hotplug = 1; 594 bridge->native_pme = 1; 595 bridge->native_ltr = 1; 596 bridge->native_dpc = 1; 597 598 device_initialize(&bridge->dev); 599 } 600 601 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 602 { 603 struct pci_host_bridge *bridge; 604 605 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 606 if (!bridge) 607 return NULL; 608 609 pci_init_host_bridge(bridge); 610 bridge->dev.release = pci_release_host_bridge_dev; 611 612 return bridge; 613 } 614 EXPORT_SYMBOL(pci_alloc_host_bridge); 615 616 static void devm_pci_alloc_host_bridge_release(void *data) 617 { 618 pci_free_host_bridge(data); 619 } 620 621 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 622 size_t priv) 623 { 624 int ret; 625 struct pci_host_bridge *bridge; 626 627 bridge = pci_alloc_host_bridge(priv); 628 if (!bridge) 629 return NULL; 630 631 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 632 bridge); 633 if (ret) 634 return NULL; 635 636 return bridge; 637 } 638 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 639 640 void pci_free_host_bridge(struct pci_host_bridge *bridge) 641 { 642 put_device(&bridge->dev); 643 } 644 EXPORT_SYMBOL(pci_free_host_bridge); 645 646 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 647 static const unsigned char pcix_bus_speed[] = { 648 PCI_SPEED_UNKNOWN, /* 0 */ 649 PCI_SPEED_66MHz_PCIX, /* 1 */ 650 PCI_SPEED_100MHz_PCIX, /* 2 */ 651 PCI_SPEED_133MHz_PCIX, /* 3 */ 652 PCI_SPEED_UNKNOWN, /* 4 */ 653 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 654 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 655 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 656 PCI_SPEED_UNKNOWN, /* 8 */ 657 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 658 PCI_SPEED_100MHz_PCIX_266, /* A */ 659 PCI_SPEED_133MHz_PCIX_266, /* B */ 660 PCI_SPEED_UNKNOWN, /* C */ 661 PCI_SPEED_66MHz_PCIX_533, /* D */ 662 PCI_SPEED_100MHz_PCIX_533, /* E */ 663 PCI_SPEED_133MHz_PCIX_533 /* F */ 664 }; 665 666 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 667 const unsigned char pcie_link_speed[] = { 668 PCI_SPEED_UNKNOWN, /* 0 */ 669 PCIE_SPEED_2_5GT, /* 1 */ 670 PCIE_SPEED_5_0GT, /* 2 */ 671 PCIE_SPEED_8_0GT, /* 3 */ 672 PCIE_SPEED_16_0GT, /* 4 */ 673 PCIE_SPEED_32_0GT, /* 5 */ 674 PCI_SPEED_UNKNOWN, /* 6 */ 675 PCI_SPEED_UNKNOWN, /* 7 */ 676 PCI_SPEED_UNKNOWN, /* 8 */ 677 PCI_SPEED_UNKNOWN, /* 9 */ 678 PCI_SPEED_UNKNOWN, /* A */ 679 PCI_SPEED_UNKNOWN, /* B */ 680 PCI_SPEED_UNKNOWN, /* C */ 681 PCI_SPEED_UNKNOWN, /* D */ 682 PCI_SPEED_UNKNOWN, /* E */ 683 PCI_SPEED_UNKNOWN /* F */ 684 }; 685 EXPORT_SYMBOL_GPL(pcie_link_speed); 686 687 const char *pci_speed_string(enum pci_bus_speed speed) 688 { 689 /* Indexed by the pci_bus_speed enum */ 690 static const char *speed_strings[] = { 691 "33 MHz PCI", /* 0x00 */ 692 "66 MHz PCI", /* 0x01 */ 693 "66 MHz PCI-X", /* 0x02 */ 694 "100 MHz PCI-X", /* 0x03 */ 695 "133 MHz PCI-X", /* 0x04 */ 696 NULL, /* 0x05 */ 697 NULL, /* 0x06 */ 698 NULL, /* 0x07 */ 699 NULL, /* 0x08 */ 700 "66 MHz PCI-X 266", /* 0x09 */ 701 "100 MHz PCI-X 266", /* 0x0a */ 702 "133 MHz PCI-X 266", /* 0x0b */ 703 "Unknown AGP", /* 0x0c */ 704 "1x AGP", /* 0x0d */ 705 "2x AGP", /* 0x0e */ 706 "4x AGP", /* 0x0f */ 707 "8x AGP", /* 0x10 */ 708 "66 MHz PCI-X 533", /* 0x11 */ 709 "100 MHz PCI-X 533", /* 0x12 */ 710 "133 MHz PCI-X 533", /* 0x13 */ 711 "2.5 GT/s PCIe", /* 0x14 */ 712 "5.0 GT/s PCIe", /* 0x15 */ 713 "8.0 GT/s PCIe", /* 0x16 */ 714 "16.0 GT/s PCIe", /* 0x17 */ 715 "32.0 GT/s PCIe", /* 0x18 */ 716 }; 717 718 if (speed < ARRAY_SIZE(speed_strings)) 719 return speed_strings[speed]; 720 return "Unknown"; 721 } 722 EXPORT_SYMBOL_GPL(pci_speed_string); 723 724 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 725 { 726 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 727 } 728 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 729 730 static unsigned char agp_speeds[] = { 731 AGP_UNKNOWN, 732 AGP_1X, 733 AGP_2X, 734 AGP_4X, 735 AGP_8X 736 }; 737 738 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 739 { 740 int index = 0; 741 742 if (agpstat & 4) 743 index = 3; 744 else if (agpstat & 2) 745 index = 2; 746 else if (agpstat & 1) 747 index = 1; 748 else 749 goto out; 750 751 if (agp3) { 752 index += 2; 753 if (index == 5) 754 index = 0; 755 } 756 757 out: 758 return agp_speeds[index]; 759 } 760 761 static void pci_set_bus_speed(struct pci_bus *bus) 762 { 763 struct pci_dev *bridge = bus->self; 764 int pos; 765 766 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 767 if (!pos) 768 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 769 if (pos) { 770 u32 agpstat, agpcmd; 771 772 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 773 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 774 775 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 776 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 777 } 778 779 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 780 if (pos) { 781 u16 status; 782 enum pci_bus_speed max; 783 784 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 785 &status); 786 787 if (status & PCI_X_SSTATUS_533MHZ) { 788 max = PCI_SPEED_133MHz_PCIX_533; 789 } else if (status & PCI_X_SSTATUS_266MHZ) { 790 max = PCI_SPEED_133MHz_PCIX_266; 791 } else if (status & PCI_X_SSTATUS_133MHZ) { 792 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 793 max = PCI_SPEED_133MHz_PCIX_ECC; 794 else 795 max = PCI_SPEED_133MHz_PCIX; 796 } else { 797 max = PCI_SPEED_66MHz_PCIX; 798 } 799 800 bus->max_bus_speed = max; 801 bus->cur_bus_speed = pcix_bus_speed[ 802 (status & PCI_X_SSTATUS_FREQ) >> 6]; 803 804 return; 805 } 806 807 if (pci_is_pcie(bridge)) { 808 u32 linkcap; 809 u16 linksta; 810 811 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 812 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 813 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); 814 815 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 816 pcie_update_link_speed(bus, linksta); 817 } 818 } 819 820 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 821 { 822 struct irq_domain *d; 823 824 /* 825 * Any firmware interface that can resolve the msi_domain 826 * should be called from here. 827 */ 828 d = pci_host_bridge_of_msi_domain(bus); 829 if (!d) 830 d = pci_host_bridge_acpi_msi_domain(bus); 831 832 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 833 /* 834 * If no IRQ domain was found via the OF tree, try looking it up 835 * directly through the fwnode_handle. 836 */ 837 if (!d) { 838 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 839 840 if (fwnode) 841 d = irq_find_matching_fwnode(fwnode, 842 DOMAIN_BUS_PCI_MSI); 843 } 844 #endif 845 846 return d; 847 } 848 849 static void pci_set_bus_msi_domain(struct pci_bus *bus) 850 { 851 struct irq_domain *d; 852 struct pci_bus *b; 853 854 /* 855 * The bus can be a root bus, a subordinate bus, or a virtual bus 856 * created by an SR-IOV device. Walk up to the first bridge device 857 * found or derive the domain from the host bridge. 858 */ 859 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 860 if (b->self) 861 d = dev_get_msi_domain(&b->self->dev); 862 } 863 864 if (!d) 865 d = pci_host_bridge_msi_domain(b); 866 867 dev_set_msi_domain(&bus->dev, d); 868 } 869 870 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 871 { 872 struct device *parent = bridge->dev.parent; 873 struct resource_entry *window, *n; 874 struct pci_bus *bus, *b; 875 resource_size_t offset; 876 LIST_HEAD(resources); 877 struct resource *res; 878 char addr[64], *fmt; 879 const char *name; 880 int err; 881 882 bus = pci_alloc_bus(NULL); 883 if (!bus) 884 return -ENOMEM; 885 886 bridge->bus = bus; 887 888 /* Temporarily move resources off the list */ 889 list_splice_init(&bridge->windows, &resources); 890 bus->sysdata = bridge->sysdata; 891 bus->msi = bridge->msi; 892 bus->ops = bridge->ops; 893 bus->number = bus->busn_res.start = bridge->busnr; 894 #ifdef CONFIG_PCI_DOMAINS_GENERIC 895 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 896 #endif 897 898 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 899 if (b) { 900 /* Ignore it if we already got here via a different bridge */ 901 dev_dbg(&b->dev, "bus already known\n"); 902 err = -EEXIST; 903 goto free; 904 } 905 906 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 907 bridge->busnr); 908 909 err = pcibios_root_bridge_prepare(bridge); 910 if (err) 911 goto free; 912 913 err = device_add(&bridge->dev); 914 if (err) { 915 put_device(&bridge->dev); 916 goto free; 917 } 918 bus->bridge = get_device(&bridge->dev); 919 device_enable_async_suspend(bus->bridge); 920 pci_set_bus_of_node(bus); 921 pci_set_bus_msi_domain(bus); 922 923 if (!parent) 924 set_dev_node(bus->bridge, pcibus_to_node(bus)); 925 926 bus->dev.class = &pcibus_class; 927 bus->dev.parent = bus->bridge; 928 929 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 930 name = dev_name(&bus->dev); 931 932 err = device_register(&bus->dev); 933 if (err) 934 goto unregister; 935 936 pcibios_add_bus(bus); 937 938 /* Create legacy_io and legacy_mem files for this bus */ 939 pci_create_legacy_files(bus); 940 941 if (parent) 942 dev_info(parent, "PCI host bridge to bus %s\n", name); 943 else 944 pr_info("PCI host bridge to bus %s\n", name); 945 946 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 947 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 948 949 /* Add initial resources to the bus */ 950 resource_list_for_each_entry_safe(window, n, &resources) { 951 list_move_tail(&window->node, &bridge->windows); 952 offset = window->offset; 953 res = window->res; 954 955 if (res->flags & IORESOURCE_BUS) 956 pci_bus_insert_busn_res(bus, bus->number, res->end); 957 else 958 pci_bus_add_resource(bus, res, 0); 959 960 if (offset) { 961 if (resource_type(res) == IORESOURCE_IO) 962 fmt = " (bus address [%#06llx-%#06llx])"; 963 else 964 fmt = " (bus address [%#010llx-%#010llx])"; 965 966 snprintf(addr, sizeof(addr), fmt, 967 (unsigned long long)(res->start - offset), 968 (unsigned long long)(res->end - offset)); 969 } else 970 addr[0] = '\0'; 971 972 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 973 } 974 975 down_write(&pci_bus_sem); 976 list_add_tail(&bus->node, &pci_root_buses); 977 up_write(&pci_bus_sem); 978 979 return 0; 980 981 unregister: 982 put_device(&bridge->dev); 983 device_del(&bridge->dev); 984 985 free: 986 kfree(bus); 987 return err; 988 } 989 990 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 991 { 992 int pos; 993 u32 status; 994 995 /* 996 * If extended config space isn't accessible on a bridge's primary 997 * bus, we certainly can't access it on the secondary bus. 998 */ 999 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1000 return false; 1001 1002 /* 1003 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1004 * extended config space is accessible on the primary, it's also 1005 * accessible on the secondary. 1006 */ 1007 if (pci_is_pcie(bridge) && 1008 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1009 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1010 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1011 return true; 1012 1013 /* 1014 * For the other bridge types: 1015 * - PCI-to-PCI bridges 1016 * - PCIe-to-PCI/PCI-X forward bridges 1017 * - PCI/PCI-X-to-PCIe reverse bridges 1018 * extended config space on the secondary side is only accessible 1019 * if the bridge supports PCI-X Mode 2. 1020 */ 1021 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1022 if (!pos) 1023 return false; 1024 1025 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1026 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1027 } 1028 1029 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1030 struct pci_dev *bridge, int busnr) 1031 { 1032 struct pci_bus *child; 1033 int i; 1034 int ret; 1035 1036 /* Allocate a new bus and inherit stuff from the parent */ 1037 child = pci_alloc_bus(parent); 1038 if (!child) 1039 return NULL; 1040 1041 child->parent = parent; 1042 child->ops = parent->ops; 1043 child->msi = parent->msi; 1044 child->sysdata = parent->sysdata; 1045 child->bus_flags = parent->bus_flags; 1046 1047 /* 1048 * Initialize some portions of the bus device, but don't register 1049 * it now as the parent is not properly set up yet. 1050 */ 1051 child->dev.class = &pcibus_class; 1052 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1053 1054 /* Set up the primary, secondary and subordinate bus numbers */ 1055 child->number = child->busn_res.start = busnr; 1056 child->primary = parent->busn_res.start; 1057 child->busn_res.end = 0xff; 1058 1059 if (!bridge) { 1060 child->dev.parent = parent->bridge; 1061 goto add_dev; 1062 } 1063 1064 child->self = bridge; 1065 child->bridge = get_device(&bridge->dev); 1066 child->dev.parent = child->bridge; 1067 pci_set_bus_of_node(child); 1068 pci_set_bus_speed(child); 1069 1070 /* 1071 * Check whether extended config space is accessible on the child 1072 * bus. Note that we currently assume it is always accessible on 1073 * the root bus. 1074 */ 1075 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1076 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1077 pci_info(child, "extended config space not accessible\n"); 1078 } 1079 1080 /* Set up default resource pointers and names */ 1081 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1082 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1083 child->resource[i]->name = child->name; 1084 } 1085 bridge->subordinate = child; 1086 1087 add_dev: 1088 pci_set_bus_msi_domain(child); 1089 ret = device_register(&child->dev); 1090 WARN_ON(ret < 0); 1091 1092 pcibios_add_bus(child); 1093 1094 if (child->ops->add_bus) { 1095 ret = child->ops->add_bus(child); 1096 if (WARN_ON(ret < 0)) 1097 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1098 } 1099 1100 /* Create legacy_io and legacy_mem files for this bus */ 1101 pci_create_legacy_files(child); 1102 1103 return child; 1104 } 1105 1106 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1107 int busnr) 1108 { 1109 struct pci_bus *child; 1110 1111 child = pci_alloc_child_bus(parent, dev, busnr); 1112 if (child) { 1113 down_write(&pci_bus_sem); 1114 list_add_tail(&child->node, &parent->children); 1115 up_write(&pci_bus_sem); 1116 } 1117 return child; 1118 } 1119 EXPORT_SYMBOL(pci_add_new_bus); 1120 1121 static void pci_enable_crs(struct pci_dev *pdev) 1122 { 1123 u16 root_cap = 0; 1124 1125 /* Enable CRS Software Visibility if supported */ 1126 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1127 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1128 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1129 PCI_EXP_RTCTL_CRSSVE); 1130 } 1131 1132 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1133 unsigned int available_buses); 1134 /** 1135 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1136 * numbers from EA capability. 1137 * @dev: Bridge 1138 * @sec: updated with secondary bus number from EA 1139 * @sub: updated with subordinate bus number from EA 1140 * 1141 * If @dev is a bridge with EA capability that specifies valid secondary 1142 * and subordinate bus numbers, return true with the bus numbers in @sec 1143 * and @sub. Otherwise return false. 1144 */ 1145 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1146 { 1147 int ea, offset; 1148 u32 dw; 1149 u8 ea_sec, ea_sub; 1150 1151 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1152 return false; 1153 1154 /* find PCI EA capability in list */ 1155 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1156 if (!ea) 1157 return false; 1158 1159 offset = ea + PCI_EA_FIRST_ENT; 1160 pci_read_config_dword(dev, offset, &dw); 1161 ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1162 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1163 if (ea_sec == 0 || ea_sub < ea_sec) 1164 return false; 1165 1166 *sec = ea_sec; 1167 *sub = ea_sub; 1168 return true; 1169 } 1170 1171 /* 1172 * pci_scan_bridge_extend() - Scan buses behind a bridge 1173 * @bus: Parent bus the bridge is on 1174 * @dev: Bridge itself 1175 * @max: Starting subordinate number of buses behind this bridge 1176 * @available_buses: Total number of buses available for this bridge and 1177 * the devices below. After the minimal bus space has 1178 * been allocated the remaining buses will be 1179 * distributed equally between hotplug-capable bridges. 1180 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1181 * that need to be reconfigured. 1182 * 1183 * If it's a bridge, configure it and scan the bus behind it. 1184 * For CardBus bridges, we don't scan behind as the devices will 1185 * be handled by the bridge driver itself. 1186 * 1187 * We need to process bridges in two passes -- first we scan those 1188 * already configured by the BIOS and after we are done with all of 1189 * them, we proceed to assigning numbers to the remaining buses in 1190 * order to avoid overlaps between old and new bus numbers. 1191 * 1192 * Return: New subordinate number covering all buses behind this bridge. 1193 */ 1194 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1195 int max, unsigned int available_buses, 1196 int pass) 1197 { 1198 struct pci_bus *child; 1199 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1200 u32 buses, i, j = 0; 1201 u16 bctl; 1202 u8 primary, secondary, subordinate; 1203 int broken = 0; 1204 bool fixed_buses; 1205 u8 fixed_sec, fixed_sub; 1206 int next_busnr; 1207 1208 /* 1209 * Make sure the bridge is powered on to be able to access config 1210 * space of devices below it. 1211 */ 1212 pm_runtime_get_sync(&dev->dev); 1213 1214 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1215 primary = buses & 0xFF; 1216 secondary = (buses >> 8) & 0xFF; 1217 subordinate = (buses >> 16) & 0xFF; 1218 1219 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1220 secondary, subordinate, pass); 1221 1222 if (!primary && (primary != bus->number) && secondary && subordinate) { 1223 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1224 primary = bus->number; 1225 } 1226 1227 /* Check if setup is sensible at all */ 1228 if (!pass && 1229 (primary != bus->number || secondary <= bus->number || 1230 secondary > subordinate)) { 1231 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1232 secondary, subordinate); 1233 broken = 1; 1234 } 1235 1236 /* 1237 * Disable Master-Abort Mode during probing to avoid reporting of 1238 * bus errors in some architectures. 1239 */ 1240 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1241 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1242 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1243 1244 pci_enable_crs(dev); 1245 1246 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1247 !is_cardbus && !broken) { 1248 unsigned int cmax; 1249 1250 /* 1251 * Bus already configured by firmware, process it in the 1252 * first pass and just note the configuration. 1253 */ 1254 if (pass) 1255 goto out; 1256 1257 /* 1258 * The bus might already exist for two reasons: Either we 1259 * are rescanning the bus or the bus is reachable through 1260 * more than one bridge. The second case can happen with 1261 * the i450NX chipset. 1262 */ 1263 child = pci_find_bus(pci_domain_nr(bus), secondary); 1264 if (!child) { 1265 child = pci_add_new_bus(bus, dev, secondary); 1266 if (!child) 1267 goto out; 1268 child->primary = primary; 1269 pci_bus_insert_busn_res(child, secondary, subordinate); 1270 child->bridge_ctl = bctl; 1271 } 1272 1273 cmax = pci_scan_child_bus(child); 1274 if (cmax > subordinate) 1275 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1276 subordinate, cmax); 1277 1278 /* Subordinate should equal child->busn_res.end */ 1279 if (subordinate > max) 1280 max = subordinate; 1281 } else { 1282 1283 /* 1284 * We need to assign a number to this bus which we always 1285 * do in the second pass. 1286 */ 1287 if (!pass) { 1288 if (pcibios_assign_all_busses() || broken || is_cardbus) 1289 1290 /* 1291 * Temporarily disable forwarding of the 1292 * configuration cycles on all bridges in 1293 * this bus segment to avoid possible 1294 * conflicts in the second pass between two 1295 * bridges programmed with overlapping bus 1296 * ranges. 1297 */ 1298 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1299 buses & ~0xffffff); 1300 goto out; 1301 } 1302 1303 /* Clear errors */ 1304 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1305 1306 /* Read bus numbers from EA Capability (if present) */ 1307 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1308 if (fixed_buses) 1309 next_busnr = fixed_sec; 1310 else 1311 next_busnr = max + 1; 1312 1313 /* 1314 * Prevent assigning a bus number that already exists. 1315 * This can happen when a bridge is hot-plugged, so in this 1316 * case we only re-scan this bus. 1317 */ 1318 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1319 if (!child) { 1320 child = pci_add_new_bus(bus, dev, next_busnr); 1321 if (!child) 1322 goto out; 1323 pci_bus_insert_busn_res(child, next_busnr, 1324 bus->busn_res.end); 1325 } 1326 max++; 1327 if (available_buses) 1328 available_buses--; 1329 1330 buses = (buses & 0xff000000) 1331 | ((unsigned int)(child->primary) << 0) 1332 | ((unsigned int)(child->busn_res.start) << 8) 1333 | ((unsigned int)(child->busn_res.end) << 16); 1334 1335 /* 1336 * yenta.c forces a secondary latency timer of 176. 1337 * Copy that behaviour here. 1338 */ 1339 if (is_cardbus) { 1340 buses &= ~0xff000000; 1341 buses |= CARDBUS_LATENCY_TIMER << 24; 1342 } 1343 1344 /* We need to blast all three values with a single write */ 1345 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1346 1347 if (!is_cardbus) { 1348 child->bridge_ctl = bctl; 1349 max = pci_scan_child_bus_extend(child, available_buses); 1350 } else { 1351 1352 /* 1353 * For CardBus bridges, we leave 4 bus numbers as 1354 * cards with a PCI-to-PCI bridge can be inserted 1355 * later. 1356 */ 1357 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1358 struct pci_bus *parent = bus; 1359 if (pci_find_bus(pci_domain_nr(bus), 1360 max+i+1)) 1361 break; 1362 while (parent->parent) { 1363 if ((!pcibios_assign_all_busses()) && 1364 (parent->busn_res.end > max) && 1365 (parent->busn_res.end <= max+i)) { 1366 j = 1; 1367 } 1368 parent = parent->parent; 1369 } 1370 if (j) { 1371 1372 /* 1373 * Often, there are two CardBus 1374 * bridges -- try to leave one 1375 * valid bus number for each one. 1376 */ 1377 i /= 2; 1378 break; 1379 } 1380 } 1381 max += i; 1382 } 1383 1384 /* 1385 * Set subordinate bus number to its real value. 1386 * If fixed subordinate bus number exists from EA 1387 * capability then use it. 1388 */ 1389 if (fixed_buses) 1390 max = fixed_sub; 1391 pci_bus_update_busn_res_end(child, max); 1392 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1393 } 1394 1395 sprintf(child->name, 1396 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1397 pci_domain_nr(bus), child->number); 1398 1399 /* Check that all devices are accessible */ 1400 while (bus->parent) { 1401 if ((child->busn_res.end > bus->busn_res.end) || 1402 (child->number > bus->busn_res.end) || 1403 (child->number < bus->number) || 1404 (child->busn_res.end < bus->number)) { 1405 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1406 &child->busn_res); 1407 break; 1408 } 1409 bus = bus->parent; 1410 } 1411 1412 out: 1413 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1414 1415 pm_runtime_put(&dev->dev); 1416 1417 return max; 1418 } 1419 1420 /* 1421 * pci_scan_bridge() - Scan buses behind a bridge 1422 * @bus: Parent bus the bridge is on 1423 * @dev: Bridge itself 1424 * @max: Starting subordinate number of buses behind this bridge 1425 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1426 * that need to be reconfigured. 1427 * 1428 * If it's a bridge, configure it and scan the bus behind it. 1429 * For CardBus bridges, we don't scan behind as the devices will 1430 * be handled by the bridge driver itself. 1431 * 1432 * We need to process bridges in two passes -- first we scan those 1433 * already configured by the BIOS and after we are done with all of 1434 * them, we proceed to assigning numbers to the remaining buses in 1435 * order to avoid overlaps between old and new bus numbers. 1436 * 1437 * Return: New subordinate number covering all buses behind this bridge. 1438 */ 1439 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1440 { 1441 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1442 } 1443 EXPORT_SYMBOL(pci_scan_bridge); 1444 1445 /* 1446 * Read interrupt line and base address registers. 1447 * The architecture-dependent code can tweak these, of course. 1448 */ 1449 static void pci_read_irq(struct pci_dev *dev) 1450 { 1451 unsigned char irq; 1452 1453 /* VFs are not allowed to use INTx, so skip the config reads */ 1454 if (dev->is_virtfn) { 1455 dev->pin = 0; 1456 dev->irq = 0; 1457 return; 1458 } 1459 1460 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1461 dev->pin = irq; 1462 if (irq) 1463 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1464 dev->irq = irq; 1465 } 1466 1467 void set_pcie_port_type(struct pci_dev *pdev) 1468 { 1469 int pos; 1470 u16 reg16; 1471 int type; 1472 struct pci_dev *parent; 1473 1474 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1475 if (!pos) 1476 return; 1477 1478 pdev->pcie_cap = pos; 1479 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1480 pdev->pcie_flags_reg = reg16; 1481 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 1482 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1483 1484 parent = pci_upstream_bridge(pdev); 1485 if (!parent) 1486 return; 1487 1488 /* 1489 * Some systems do not identify their upstream/downstream ports 1490 * correctly so detect impossible configurations here and correct 1491 * the port type accordingly. 1492 */ 1493 type = pci_pcie_type(pdev); 1494 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1495 /* 1496 * If pdev claims to be downstream port but the parent 1497 * device is also downstream port assume pdev is actually 1498 * upstream port. 1499 */ 1500 if (pcie_downstream_port(parent)) { 1501 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1502 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1503 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1504 } 1505 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1506 /* 1507 * If pdev claims to be upstream port but the parent 1508 * device is also upstream port assume pdev is actually 1509 * downstream port. 1510 */ 1511 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1512 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1513 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1514 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1515 } 1516 } 1517 } 1518 1519 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1520 { 1521 u32 reg32; 1522 1523 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1524 if (reg32 & PCI_EXP_SLTCAP_HPC) 1525 pdev->is_hotplug_bridge = 1; 1526 } 1527 1528 static void set_pcie_thunderbolt(struct pci_dev *dev) 1529 { 1530 int vsec = 0; 1531 u32 header; 1532 1533 while ((vsec = pci_find_next_ext_capability(dev, vsec, 1534 PCI_EXT_CAP_ID_VNDR))) { 1535 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); 1536 1537 /* Is the device part of a Thunderbolt controller? */ 1538 if (dev->vendor == PCI_VENDOR_ID_INTEL && 1539 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { 1540 dev->is_thunderbolt = 1; 1541 return; 1542 } 1543 } 1544 } 1545 1546 static void set_pcie_untrusted(struct pci_dev *dev) 1547 { 1548 struct pci_dev *parent; 1549 1550 /* 1551 * If the upstream bridge is untrusted we treat this device 1552 * untrusted as well. 1553 */ 1554 parent = pci_upstream_bridge(dev); 1555 if (parent && parent->untrusted) 1556 dev->untrusted = true; 1557 } 1558 1559 /** 1560 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1561 * @dev: PCI device 1562 * 1563 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1564 * when forwarding a type1 configuration request the bridge must check that 1565 * the extended register address field is zero. The bridge is not permitted 1566 * to forward the transactions and must handle it as an Unsupported Request. 1567 * Some bridges do not follow this rule and simply drop the extended register 1568 * bits, resulting in the standard config space being aliased, every 256 1569 * bytes across the entire configuration space. Test for this condition by 1570 * comparing the first dword of each potential alias to the vendor/device ID. 1571 * Known offenders: 1572 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1573 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1574 */ 1575 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1576 { 1577 #ifdef CONFIG_PCI_QUIRKS 1578 int pos; 1579 u32 header, tmp; 1580 1581 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1582 1583 for (pos = PCI_CFG_SPACE_SIZE; 1584 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1585 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1586 || header != tmp) 1587 return false; 1588 } 1589 1590 return true; 1591 #else 1592 return false; 1593 #endif 1594 } 1595 1596 /** 1597 * pci_cfg_space_size - Get the configuration space size of the PCI device 1598 * @dev: PCI device 1599 * 1600 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1601 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1602 * access it. Maybe we don't have a way to generate extended config space 1603 * accesses, or the device is behind a reverse Express bridge. So we try 1604 * reading the dword at 0x100 which must either be 0 or a valid extended 1605 * capability header. 1606 */ 1607 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1608 { 1609 u32 status; 1610 int pos = PCI_CFG_SPACE_SIZE; 1611 1612 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1613 return PCI_CFG_SPACE_SIZE; 1614 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) 1615 return PCI_CFG_SPACE_SIZE; 1616 1617 return PCI_CFG_SPACE_EXP_SIZE; 1618 } 1619 1620 int pci_cfg_space_size(struct pci_dev *dev) 1621 { 1622 int pos; 1623 u32 status; 1624 u16 class; 1625 1626 #ifdef CONFIG_PCI_IOV 1627 /* 1628 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1629 * implement a PCIe capability and therefore must implement extended 1630 * config space. We can skip the NO_EXTCFG test below and the 1631 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1632 * the fact that the SR-IOV capability on the PF resides in extended 1633 * config space and must be accessible and non-aliased to have enabled 1634 * support for this VF. This is a micro performance optimization for 1635 * systems supporting many VFs. 1636 */ 1637 if (dev->is_virtfn) 1638 return PCI_CFG_SPACE_EXP_SIZE; 1639 #endif 1640 1641 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1642 return PCI_CFG_SPACE_SIZE; 1643 1644 class = dev->class >> 8; 1645 if (class == PCI_CLASS_BRIDGE_HOST) 1646 return pci_cfg_space_size_ext(dev); 1647 1648 if (pci_is_pcie(dev)) 1649 return pci_cfg_space_size_ext(dev); 1650 1651 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1652 if (!pos) 1653 return PCI_CFG_SPACE_SIZE; 1654 1655 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1656 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1657 return pci_cfg_space_size_ext(dev); 1658 1659 return PCI_CFG_SPACE_SIZE; 1660 } 1661 1662 static u32 pci_class(struct pci_dev *dev) 1663 { 1664 u32 class; 1665 1666 #ifdef CONFIG_PCI_IOV 1667 if (dev->is_virtfn) 1668 return dev->physfn->sriov->class; 1669 #endif 1670 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1671 return class; 1672 } 1673 1674 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1675 { 1676 #ifdef CONFIG_PCI_IOV 1677 if (dev->is_virtfn) { 1678 *vendor = dev->physfn->sriov->subsystem_vendor; 1679 *device = dev->physfn->sriov->subsystem_device; 1680 return; 1681 } 1682 #endif 1683 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1684 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1685 } 1686 1687 static u8 pci_hdr_type(struct pci_dev *dev) 1688 { 1689 u8 hdr_type; 1690 1691 #ifdef CONFIG_PCI_IOV 1692 if (dev->is_virtfn) 1693 return dev->physfn->sriov->hdr_type; 1694 #endif 1695 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1696 return hdr_type; 1697 } 1698 1699 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1700 1701 static void pci_msi_setup_pci_dev(struct pci_dev *dev) 1702 { 1703 /* 1704 * Disable the MSI hardware to avoid screaming interrupts 1705 * during boot. This is the power on reset default so 1706 * usually this should be a noop. 1707 */ 1708 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); 1709 if (dev->msi_cap) 1710 pci_msi_set_enable(dev, 0); 1711 1712 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1713 if (dev->msix_cap) 1714 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); 1715 } 1716 1717 /** 1718 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1719 * @dev: PCI device 1720 * 1721 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1722 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1723 */ 1724 static int pci_intx_mask_broken(struct pci_dev *dev) 1725 { 1726 u16 orig, toggle, new; 1727 1728 pci_read_config_word(dev, PCI_COMMAND, &orig); 1729 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1730 pci_write_config_word(dev, PCI_COMMAND, toggle); 1731 pci_read_config_word(dev, PCI_COMMAND, &new); 1732 1733 pci_write_config_word(dev, PCI_COMMAND, orig); 1734 1735 /* 1736 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1737 * r2.3, so strictly speaking, a device is not *broken* if it's not 1738 * writable. But we'll live with the misnomer for now. 1739 */ 1740 if (new != toggle) 1741 return 1; 1742 return 0; 1743 } 1744 1745 static void early_dump_pci_device(struct pci_dev *pdev) 1746 { 1747 u32 value[256 / 4]; 1748 int i; 1749 1750 pci_info(pdev, "config space:\n"); 1751 1752 for (i = 0; i < 256; i += 4) 1753 pci_read_config_dword(pdev, i, &value[i / 4]); 1754 1755 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1756 value, 256, false); 1757 } 1758 1759 /** 1760 * pci_setup_device - Fill in class and map information of a device 1761 * @dev: the device structure to fill 1762 * 1763 * Initialize the device structure with information about the device's 1764 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1765 * Called at initialisation of the PCI subsystem and by CardBus services. 1766 * Returns 0 on success and negative if unknown type of device (not normal, 1767 * bridge or CardBus). 1768 */ 1769 int pci_setup_device(struct pci_dev *dev) 1770 { 1771 u32 class; 1772 u16 cmd; 1773 u8 hdr_type; 1774 int pos = 0; 1775 struct pci_bus_region region; 1776 struct resource *res; 1777 1778 hdr_type = pci_hdr_type(dev); 1779 1780 dev->sysdata = dev->bus->sysdata; 1781 dev->dev.parent = dev->bus->bridge; 1782 dev->dev.bus = &pci_bus_type; 1783 dev->hdr_type = hdr_type & 0x7f; 1784 dev->multifunction = !!(hdr_type & 0x80); 1785 dev->error_state = pci_channel_io_normal; 1786 set_pcie_port_type(dev); 1787 1788 pci_dev_assign_slot(dev); 1789 1790 /* 1791 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1792 * set this higher, assuming the system even supports it. 1793 */ 1794 dev->dma_mask = 0xffffffff; 1795 1796 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1797 dev->bus->number, PCI_SLOT(dev->devfn), 1798 PCI_FUNC(dev->devfn)); 1799 1800 class = pci_class(dev); 1801 1802 dev->revision = class & 0xff; 1803 dev->class = class >> 8; /* upper 3 bytes */ 1804 1805 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 1806 dev->vendor, dev->device, dev->hdr_type, dev->class); 1807 1808 if (pci_early_dump) 1809 early_dump_pci_device(dev); 1810 1811 /* Need to have dev->class ready */ 1812 dev->cfg_size = pci_cfg_space_size(dev); 1813 1814 /* Need to have dev->cfg_size ready */ 1815 set_pcie_thunderbolt(dev); 1816 1817 set_pcie_untrusted(dev); 1818 1819 /* "Unknown power state" */ 1820 dev->current_state = PCI_UNKNOWN; 1821 1822 /* Early fixups, before probing the BARs */ 1823 pci_fixup_device(pci_fixup_early, dev); 1824 1825 /* Device class may be changed after fixup */ 1826 class = dev->class >> 8; 1827 1828 if (dev->non_compliant_bars && !dev->mmio_always_on) { 1829 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1830 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1831 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1832 cmd &= ~PCI_COMMAND_IO; 1833 cmd &= ~PCI_COMMAND_MEMORY; 1834 pci_write_config_word(dev, PCI_COMMAND, cmd); 1835 } 1836 } 1837 1838 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1839 1840 switch (dev->hdr_type) { /* header type */ 1841 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1842 if (class == PCI_CLASS_BRIDGE_PCI) 1843 goto bad; 1844 pci_read_irq(dev); 1845 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1846 1847 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1848 1849 /* 1850 * Do the ugly legacy mode stuff here rather than broken chip 1851 * quirk code. Legacy mode ATA controllers have fixed 1852 * addresses. These are not always echoed in BAR0-3, and 1853 * BAR0-3 in a few cases contain junk! 1854 */ 1855 if (class == PCI_CLASS_STORAGE_IDE) { 1856 u8 progif; 1857 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1858 if ((progif & 1) == 0) { 1859 region.start = 0x1F0; 1860 region.end = 0x1F7; 1861 res = &dev->resource[0]; 1862 res->flags = LEGACY_IO_RESOURCE; 1863 pcibios_bus_to_resource(dev->bus, res, ®ion); 1864 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1865 res); 1866 region.start = 0x3F6; 1867 region.end = 0x3F6; 1868 res = &dev->resource[1]; 1869 res->flags = LEGACY_IO_RESOURCE; 1870 pcibios_bus_to_resource(dev->bus, res, ®ion); 1871 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1872 res); 1873 } 1874 if ((progif & 4) == 0) { 1875 region.start = 0x170; 1876 region.end = 0x177; 1877 res = &dev->resource[2]; 1878 res->flags = LEGACY_IO_RESOURCE; 1879 pcibios_bus_to_resource(dev->bus, res, ®ion); 1880 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1881 res); 1882 region.start = 0x376; 1883 region.end = 0x376; 1884 res = &dev->resource[3]; 1885 res->flags = LEGACY_IO_RESOURCE; 1886 pcibios_bus_to_resource(dev->bus, res, ®ion); 1887 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1888 res); 1889 } 1890 } 1891 break; 1892 1893 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1894 /* 1895 * The PCI-to-PCI bridge spec requires that subtractive 1896 * decoding (i.e. transparent) bridge must have programming 1897 * interface code of 0x01. 1898 */ 1899 pci_read_irq(dev); 1900 dev->transparent = ((dev->class & 0xff) == 1); 1901 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1902 pci_read_bridge_windows(dev); 1903 set_pcie_hotplug_bridge(dev); 1904 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1905 if (pos) { 1906 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1907 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1908 } 1909 break; 1910 1911 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1912 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1913 goto bad; 1914 pci_read_irq(dev); 1915 pci_read_bases(dev, 1, 0); 1916 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1917 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1918 break; 1919 1920 default: /* unknown header */ 1921 pci_err(dev, "unknown header type %02x, ignoring device\n", 1922 dev->hdr_type); 1923 return -EIO; 1924 1925 bad: 1926 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1927 dev->class, dev->hdr_type); 1928 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1929 } 1930 1931 /* We found a fine healthy device, go go go... */ 1932 return 0; 1933 } 1934 1935 static void pci_configure_mps(struct pci_dev *dev) 1936 { 1937 struct pci_dev *bridge = pci_upstream_bridge(dev); 1938 int mps, mpss, p_mps, rc; 1939 1940 if (!pci_is_pcie(dev)) 1941 return; 1942 1943 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 1944 if (dev->is_virtfn) 1945 return; 1946 1947 /* 1948 * For Root Complex Integrated Endpoints, program the maximum 1949 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 1950 */ 1951 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 1952 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 1953 mps = 128; 1954 else 1955 mps = 128 << dev->pcie_mpss; 1956 rc = pcie_set_mps(dev, mps); 1957 if (rc) { 1958 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1959 mps); 1960 } 1961 return; 1962 } 1963 1964 if (!bridge || !pci_is_pcie(bridge)) 1965 return; 1966 1967 mps = pcie_get_mps(dev); 1968 p_mps = pcie_get_mps(bridge); 1969 1970 if (mps == p_mps) 1971 return; 1972 1973 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 1974 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1975 mps, pci_name(bridge), p_mps); 1976 return; 1977 } 1978 1979 /* 1980 * Fancier MPS configuration is done later by 1981 * pcie_bus_configure_settings() 1982 */ 1983 if (pcie_bus_config != PCIE_BUS_DEFAULT) 1984 return; 1985 1986 mpss = 128 << dev->pcie_mpss; 1987 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 1988 pcie_set_mps(bridge, mpss); 1989 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 1990 mpss, p_mps, 128 << bridge->pcie_mpss); 1991 p_mps = pcie_get_mps(bridge); 1992 } 1993 1994 rc = pcie_set_mps(dev, p_mps); 1995 if (rc) { 1996 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1997 p_mps); 1998 return; 1999 } 2000 2001 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2002 p_mps, mps, mpss); 2003 } 2004 2005 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2006 { 2007 struct pci_host_bridge *host; 2008 u32 cap; 2009 u16 ctl; 2010 int ret; 2011 2012 if (!pci_is_pcie(dev)) 2013 return 0; 2014 2015 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2016 if (ret) 2017 return 0; 2018 2019 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2020 return 0; 2021 2022 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2023 if (ret) 2024 return 0; 2025 2026 host = pci_find_host_bridge(dev->bus); 2027 if (!host) 2028 return 0; 2029 2030 /* 2031 * If some device in the hierarchy doesn't handle Extended Tags 2032 * correctly, make sure they're disabled. 2033 */ 2034 if (host->no_ext_tags) { 2035 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2036 pci_info(dev, "disabling Extended Tags\n"); 2037 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2038 PCI_EXP_DEVCTL_EXT_TAG); 2039 } 2040 return 0; 2041 } 2042 2043 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2044 pci_info(dev, "enabling Extended Tags\n"); 2045 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2046 PCI_EXP_DEVCTL_EXT_TAG); 2047 } 2048 return 0; 2049 } 2050 2051 /** 2052 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2053 * @dev: PCI device to query 2054 * 2055 * Returns true if the device has enabled relaxed ordering attribute. 2056 */ 2057 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2058 { 2059 u16 v; 2060 2061 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2062 2063 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2064 } 2065 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2066 2067 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2068 { 2069 struct pci_dev *root; 2070 2071 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2072 if (dev->is_virtfn) 2073 return; 2074 2075 if (!pcie_relaxed_ordering_enabled(dev)) 2076 return; 2077 2078 /* 2079 * For now, we only deal with Relaxed Ordering issues with Root 2080 * Ports. Peer-to-Peer DMA is another can of worms. 2081 */ 2082 root = pcie_find_root_port(dev); 2083 if (!root) 2084 return; 2085 2086 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2087 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2088 PCI_EXP_DEVCTL_RELAX_EN); 2089 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2090 } 2091 } 2092 2093 static void pci_configure_ltr(struct pci_dev *dev) 2094 { 2095 #ifdef CONFIG_PCIEASPM 2096 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2097 struct pci_dev *bridge; 2098 u32 cap, ctl; 2099 2100 if (!pci_is_pcie(dev)) 2101 return; 2102 2103 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2104 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2105 return; 2106 2107 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); 2108 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { 2109 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 2110 dev->ltr_path = 1; 2111 return; 2112 } 2113 2114 bridge = pci_upstream_bridge(dev); 2115 if (bridge && bridge->ltr_path) 2116 dev->ltr_path = 1; 2117 2118 return; 2119 } 2120 2121 if (!host->native_ltr) 2122 return; 2123 2124 /* 2125 * Software must not enable LTR in an Endpoint unless the Root 2126 * Complex and all intermediate Switches indicate support for LTR. 2127 * PCIe r4.0, sec 6.18. 2128 */ 2129 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 2130 ((bridge = pci_upstream_bridge(dev)) && 2131 bridge->ltr_path)) { 2132 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2133 PCI_EXP_DEVCTL2_LTR_EN); 2134 dev->ltr_path = 1; 2135 } 2136 #endif 2137 } 2138 2139 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2140 { 2141 #ifdef CONFIG_PCI_PASID 2142 struct pci_dev *bridge; 2143 int pcie_type; 2144 u32 cap; 2145 2146 if (!pci_is_pcie(dev)) 2147 return; 2148 2149 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2150 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2151 return; 2152 2153 pcie_type = pci_pcie_type(dev); 2154 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2155 pcie_type == PCI_EXP_TYPE_RC_END) 2156 dev->eetlp_prefix_path = 1; 2157 else { 2158 bridge = pci_upstream_bridge(dev); 2159 if (bridge && bridge->eetlp_prefix_path) 2160 dev->eetlp_prefix_path = 1; 2161 } 2162 #endif 2163 } 2164 2165 static void pci_configure_serr(struct pci_dev *dev) 2166 { 2167 u16 control; 2168 2169 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2170 2171 /* 2172 * A bridge will not forward ERR_ messages coming from an 2173 * endpoint unless SERR# forwarding is enabled. 2174 */ 2175 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2176 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2177 control |= PCI_BRIDGE_CTL_SERR; 2178 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2179 } 2180 } 2181 } 2182 2183 static void pci_configure_device(struct pci_dev *dev) 2184 { 2185 pci_configure_mps(dev); 2186 pci_configure_extended_tags(dev, NULL); 2187 pci_configure_relaxed_ordering(dev); 2188 pci_configure_ltr(dev); 2189 pci_configure_eetlp_prefix(dev); 2190 pci_configure_serr(dev); 2191 2192 pci_acpi_program_hp_params(dev); 2193 } 2194 2195 static void pci_release_capabilities(struct pci_dev *dev) 2196 { 2197 pci_aer_exit(dev); 2198 pci_vpd_release(dev); 2199 pci_iov_release(dev); 2200 pci_free_cap_save_buffers(dev); 2201 } 2202 2203 /** 2204 * pci_release_dev - Free a PCI device structure when all users of it are 2205 * finished 2206 * @dev: device that's been disconnected 2207 * 2208 * Will be called only by the device core when all users of this PCI device are 2209 * done. 2210 */ 2211 static void pci_release_dev(struct device *dev) 2212 { 2213 struct pci_dev *pci_dev; 2214 2215 pci_dev = to_pci_dev(dev); 2216 pci_release_capabilities(pci_dev); 2217 pci_release_of_node(pci_dev); 2218 pcibios_release_device(pci_dev); 2219 pci_bus_put(pci_dev->bus); 2220 kfree(pci_dev->driver_override); 2221 bitmap_free(pci_dev->dma_alias_mask); 2222 kfree(pci_dev); 2223 } 2224 2225 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2226 { 2227 struct pci_dev *dev; 2228 2229 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2230 if (!dev) 2231 return NULL; 2232 2233 INIT_LIST_HEAD(&dev->bus_list); 2234 dev->dev.type = &pci_dev_type; 2235 dev->bus = pci_bus_get(bus); 2236 2237 return dev; 2238 } 2239 EXPORT_SYMBOL(pci_alloc_dev); 2240 2241 static bool pci_bus_crs_vendor_id(u32 l) 2242 { 2243 return (l & 0xffff) == 0x0001; 2244 } 2245 2246 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2247 int timeout) 2248 { 2249 int delay = 1; 2250 2251 if (!pci_bus_crs_vendor_id(*l)) 2252 return true; /* not a CRS completion */ 2253 2254 if (!timeout) 2255 return false; /* CRS, but caller doesn't want to wait */ 2256 2257 /* 2258 * We got the reserved Vendor ID that indicates a completion with 2259 * Configuration Request Retry Status (CRS). Retry until we get a 2260 * valid Vendor ID or we time out. 2261 */ 2262 while (pci_bus_crs_vendor_id(*l)) { 2263 if (delay > timeout) { 2264 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2265 pci_domain_nr(bus), bus->number, 2266 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2267 2268 return false; 2269 } 2270 if (delay >= 1000) 2271 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2272 pci_domain_nr(bus), bus->number, 2273 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2274 2275 msleep(delay); 2276 delay *= 2; 2277 2278 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2279 return false; 2280 } 2281 2282 if (delay >= 1000) 2283 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2284 pci_domain_nr(bus), bus->number, 2285 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2286 2287 return true; 2288 } 2289 2290 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2291 int timeout) 2292 { 2293 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2294 return false; 2295 2296 /* Some broken boards return 0 or ~0 if a slot is empty: */ 2297 if (*l == 0xffffffff || *l == 0x00000000 || 2298 *l == 0x0000ffff || *l == 0xffff0000) 2299 return false; 2300 2301 if (pci_bus_crs_vendor_id(*l)) 2302 return pci_bus_wait_crs(bus, devfn, l, timeout); 2303 2304 return true; 2305 } 2306 2307 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2308 int timeout) 2309 { 2310 #ifdef CONFIG_PCI_QUIRKS 2311 struct pci_dev *bridge = bus->self; 2312 2313 /* 2314 * Certain IDT switches have an issue where they improperly trigger 2315 * ACS Source Validation errors on completions for config reads. 2316 */ 2317 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2318 bridge->device == 0x80b5) 2319 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2320 #endif 2321 2322 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2323 } 2324 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2325 2326 /* 2327 * Read the config data for a PCI device, sanity-check it, 2328 * and fill in the dev structure. 2329 */ 2330 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2331 { 2332 struct pci_dev *dev; 2333 u32 l; 2334 2335 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2336 return NULL; 2337 2338 dev = pci_alloc_dev(bus); 2339 if (!dev) 2340 return NULL; 2341 2342 dev->devfn = devfn; 2343 dev->vendor = l & 0xffff; 2344 dev->device = (l >> 16) & 0xffff; 2345 2346 pci_set_of_node(dev); 2347 2348 if (pci_setup_device(dev)) { 2349 pci_bus_put(dev->bus); 2350 kfree(dev); 2351 return NULL; 2352 } 2353 2354 return dev; 2355 } 2356 2357 void pcie_report_downtraining(struct pci_dev *dev) 2358 { 2359 if (!pci_is_pcie(dev)) 2360 return; 2361 2362 /* Look from the device up to avoid downstream ports with no devices */ 2363 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2364 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2365 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2366 return; 2367 2368 /* Multi-function PCIe devices share the same link/status */ 2369 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2370 return; 2371 2372 /* Print link status only if the device is constrained by the fabric */ 2373 __pcie_print_link_status(dev, false); 2374 } 2375 2376 static void pci_init_capabilities(struct pci_dev *dev) 2377 { 2378 pci_ea_init(dev); /* Enhanced Allocation */ 2379 2380 /* Setup MSI caps & disable MSI/MSI-X interrupts */ 2381 pci_msi_setup_pci_dev(dev); 2382 2383 /* Buffers for saving PCIe and PCI-X capabilities */ 2384 pci_allocate_cap_save_buffers(dev); 2385 2386 pci_pm_init(dev); /* Power Management */ 2387 pci_vpd_init(dev); /* Vital Product Data */ 2388 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2389 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2390 pci_ats_init(dev); /* Address Translation Services */ 2391 pci_pri_init(dev); /* Page Request Interface */ 2392 pci_pasid_init(dev); /* Process Address Space ID */ 2393 pci_enable_acs(dev); /* Enable ACS P2P upstream forwarding */ 2394 pci_ptm_init(dev); /* Precision Time Measurement */ 2395 pci_aer_init(dev); /* Advanced Error Reporting */ 2396 pci_dpc_init(dev); /* Downstream Port Containment */ 2397 2398 pcie_report_downtraining(dev); 2399 2400 if (pci_probe_reset_function(dev) == 0) 2401 dev->reset_fn = 1; 2402 } 2403 2404 /* 2405 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2406 * devices. Firmware interfaces that can select the MSI domain on a 2407 * per-device basis should be called from here. 2408 */ 2409 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2410 { 2411 struct irq_domain *d; 2412 2413 /* 2414 * If a domain has been set through the pcibios_add_device() 2415 * callback, then this is the one (platform code knows best). 2416 */ 2417 d = dev_get_msi_domain(&dev->dev); 2418 if (d) 2419 return d; 2420 2421 /* 2422 * Let's see if we have a firmware interface able to provide 2423 * the domain. 2424 */ 2425 d = pci_msi_get_device_domain(dev); 2426 if (d) 2427 return d; 2428 2429 return NULL; 2430 } 2431 2432 static void pci_set_msi_domain(struct pci_dev *dev) 2433 { 2434 struct irq_domain *d; 2435 2436 /* 2437 * If the platform or firmware interfaces cannot supply a 2438 * device-specific MSI domain, then inherit the default domain 2439 * from the host bridge itself. 2440 */ 2441 d = pci_dev_msi_domain(dev); 2442 if (!d) 2443 d = dev_get_msi_domain(&dev->bus->dev); 2444 2445 dev_set_msi_domain(&dev->dev, d); 2446 } 2447 2448 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2449 { 2450 int ret; 2451 2452 pci_configure_device(dev); 2453 2454 device_initialize(&dev->dev); 2455 dev->dev.release = pci_release_dev; 2456 2457 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2458 dev->dev.dma_mask = &dev->dma_mask; 2459 dev->dev.dma_parms = &dev->dma_parms; 2460 dev->dev.coherent_dma_mask = 0xffffffffull; 2461 2462 dma_set_max_seg_size(&dev->dev, 65536); 2463 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2464 2465 /* Fix up broken headers */ 2466 pci_fixup_device(pci_fixup_header, dev); 2467 2468 pci_reassigndev_resource_alignment(dev); 2469 2470 dev->state_saved = false; 2471 2472 pci_init_capabilities(dev); 2473 2474 /* 2475 * Add the device to our list of discovered devices 2476 * and the bus list for fixup functions, etc. 2477 */ 2478 down_write(&pci_bus_sem); 2479 list_add_tail(&dev->bus_list, &bus->devices); 2480 up_write(&pci_bus_sem); 2481 2482 ret = pcibios_add_device(dev); 2483 WARN_ON(ret < 0); 2484 2485 /* Set up MSI IRQ domain */ 2486 pci_set_msi_domain(dev); 2487 2488 /* Notifier could use PCI capabilities */ 2489 dev->match_driver = false; 2490 ret = device_add(&dev->dev); 2491 WARN_ON(ret < 0); 2492 } 2493 2494 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2495 { 2496 struct pci_dev *dev; 2497 2498 dev = pci_get_slot(bus, devfn); 2499 if (dev) { 2500 pci_dev_put(dev); 2501 return dev; 2502 } 2503 2504 dev = pci_scan_device(bus, devfn); 2505 if (!dev) 2506 return NULL; 2507 2508 pci_device_add(dev, bus); 2509 2510 return dev; 2511 } 2512 EXPORT_SYMBOL(pci_scan_single_device); 2513 2514 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) 2515 { 2516 int pos; 2517 u16 cap = 0; 2518 unsigned next_fn; 2519 2520 if (pci_ari_enabled(bus)) { 2521 if (!dev) 2522 return 0; 2523 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2524 if (!pos) 2525 return 0; 2526 2527 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2528 next_fn = PCI_ARI_CAP_NFN(cap); 2529 if (next_fn <= fn) 2530 return 0; /* protect against malformed list */ 2531 2532 return next_fn; 2533 } 2534 2535 /* dev may be NULL for non-contiguous multifunction devices */ 2536 if (!dev || dev->multifunction) 2537 return (fn + 1) % 8; 2538 2539 return 0; 2540 } 2541 2542 static int only_one_child(struct pci_bus *bus) 2543 { 2544 struct pci_dev *bridge = bus->self; 2545 2546 /* 2547 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2548 * we scan for all possible devices, not just Device 0. 2549 */ 2550 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2551 return 0; 2552 2553 /* 2554 * A PCIe Downstream Port normally leads to a Link with only Device 2555 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2556 * only for Device 0 in that situation. 2557 */ 2558 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2559 return 1; 2560 2561 return 0; 2562 } 2563 2564 /** 2565 * pci_scan_slot - Scan a PCI slot on a bus for devices 2566 * @bus: PCI bus to scan 2567 * @devfn: slot number to scan (must have zero function) 2568 * 2569 * Scan a PCI slot on the specified PCI bus for devices, adding 2570 * discovered devices to the @bus->devices list. New devices 2571 * will not have is_added set. 2572 * 2573 * Returns the number of new devices found. 2574 */ 2575 int pci_scan_slot(struct pci_bus *bus, int devfn) 2576 { 2577 unsigned fn, nr = 0; 2578 struct pci_dev *dev; 2579 2580 if (only_one_child(bus) && (devfn > 0)) 2581 return 0; /* Already scanned the entire slot */ 2582 2583 dev = pci_scan_single_device(bus, devfn); 2584 if (!dev) 2585 return 0; 2586 if (!pci_dev_is_added(dev)) 2587 nr++; 2588 2589 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { 2590 dev = pci_scan_single_device(bus, devfn + fn); 2591 if (dev) { 2592 if (!pci_dev_is_added(dev)) 2593 nr++; 2594 dev->multifunction = 1; 2595 } 2596 } 2597 2598 /* Only one slot has PCIe device */ 2599 if (bus->self && nr) 2600 pcie_aspm_init_link_state(bus->self); 2601 2602 return nr; 2603 } 2604 EXPORT_SYMBOL(pci_scan_slot); 2605 2606 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2607 { 2608 u8 *smpss = data; 2609 2610 if (!pci_is_pcie(dev)) 2611 return 0; 2612 2613 /* 2614 * We don't have a way to change MPS settings on devices that have 2615 * drivers attached. A hot-added device might support only the minimum 2616 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2617 * where devices may be hot-added, we limit the fabric MPS to 128 so 2618 * hot-added devices will work correctly. 2619 * 2620 * However, if we hot-add a device to a slot directly below a Root 2621 * Port, it's impossible for there to be other existing devices below 2622 * the port. We don't limit the MPS in this case because we can 2623 * reconfigure MPS on both the Root Port and the hot-added device, 2624 * and there are no other devices involved. 2625 * 2626 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2627 */ 2628 if (dev->is_hotplug_bridge && 2629 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2630 *smpss = 0; 2631 2632 if (*smpss > dev->pcie_mpss) 2633 *smpss = dev->pcie_mpss; 2634 2635 return 0; 2636 } 2637 2638 static void pcie_write_mps(struct pci_dev *dev, int mps) 2639 { 2640 int rc; 2641 2642 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2643 mps = 128 << dev->pcie_mpss; 2644 2645 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2646 dev->bus->self) 2647 2648 /* 2649 * For "Performance", the assumption is made that 2650 * downstream communication will never be larger than 2651 * the MRRS. So, the MPS only needs to be configured 2652 * for the upstream communication. This being the case, 2653 * walk from the top down and set the MPS of the child 2654 * to that of the parent bus. 2655 * 2656 * Configure the device MPS with the smaller of the 2657 * device MPSS or the bridge MPS (which is assumed to be 2658 * properly configured at this point to the largest 2659 * allowable MPS based on its parent bus). 2660 */ 2661 mps = min(mps, pcie_get_mps(dev->bus->self)); 2662 } 2663 2664 rc = pcie_set_mps(dev, mps); 2665 if (rc) 2666 pci_err(dev, "Failed attempting to set the MPS\n"); 2667 } 2668 2669 static void pcie_write_mrrs(struct pci_dev *dev) 2670 { 2671 int rc, mrrs; 2672 2673 /* 2674 * In the "safe" case, do not configure the MRRS. There appear to be 2675 * issues with setting MRRS to 0 on a number of devices. 2676 */ 2677 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2678 return; 2679 2680 /* 2681 * For max performance, the MRRS must be set to the largest supported 2682 * value. However, it cannot be configured larger than the MPS the 2683 * device or the bus can support. This should already be properly 2684 * configured by a prior call to pcie_write_mps(). 2685 */ 2686 mrrs = pcie_get_mps(dev); 2687 2688 /* 2689 * MRRS is a R/W register. Invalid values can be written, but a 2690 * subsequent read will verify if the value is acceptable or not. 2691 * If the MRRS value provided is not acceptable (e.g., too large), 2692 * shrink the value until it is acceptable to the HW. 2693 */ 2694 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2695 rc = pcie_set_readrq(dev, mrrs); 2696 if (!rc) 2697 break; 2698 2699 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2700 mrrs /= 2; 2701 } 2702 2703 if (mrrs < 128) 2704 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2705 } 2706 2707 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2708 { 2709 int mps, orig_mps; 2710 2711 if (!pci_is_pcie(dev)) 2712 return 0; 2713 2714 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2715 pcie_bus_config == PCIE_BUS_DEFAULT) 2716 return 0; 2717 2718 mps = 128 << *(u8 *)data; 2719 orig_mps = pcie_get_mps(dev); 2720 2721 pcie_write_mps(dev, mps); 2722 pcie_write_mrrs(dev); 2723 2724 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2725 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2726 orig_mps, pcie_get_readrq(dev)); 2727 2728 return 0; 2729 } 2730 2731 /* 2732 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2733 * parents then children fashion. If this changes, then this code will not 2734 * work as designed. 2735 */ 2736 void pcie_bus_configure_settings(struct pci_bus *bus) 2737 { 2738 u8 smpss = 0; 2739 2740 if (!bus->self) 2741 return; 2742 2743 if (!pci_is_pcie(bus->self)) 2744 return; 2745 2746 /* 2747 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2748 * to be aware of the MPS of the destination. To work around this, 2749 * simply force the MPS of the entire system to the smallest possible. 2750 */ 2751 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2752 smpss = 0; 2753 2754 if (pcie_bus_config == PCIE_BUS_SAFE) { 2755 smpss = bus->self->pcie_mpss; 2756 2757 pcie_find_smpss(bus->self, &smpss); 2758 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2759 } 2760 2761 pcie_bus_configure_set(bus->self, &smpss); 2762 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2763 } 2764 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2765 2766 /* 2767 * Called after each bus is probed, but before its children are examined. This 2768 * is marked as __weak because multiple architectures define it. 2769 */ 2770 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2771 { 2772 /* nothing to do, expected to be removed in the future */ 2773 } 2774 2775 /** 2776 * pci_scan_child_bus_extend() - Scan devices below a bus 2777 * @bus: Bus to scan for devices 2778 * @available_buses: Total number of buses available (%0 does not try to 2779 * extend beyond the minimal) 2780 * 2781 * Scans devices below @bus including subordinate buses. Returns new 2782 * subordinate number including all the found devices. Passing 2783 * @available_buses causes the remaining bus space to be distributed 2784 * equally between hotplug-capable bridges to allow future extension of the 2785 * hierarchy. 2786 */ 2787 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2788 unsigned int available_buses) 2789 { 2790 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2791 unsigned int start = bus->busn_res.start; 2792 unsigned int devfn, fn, cmax, max = start; 2793 struct pci_dev *dev; 2794 int nr_devs; 2795 2796 dev_dbg(&bus->dev, "scanning bus\n"); 2797 2798 /* Go find them, Rover! */ 2799 for (devfn = 0; devfn < 256; devfn += 8) { 2800 nr_devs = pci_scan_slot(bus, devfn); 2801 2802 /* 2803 * The Jailhouse hypervisor may pass individual functions of a 2804 * multi-function device to a guest without passing function 0. 2805 * Look for them as well. 2806 */ 2807 if (jailhouse_paravirt() && nr_devs == 0) { 2808 for (fn = 1; fn < 8; fn++) { 2809 dev = pci_scan_single_device(bus, devfn + fn); 2810 if (dev) 2811 dev->multifunction = 1; 2812 } 2813 } 2814 } 2815 2816 /* Reserve buses for SR-IOV capability */ 2817 used_buses = pci_iov_bus_range(bus); 2818 max += used_buses; 2819 2820 /* 2821 * After performing arch-dependent fixup of the bus, look behind 2822 * all PCI-to-PCI bridges on this bus. 2823 */ 2824 if (!bus->is_added) { 2825 dev_dbg(&bus->dev, "fixups for bus\n"); 2826 pcibios_fixup_bus(bus); 2827 bus->is_added = 1; 2828 } 2829 2830 /* 2831 * Calculate how many hotplug bridges and normal bridges there 2832 * are on this bus. We will distribute the additional available 2833 * buses between hotplug bridges. 2834 */ 2835 for_each_pci_bridge(dev, bus) { 2836 if (dev->is_hotplug_bridge) 2837 hotplug_bridges++; 2838 else 2839 normal_bridges++; 2840 } 2841 2842 /* 2843 * Scan bridges that are already configured. We don't touch them 2844 * unless they are misconfigured (which will be done in the second 2845 * scan below). 2846 */ 2847 for_each_pci_bridge(dev, bus) { 2848 cmax = max; 2849 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2850 2851 /* 2852 * Reserve one bus for each bridge now to avoid extending 2853 * hotplug bridges too much during the second scan below. 2854 */ 2855 used_buses++; 2856 if (cmax - max > 1) 2857 used_buses += cmax - max - 1; 2858 } 2859 2860 /* Scan bridges that need to be reconfigured */ 2861 for_each_pci_bridge(dev, bus) { 2862 unsigned int buses = 0; 2863 2864 if (!hotplug_bridges && normal_bridges == 1) { 2865 2866 /* 2867 * There is only one bridge on the bus (upstream 2868 * port) so it gets all available buses which it 2869 * can then distribute to the possible hotplug 2870 * bridges below. 2871 */ 2872 buses = available_buses; 2873 } else if (dev->is_hotplug_bridge) { 2874 2875 /* 2876 * Distribute the extra buses between hotplug 2877 * bridges if any. 2878 */ 2879 buses = available_buses / hotplug_bridges; 2880 buses = min(buses, available_buses - used_buses + 1); 2881 } 2882 2883 cmax = max; 2884 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2885 /* One bus is already accounted so don't add it again */ 2886 if (max - cmax > 1) 2887 used_buses += max - cmax - 1; 2888 } 2889 2890 /* 2891 * Make sure a hotplug bridge has at least the minimum requested 2892 * number of buses but allow it to grow up to the maximum available 2893 * bus number of there is room. 2894 */ 2895 if (bus->self && bus->self->is_hotplug_bridge) { 2896 used_buses = max_t(unsigned int, available_buses, 2897 pci_hotplug_bus_size - 1); 2898 if (max - start < used_buses) { 2899 max = start + used_buses; 2900 2901 /* Do not allocate more buses than we have room left */ 2902 if (max > bus->busn_res.end) 2903 max = bus->busn_res.end; 2904 2905 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2906 &bus->busn_res, max - start); 2907 } 2908 } 2909 2910 /* 2911 * We've scanned the bus and so we know all about what's on 2912 * the other side of any bridges that may be on this bus plus 2913 * any devices. 2914 * 2915 * Return how far we've got finding sub-buses. 2916 */ 2917 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2918 return max; 2919 } 2920 2921 /** 2922 * pci_scan_child_bus() - Scan devices below a bus 2923 * @bus: Bus to scan for devices 2924 * 2925 * Scans devices below @bus including subordinate buses. Returns new 2926 * subordinate number including all the found devices. 2927 */ 2928 unsigned int pci_scan_child_bus(struct pci_bus *bus) 2929 { 2930 return pci_scan_child_bus_extend(bus, 0); 2931 } 2932 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 2933 2934 /** 2935 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 2936 * @bridge: Host bridge to set up 2937 * 2938 * Default empty implementation. Replace with an architecture-specific setup 2939 * routine, if necessary. 2940 */ 2941 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 2942 { 2943 return 0; 2944 } 2945 2946 void __weak pcibios_add_bus(struct pci_bus *bus) 2947 { 2948 } 2949 2950 void __weak pcibios_remove_bus(struct pci_bus *bus) 2951 { 2952 } 2953 2954 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 2955 struct pci_ops *ops, void *sysdata, struct list_head *resources) 2956 { 2957 int error; 2958 struct pci_host_bridge *bridge; 2959 2960 bridge = pci_alloc_host_bridge(0); 2961 if (!bridge) 2962 return NULL; 2963 2964 bridge->dev.parent = parent; 2965 2966 list_splice_init(resources, &bridge->windows); 2967 bridge->sysdata = sysdata; 2968 bridge->busnr = bus; 2969 bridge->ops = ops; 2970 2971 error = pci_register_host_bridge(bridge); 2972 if (error < 0) 2973 goto err_out; 2974 2975 return bridge->bus; 2976 2977 err_out: 2978 put_device(&bridge->dev); 2979 return NULL; 2980 } 2981 EXPORT_SYMBOL_GPL(pci_create_root_bus); 2982 2983 int pci_host_probe(struct pci_host_bridge *bridge) 2984 { 2985 struct pci_bus *bus, *child; 2986 int ret; 2987 2988 ret = pci_scan_root_bus_bridge(bridge); 2989 if (ret < 0) { 2990 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 2991 return ret; 2992 } 2993 2994 bus = bridge->bus; 2995 2996 /* 2997 * We insert PCI resources into the iomem_resource and 2998 * ioport_resource trees in either pci_bus_claim_resources() 2999 * or pci_bus_assign_resources(). 3000 */ 3001 if (pci_has_flag(PCI_PROBE_ONLY)) { 3002 pci_bus_claim_resources(bus); 3003 } else { 3004 pci_bus_size_bridges(bus); 3005 pci_bus_assign_resources(bus); 3006 3007 list_for_each_entry(child, &bus->children, node) 3008 pcie_bus_configure_settings(child); 3009 } 3010 3011 pci_bus_add_devices(bus); 3012 return 0; 3013 } 3014 EXPORT_SYMBOL_GPL(pci_host_probe); 3015 3016 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3017 { 3018 struct resource *res = &b->busn_res; 3019 struct resource *parent_res, *conflict; 3020 3021 res->start = bus; 3022 res->end = bus_max; 3023 res->flags = IORESOURCE_BUS; 3024 3025 if (!pci_is_root_bus(b)) 3026 parent_res = &b->parent->busn_res; 3027 else { 3028 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3029 res->flags |= IORESOURCE_PCI_FIXED; 3030 } 3031 3032 conflict = request_resource_conflict(parent_res, res); 3033 3034 if (conflict) 3035 dev_info(&b->dev, 3036 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3037 res, pci_is_root_bus(b) ? "domain " : "", 3038 parent_res, conflict->name, conflict); 3039 3040 return conflict == NULL; 3041 } 3042 3043 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3044 { 3045 struct resource *res = &b->busn_res; 3046 struct resource old_res = *res; 3047 resource_size_t size; 3048 int ret; 3049 3050 if (res->start > bus_max) 3051 return -EINVAL; 3052 3053 size = bus_max - res->start + 1; 3054 ret = adjust_resource(res, res->start, size); 3055 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3056 &old_res, ret ? "can not be" : "is", bus_max); 3057 3058 if (!ret && !res->parent) 3059 pci_bus_insert_busn_res(b, res->start, res->end); 3060 3061 return ret; 3062 } 3063 3064 void pci_bus_release_busn_res(struct pci_bus *b) 3065 { 3066 struct resource *res = &b->busn_res; 3067 int ret; 3068 3069 if (!res->flags || !res->parent) 3070 return; 3071 3072 ret = release_resource(res); 3073 dev_info(&b->dev, "busn_res: %pR %s released\n", 3074 res, ret ? "can not be" : "is"); 3075 } 3076 3077 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3078 { 3079 struct resource_entry *window; 3080 bool found = false; 3081 struct pci_bus *b; 3082 int max, bus, ret; 3083 3084 if (!bridge) 3085 return -EINVAL; 3086 3087 resource_list_for_each_entry(window, &bridge->windows) 3088 if (window->res->flags & IORESOURCE_BUS) { 3089 found = true; 3090 break; 3091 } 3092 3093 ret = pci_register_host_bridge(bridge); 3094 if (ret < 0) 3095 return ret; 3096 3097 b = bridge->bus; 3098 bus = bridge->busnr; 3099 3100 if (!found) { 3101 dev_info(&b->dev, 3102 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3103 bus); 3104 pci_bus_insert_busn_res(b, bus, 255); 3105 } 3106 3107 max = pci_scan_child_bus(b); 3108 3109 if (!found) 3110 pci_bus_update_busn_res_end(b, max); 3111 3112 return 0; 3113 } 3114 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3115 3116 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3117 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3118 { 3119 struct resource_entry *window; 3120 bool found = false; 3121 struct pci_bus *b; 3122 int max; 3123 3124 resource_list_for_each_entry(window, resources) 3125 if (window->res->flags & IORESOURCE_BUS) { 3126 found = true; 3127 break; 3128 } 3129 3130 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3131 if (!b) 3132 return NULL; 3133 3134 if (!found) { 3135 dev_info(&b->dev, 3136 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3137 bus); 3138 pci_bus_insert_busn_res(b, bus, 255); 3139 } 3140 3141 max = pci_scan_child_bus(b); 3142 3143 if (!found) 3144 pci_bus_update_busn_res_end(b, max); 3145 3146 return b; 3147 } 3148 EXPORT_SYMBOL(pci_scan_root_bus); 3149 3150 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3151 void *sysdata) 3152 { 3153 LIST_HEAD(resources); 3154 struct pci_bus *b; 3155 3156 pci_add_resource(&resources, &ioport_resource); 3157 pci_add_resource(&resources, &iomem_resource); 3158 pci_add_resource(&resources, &busn_resource); 3159 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3160 if (b) { 3161 pci_scan_child_bus(b); 3162 } else { 3163 pci_free_resource_list(&resources); 3164 } 3165 return b; 3166 } 3167 EXPORT_SYMBOL(pci_scan_bus); 3168 3169 /** 3170 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3171 * @bridge: PCI bridge for the bus to scan 3172 * 3173 * Scan a PCI bus and child buses for new devices, add them, 3174 * and enable them, resizing bridge mmio/io resource if necessary 3175 * and possible. The caller must ensure the child devices are already 3176 * removed for resizing to occur. 3177 * 3178 * Returns the max number of subordinate bus discovered. 3179 */ 3180 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3181 { 3182 unsigned int max; 3183 struct pci_bus *bus = bridge->subordinate; 3184 3185 max = pci_scan_child_bus(bus); 3186 3187 pci_assign_unassigned_bridge_resources(bridge); 3188 3189 pci_bus_add_devices(bus); 3190 3191 return max; 3192 } 3193 3194 /** 3195 * pci_rescan_bus - Scan a PCI bus for devices 3196 * @bus: PCI bus to scan 3197 * 3198 * Scan a PCI bus and child buses for new devices, add them, 3199 * and enable them. 3200 * 3201 * Returns the max number of subordinate bus discovered. 3202 */ 3203 unsigned int pci_rescan_bus(struct pci_bus *bus) 3204 { 3205 unsigned int max; 3206 3207 max = pci_scan_child_bus(bus); 3208 pci_assign_unassigned_bus_resources(bus); 3209 pci_bus_add_devices(bus); 3210 3211 return max; 3212 } 3213 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3214 3215 /* 3216 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3217 * routines should always be executed under this mutex. 3218 */ 3219 static DEFINE_MUTEX(pci_rescan_remove_lock); 3220 3221 void pci_lock_rescan_remove(void) 3222 { 3223 mutex_lock(&pci_rescan_remove_lock); 3224 } 3225 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3226 3227 void pci_unlock_rescan_remove(void) 3228 { 3229 mutex_unlock(&pci_rescan_remove_lock); 3230 } 3231 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3232 3233 static int __init pci_sort_bf_cmp(const struct device *d_a, 3234 const struct device *d_b) 3235 { 3236 const struct pci_dev *a = to_pci_dev(d_a); 3237 const struct pci_dev *b = to_pci_dev(d_b); 3238 3239 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3240 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3241 3242 if (a->bus->number < b->bus->number) return -1; 3243 else if (a->bus->number > b->bus->number) return 1; 3244 3245 if (a->devfn < b->devfn) return -1; 3246 else if (a->devfn > b->devfn) return 1; 3247 3248 return 0; 3249 } 3250 3251 void __init pci_sort_breadthfirst(void) 3252 { 3253 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3254 } 3255 3256 int pci_hp_add_bridge(struct pci_dev *dev) 3257 { 3258 struct pci_bus *parent = dev->bus; 3259 int busnr, start = parent->busn_res.start; 3260 unsigned int available_buses = 0; 3261 int end = parent->busn_res.end; 3262 3263 for (busnr = start; busnr <= end; busnr++) { 3264 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3265 break; 3266 } 3267 if (busnr-- > end) { 3268 pci_err(dev, "No bus number available for hot-added bridge\n"); 3269 return -1; 3270 } 3271 3272 /* Scan bridges that are already configured */ 3273 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3274 3275 /* 3276 * Distribute the available bus numbers between hotplug-capable 3277 * bridges to make extending the chain later possible. 3278 */ 3279 available_buses = end - busnr; 3280 3281 /* Scan bridges that need to be reconfigured */ 3282 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3283 3284 if (!dev->subordinate) 3285 return -1; 3286 3287 return 0; 3288 } 3289 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3290