1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI detection and setup code 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/of_device.h> 11 #include <linux/of_pci.h> 12 #include <linux/pci_hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/cpumask.h> 16 #include <linux/aer.h> 17 #include <linux/acpi.h> 18 #include <linux/hypervisor.h> 19 #include <linux/irqdomain.h> 20 #include <linux/pm_runtime.h> 21 #include "pci.h" 22 23 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 24 #define CARDBUS_RESERVE_BUSNR 3 25 26 static struct resource busn_resource = { 27 .name = "PCI busn", 28 .start = 0, 29 .end = 255, 30 .flags = IORESOURCE_BUS, 31 }; 32 33 /* Ugh. Need to stop exporting this to modules. */ 34 LIST_HEAD(pci_root_buses); 35 EXPORT_SYMBOL(pci_root_buses); 36 37 static LIST_HEAD(pci_domain_busn_res_list); 38 39 struct pci_domain_busn_res { 40 struct list_head list; 41 struct resource res; 42 int domain_nr; 43 }; 44 45 static struct resource *get_pci_domain_busn_res(int domain_nr) 46 { 47 struct pci_domain_busn_res *r; 48 49 list_for_each_entry(r, &pci_domain_busn_res_list, list) 50 if (r->domain_nr == domain_nr) 51 return &r->res; 52 53 r = kzalloc(sizeof(*r), GFP_KERNEL); 54 if (!r) 55 return NULL; 56 57 r->domain_nr = domain_nr; 58 r->res.start = 0; 59 r->res.end = 0xff; 60 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 61 62 list_add_tail(&r->list, &pci_domain_busn_res_list); 63 64 return &r->res; 65 } 66 67 static int find_anything(struct device *dev, void *data) 68 { 69 return 1; 70 } 71 72 /* 73 * Some device drivers need know if PCI is initiated. 74 * Basically, we think PCI is not initiated when there 75 * is no device to be found on the pci_bus_type. 76 */ 77 int no_pci_devices(void) 78 { 79 struct device *dev; 80 int no_devices; 81 82 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); 83 no_devices = (dev == NULL); 84 put_device(dev); 85 return no_devices; 86 } 87 EXPORT_SYMBOL(no_pci_devices); 88 89 /* 90 * PCI Bus Class 91 */ 92 static void release_pcibus_dev(struct device *dev) 93 { 94 struct pci_bus *pci_bus = to_pci_bus(dev); 95 96 put_device(pci_bus->bridge); 97 pci_bus_remove_resources(pci_bus); 98 pci_release_bus_of_node(pci_bus); 99 kfree(pci_bus); 100 } 101 102 static struct class pcibus_class = { 103 .name = "pci_bus", 104 .dev_release = &release_pcibus_dev, 105 .dev_groups = pcibus_groups, 106 }; 107 108 static int __init pcibus_class_init(void) 109 { 110 return class_register(&pcibus_class); 111 } 112 postcore_initcall(pcibus_class_init); 113 114 static u64 pci_size(u64 base, u64 maxbase, u64 mask) 115 { 116 u64 size = mask & maxbase; /* Find the significant bits */ 117 if (!size) 118 return 0; 119 120 /* 121 * Get the lowest of them to find the decode size, and from that 122 * the extent. 123 */ 124 size = (size & ~(size-1)) - 1; 125 126 /* 127 * base == maxbase can be valid only if the BAR has already been 128 * programmed with all 1s. 129 */ 130 if (base == maxbase && ((base | size) & mask) != mask) 131 return 0; 132 133 return size; 134 } 135 136 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 137 { 138 u32 mem_type; 139 unsigned long flags; 140 141 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 142 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 143 flags |= IORESOURCE_IO; 144 return flags; 145 } 146 147 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 148 flags |= IORESOURCE_MEM; 149 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 150 flags |= IORESOURCE_PREFETCH; 151 152 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 153 switch (mem_type) { 154 case PCI_BASE_ADDRESS_MEM_TYPE_32: 155 break; 156 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 157 /* 1M mem BAR treated as 32-bit BAR */ 158 break; 159 case PCI_BASE_ADDRESS_MEM_TYPE_64: 160 flags |= IORESOURCE_MEM_64; 161 break; 162 default: 163 /* mem unknown type treated as 32-bit BAR */ 164 break; 165 } 166 return flags; 167 } 168 169 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 170 171 /** 172 * pci_read_base - Read a PCI BAR 173 * @dev: the PCI device 174 * @type: type of the BAR 175 * @res: resource buffer to be filled in 176 * @pos: BAR position in the config space 177 * 178 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 179 */ 180 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 181 struct resource *res, unsigned int pos) 182 { 183 u32 l = 0, sz = 0, mask; 184 u64 l64, sz64, mask64; 185 u16 orig_cmd; 186 struct pci_bus_region region, inverted_region; 187 188 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 189 190 /* No printks while decoding is disabled! */ 191 if (!dev->mmio_always_on) { 192 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 193 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 194 pci_write_config_word(dev, PCI_COMMAND, 195 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 196 } 197 } 198 199 res->name = pci_name(dev); 200 201 pci_read_config_dword(dev, pos, &l); 202 pci_write_config_dword(dev, pos, l | mask); 203 pci_read_config_dword(dev, pos, &sz); 204 pci_write_config_dword(dev, pos, l); 205 206 /* 207 * All bits set in sz means the device isn't working properly. 208 * If the BAR isn't implemented, all bits must be 0. If it's a 209 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 210 * 1 must be clear. 211 */ 212 if (sz == 0xffffffff) 213 sz = 0; 214 215 /* 216 * I don't know how l can have all bits set. Copied from old code. 217 * Maybe it fixes a bug on some ancient platform. 218 */ 219 if (l == 0xffffffff) 220 l = 0; 221 222 if (type == pci_bar_unknown) { 223 res->flags = decode_bar(dev, l); 224 res->flags |= IORESOURCE_SIZEALIGN; 225 if (res->flags & IORESOURCE_IO) { 226 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 227 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 228 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 229 } else { 230 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 231 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 232 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 233 } 234 } else { 235 if (l & PCI_ROM_ADDRESS_ENABLE) 236 res->flags |= IORESOURCE_ROM_ENABLE; 237 l64 = l & PCI_ROM_ADDRESS_MASK; 238 sz64 = sz & PCI_ROM_ADDRESS_MASK; 239 mask64 = PCI_ROM_ADDRESS_MASK; 240 } 241 242 if (res->flags & IORESOURCE_MEM_64) { 243 pci_read_config_dword(dev, pos + 4, &l); 244 pci_write_config_dword(dev, pos + 4, ~0); 245 pci_read_config_dword(dev, pos + 4, &sz); 246 pci_write_config_dword(dev, pos + 4, l); 247 248 l64 |= ((u64)l << 32); 249 sz64 |= ((u64)sz << 32); 250 mask64 |= ((u64)~0 << 32); 251 } 252 253 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 254 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 255 256 if (!sz64) 257 goto fail; 258 259 sz64 = pci_size(l64, sz64, mask64); 260 if (!sz64) { 261 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", 262 pos); 263 goto fail; 264 } 265 266 if (res->flags & IORESOURCE_MEM_64) { 267 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 268 && sz64 > 0x100000000ULL) { 269 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 270 res->start = 0; 271 res->end = 0; 272 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", 273 pos, (unsigned long long)sz64); 274 goto out; 275 } 276 277 if ((sizeof(pci_bus_addr_t) < 8) && l) { 278 /* Above 32-bit boundary; try to reallocate */ 279 res->flags |= IORESOURCE_UNSET; 280 res->start = 0; 281 res->end = sz64; 282 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", 283 pos, (unsigned long long)l64); 284 goto out; 285 } 286 } 287 288 region.start = l64; 289 region.end = l64 + sz64; 290 291 pcibios_bus_to_resource(dev->bus, res, ®ion); 292 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 293 294 /* 295 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 296 * the corresponding resource address (the physical address used by 297 * the CPU. Converting that resource address back to a bus address 298 * should yield the original BAR value: 299 * 300 * resource_to_bus(bus_to_resource(A)) == A 301 * 302 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 303 * be claimed by the device. 304 */ 305 if (inverted_region.start != region.start) { 306 res->flags |= IORESOURCE_UNSET; 307 res->start = 0; 308 res->end = region.end - region.start; 309 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", 310 pos, (unsigned long long)region.start); 311 } 312 313 goto out; 314 315 316 fail: 317 res->flags = 0; 318 out: 319 if (res->flags) 320 pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res); 321 322 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 323 } 324 325 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 326 { 327 unsigned int pos, reg; 328 329 if (dev->non_compliant_bars) 330 return; 331 332 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 333 if (dev->is_virtfn) 334 return; 335 336 for (pos = 0; pos < howmany; pos++) { 337 struct resource *res = &dev->resource[pos]; 338 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 339 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 340 } 341 342 if (rom) { 343 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 344 dev->rom_base_reg = rom; 345 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 346 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 347 __pci_read_base(dev, pci_bar_mem32, res, rom); 348 } 349 } 350 351 static void pci_read_bridge_io(struct pci_bus *child) 352 { 353 struct pci_dev *dev = child->self; 354 u8 io_base_lo, io_limit_lo; 355 unsigned long io_mask, io_granularity, base, limit; 356 struct pci_bus_region region; 357 struct resource *res; 358 359 io_mask = PCI_IO_RANGE_MASK; 360 io_granularity = 0x1000; 361 if (dev->io_window_1k) { 362 /* Support 1K I/O space granularity */ 363 io_mask = PCI_IO_1K_RANGE_MASK; 364 io_granularity = 0x400; 365 } 366 367 res = child->resource[0]; 368 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 369 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 370 base = (io_base_lo & io_mask) << 8; 371 limit = (io_limit_lo & io_mask) << 8; 372 373 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 374 u16 io_base_hi, io_limit_hi; 375 376 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 377 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 378 base |= ((unsigned long) io_base_hi << 16); 379 limit |= ((unsigned long) io_limit_hi << 16); 380 } 381 382 if (base <= limit) { 383 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 384 region.start = base; 385 region.end = limit + io_granularity - 1; 386 pcibios_bus_to_resource(dev->bus, res, ®ion); 387 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res); 388 } 389 } 390 391 static void pci_read_bridge_mmio(struct pci_bus *child) 392 { 393 struct pci_dev *dev = child->self; 394 u16 mem_base_lo, mem_limit_lo; 395 unsigned long base, limit; 396 struct pci_bus_region region; 397 struct resource *res; 398 399 res = child->resource[1]; 400 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 401 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 402 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 403 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 404 if (base <= limit) { 405 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 406 region.start = base; 407 region.end = limit + 0xfffff; 408 pcibios_bus_to_resource(dev->bus, res, ®ion); 409 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res); 410 } 411 } 412 413 static void pci_read_bridge_mmio_pref(struct pci_bus *child) 414 { 415 struct pci_dev *dev = child->self; 416 u16 mem_base_lo, mem_limit_lo; 417 u64 base64, limit64; 418 pci_bus_addr_t base, limit; 419 struct pci_bus_region region; 420 struct resource *res; 421 422 res = child->resource[2]; 423 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 424 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 425 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 426 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 427 428 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 429 u32 mem_base_hi, mem_limit_hi; 430 431 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 432 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 433 434 /* 435 * Some bridges set the base > limit by default, and some 436 * (broken) BIOSes do not initialize them. If we find 437 * this, just assume they are not being used. 438 */ 439 if (mem_base_hi <= mem_limit_hi) { 440 base64 |= (u64) mem_base_hi << 32; 441 limit64 |= (u64) mem_limit_hi << 32; 442 } 443 } 444 445 base = (pci_bus_addr_t) base64; 446 limit = (pci_bus_addr_t) limit64; 447 448 if (base != base64) { 449 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 450 (unsigned long long) base64); 451 return; 452 } 453 454 if (base <= limit) { 455 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 456 IORESOURCE_MEM | IORESOURCE_PREFETCH; 457 if (res->flags & PCI_PREF_RANGE_TYPE_64) 458 res->flags |= IORESOURCE_MEM_64; 459 region.start = base; 460 region.end = limit + 0xfffff; 461 pcibios_bus_to_resource(dev->bus, res, ®ion); 462 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res); 463 } 464 } 465 466 void pci_read_bridge_bases(struct pci_bus *child) 467 { 468 struct pci_dev *dev = child->self; 469 struct resource *res; 470 int i; 471 472 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 473 return; 474 475 pci_info(dev, "PCI bridge to %pR%s\n", 476 &child->busn_res, 477 dev->transparent ? " (subtractive decode)" : ""); 478 479 pci_bus_remove_resources(child); 480 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 481 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 482 483 pci_read_bridge_io(child); 484 pci_read_bridge_mmio(child); 485 pci_read_bridge_mmio_pref(child); 486 487 if (dev->transparent) { 488 pci_bus_for_each_resource(child->parent, res, i) { 489 if (res && res->flags) { 490 pci_bus_add_resource(child, res, 491 PCI_SUBTRACTIVE_DECODE); 492 pci_printk(KERN_DEBUG, dev, 493 " bridge window %pR (subtractive decode)\n", 494 res); 495 } 496 } 497 } 498 } 499 500 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 501 { 502 struct pci_bus *b; 503 504 b = kzalloc(sizeof(*b), GFP_KERNEL); 505 if (!b) 506 return NULL; 507 508 INIT_LIST_HEAD(&b->node); 509 INIT_LIST_HEAD(&b->children); 510 INIT_LIST_HEAD(&b->devices); 511 INIT_LIST_HEAD(&b->slots); 512 INIT_LIST_HEAD(&b->resources); 513 b->max_bus_speed = PCI_SPEED_UNKNOWN; 514 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 515 #ifdef CONFIG_PCI_DOMAINS_GENERIC 516 if (parent) 517 b->domain_nr = parent->domain_nr; 518 #endif 519 return b; 520 } 521 522 static void devm_pci_release_host_bridge_dev(struct device *dev) 523 { 524 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 525 526 if (bridge->release_fn) 527 bridge->release_fn(bridge); 528 529 pci_free_resource_list(&bridge->windows); 530 } 531 532 static void pci_release_host_bridge_dev(struct device *dev) 533 { 534 devm_pci_release_host_bridge_dev(dev); 535 kfree(to_pci_host_bridge(dev)); 536 } 537 538 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 539 { 540 struct pci_host_bridge *bridge; 541 542 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 543 if (!bridge) 544 return NULL; 545 546 INIT_LIST_HEAD(&bridge->windows); 547 bridge->dev.release = pci_release_host_bridge_dev; 548 549 /* 550 * We assume we can manage these PCIe features. Some systems may 551 * reserve these for use by the platform itself, e.g., an ACPI BIOS 552 * may implement its own AER handling and use _OSC to prevent the 553 * OS from interfering. 554 */ 555 bridge->native_aer = 1; 556 bridge->native_pcie_hotplug = 1; 557 bridge->native_shpc_hotplug = 1; 558 bridge->native_pme = 1; 559 bridge->native_ltr = 1; 560 561 return bridge; 562 } 563 EXPORT_SYMBOL(pci_alloc_host_bridge); 564 565 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 566 size_t priv) 567 { 568 struct pci_host_bridge *bridge; 569 570 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL); 571 if (!bridge) 572 return NULL; 573 574 INIT_LIST_HEAD(&bridge->windows); 575 bridge->dev.release = devm_pci_release_host_bridge_dev; 576 577 return bridge; 578 } 579 EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 580 581 void pci_free_host_bridge(struct pci_host_bridge *bridge) 582 { 583 pci_free_resource_list(&bridge->windows); 584 585 kfree(bridge); 586 } 587 EXPORT_SYMBOL(pci_free_host_bridge); 588 589 static const unsigned char pcix_bus_speed[] = { 590 PCI_SPEED_UNKNOWN, /* 0 */ 591 PCI_SPEED_66MHz_PCIX, /* 1 */ 592 PCI_SPEED_100MHz_PCIX, /* 2 */ 593 PCI_SPEED_133MHz_PCIX, /* 3 */ 594 PCI_SPEED_UNKNOWN, /* 4 */ 595 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 596 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 597 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 598 PCI_SPEED_UNKNOWN, /* 8 */ 599 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 600 PCI_SPEED_100MHz_PCIX_266, /* A */ 601 PCI_SPEED_133MHz_PCIX_266, /* B */ 602 PCI_SPEED_UNKNOWN, /* C */ 603 PCI_SPEED_66MHz_PCIX_533, /* D */ 604 PCI_SPEED_100MHz_PCIX_533, /* E */ 605 PCI_SPEED_133MHz_PCIX_533 /* F */ 606 }; 607 608 const unsigned char pcie_link_speed[] = { 609 PCI_SPEED_UNKNOWN, /* 0 */ 610 PCIE_SPEED_2_5GT, /* 1 */ 611 PCIE_SPEED_5_0GT, /* 2 */ 612 PCIE_SPEED_8_0GT, /* 3 */ 613 PCIE_SPEED_16_0GT, /* 4 */ 614 PCI_SPEED_UNKNOWN, /* 5 */ 615 PCI_SPEED_UNKNOWN, /* 6 */ 616 PCI_SPEED_UNKNOWN, /* 7 */ 617 PCI_SPEED_UNKNOWN, /* 8 */ 618 PCI_SPEED_UNKNOWN, /* 9 */ 619 PCI_SPEED_UNKNOWN, /* A */ 620 PCI_SPEED_UNKNOWN, /* B */ 621 PCI_SPEED_UNKNOWN, /* C */ 622 PCI_SPEED_UNKNOWN, /* D */ 623 PCI_SPEED_UNKNOWN, /* E */ 624 PCI_SPEED_UNKNOWN /* F */ 625 }; 626 627 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 628 { 629 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 630 } 631 EXPORT_SYMBOL_GPL(pcie_update_link_speed); 632 633 static unsigned char agp_speeds[] = { 634 AGP_UNKNOWN, 635 AGP_1X, 636 AGP_2X, 637 AGP_4X, 638 AGP_8X 639 }; 640 641 static enum pci_bus_speed agp_speed(int agp3, int agpstat) 642 { 643 int index = 0; 644 645 if (agpstat & 4) 646 index = 3; 647 else if (agpstat & 2) 648 index = 2; 649 else if (agpstat & 1) 650 index = 1; 651 else 652 goto out; 653 654 if (agp3) { 655 index += 2; 656 if (index == 5) 657 index = 0; 658 } 659 660 out: 661 return agp_speeds[index]; 662 } 663 664 static void pci_set_bus_speed(struct pci_bus *bus) 665 { 666 struct pci_dev *bridge = bus->self; 667 int pos; 668 669 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 670 if (!pos) 671 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 672 if (pos) { 673 u32 agpstat, agpcmd; 674 675 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 676 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 677 678 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 679 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 680 } 681 682 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 683 if (pos) { 684 u16 status; 685 enum pci_bus_speed max; 686 687 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 688 &status); 689 690 if (status & PCI_X_SSTATUS_533MHZ) { 691 max = PCI_SPEED_133MHz_PCIX_533; 692 } else if (status & PCI_X_SSTATUS_266MHZ) { 693 max = PCI_SPEED_133MHz_PCIX_266; 694 } else if (status & PCI_X_SSTATUS_133MHZ) { 695 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 696 max = PCI_SPEED_133MHz_PCIX_ECC; 697 else 698 max = PCI_SPEED_133MHz_PCIX; 699 } else { 700 max = PCI_SPEED_66MHz_PCIX; 701 } 702 703 bus->max_bus_speed = max; 704 bus->cur_bus_speed = pcix_bus_speed[ 705 (status & PCI_X_SSTATUS_FREQ) >> 6]; 706 707 return; 708 } 709 710 if (pci_is_pcie(bridge)) { 711 u32 linkcap; 712 u16 linksta; 713 714 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 715 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 716 717 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 718 pcie_update_link_speed(bus, linksta); 719 } 720 } 721 722 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 723 { 724 struct irq_domain *d; 725 726 /* 727 * Any firmware interface that can resolve the msi_domain 728 * should be called from here. 729 */ 730 d = pci_host_bridge_of_msi_domain(bus); 731 if (!d) 732 d = pci_host_bridge_acpi_msi_domain(bus); 733 734 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN 735 /* 736 * If no IRQ domain was found via the OF tree, try looking it up 737 * directly through the fwnode_handle. 738 */ 739 if (!d) { 740 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 741 742 if (fwnode) 743 d = irq_find_matching_fwnode(fwnode, 744 DOMAIN_BUS_PCI_MSI); 745 } 746 #endif 747 748 return d; 749 } 750 751 static void pci_set_bus_msi_domain(struct pci_bus *bus) 752 { 753 struct irq_domain *d; 754 struct pci_bus *b; 755 756 /* 757 * The bus can be a root bus, a subordinate bus, or a virtual bus 758 * created by an SR-IOV device. Walk up to the first bridge device 759 * found or derive the domain from the host bridge. 760 */ 761 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 762 if (b->self) 763 d = dev_get_msi_domain(&b->self->dev); 764 } 765 766 if (!d) 767 d = pci_host_bridge_msi_domain(b); 768 769 dev_set_msi_domain(&bus->dev, d); 770 } 771 772 static int pci_register_host_bridge(struct pci_host_bridge *bridge) 773 { 774 struct device *parent = bridge->dev.parent; 775 struct resource_entry *window, *n; 776 struct pci_bus *bus, *b; 777 resource_size_t offset; 778 LIST_HEAD(resources); 779 struct resource *res; 780 char addr[64], *fmt; 781 const char *name; 782 int err; 783 784 bus = pci_alloc_bus(NULL); 785 if (!bus) 786 return -ENOMEM; 787 788 bridge->bus = bus; 789 790 /* Temporarily move resources off the list */ 791 list_splice_init(&bridge->windows, &resources); 792 bus->sysdata = bridge->sysdata; 793 bus->msi = bridge->msi; 794 bus->ops = bridge->ops; 795 bus->number = bus->busn_res.start = bridge->busnr; 796 #ifdef CONFIG_PCI_DOMAINS_GENERIC 797 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 798 #endif 799 800 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 801 if (b) { 802 /* Ignore it if we already got here via a different bridge */ 803 dev_dbg(&b->dev, "bus already known\n"); 804 err = -EEXIST; 805 goto free; 806 } 807 808 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 809 bridge->busnr); 810 811 err = pcibios_root_bridge_prepare(bridge); 812 if (err) 813 goto free; 814 815 err = device_register(&bridge->dev); 816 if (err) 817 put_device(&bridge->dev); 818 819 bus->bridge = get_device(&bridge->dev); 820 device_enable_async_suspend(bus->bridge); 821 pci_set_bus_of_node(bus); 822 pci_set_bus_msi_domain(bus); 823 824 if (!parent) 825 set_dev_node(bus->bridge, pcibus_to_node(bus)); 826 827 bus->dev.class = &pcibus_class; 828 bus->dev.parent = bus->bridge; 829 830 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 831 name = dev_name(&bus->dev); 832 833 err = device_register(&bus->dev); 834 if (err) 835 goto unregister; 836 837 pcibios_add_bus(bus); 838 839 /* Create legacy_io and legacy_mem files for this bus */ 840 pci_create_legacy_files(bus); 841 842 if (parent) 843 dev_info(parent, "PCI host bridge to bus %s\n", name); 844 else 845 pr_info("PCI host bridge to bus %s\n", name); 846 847 /* Add initial resources to the bus */ 848 resource_list_for_each_entry_safe(window, n, &resources) { 849 list_move_tail(&window->node, &bridge->windows); 850 offset = window->offset; 851 res = window->res; 852 853 if (res->flags & IORESOURCE_BUS) 854 pci_bus_insert_busn_res(bus, bus->number, res->end); 855 else 856 pci_bus_add_resource(bus, res, 0); 857 858 if (offset) { 859 if (resource_type(res) == IORESOURCE_IO) 860 fmt = " (bus address [%#06llx-%#06llx])"; 861 else 862 fmt = " (bus address [%#010llx-%#010llx])"; 863 864 snprintf(addr, sizeof(addr), fmt, 865 (unsigned long long)(res->start - offset), 866 (unsigned long long)(res->end - offset)); 867 } else 868 addr[0] = '\0'; 869 870 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 871 } 872 873 down_write(&pci_bus_sem); 874 list_add_tail(&bus->node, &pci_root_buses); 875 up_write(&pci_bus_sem); 876 877 return 0; 878 879 unregister: 880 put_device(&bridge->dev); 881 device_unregister(&bridge->dev); 882 883 free: 884 kfree(bus); 885 return err; 886 } 887 888 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 889 { 890 int pos; 891 u32 status; 892 893 /* 894 * If extended config space isn't accessible on a bridge's primary 895 * bus, we certainly can't access it on the secondary bus. 896 */ 897 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 898 return false; 899 900 /* 901 * PCIe Root Ports and switch ports are PCIe on both sides, so if 902 * extended config space is accessible on the primary, it's also 903 * accessible on the secondary. 904 */ 905 if (pci_is_pcie(bridge) && 906 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 907 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 908 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 909 return true; 910 911 /* 912 * For the other bridge types: 913 * - PCI-to-PCI bridges 914 * - PCIe-to-PCI/PCI-X forward bridges 915 * - PCI/PCI-X-to-PCIe reverse bridges 916 * extended config space on the secondary side is only accessible 917 * if the bridge supports PCI-X Mode 2. 918 */ 919 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 920 if (!pos) 921 return false; 922 923 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 924 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 925 } 926 927 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 928 struct pci_dev *bridge, int busnr) 929 { 930 struct pci_bus *child; 931 int i; 932 int ret; 933 934 /* Allocate a new bus and inherit stuff from the parent */ 935 child = pci_alloc_bus(parent); 936 if (!child) 937 return NULL; 938 939 child->parent = parent; 940 child->ops = parent->ops; 941 child->msi = parent->msi; 942 child->sysdata = parent->sysdata; 943 child->bus_flags = parent->bus_flags; 944 945 /* 946 * Initialize some portions of the bus device, but don't register 947 * it now as the parent is not properly set up yet. 948 */ 949 child->dev.class = &pcibus_class; 950 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 951 952 /* Set up the primary, secondary and subordinate bus numbers */ 953 child->number = child->busn_res.start = busnr; 954 child->primary = parent->busn_res.start; 955 child->busn_res.end = 0xff; 956 957 if (!bridge) { 958 child->dev.parent = parent->bridge; 959 goto add_dev; 960 } 961 962 child->self = bridge; 963 child->bridge = get_device(&bridge->dev); 964 child->dev.parent = child->bridge; 965 pci_set_bus_of_node(child); 966 pci_set_bus_speed(child); 967 968 /* 969 * Check whether extended config space is accessible on the child 970 * bus. Note that we currently assume it is always accessible on 971 * the root bus. 972 */ 973 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 974 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 975 pci_info(child, "extended config space not accessible\n"); 976 } 977 978 /* Set up default resource pointers and names */ 979 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 980 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 981 child->resource[i]->name = child->name; 982 } 983 bridge->subordinate = child; 984 985 add_dev: 986 pci_set_bus_msi_domain(child); 987 ret = device_register(&child->dev); 988 WARN_ON(ret < 0); 989 990 pcibios_add_bus(child); 991 992 if (child->ops->add_bus) { 993 ret = child->ops->add_bus(child); 994 if (WARN_ON(ret < 0)) 995 dev_err(&child->dev, "failed to add bus: %d\n", ret); 996 } 997 998 /* Create legacy_io and legacy_mem files for this bus */ 999 pci_create_legacy_files(child); 1000 1001 return child; 1002 } 1003 1004 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1005 int busnr) 1006 { 1007 struct pci_bus *child; 1008 1009 child = pci_alloc_child_bus(parent, dev, busnr); 1010 if (child) { 1011 down_write(&pci_bus_sem); 1012 list_add_tail(&child->node, &parent->children); 1013 up_write(&pci_bus_sem); 1014 } 1015 return child; 1016 } 1017 EXPORT_SYMBOL(pci_add_new_bus); 1018 1019 static void pci_enable_crs(struct pci_dev *pdev) 1020 { 1021 u16 root_cap = 0; 1022 1023 /* Enable CRS Software Visibility if supported */ 1024 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1025 if (root_cap & PCI_EXP_RTCAP_CRSVIS) 1026 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1027 PCI_EXP_RTCTL_CRSSVE); 1028 } 1029 1030 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1031 unsigned int available_buses); 1032 1033 /* 1034 * pci_scan_bridge_extend() - Scan buses behind a bridge 1035 * @bus: Parent bus the bridge is on 1036 * @dev: Bridge itself 1037 * @max: Starting subordinate number of buses behind this bridge 1038 * @available_buses: Total number of buses available for this bridge and 1039 * the devices below. After the minimal bus space has 1040 * been allocated the remaining buses will be 1041 * distributed equally between hotplug-capable bridges. 1042 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1043 * that need to be reconfigured. 1044 * 1045 * If it's a bridge, configure it and scan the bus behind it. 1046 * For CardBus bridges, we don't scan behind as the devices will 1047 * be handled by the bridge driver itself. 1048 * 1049 * We need to process bridges in two passes -- first we scan those 1050 * already configured by the BIOS and after we are done with all of 1051 * them, we proceed to assigning numbers to the remaining buses in 1052 * order to avoid overlaps between old and new bus numbers. 1053 * 1054 * Return: New subordinate number covering all buses behind this bridge. 1055 */ 1056 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1057 int max, unsigned int available_buses, 1058 int pass) 1059 { 1060 struct pci_bus *child; 1061 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1062 u32 buses, i, j = 0; 1063 u16 bctl; 1064 u8 primary, secondary, subordinate; 1065 int broken = 0; 1066 1067 /* 1068 * Make sure the bridge is powered on to be able to access config 1069 * space of devices below it. 1070 */ 1071 pm_runtime_get_sync(&dev->dev); 1072 1073 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1074 primary = buses & 0xFF; 1075 secondary = (buses >> 8) & 0xFF; 1076 subordinate = (buses >> 16) & 0xFF; 1077 1078 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1079 secondary, subordinate, pass); 1080 1081 if (!primary && (primary != bus->number) && secondary && subordinate) { 1082 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1083 primary = bus->number; 1084 } 1085 1086 /* Check if setup is sensible at all */ 1087 if (!pass && 1088 (primary != bus->number || secondary <= bus->number || 1089 secondary > subordinate)) { 1090 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1091 secondary, subordinate); 1092 broken = 1; 1093 } 1094 1095 /* 1096 * Disable Master-Abort Mode during probing to avoid reporting of 1097 * bus errors in some architectures. 1098 */ 1099 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1100 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1101 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1102 1103 pci_enable_crs(dev); 1104 1105 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1106 !is_cardbus && !broken) { 1107 unsigned int cmax; 1108 1109 /* 1110 * Bus already configured by firmware, process it in the 1111 * first pass and just note the configuration. 1112 */ 1113 if (pass) 1114 goto out; 1115 1116 /* 1117 * The bus might already exist for two reasons: Either we 1118 * are rescanning the bus or the bus is reachable through 1119 * more than one bridge. The second case can happen with 1120 * the i450NX chipset. 1121 */ 1122 child = pci_find_bus(pci_domain_nr(bus), secondary); 1123 if (!child) { 1124 child = pci_add_new_bus(bus, dev, secondary); 1125 if (!child) 1126 goto out; 1127 child->primary = primary; 1128 pci_bus_insert_busn_res(child, secondary, subordinate); 1129 child->bridge_ctl = bctl; 1130 } 1131 1132 cmax = pci_scan_child_bus(child); 1133 if (cmax > subordinate) 1134 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1135 subordinate, cmax); 1136 1137 /* Subordinate should equal child->busn_res.end */ 1138 if (subordinate > max) 1139 max = subordinate; 1140 } else { 1141 1142 /* 1143 * We need to assign a number to this bus which we always 1144 * do in the second pass. 1145 */ 1146 if (!pass) { 1147 if (pcibios_assign_all_busses() || broken || is_cardbus) 1148 1149 /* 1150 * Temporarily disable forwarding of the 1151 * configuration cycles on all bridges in 1152 * this bus segment to avoid possible 1153 * conflicts in the second pass between two 1154 * bridges programmed with overlapping bus 1155 * ranges. 1156 */ 1157 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1158 buses & ~0xffffff); 1159 goto out; 1160 } 1161 1162 /* Clear errors */ 1163 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1164 1165 /* 1166 * Prevent assigning a bus number that already exists. 1167 * This can happen when a bridge is hot-plugged, so in this 1168 * case we only re-scan this bus. 1169 */ 1170 child = pci_find_bus(pci_domain_nr(bus), max+1); 1171 if (!child) { 1172 child = pci_add_new_bus(bus, dev, max+1); 1173 if (!child) 1174 goto out; 1175 pci_bus_insert_busn_res(child, max+1, 1176 bus->busn_res.end); 1177 } 1178 max++; 1179 if (available_buses) 1180 available_buses--; 1181 1182 buses = (buses & 0xff000000) 1183 | ((unsigned int)(child->primary) << 0) 1184 | ((unsigned int)(child->busn_res.start) << 8) 1185 | ((unsigned int)(child->busn_res.end) << 16); 1186 1187 /* 1188 * yenta.c forces a secondary latency timer of 176. 1189 * Copy that behaviour here. 1190 */ 1191 if (is_cardbus) { 1192 buses &= ~0xff000000; 1193 buses |= CARDBUS_LATENCY_TIMER << 24; 1194 } 1195 1196 /* We need to blast all three values with a single write */ 1197 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1198 1199 if (!is_cardbus) { 1200 child->bridge_ctl = bctl; 1201 max = pci_scan_child_bus_extend(child, available_buses); 1202 } else { 1203 1204 /* 1205 * For CardBus bridges, we leave 4 bus numbers as 1206 * cards with a PCI-to-PCI bridge can be inserted 1207 * later. 1208 */ 1209 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1210 struct pci_bus *parent = bus; 1211 if (pci_find_bus(pci_domain_nr(bus), 1212 max+i+1)) 1213 break; 1214 while (parent->parent) { 1215 if ((!pcibios_assign_all_busses()) && 1216 (parent->busn_res.end > max) && 1217 (parent->busn_res.end <= max+i)) { 1218 j = 1; 1219 } 1220 parent = parent->parent; 1221 } 1222 if (j) { 1223 1224 /* 1225 * Often, there are two CardBus 1226 * bridges -- try to leave one 1227 * valid bus number for each one. 1228 */ 1229 i /= 2; 1230 break; 1231 } 1232 } 1233 max += i; 1234 } 1235 1236 /* Set subordinate bus number to its real value */ 1237 pci_bus_update_busn_res_end(child, max); 1238 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1239 } 1240 1241 sprintf(child->name, 1242 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1243 pci_domain_nr(bus), child->number); 1244 1245 /* Check that all devices are accessible */ 1246 while (bus->parent) { 1247 if ((child->busn_res.end > bus->busn_res.end) || 1248 (child->number > bus->busn_res.end) || 1249 (child->number < bus->number) || 1250 (child->busn_res.end < bus->number)) { 1251 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1252 &child->busn_res); 1253 break; 1254 } 1255 bus = bus->parent; 1256 } 1257 1258 out: 1259 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1260 1261 pm_runtime_put(&dev->dev); 1262 1263 return max; 1264 } 1265 1266 /* 1267 * pci_scan_bridge() - Scan buses behind a bridge 1268 * @bus: Parent bus the bridge is on 1269 * @dev: Bridge itself 1270 * @max: Starting subordinate number of buses behind this bridge 1271 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1272 * that need to be reconfigured. 1273 * 1274 * If it's a bridge, configure it and scan the bus behind it. 1275 * For CardBus bridges, we don't scan behind as the devices will 1276 * be handled by the bridge driver itself. 1277 * 1278 * We need to process bridges in two passes -- first we scan those 1279 * already configured by the BIOS and after we are done with all of 1280 * them, we proceed to assigning numbers to the remaining buses in 1281 * order to avoid overlaps between old and new bus numbers. 1282 * 1283 * Return: New subordinate number covering all buses behind this bridge. 1284 */ 1285 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1286 { 1287 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1288 } 1289 EXPORT_SYMBOL(pci_scan_bridge); 1290 1291 /* 1292 * Read interrupt line and base address registers. 1293 * The architecture-dependent code can tweak these, of course. 1294 */ 1295 static void pci_read_irq(struct pci_dev *dev) 1296 { 1297 unsigned char irq; 1298 1299 /* VFs are not allowed to use INTx, so skip the config reads */ 1300 if (dev->is_virtfn) { 1301 dev->pin = 0; 1302 dev->irq = 0; 1303 return; 1304 } 1305 1306 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1307 dev->pin = irq; 1308 if (irq) 1309 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1310 dev->irq = irq; 1311 } 1312 1313 void set_pcie_port_type(struct pci_dev *pdev) 1314 { 1315 int pos; 1316 u16 reg16; 1317 int type; 1318 struct pci_dev *parent; 1319 1320 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1321 if (!pos) 1322 return; 1323 1324 pdev->pcie_cap = pos; 1325 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1326 pdev->pcie_flags_reg = reg16; 1327 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 1328 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1329 1330 /* 1331 * A Root Port or a PCI-to-PCIe bridge is always the upstream end 1332 * of a Link. No PCIe component has two Links. Two Links are 1333 * connected by a Switch that has a Port on each Link and internal 1334 * logic to connect the two Ports. 1335 */ 1336 type = pci_pcie_type(pdev); 1337 if (type == PCI_EXP_TYPE_ROOT_PORT || 1338 type == PCI_EXP_TYPE_PCIE_BRIDGE) 1339 pdev->has_secondary_link = 1; 1340 else if (type == PCI_EXP_TYPE_UPSTREAM || 1341 type == PCI_EXP_TYPE_DOWNSTREAM) { 1342 parent = pci_upstream_bridge(pdev); 1343 1344 /* 1345 * Usually there's an upstream device (Root Port or Switch 1346 * Downstream Port), but we can't assume one exists. 1347 */ 1348 if (parent && !parent->has_secondary_link) 1349 pdev->has_secondary_link = 1; 1350 } 1351 } 1352 1353 void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1354 { 1355 u32 reg32; 1356 1357 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1358 if (reg32 & PCI_EXP_SLTCAP_HPC) 1359 pdev->is_hotplug_bridge = 1; 1360 } 1361 1362 static void set_pcie_thunderbolt(struct pci_dev *dev) 1363 { 1364 int vsec = 0; 1365 u32 header; 1366 1367 while ((vsec = pci_find_next_ext_capability(dev, vsec, 1368 PCI_EXT_CAP_ID_VNDR))) { 1369 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); 1370 1371 /* Is the device part of a Thunderbolt controller? */ 1372 if (dev->vendor == PCI_VENDOR_ID_INTEL && 1373 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { 1374 dev->is_thunderbolt = 1; 1375 return; 1376 } 1377 } 1378 } 1379 1380 /** 1381 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1382 * @dev: PCI device 1383 * 1384 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1385 * when forwarding a type1 configuration request the bridge must check that 1386 * the extended register address field is zero. The bridge is not permitted 1387 * to forward the transactions and must handle it as an Unsupported Request. 1388 * Some bridges do not follow this rule and simply drop the extended register 1389 * bits, resulting in the standard config space being aliased, every 256 1390 * bytes across the entire configuration space. Test for this condition by 1391 * comparing the first dword of each potential alias to the vendor/device ID. 1392 * Known offenders: 1393 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1394 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1395 */ 1396 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1397 { 1398 #ifdef CONFIG_PCI_QUIRKS 1399 int pos; 1400 u32 header, tmp; 1401 1402 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1403 1404 for (pos = PCI_CFG_SPACE_SIZE; 1405 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1406 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL 1407 || header != tmp) 1408 return false; 1409 } 1410 1411 return true; 1412 #else 1413 return false; 1414 #endif 1415 } 1416 1417 /** 1418 * pci_cfg_space_size - Get the configuration space size of the PCI device 1419 * @dev: PCI device 1420 * 1421 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1422 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1423 * access it. Maybe we don't have a way to generate extended config space 1424 * accesses, or the device is behind a reverse Express bridge. So we try 1425 * reading the dword at 0x100 which must either be 0 or a valid extended 1426 * capability header. 1427 */ 1428 static int pci_cfg_space_size_ext(struct pci_dev *dev) 1429 { 1430 u32 status; 1431 int pos = PCI_CFG_SPACE_SIZE; 1432 1433 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1434 return PCI_CFG_SPACE_SIZE; 1435 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) 1436 return PCI_CFG_SPACE_SIZE; 1437 1438 return PCI_CFG_SPACE_EXP_SIZE; 1439 } 1440 1441 int pci_cfg_space_size(struct pci_dev *dev) 1442 { 1443 int pos; 1444 u32 status; 1445 u16 class; 1446 1447 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1448 return PCI_CFG_SPACE_SIZE; 1449 1450 class = dev->class >> 8; 1451 if (class == PCI_CLASS_BRIDGE_HOST) 1452 return pci_cfg_space_size_ext(dev); 1453 1454 if (pci_is_pcie(dev)) 1455 return pci_cfg_space_size_ext(dev); 1456 1457 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1458 if (!pos) 1459 return PCI_CFG_SPACE_SIZE; 1460 1461 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1462 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1463 return pci_cfg_space_size_ext(dev); 1464 1465 return PCI_CFG_SPACE_SIZE; 1466 } 1467 1468 static u32 pci_class(struct pci_dev *dev) 1469 { 1470 u32 class; 1471 1472 #ifdef CONFIG_PCI_IOV 1473 if (dev->is_virtfn) 1474 return dev->physfn->sriov->class; 1475 #endif 1476 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1477 return class; 1478 } 1479 1480 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1481 { 1482 #ifdef CONFIG_PCI_IOV 1483 if (dev->is_virtfn) { 1484 *vendor = dev->physfn->sriov->subsystem_vendor; 1485 *device = dev->physfn->sriov->subsystem_device; 1486 return; 1487 } 1488 #endif 1489 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1490 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1491 } 1492 1493 static u8 pci_hdr_type(struct pci_dev *dev) 1494 { 1495 u8 hdr_type; 1496 1497 #ifdef CONFIG_PCI_IOV 1498 if (dev->is_virtfn) 1499 return dev->physfn->sriov->hdr_type; 1500 #endif 1501 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1502 return hdr_type; 1503 } 1504 1505 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1506 1507 static void pci_msi_setup_pci_dev(struct pci_dev *dev) 1508 { 1509 /* 1510 * Disable the MSI hardware to avoid screaming interrupts 1511 * during boot. This is the power on reset default so 1512 * usually this should be a noop. 1513 */ 1514 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); 1515 if (dev->msi_cap) 1516 pci_msi_set_enable(dev, 0); 1517 1518 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1519 if (dev->msix_cap) 1520 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); 1521 } 1522 1523 /** 1524 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1525 * @dev: PCI device 1526 * 1527 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1528 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1529 */ 1530 static int pci_intx_mask_broken(struct pci_dev *dev) 1531 { 1532 u16 orig, toggle, new; 1533 1534 pci_read_config_word(dev, PCI_COMMAND, &orig); 1535 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1536 pci_write_config_word(dev, PCI_COMMAND, toggle); 1537 pci_read_config_word(dev, PCI_COMMAND, &new); 1538 1539 pci_write_config_word(dev, PCI_COMMAND, orig); 1540 1541 /* 1542 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1543 * r2.3, so strictly speaking, a device is not *broken* if it's not 1544 * writable. But we'll live with the misnomer for now. 1545 */ 1546 if (new != toggle) 1547 return 1; 1548 return 0; 1549 } 1550 1551 static void early_dump_pci_device(struct pci_dev *pdev) 1552 { 1553 u32 value[256 / 4]; 1554 int i; 1555 1556 pci_info(pdev, "config space:\n"); 1557 1558 for (i = 0; i < 256; i += 4) 1559 pci_read_config_dword(pdev, i, &value[i / 4]); 1560 1561 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1562 value, 256, false); 1563 } 1564 1565 /** 1566 * pci_setup_device - Fill in class and map information of a device 1567 * @dev: the device structure to fill 1568 * 1569 * Initialize the device structure with information about the device's 1570 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1571 * Called at initialisation of the PCI subsystem and by CardBus services. 1572 * Returns 0 on success and negative if unknown type of device (not normal, 1573 * bridge or CardBus). 1574 */ 1575 int pci_setup_device(struct pci_dev *dev) 1576 { 1577 u32 class; 1578 u16 cmd; 1579 u8 hdr_type; 1580 int pos = 0; 1581 struct pci_bus_region region; 1582 struct resource *res; 1583 1584 hdr_type = pci_hdr_type(dev); 1585 1586 dev->sysdata = dev->bus->sysdata; 1587 dev->dev.parent = dev->bus->bridge; 1588 dev->dev.bus = &pci_bus_type; 1589 dev->hdr_type = hdr_type & 0x7f; 1590 dev->multifunction = !!(hdr_type & 0x80); 1591 dev->error_state = pci_channel_io_normal; 1592 set_pcie_port_type(dev); 1593 1594 pci_dev_assign_slot(dev); 1595 1596 /* 1597 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1598 * set this higher, assuming the system even supports it. 1599 */ 1600 dev->dma_mask = 0xffffffff; 1601 1602 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1603 dev->bus->number, PCI_SLOT(dev->devfn), 1604 PCI_FUNC(dev->devfn)); 1605 1606 class = pci_class(dev); 1607 1608 dev->revision = class & 0xff; 1609 dev->class = class >> 8; /* upper 3 bytes */ 1610 1611 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n", 1612 dev->vendor, dev->device, dev->hdr_type, dev->class); 1613 1614 if (pci_early_dump) 1615 early_dump_pci_device(dev); 1616 1617 /* Need to have dev->class ready */ 1618 dev->cfg_size = pci_cfg_space_size(dev); 1619 1620 /* Need to have dev->cfg_size ready */ 1621 set_pcie_thunderbolt(dev); 1622 1623 /* "Unknown power state" */ 1624 dev->current_state = PCI_UNKNOWN; 1625 1626 /* Early fixups, before probing the BARs */ 1627 pci_fixup_device(pci_fixup_early, dev); 1628 1629 /* Device class may be changed after fixup */ 1630 class = dev->class >> 8; 1631 1632 if (dev->non_compliant_bars) { 1633 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1634 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1635 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1636 cmd &= ~PCI_COMMAND_IO; 1637 cmd &= ~PCI_COMMAND_MEMORY; 1638 pci_write_config_word(dev, PCI_COMMAND, cmd); 1639 } 1640 } 1641 1642 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1643 1644 switch (dev->hdr_type) { /* header type */ 1645 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1646 if (class == PCI_CLASS_BRIDGE_PCI) 1647 goto bad; 1648 pci_read_irq(dev); 1649 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1650 1651 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 1652 1653 /* 1654 * Do the ugly legacy mode stuff here rather than broken chip 1655 * quirk code. Legacy mode ATA controllers have fixed 1656 * addresses. These are not always echoed in BAR0-3, and 1657 * BAR0-3 in a few cases contain junk! 1658 */ 1659 if (class == PCI_CLASS_STORAGE_IDE) { 1660 u8 progif; 1661 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1662 if ((progif & 1) == 0) { 1663 region.start = 0x1F0; 1664 region.end = 0x1F7; 1665 res = &dev->resource[0]; 1666 res->flags = LEGACY_IO_RESOURCE; 1667 pcibios_bus_to_resource(dev->bus, res, ®ion); 1668 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1669 res); 1670 region.start = 0x3F6; 1671 region.end = 0x3F6; 1672 res = &dev->resource[1]; 1673 res->flags = LEGACY_IO_RESOURCE; 1674 pcibios_bus_to_resource(dev->bus, res, ®ion); 1675 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1676 res); 1677 } 1678 if ((progif & 4) == 0) { 1679 region.start = 0x170; 1680 region.end = 0x177; 1681 res = &dev->resource[2]; 1682 res->flags = LEGACY_IO_RESOURCE; 1683 pcibios_bus_to_resource(dev->bus, res, ®ion); 1684 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1685 res); 1686 region.start = 0x376; 1687 region.end = 0x376; 1688 res = &dev->resource[3]; 1689 res->flags = LEGACY_IO_RESOURCE; 1690 pcibios_bus_to_resource(dev->bus, res, ®ion); 1691 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1692 res); 1693 } 1694 } 1695 break; 1696 1697 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1698 if (class != PCI_CLASS_BRIDGE_PCI) 1699 goto bad; 1700 1701 /* 1702 * The PCI-to-PCI bridge spec requires that subtractive 1703 * decoding (i.e. transparent) bridge must have programming 1704 * interface code of 0x01. 1705 */ 1706 pci_read_irq(dev); 1707 dev->transparent = ((dev->class & 0xff) == 1); 1708 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1709 set_pcie_hotplug_bridge(dev); 1710 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1711 if (pos) { 1712 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1713 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1714 } 1715 break; 1716 1717 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1718 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1719 goto bad; 1720 pci_read_irq(dev); 1721 pci_read_bases(dev, 1, 0); 1722 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1723 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1724 break; 1725 1726 default: /* unknown header */ 1727 pci_err(dev, "unknown header type %02x, ignoring device\n", 1728 dev->hdr_type); 1729 return -EIO; 1730 1731 bad: 1732 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1733 dev->class, dev->hdr_type); 1734 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1735 } 1736 1737 /* We found a fine healthy device, go go go... */ 1738 return 0; 1739 } 1740 1741 static void pci_configure_mps(struct pci_dev *dev) 1742 { 1743 struct pci_dev *bridge = pci_upstream_bridge(dev); 1744 int mps, mpss, p_mps, rc; 1745 1746 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) 1747 return; 1748 1749 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 1750 if (dev->is_virtfn) 1751 return; 1752 1753 mps = pcie_get_mps(dev); 1754 p_mps = pcie_get_mps(bridge); 1755 1756 if (mps == p_mps) 1757 return; 1758 1759 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 1760 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1761 mps, pci_name(bridge), p_mps); 1762 return; 1763 } 1764 1765 /* 1766 * Fancier MPS configuration is done later by 1767 * pcie_bus_configure_settings() 1768 */ 1769 if (pcie_bus_config != PCIE_BUS_DEFAULT) 1770 return; 1771 1772 mpss = 128 << dev->pcie_mpss; 1773 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 1774 pcie_set_mps(bridge, mpss); 1775 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 1776 mpss, p_mps, 128 << bridge->pcie_mpss); 1777 p_mps = pcie_get_mps(bridge); 1778 } 1779 1780 rc = pcie_set_mps(dev, p_mps); 1781 if (rc) { 1782 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 1783 p_mps); 1784 return; 1785 } 1786 1787 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 1788 p_mps, mps, mpss); 1789 } 1790 1791 static struct hpp_type0 pci_default_type0 = { 1792 .revision = 1, 1793 .cache_line_size = 8, 1794 .latency_timer = 0x40, 1795 .enable_serr = 0, 1796 .enable_perr = 0, 1797 }; 1798 1799 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) 1800 { 1801 u16 pci_cmd, pci_bctl; 1802 1803 if (!hpp) 1804 hpp = &pci_default_type0; 1805 1806 if (hpp->revision > 1) { 1807 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n", 1808 hpp->revision); 1809 hpp = &pci_default_type0; 1810 } 1811 1812 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); 1813 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); 1814 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); 1815 if (hpp->enable_serr) 1816 pci_cmd |= PCI_COMMAND_SERR; 1817 if (hpp->enable_perr) 1818 pci_cmd |= PCI_COMMAND_PARITY; 1819 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); 1820 1821 /* Program bridge control value */ 1822 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 1823 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 1824 hpp->latency_timer); 1825 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); 1826 if (hpp->enable_serr) 1827 pci_bctl |= PCI_BRIDGE_CTL_SERR; 1828 if (hpp->enable_perr) 1829 pci_bctl |= PCI_BRIDGE_CTL_PARITY; 1830 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); 1831 } 1832 } 1833 1834 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) 1835 { 1836 int pos; 1837 1838 if (!hpp) 1839 return; 1840 1841 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1842 if (!pos) 1843 return; 1844 1845 pci_warn(dev, "PCI-X settings not supported\n"); 1846 } 1847 1848 static bool pcie_root_rcb_set(struct pci_dev *dev) 1849 { 1850 struct pci_dev *rp = pcie_find_root_port(dev); 1851 u16 lnkctl; 1852 1853 if (!rp) 1854 return false; 1855 1856 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); 1857 if (lnkctl & PCI_EXP_LNKCTL_RCB) 1858 return true; 1859 1860 return false; 1861 } 1862 1863 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) 1864 { 1865 int pos; 1866 u32 reg32; 1867 1868 if (!hpp) 1869 return; 1870 1871 if (!pci_is_pcie(dev)) 1872 return; 1873 1874 if (hpp->revision > 1) { 1875 pci_warn(dev, "PCIe settings rev %d not supported\n", 1876 hpp->revision); 1877 return; 1878 } 1879 1880 /* 1881 * Don't allow _HPX to change MPS or MRRS settings. We manage 1882 * those to make sure they're consistent with the rest of the 1883 * platform. 1884 */ 1885 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | 1886 PCI_EXP_DEVCTL_READRQ; 1887 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | 1888 PCI_EXP_DEVCTL_READRQ); 1889 1890 /* Initialize Device Control Register */ 1891 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 1892 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); 1893 1894 /* Initialize Link Control Register */ 1895 if (pcie_cap_has_lnkctl(dev)) { 1896 1897 /* 1898 * If the Root Port supports Read Completion Boundary of 1899 * 128, set RCB to 128. Otherwise, clear it. 1900 */ 1901 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB; 1902 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB; 1903 if (pcie_root_rcb_set(dev)) 1904 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB; 1905 1906 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, 1907 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); 1908 } 1909 1910 /* Find Advanced Error Reporting Enhanced Capability */ 1911 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 1912 if (!pos) 1913 return; 1914 1915 /* Initialize Uncorrectable Error Mask Register */ 1916 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); 1917 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; 1918 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); 1919 1920 /* Initialize Uncorrectable Error Severity Register */ 1921 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); 1922 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; 1923 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); 1924 1925 /* Initialize Correctable Error Mask Register */ 1926 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); 1927 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; 1928 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); 1929 1930 /* Initialize Advanced Error Capabilities and Control Register */ 1931 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); 1932 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; 1933 1934 /* Don't enable ECRC generation or checking if unsupported */ 1935 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) 1936 reg32 &= ~PCI_ERR_CAP_ECRC_GENE; 1937 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC)) 1938 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE; 1939 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); 1940 1941 /* 1942 * FIXME: The following two registers are not supported yet. 1943 * 1944 * o Secondary Uncorrectable Error Severity Register 1945 * o Secondary Uncorrectable Error Mask Register 1946 */ 1947 } 1948 1949 int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 1950 { 1951 struct pci_host_bridge *host; 1952 u32 cap; 1953 u16 ctl; 1954 int ret; 1955 1956 if (!pci_is_pcie(dev)) 1957 return 0; 1958 1959 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 1960 if (ret) 1961 return 0; 1962 1963 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 1964 return 0; 1965 1966 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 1967 if (ret) 1968 return 0; 1969 1970 host = pci_find_host_bridge(dev->bus); 1971 if (!host) 1972 return 0; 1973 1974 /* 1975 * If some device in the hierarchy doesn't handle Extended Tags 1976 * correctly, make sure they're disabled. 1977 */ 1978 if (host->no_ext_tags) { 1979 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 1980 pci_info(dev, "disabling Extended Tags\n"); 1981 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 1982 PCI_EXP_DEVCTL_EXT_TAG); 1983 } 1984 return 0; 1985 } 1986 1987 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 1988 pci_info(dev, "enabling Extended Tags\n"); 1989 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 1990 PCI_EXP_DEVCTL_EXT_TAG); 1991 } 1992 return 0; 1993 } 1994 1995 /** 1996 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 1997 * @dev: PCI device to query 1998 * 1999 * Returns true if the device has enabled relaxed ordering attribute. 2000 */ 2001 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2002 { 2003 u16 v; 2004 2005 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2006 2007 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2008 } 2009 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2010 2011 static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2012 { 2013 struct pci_dev *root; 2014 2015 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ 2016 if (dev->is_virtfn) 2017 return; 2018 2019 if (!pcie_relaxed_ordering_enabled(dev)) 2020 return; 2021 2022 /* 2023 * For now, we only deal with Relaxed Ordering issues with Root 2024 * Ports. Peer-to-Peer DMA is another can of worms. 2025 */ 2026 root = pci_find_pcie_root_port(dev); 2027 if (!root) 2028 return; 2029 2030 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2031 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2032 PCI_EXP_DEVCTL_RELAX_EN); 2033 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2034 } 2035 } 2036 2037 static void pci_configure_ltr(struct pci_dev *dev) 2038 { 2039 #ifdef CONFIG_PCIEASPM 2040 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 2041 u32 cap; 2042 struct pci_dev *bridge; 2043 2044 if (!host->native_ltr) 2045 return; 2046 2047 if (!pci_is_pcie(dev)) 2048 return; 2049 2050 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2051 if (!(cap & PCI_EXP_DEVCAP2_LTR)) 2052 return; 2053 2054 /* 2055 * Software must not enable LTR in an Endpoint unless the Root 2056 * Complex and all intermediate Switches indicate support for LTR. 2057 * PCIe r3.1, sec 6.18. 2058 */ 2059 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2060 dev->ltr_path = 1; 2061 else { 2062 bridge = pci_upstream_bridge(dev); 2063 if (bridge && bridge->ltr_path) 2064 dev->ltr_path = 1; 2065 } 2066 2067 if (dev->ltr_path) 2068 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2069 PCI_EXP_DEVCTL2_LTR_EN); 2070 #endif 2071 } 2072 2073 static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2074 { 2075 #ifdef CONFIG_PCI_PASID 2076 struct pci_dev *bridge; 2077 u32 cap; 2078 2079 if (!pci_is_pcie(dev)) 2080 return; 2081 2082 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2083 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2084 return; 2085 2086 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2087 dev->eetlp_prefix_path = 1; 2088 else { 2089 bridge = pci_upstream_bridge(dev); 2090 if (bridge && bridge->eetlp_prefix_path) 2091 dev->eetlp_prefix_path = 1; 2092 } 2093 #endif 2094 } 2095 2096 static void pci_configure_device(struct pci_dev *dev) 2097 { 2098 struct hotplug_params hpp; 2099 int ret; 2100 2101 pci_configure_mps(dev); 2102 pci_configure_extended_tags(dev, NULL); 2103 pci_configure_relaxed_ordering(dev); 2104 pci_configure_ltr(dev); 2105 pci_configure_eetlp_prefix(dev); 2106 2107 memset(&hpp, 0, sizeof(hpp)); 2108 ret = pci_get_hp_params(dev, &hpp); 2109 if (ret) 2110 return; 2111 2112 program_hpp_type2(dev, hpp.t2); 2113 program_hpp_type1(dev, hpp.t1); 2114 program_hpp_type0(dev, hpp.t0); 2115 } 2116 2117 static void pci_release_capabilities(struct pci_dev *dev) 2118 { 2119 pci_aer_exit(dev); 2120 pci_vpd_release(dev); 2121 pci_iov_release(dev); 2122 pci_free_cap_save_buffers(dev); 2123 } 2124 2125 /** 2126 * pci_release_dev - Free a PCI device structure when all users of it are 2127 * finished 2128 * @dev: device that's been disconnected 2129 * 2130 * Will be called only by the device core when all users of this PCI device are 2131 * done. 2132 */ 2133 static void pci_release_dev(struct device *dev) 2134 { 2135 struct pci_dev *pci_dev; 2136 2137 pci_dev = to_pci_dev(dev); 2138 pci_release_capabilities(pci_dev); 2139 pci_release_of_node(pci_dev); 2140 pcibios_release_device(pci_dev); 2141 pci_bus_put(pci_dev->bus); 2142 kfree(pci_dev->driver_override); 2143 kfree(pci_dev->dma_alias_mask); 2144 kfree(pci_dev); 2145 } 2146 2147 struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2148 { 2149 struct pci_dev *dev; 2150 2151 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2152 if (!dev) 2153 return NULL; 2154 2155 INIT_LIST_HEAD(&dev->bus_list); 2156 dev->dev.type = &pci_dev_type; 2157 dev->bus = pci_bus_get(bus); 2158 2159 return dev; 2160 } 2161 EXPORT_SYMBOL(pci_alloc_dev); 2162 2163 static bool pci_bus_crs_vendor_id(u32 l) 2164 { 2165 return (l & 0xffff) == 0x0001; 2166 } 2167 2168 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 2169 int timeout) 2170 { 2171 int delay = 1; 2172 2173 if (!pci_bus_crs_vendor_id(*l)) 2174 return true; /* not a CRS completion */ 2175 2176 if (!timeout) 2177 return false; /* CRS, but caller doesn't want to wait */ 2178 2179 /* 2180 * We got the reserved Vendor ID that indicates a completion with 2181 * Configuration Request Retry Status (CRS). Retry until we get a 2182 * valid Vendor ID or we time out. 2183 */ 2184 while (pci_bus_crs_vendor_id(*l)) { 2185 if (delay > timeout) { 2186 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2187 pci_domain_nr(bus), bus->number, 2188 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2189 2190 return false; 2191 } 2192 if (delay >= 1000) 2193 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2194 pci_domain_nr(bus), bus->number, 2195 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2196 2197 msleep(delay); 2198 delay *= 2; 2199 2200 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2201 return false; 2202 } 2203 2204 if (delay >= 1000) 2205 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2206 pci_domain_nr(bus), bus->number, 2207 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2208 2209 return true; 2210 } 2211 2212 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2213 int timeout) 2214 { 2215 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2216 return false; 2217 2218 /* Some broken boards return 0 or ~0 if a slot is empty: */ 2219 if (*l == 0xffffffff || *l == 0x00000000 || 2220 *l == 0x0000ffff || *l == 0xffff0000) 2221 return false; 2222 2223 if (pci_bus_crs_vendor_id(*l)) 2224 return pci_bus_wait_crs(bus, devfn, l, timeout); 2225 2226 return true; 2227 } 2228 2229 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2230 int timeout) 2231 { 2232 #ifdef CONFIG_PCI_QUIRKS 2233 struct pci_dev *bridge = bus->self; 2234 2235 /* 2236 * Certain IDT switches have an issue where they improperly trigger 2237 * ACS Source Validation errors on completions for config reads. 2238 */ 2239 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2240 bridge->device == 0x80b5) 2241 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2242 #endif 2243 2244 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2245 } 2246 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2247 2248 /* 2249 * Read the config data for a PCI device, sanity-check it, 2250 * and fill in the dev structure. 2251 */ 2252 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2253 { 2254 struct pci_dev *dev; 2255 u32 l; 2256 2257 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2258 return NULL; 2259 2260 dev = pci_alloc_dev(bus); 2261 if (!dev) 2262 return NULL; 2263 2264 dev->devfn = devfn; 2265 dev->vendor = l & 0xffff; 2266 dev->device = (l >> 16) & 0xffff; 2267 2268 pci_set_of_node(dev); 2269 2270 if (pci_setup_device(dev)) { 2271 pci_bus_put(dev->bus); 2272 kfree(dev); 2273 return NULL; 2274 } 2275 2276 return dev; 2277 } 2278 2279 static void pcie_report_downtraining(struct pci_dev *dev) 2280 { 2281 if (!pci_is_pcie(dev)) 2282 return; 2283 2284 /* Look from the device up to avoid downstream ports with no devices */ 2285 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2286 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2287 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2288 return; 2289 2290 /* Multi-function PCIe devices share the same link/status */ 2291 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2292 return; 2293 2294 /* Print link status only if the device is constrained by the fabric */ 2295 __pcie_print_link_status(dev, false); 2296 } 2297 2298 static void pci_init_capabilities(struct pci_dev *dev) 2299 { 2300 /* Enhanced Allocation */ 2301 pci_ea_init(dev); 2302 2303 /* Setup MSI caps & disable MSI/MSI-X interrupts */ 2304 pci_msi_setup_pci_dev(dev); 2305 2306 /* Buffers for saving PCIe and PCI-X capabilities */ 2307 pci_allocate_cap_save_buffers(dev); 2308 2309 /* Power Management */ 2310 pci_pm_init(dev); 2311 2312 /* Vital Product Data */ 2313 pci_vpd_init(dev); 2314 2315 /* Alternative Routing-ID Forwarding */ 2316 pci_configure_ari(dev); 2317 2318 /* Single Root I/O Virtualization */ 2319 pci_iov_init(dev); 2320 2321 /* Address Translation Services */ 2322 pci_ats_init(dev); 2323 2324 /* Enable ACS P2P upstream forwarding */ 2325 pci_enable_acs(dev); 2326 2327 /* Precision Time Measurement */ 2328 pci_ptm_init(dev); 2329 2330 /* Advanced Error Reporting */ 2331 pci_aer_init(dev); 2332 2333 pcie_report_downtraining(dev); 2334 2335 if (pci_probe_reset_function(dev) == 0) 2336 dev->reset_fn = 1; 2337 } 2338 2339 /* 2340 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2341 * devices. Firmware interfaces that can select the MSI domain on a 2342 * per-device basis should be called from here. 2343 */ 2344 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2345 { 2346 struct irq_domain *d; 2347 2348 /* 2349 * If a domain has been set through the pcibios_add_device() 2350 * callback, then this is the one (platform code knows best). 2351 */ 2352 d = dev_get_msi_domain(&dev->dev); 2353 if (d) 2354 return d; 2355 2356 /* 2357 * Let's see if we have a firmware interface able to provide 2358 * the domain. 2359 */ 2360 d = pci_msi_get_device_domain(dev); 2361 if (d) 2362 return d; 2363 2364 return NULL; 2365 } 2366 2367 static void pci_set_msi_domain(struct pci_dev *dev) 2368 { 2369 struct irq_domain *d; 2370 2371 /* 2372 * If the platform or firmware interfaces cannot supply a 2373 * device-specific MSI domain, then inherit the default domain 2374 * from the host bridge itself. 2375 */ 2376 d = pci_dev_msi_domain(dev); 2377 if (!d) 2378 d = dev_get_msi_domain(&dev->bus->dev); 2379 2380 dev_set_msi_domain(&dev->dev, d); 2381 } 2382 2383 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2384 { 2385 int ret; 2386 2387 pci_configure_device(dev); 2388 2389 device_initialize(&dev->dev); 2390 dev->dev.release = pci_release_dev; 2391 2392 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2393 dev->dev.dma_mask = &dev->dma_mask; 2394 dev->dev.dma_parms = &dev->dma_parms; 2395 dev->dev.coherent_dma_mask = 0xffffffffull; 2396 2397 pci_set_dma_max_seg_size(dev, 65536); 2398 pci_set_dma_seg_boundary(dev, 0xffffffff); 2399 2400 /* Fix up broken headers */ 2401 pci_fixup_device(pci_fixup_header, dev); 2402 2403 /* Moved out from quirk header fixup code */ 2404 pci_reassigndev_resource_alignment(dev); 2405 2406 /* Clear the state_saved flag */ 2407 dev->state_saved = false; 2408 2409 /* Initialize various capabilities */ 2410 pci_init_capabilities(dev); 2411 2412 /* 2413 * Add the device to our list of discovered devices 2414 * and the bus list for fixup functions, etc. 2415 */ 2416 down_write(&pci_bus_sem); 2417 list_add_tail(&dev->bus_list, &bus->devices); 2418 up_write(&pci_bus_sem); 2419 2420 ret = pcibios_add_device(dev); 2421 WARN_ON(ret < 0); 2422 2423 /* Set up MSI IRQ domain */ 2424 pci_set_msi_domain(dev); 2425 2426 /* Notifier could use PCI capabilities */ 2427 dev->match_driver = false; 2428 ret = device_add(&dev->dev); 2429 WARN_ON(ret < 0); 2430 } 2431 2432 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2433 { 2434 struct pci_dev *dev; 2435 2436 dev = pci_get_slot(bus, devfn); 2437 if (dev) { 2438 pci_dev_put(dev); 2439 return dev; 2440 } 2441 2442 dev = pci_scan_device(bus, devfn); 2443 if (!dev) 2444 return NULL; 2445 2446 pci_device_add(dev, bus); 2447 2448 return dev; 2449 } 2450 EXPORT_SYMBOL(pci_scan_single_device); 2451 2452 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) 2453 { 2454 int pos; 2455 u16 cap = 0; 2456 unsigned next_fn; 2457 2458 if (pci_ari_enabled(bus)) { 2459 if (!dev) 2460 return 0; 2461 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2462 if (!pos) 2463 return 0; 2464 2465 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2466 next_fn = PCI_ARI_CAP_NFN(cap); 2467 if (next_fn <= fn) 2468 return 0; /* protect against malformed list */ 2469 2470 return next_fn; 2471 } 2472 2473 /* dev may be NULL for non-contiguous multifunction devices */ 2474 if (!dev || dev->multifunction) 2475 return (fn + 1) % 8; 2476 2477 return 0; 2478 } 2479 2480 static int only_one_child(struct pci_bus *bus) 2481 { 2482 struct pci_dev *bridge = bus->self; 2483 2484 /* 2485 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2486 * we scan for all possible devices, not just Device 0. 2487 */ 2488 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2489 return 0; 2490 2491 /* 2492 * A PCIe Downstream Port normally leads to a Link with only Device 2493 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2494 * only for Device 0 in that situation. 2495 * 2496 * Checking has_secondary_link is a hack to identify Downstream 2497 * Ports because sometimes Switches are configured such that the 2498 * PCIe Port Type labels are backwards. 2499 */ 2500 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link) 2501 return 1; 2502 2503 return 0; 2504 } 2505 2506 /** 2507 * pci_scan_slot - Scan a PCI slot on a bus for devices 2508 * @bus: PCI bus to scan 2509 * @devfn: slot number to scan (must have zero function) 2510 * 2511 * Scan a PCI slot on the specified PCI bus for devices, adding 2512 * discovered devices to the @bus->devices list. New devices 2513 * will not have is_added set. 2514 * 2515 * Returns the number of new devices found. 2516 */ 2517 int pci_scan_slot(struct pci_bus *bus, int devfn) 2518 { 2519 unsigned fn, nr = 0; 2520 struct pci_dev *dev; 2521 2522 if (only_one_child(bus) && (devfn > 0)) 2523 return 0; /* Already scanned the entire slot */ 2524 2525 dev = pci_scan_single_device(bus, devfn); 2526 if (!dev) 2527 return 0; 2528 if (!pci_dev_is_added(dev)) 2529 nr++; 2530 2531 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { 2532 dev = pci_scan_single_device(bus, devfn + fn); 2533 if (dev) { 2534 if (!pci_dev_is_added(dev)) 2535 nr++; 2536 dev->multifunction = 1; 2537 } 2538 } 2539 2540 /* Only one slot has PCIe device */ 2541 if (bus->self && nr) 2542 pcie_aspm_init_link_state(bus->self); 2543 2544 return nr; 2545 } 2546 EXPORT_SYMBOL(pci_scan_slot); 2547 2548 static int pcie_find_smpss(struct pci_dev *dev, void *data) 2549 { 2550 u8 *smpss = data; 2551 2552 if (!pci_is_pcie(dev)) 2553 return 0; 2554 2555 /* 2556 * We don't have a way to change MPS settings on devices that have 2557 * drivers attached. A hot-added device might support only the minimum 2558 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2559 * where devices may be hot-added, we limit the fabric MPS to 128 so 2560 * hot-added devices will work correctly. 2561 * 2562 * However, if we hot-add a device to a slot directly below a Root 2563 * Port, it's impossible for there to be other existing devices below 2564 * the port. We don't limit the MPS in this case because we can 2565 * reconfigure MPS on both the Root Port and the hot-added device, 2566 * and there are no other devices involved. 2567 * 2568 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2569 */ 2570 if (dev->is_hotplug_bridge && 2571 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2572 *smpss = 0; 2573 2574 if (*smpss > dev->pcie_mpss) 2575 *smpss = dev->pcie_mpss; 2576 2577 return 0; 2578 } 2579 2580 static void pcie_write_mps(struct pci_dev *dev, int mps) 2581 { 2582 int rc; 2583 2584 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 2585 mps = 128 << dev->pcie_mpss; 2586 2587 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2588 dev->bus->self) 2589 2590 /* 2591 * For "Performance", the assumption is made that 2592 * downstream communication will never be larger than 2593 * the MRRS. So, the MPS only needs to be configured 2594 * for the upstream communication. This being the case, 2595 * walk from the top down and set the MPS of the child 2596 * to that of the parent bus. 2597 * 2598 * Configure the device MPS with the smaller of the 2599 * device MPSS or the bridge MPS (which is assumed to be 2600 * properly configured at this point to the largest 2601 * allowable MPS based on its parent bus). 2602 */ 2603 mps = min(mps, pcie_get_mps(dev->bus->self)); 2604 } 2605 2606 rc = pcie_set_mps(dev, mps); 2607 if (rc) 2608 pci_err(dev, "Failed attempting to set the MPS\n"); 2609 } 2610 2611 static void pcie_write_mrrs(struct pci_dev *dev) 2612 { 2613 int rc, mrrs; 2614 2615 /* 2616 * In the "safe" case, do not configure the MRRS. There appear to be 2617 * issues with setting MRRS to 0 on a number of devices. 2618 */ 2619 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2620 return; 2621 2622 /* 2623 * For max performance, the MRRS must be set to the largest supported 2624 * value. However, it cannot be configured larger than the MPS the 2625 * device or the bus can support. This should already be properly 2626 * configured by a prior call to pcie_write_mps(). 2627 */ 2628 mrrs = pcie_get_mps(dev); 2629 2630 /* 2631 * MRRS is a R/W register. Invalid values can be written, but a 2632 * subsequent read will verify if the value is acceptable or not. 2633 * If the MRRS value provided is not acceptable (e.g., too large), 2634 * shrink the value until it is acceptable to the HW. 2635 */ 2636 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 2637 rc = pcie_set_readrq(dev, mrrs); 2638 if (!rc) 2639 break; 2640 2641 pci_warn(dev, "Failed attempting to set the MRRS\n"); 2642 mrrs /= 2; 2643 } 2644 2645 if (mrrs < 128) 2646 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 2647 } 2648 2649 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 2650 { 2651 int mps, orig_mps; 2652 2653 if (!pci_is_pcie(dev)) 2654 return 0; 2655 2656 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2657 pcie_bus_config == PCIE_BUS_DEFAULT) 2658 return 0; 2659 2660 mps = 128 << *(u8 *)data; 2661 orig_mps = pcie_get_mps(dev); 2662 2663 pcie_write_mps(dev, mps); 2664 pcie_write_mrrs(dev); 2665 2666 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 2667 pcie_get_mps(dev), 128 << dev->pcie_mpss, 2668 orig_mps, pcie_get_readrq(dev)); 2669 2670 return 0; 2671 } 2672 2673 /* 2674 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 2675 * parents then children fashion. If this changes, then this code will not 2676 * work as designed. 2677 */ 2678 void pcie_bus_configure_settings(struct pci_bus *bus) 2679 { 2680 u8 smpss = 0; 2681 2682 if (!bus->self) 2683 return; 2684 2685 if (!pci_is_pcie(bus->self)) 2686 return; 2687 2688 /* 2689 * FIXME - Peer to peer DMA is possible, though the endpoint would need 2690 * to be aware of the MPS of the destination. To work around this, 2691 * simply force the MPS of the entire system to the smallest possible. 2692 */ 2693 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2694 smpss = 0; 2695 2696 if (pcie_bus_config == PCIE_BUS_SAFE) { 2697 smpss = bus->self->pcie_mpss; 2698 2699 pcie_find_smpss(bus->self, &smpss); 2700 pci_walk_bus(bus, pcie_find_smpss, &smpss); 2701 } 2702 2703 pcie_bus_configure_set(bus->self, &smpss); 2704 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 2705 } 2706 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 2707 2708 /* 2709 * Called after each bus is probed, but before its children are examined. This 2710 * is marked as __weak because multiple architectures define it. 2711 */ 2712 void __weak pcibios_fixup_bus(struct pci_bus *bus) 2713 { 2714 /* nothing to do, expected to be removed in the future */ 2715 } 2716 2717 /** 2718 * pci_scan_child_bus_extend() - Scan devices below a bus 2719 * @bus: Bus to scan for devices 2720 * @available_buses: Total number of buses available (%0 does not try to 2721 * extend beyond the minimal) 2722 * 2723 * Scans devices below @bus including subordinate buses. Returns new 2724 * subordinate number including all the found devices. Passing 2725 * @available_buses causes the remaining bus space to be distributed 2726 * equally between hotplug-capable bridges to allow future extension of the 2727 * hierarchy. 2728 */ 2729 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 2730 unsigned int available_buses) 2731 { 2732 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 2733 unsigned int start = bus->busn_res.start; 2734 unsigned int devfn, fn, cmax, max = start; 2735 struct pci_dev *dev; 2736 int nr_devs; 2737 2738 dev_dbg(&bus->dev, "scanning bus\n"); 2739 2740 /* Go find them, Rover! */ 2741 for (devfn = 0; devfn < 256; devfn += 8) { 2742 nr_devs = pci_scan_slot(bus, devfn); 2743 2744 /* 2745 * The Jailhouse hypervisor may pass individual functions of a 2746 * multi-function device to a guest without passing function 0. 2747 * Look for them as well. 2748 */ 2749 if (jailhouse_paravirt() && nr_devs == 0) { 2750 for (fn = 1; fn < 8; fn++) { 2751 dev = pci_scan_single_device(bus, devfn + fn); 2752 if (dev) 2753 dev->multifunction = 1; 2754 } 2755 } 2756 } 2757 2758 /* Reserve buses for SR-IOV capability */ 2759 used_buses = pci_iov_bus_range(bus); 2760 max += used_buses; 2761 2762 /* 2763 * After performing arch-dependent fixup of the bus, look behind 2764 * all PCI-to-PCI bridges on this bus. 2765 */ 2766 if (!bus->is_added) { 2767 dev_dbg(&bus->dev, "fixups for bus\n"); 2768 pcibios_fixup_bus(bus); 2769 bus->is_added = 1; 2770 } 2771 2772 /* 2773 * Calculate how many hotplug bridges and normal bridges there 2774 * are on this bus. We will distribute the additional available 2775 * buses between hotplug bridges. 2776 */ 2777 for_each_pci_bridge(dev, bus) { 2778 if (dev->is_hotplug_bridge) 2779 hotplug_bridges++; 2780 else 2781 normal_bridges++; 2782 } 2783 2784 /* 2785 * Scan bridges that are already configured. We don't touch them 2786 * unless they are misconfigured (which will be done in the second 2787 * scan below). 2788 */ 2789 for_each_pci_bridge(dev, bus) { 2790 cmax = max; 2791 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 2792 2793 /* 2794 * Reserve one bus for each bridge now to avoid extending 2795 * hotplug bridges too much during the second scan below. 2796 */ 2797 used_buses++; 2798 if (cmax - max > 1) 2799 used_buses += cmax - max - 1; 2800 } 2801 2802 /* Scan bridges that need to be reconfigured */ 2803 for_each_pci_bridge(dev, bus) { 2804 unsigned int buses = 0; 2805 2806 if (!hotplug_bridges && normal_bridges == 1) { 2807 2808 /* 2809 * There is only one bridge on the bus (upstream 2810 * port) so it gets all available buses which it 2811 * can then distribute to the possible hotplug 2812 * bridges below. 2813 */ 2814 buses = available_buses; 2815 } else if (dev->is_hotplug_bridge) { 2816 2817 /* 2818 * Distribute the extra buses between hotplug 2819 * bridges if any. 2820 */ 2821 buses = available_buses / hotplug_bridges; 2822 buses = min(buses, available_buses - used_buses + 1); 2823 } 2824 2825 cmax = max; 2826 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 2827 /* One bus is already accounted so don't add it again */ 2828 if (max - cmax > 1) 2829 used_buses += max - cmax - 1; 2830 } 2831 2832 /* 2833 * Make sure a hotplug bridge has at least the minimum requested 2834 * number of buses but allow it to grow up to the maximum available 2835 * bus number of there is room. 2836 */ 2837 if (bus->self && bus->self->is_hotplug_bridge) { 2838 used_buses = max_t(unsigned int, available_buses, 2839 pci_hotplug_bus_size - 1); 2840 if (max - start < used_buses) { 2841 max = start + used_buses; 2842 2843 /* Do not allocate more buses than we have room left */ 2844 if (max > bus->busn_res.end) 2845 max = bus->busn_res.end; 2846 2847 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 2848 &bus->busn_res, max - start); 2849 } 2850 } 2851 2852 /* 2853 * We've scanned the bus and so we know all about what's on 2854 * the other side of any bridges that may be on this bus plus 2855 * any devices. 2856 * 2857 * Return how far we've got finding sub-buses. 2858 */ 2859 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 2860 return max; 2861 } 2862 2863 /** 2864 * pci_scan_child_bus() - Scan devices below a bus 2865 * @bus: Bus to scan for devices 2866 * 2867 * Scans devices below @bus including subordinate buses. Returns new 2868 * subordinate number including all the found devices. 2869 */ 2870 unsigned int pci_scan_child_bus(struct pci_bus *bus) 2871 { 2872 return pci_scan_child_bus_extend(bus, 0); 2873 } 2874 EXPORT_SYMBOL_GPL(pci_scan_child_bus); 2875 2876 /** 2877 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 2878 * @bridge: Host bridge to set up 2879 * 2880 * Default empty implementation. Replace with an architecture-specific setup 2881 * routine, if necessary. 2882 */ 2883 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 2884 { 2885 return 0; 2886 } 2887 2888 void __weak pcibios_add_bus(struct pci_bus *bus) 2889 { 2890 } 2891 2892 void __weak pcibios_remove_bus(struct pci_bus *bus) 2893 { 2894 } 2895 2896 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 2897 struct pci_ops *ops, void *sysdata, struct list_head *resources) 2898 { 2899 int error; 2900 struct pci_host_bridge *bridge; 2901 2902 bridge = pci_alloc_host_bridge(0); 2903 if (!bridge) 2904 return NULL; 2905 2906 bridge->dev.parent = parent; 2907 2908 list_splice_init(resources, &bridge->windows); 2909 bridge->sysdata = sysdata; 2910 bridge->busnr = bus; 2911 bridge->ops = ops; 2912 2913 error = pci_register_host_bridge(bridge); 2914 if (error < 0) 2915 goto err_out; 2916 2917 return bridge->bus; 2918 2919 err_out: 2920 kfree(bridge); 2921 return NULL; 2922 } 2923 EXPORT_SYMBOL_GPL(pci_create_root_bus); 2924 2925 int pci_host_probe(struct pci_host_bridge *bridge) 2926 { 2927 struct pci_bus *bus, *child; 2928 int ret; 2929 2930 ret = pci_scan_root_bus_bridge(bridge); 2931 if (ret < 0) { 2932 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 2933 return ret; 2934 } 2935 2936 bus = bridge->bus; 2937 2938 /* 2939 * We insert PCI resources into the iomem_resource and 2940 * ioport_resource trees in either pci_bus_claim_resources() 2941 * or pci_bus_assign_resources(). 2942 */ 2943 if (pci_has_flag(PCI_PROBE_ONLY)) { 2944 pci_bus_claim_resources(bus); 2945 } else { 2946 pci_bus_size_bridges(bus); 2947 pci_bus_assign_resources(bus); 2948 2949 list_for_each_entry(child, &bus->children, node) 2950 pcie_bus_configure_settings(child); 2951 } 2952 2953 pci_bus_add_devices(bus); 2954 return 0; 2955 } 2956 EXPORT_SYMBOL_GPL(pci_host_probe); 2957 2958 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 2959 { 2960 struct resource *res = &b->busn_res; 2961 struct resource *parent_res, *conflict; 2962 2963 res->start = bus; 2964 res->end = bus_max; 2965 res->flags = IORESOURCE_BUS; 2966 2967 if (!pci_is_root_bus(b)) 2968 parent_res = &b->parent->busn_res; 2969 else { 2970 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 2971 res->flags |= IORESOURCE_PCI_FIXED; 2972 } 2973 2974 conflict = request_resource_conflict(parent_res, res); 2975 2976 if (conflict) 2977 dev_printk(KERN_DEBUG, &b->dev, 2978 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 2979 res, pci_is_root_bus(b) ? "domain " : "", 2980 parent_res, conflict->name, conflict); 2981 2982 return conflict == NULL; 2983 } 2984 2985 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 2986 { 2987 struct resource *res = &b->busn_res; 2988 struct resource old_res = *res; 2989 resource_size_t size; 2990 int ret; 2991 2992 if (res->start > bus_max) 2993 return -EINVAL; 2994 2995 size = bus_max - res->start + 1; 2996 ret = adjust_resource(res, res->start, size); 2997 dev_printk(KERN_DEBUG, &b->dev, 2998 "busn_res: %pR end %s updated to %02x\n", 2999 &old_res, ret ? "can not be" : "is", bus_max); 3000 3001 if (!ret && !res->parent) 3002 pci_bus_insert_busn_res(b, res->start, res->end); 3003 3004 return ret; 3005 } 3006 3007 void pci_bus_release_busn_res(struct pci_bus *b) 3008 { 3009 struct resource *res = &b->busn_res; 3010 int ret; 3011 3012 if (!res->flags || !res->parent) 3013 return; 3014 3015 ret = release_resource(res); 3016 dev_printk(KERN_DEBUG, &b->dev, 3017 "busn_res: %pR %s released\n", 3018 res, ret ? "can not be" : "is"); 3019 } 3020 3021 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3022 { 3023 struct resource_entry *window; 3024 bool found = false; 3025 struct pci_bus *b; 3026 int max, bus, ret; 3027 3028 if (!bridge) 3029 return -EINVAL; 3030 3031 resource_list_for_each_entry(window, &bridge->windows) 3032 if (window->res->flags & IORESOURCE_BUS) { 3033 found = true; 3034 break; 3035 } 3036 3037 ret = pci_register_host_bridge(bridge); 3038 if (ret < 0) 3039 return ret; 3040 3041 b = bridge->bus; 3042 bus = bridge->busnr; 3043 3044 if (!found) { 3045 dev_info(&b->dev, 3046 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3047 bus); 3048 pci_bus_insert_busn_res(b, bus, 255); 3049 } 3050 3051 max = pci_scan_child_bus(b); 3052 3053 if (!found) 3054 pci_bus_update_busn_res_end(b, max); 3055 3056 return 0; 3057 } 3058 EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3059 3060 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3061 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3062 { 3063 struct resource_entry *window; 3064 bool found = false; 3065 struct pci_bus *b; 3066 int max; 3067 3068 resource_list_for_each_entry(window, resources) 3069 if (window->res->flags & IORESOURCE_BUS) { 3070 found = true; 3071 break; 3072 } 3073 3074 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3075 if (!b) 3076 return NULL; 3077 3078 if (!found) { 3079 dev_info(&b->dev, 3080 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3081 bus); 3082 pci_bus_insert_busn_res(b, bus, 255); 3083 } 3084 3085 max = pci_scan_child_bus(b); 3086 3087 if (!found) 3088 pci_bus_update_busn_res_end(b, max); 3089 3090 return b; 3091 } 3092 EXPORT_SYMBOL(pci_scan_root_bus); 3093 3094 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3095 void *sysdata) 3096 { 3097 LIST_HEAD(resources); 3098 struct pci_bus *b; 3099 3100 pci_add_resource(&resources, &ioport_resource); 3101 pci_add_resource(&resources, &iomem_resource); 3102 pci_add_resource(&resources, &busn_resource); 3103 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3104 if (b) { 3105 pci_scan_child_bus(b); 3106 } else { 3107 pci_free_resource_list(&resources); 3108 } 3109 return b; 3110 } 3111 EXPORT_SYMBOL(pci_scan_bus); 3112 3113 /** 3114 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3115 * @bridge: PCI bridge for the bus to scan 3116 * 3117 * Scan a PCI bus and child buses for new devices, add them, 3118 * and enable them, resizing bridge mmio/io resource if necessary 3119 * and possible. The caller must ensure the child devices are already 3120 * removed for resizing to occur. 3121 * 3122 * Returns the max number of subordinate bus discovered. 3123 */ 3124 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3125 { 3126 unsigned int max; 3127 struct pci_bus *bus = bridge->subordinate; 3128 3129 max = pci_scan_child_bus(bus); 3130 3131 pci_assign_unassigned_bridge_resources(bridge); 3132 3133 pci_bus_add_devices(bus); 3134 3135 return max; 3136 } 3137 3138 /** 3139 * pci_rescan_bus - Scan a PCI bus for devices 3140 * @bus: PCI bus to scan 3141 * 3142 * Scan a PCI bus and child buses for new devices, add them, 3143 * and enable them. 3144 * 3145 * Returns the max number of subordinate bus discovered. 3146 */ 3147 unsigned int pci_rescan_bus(struct pci_bus *bus) 3148 { 3149 unsigned int max; 3150 3151 max = pci_scan_child_bus(bus); 3152 pci_assign_unassigned_bus_resources(bus); 3153 pci_bus_add_devices(bus); 3154 3155 return max; 3156 } 3157 EXPORT_SYMBOL_GPL(pci_rescan_bus); 3158 3159 /* 3160 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3161 * routines should always be executed under this mutex. 3162 */ 3163 static DEFINE_MUTEX(pci_rescan_remove_lock); 3164 3165 void pci_lock_rescan_remove(void) 3166 { 3167 mutex_lock(&pci_rescan_remove_lock); 3168 } 3169 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3170 3171 void pci_unlock_rescan_remove(void) 3172 { 3173 mutex_unlock(&pci_rescan_remove_lock); 3174 } 3175 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3176 3177 static int __init pci_sort_bf_cmp(const struct device *d_a, 3178 const struct device *d_b) 3179 { 3180 const struct pci_dev *a = to_pci_dev(d_a); 3181 const struct pci_dev *b = to_pci_dev(d_b); 3182 3183 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3184 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3185 3186 if (a->bus->number < b->bus->number) return -1; 3187 else if (a->bus->number > b->bus->number) return 1; 3188 3189 if (a->devfn < b->devfn) return -1; 3190 else if (a->devfn > b->devfn) return 1; 3191 3192 return 0; 3193 } 3194 3195 void __init pci_sort_breadthfirst(void) 3196 { 3197 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3198 } 3199 3200 int pci_hp_add_bridge(struct pci_dev *dev) 3201 { 3202 struct pci_bus *parent = dev->bus; 3203 int busnr, start = parent->busn_res.start; 3204 unsigned int available_buses = 0; 3205 int end = parent->busn_res.end; 3206 3207 for (busnr = start; busnr <= end; busnr++) { 3208 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3209 break; 3210 } 3211 if (busnr-- > end) { 3212 pci_err(dev, "No bus number available for hot-added bridge\n"); 3213 return -1; 3214 } 3215 3216 /* Scan bridges that are already configured */ 3217 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3218 3219 /* 3220 * Distribute the available bus numbers between hotplug-capable 3221 * bridges to make extending the chain later possible. 3222 */ 3223 available_buses = end - busnr; 3224 3225 /* Scan bridges that need to be reconfigured */ 3226 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3227 3228 if (!dev->subordinate) 3229 return -1; 3230 3231 return 0; 3232 } 3233 EXPORT_SYMBOL_GPL(pci_hp_add_bridge); 3234