1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI Express Precision Time Measurement 4 * Copyright (c) 2016, Intel Corporation. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include "../pci.h" 11 12 static void pci_ptm_info(struct pci_dev *dev) 13 { 14 char clock_desc[8]; 15 16 switch (dev->ptm_granularity) { 17 case 0: 18 snprintf(clock_desc, sizeof(clock_desc), "unknown"); 19 break; 20 case 255: 21 snprintf(clock_desc, sizeof(clock_desc), ">254ns"); 22 break; 23 default: 24 snprintf(clock_desc, sizeof(clock_desc), "%uns", 25 dev->ptm_granularity); 26 break; 27 } 28 pci_info(dev, "PTM enabled%s, %s granularity\n", 29 dev->ptm_root ? " (root)" : "", clock_desc); 30 } 31 32 void pci_disable_ptm(struct pci_dev *dev) 33 { 34 int ptm; 35 u16 ctrl; 36 37 if (!pci_is_pcie(dev)) 38 return; 39 40 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 41 if (!ptm) 42 return; 43 44 pci_read_config_word(dev, ptm + PCI_PTM_CTRL, &ctrl); 45 ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT); 46 pci_write_config_word(dev, ptm + PCI_PTM_CTRL, ctrl); 47 } 48 49 void pci_save_ptm_state(struct pci_dev *dev) 50 { 51 int ptm; 52 struct pci_cap_saved_state *save_state; 53 u16 *cap; 54 55 if (!pci_is_pcie(dev)) 56 return; 57 58 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 59 if (!ptm) 60 return; 61 62 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); 63 if (!save_state) { 64 pci_err(dev, "no suspend buffer for PTM\n"); 65 return; 66 } 67 68 cap = (u16 *)&save_state->cap.data[0]; 69 pci_read_config_word(dev, ptm + PCI_PTM_CTRL, cap); 70 } 71 72 void pci_restore_ptm_state(struct pci_dev *dev) 73 { 74 struct pci_cap_saved_state *save_state; 75 int ptm; 76 u16 *cap; 77 78 if (!pci_is_pcie(dev)) 79 return; 80 81 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); 82 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 83 if (!save_state || !ptm) 84 return; 85 86 cap = (u16 *)&save_state->cap.data[0]; 87 pci_write_config_word(dev, ptm + PCI_PTM_CTRL, *cap); 88 } 89 90 void pci_ptm_init(struct pci_dev *dev) 91 { 92 int pos; 93 u32 cap, ctrl; 94 u8 local_clock; 95 struct pci_dev *ups; 96 97 if (!pci_is_pcie(dev)) 98 return; 99 100 /* 101 * Enable PTM only on interior devices (root ports, switch ports, 102 * etc.) on the assumption that it causes no link traffic until an 103 * endpoint enables it. 104 */ 105 if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT || 106 pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)) 107 return; 108 109 /* 110 * Switch Downstream Ports are not permitted to have a PTM 111 * capability; their PTM behavior is controlled by the Upstream 112 * Port (PCIe r5.0, sec 7.9.16). 113 */ 114 ups = pci_upstream_bridge(dev); 115 if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM && 116 ups && ups->ptm_enabled) { 117 dev->ptm_granularity = ups->ptm_granularity; 118 dev->ptm_enabled = 1; 119 return; 120 } 121 122 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 123 if (!pos) 124 return; 125 126 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u16)); 127 128 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap); 129 local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8; 130 131 /* 132 * There's no point in enabling PTM unless it's enabled in the 133 * upstream device or this device can be a PTM Root itself. Per 134 * the spec recommendation (PCIe r3.1, sec 7.32.3), select the 135 * furthest upstream Time Source as the PTM Root. 136 */ 137 if (ups && ups->ptm_enabled) { 138 ctrl = PCI_PTM_CTRL_ENABLE; 139 if (ups->ptm_granularity == 0) 140 dev->ptm_granularity = 0; 141 else if (ups->ptm_granularity > local_clock) 142 dev->ptm_granularity = ups->ptm_granularity; 143 } else { 144 if (cap & PCI_PTM_CAP_ROOT) { 145 ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT; 146 dev->ptm_root = 1; 147 dev->ptm_granularity = local_clock; 148 } else 149 return; 150 } 151 152 ctrl |= dev->ptm_granularity << 8; 153 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl); 154 dev->ptm_enabled = 1; 155 156 pci_ptm_info(dev); 157 } 158 159 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 160 { 161 int pos; 162 u32 cap, ctrl; 163 struct pci_dev *ups; 164 165 if (!pci_is_pcie(dev)) 166 return -EINVAL; 167 168 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 169 if (!pos) 170 return -EINVAL; 171 172 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap); 173 if (!(cap & PCI_PTM_CAP_REQ)) 174 return -EINVAL; 175 176 /* 177 * For a PCIe Endpoint, PTM is only useful if the endpoint can 178 * issue PTM requests to upstream devices that have PTM enabled. 179 * 180 * For Root Complex Integrated Endpoints, there is no upstream 181 * device, so there must be some implementation-specific way to 182 * associate the endpoint with a time source. 183 */ 184 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) { 185 ups = pci_upstream_bridge(dev); 186 if (!ups || !ups->ptm_enabled) 187 return -EINVAL; 188 189 dev->ptm_granularity = ups->ptm_granularity; 190 } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 191 dev->ptm_granularity = 0; 192 } else 193 return -EINVAL; 194 195 ctrl = PCI_PTM_CTRL_ENABLE; 196 ctrl |= dev->ptm_granularity << 8; 197 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl); 198 dev->ptm_enabled = 1; 199 200 pci_ptm_info(dev); 201 202 if (granularity) 203 *granularity = dev->ptm_granularity; 204 return 0; 205 } 206 EXPORT_SYMBOL(pci_enable_ptm); 207