1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Purpose: PCI Express Port Bus Driver's Internal Data Structures 4 * 5 * Copyright (C) 2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9 #ifndef _PORTDRV_H_ 10 #define _PORTDRV_H_ 11 12 #include <linux/compiler.h> 13 14 /* Service Type */ 15 #define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */ 16 #define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT) 17 #define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */ 18 #define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT) 19 #define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */ 20 #define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT) 21 #define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */ 22 #define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT) 23 #define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4 /* Bandwidth notification */ 24 #define PCIE_PORT_SERVICE_BWNOTIF (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT) 25 26 #define PCIE_PORT_DEVICE_MAXSERVICES 5 27 28 extern bool pcie_ports_dpc_native; 29 30 #ifdef CONFIG_PCIEAER 31 int pcie_aer_init(void); 32 int pcie_aer_is_native(struct pci_dev *dev); 33 #else 34 static inline int pcie_aer_init(void) { return 0; } 35 static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } 36 #endif 37 38 #ifdef CONFIG_HOTPLUG_PCI_PCIE 39 int pcie_hp_init(void); 40 #else 41 static inline int pcie_hp_init(void) { return 0; } 42 #endif 43 44 #ifdef CONFIG_PCIE_PME 45 int pcie_pme_init(void); 46 #else 47 static inline int pcie_pme_init(void) { return 0; } 48 #endif 49 50 #ifdef CONFIG_PCIE_DPC 51 int pcie_dpc_init(void); 52 #else 53 static inline int pcie_dpc_init(void) { return 0; } 54 #endif 55 56 #ifdef CONFIG_PCIE_BW 57 int pcie_bandwidth_notification_init(void); 58 #else 59 static inline int pcie_bandwidth_notification_init(void) { return 0; } 60 #endif 61 62 /* Port Type */ 63 #define PCIE_ANY_PORT (~0) 64 65 struct pcie_device { 66 int irq; /* Service IRQ/MSI/MSI-X Vector */ 67 struct pci_dev *port; /* Root/Upstream/Downstream Port */ 68 u32 service; /* Port service this device represents */ 69 void *priv_data; /* Service Private Data */ 70 struct device device; /* Generic Device Interface */ 71 }; 72 #define to_pcie_device(d) container_of(d, struct pcie_device, device) 73 74 static inline void set_service_data(struct pcie_device *dev, void *data) 75 { 76 dev->priv_data = data; 77 } 78 79 static inline void *get_service_data(struct pcie_device *dev) 80 { 81 return dev->priv_data; 82 } 83 84 struct pcie_port_service_driver { 85 const char *name; 86 int (*probe)(struct pcie_device *dev); 87 void (*remove)(struct pcie_device *dev); 88 int (*suspend)(struct pcie_device *dev); 89 int (*resume_noirq)(struct pcie_device *dev); 90 int (*resume)(struct pcie_device *dev); 91 int (*runtime_suspend)(struct pcie_device *dev); 92 int (*runtime_resume)(struct pcie_device *dev); 93 94 /* Device driver may resume normal operations */ 95 void (*error_resume)(struct pci_dev *dev); 96 97 int port_type; /* Type of the port this driver can handle */ 98 u32 service; /* Port service this device represents */ 99 100 struct device_driver driver; 101 }; 102 #define to_service_driver(d) \ 103 container_of(d, struct pcie_port_service_driver, driver) 104 105 int pcie_port_service_register(struct pcie_port_service_driver *new); 106 void pcie_port_service_unregister(struct pcie_port_service_driver *new); 107 108 /* 109 * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must 110 * be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI 111 * supports a maximum of 32 vectors per function. 112 */ 113 #define PCIE_PORT_MAX_MSI_ENTRIES 32 114 115 #define get_descriptor_id(type, service) (((type - 4) << 8) | service) 116 117 extern struct bus_type pcie_port_bus_type; 118 int pcie_port_device_register(struct pci_dev *dev); 119 #ifdef CONFIG_PM 120 int pcie_port_device_suspend(struct device *dev); 121 int pcie_port_device_resume_noirq(struct device *dev); 122 int pcie_port_device_resume(struct device *dev); 123 int pcie_port_device_runtime_suspend(struct device *dev); 124 int pcie_port_device_runtime_resume(struct device *dev); 125 #endif 126 void pcie_port_device_remove(struct pci_dev *dev); 127 int __must_check pcie_port_bus_register(void); 128 void pcie_port_bus_unregister(void); 129 130 struct pci_dev; 131 132 #ifdef CONFIG_PCIE_PME 133 extern bool pcie_pme_msi_disabled; 134 135 static inline void pcie_pme_disable_msi(void) 136 { 137 pcie_pme_msi_disabled = true; 138 } 139 140 static inline bool pcie_pme_no_msi(void) 141 { 142 return pcie_pme_msi_disabled; 143 } 144 145 void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable); 146 #else /* !CONFIG_PCIE_PME */ 147 static inline void pcie_pme_disable_msi(void) {} 148 static inline bool pcie_pme_no_msi(void) { return false; } 149 static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} 150 #endif /* !CONFIG_PCIE_PME */ 151 152 struct device *pcie_port_find_device(struct pci_dev *dev, u32 service); 153 #endif /* _PORTDRV_H_ */ 154