1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI Express Downstream Port Containment services driver 4 * Author: Keith Busch <keith.busch@intel.com> 5 * 6 * Copyright (C) 2016 Intel Corp. 7 */ 8 9 #define dev_fmt(fmt) "DPC: " fmt 10 11 #include <linux/aer.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 17 #include "portdrv.h" 18 #include "../pci.h" 19 20 static const char * const rp_pio_error_string[] = { 21 "Configuration Request received UR Completion", /* Bit Position 0 */ 22 "Configuration Request received CA Completion", /* Bit Position 1 */ 23 "Configuration Request Completion Timeout", /* Bit Position 2 */ 24 NULL, 25 NULL, 26 NULL, 27 NULL, 28 NULL, 29 "I/O Request received UR Completion", /* Bit Position 8 */ 30 "I/O Request received CA Completion", /* Bit Position 9 */ 31 "I/O Request Completion Timeout", /* Bit Position 10 */ 32 NULL, 33 NULL, 34 NULL, 35 NULL, 36 NULL, 37 "Memory Request received UR Completion", /* Bit Position 16 */ 38 "Memory Request received CA Completion", /* Bit Position 17 */ 39 "Memory Request Completion Timeout", /* Bit Position 18 */ 40 }; 41 42 void pci_save_dpc_state(struct pci_dev *dev) 43 { 44 struct pci_cap_saved_state *save_state; 45 u16 *cap; 46 47 if (!pci_is_pcie(dev)) 48 return; 49 50 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC); 51 if (!save_state) 52 return; 53 54 cap = (u16 *)&save_state->cap.data[0]; 55 pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap); 56 } 57 58 void pci_restore_dpc_state(struct pci_dev *dev) 59 { 60 struct pci_cap_saved_state *save_state; 61 u16 *cap; 62 63 if (!pci_is_pcie(dev)) 64 return; 65 66 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC); 67 if (!save_state) 68 return; 69 70 cap = (u16 *)&save_state->cap.data[0]; 71 pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap); 72 } 73 74 static int dpc_wait_rp_inactive(struct pci_dev *pdev) 75 { 76 unsigned long timeout = jiffies + HZ; 77 u16 cap = pdev->dpc_cap, status; 78 79 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 80 while (status & PCI_EXP_DPC_RP_BUSY && 81 !time_after(jiffies, timeout)) { 82 msleep(10); 83 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 84 } 85 if (status & PCI_EXP_DPC_RP_BUSY) { 86 pci_warn(pdev, "root port still busy\n"); 87 return -EBUSY; 88 } 89 return 0; 90 } 91 92 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 93 { 94 u16 cap; 95 96 /* 97 * DPC disables the Link automatically in hardware, so it has 98 * already been reset by the time we get here. 99 */ 100 cap = pdev->dpc_cap; 101 102 /* 103 * Wait until the Link is inactive, then clear DPC Trigger Status 104 * to allow the Port to leave DPC. 105 */ 106 if (!pcie_wait_for_link(pdev, false)) 107 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n"); 108 109 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) 110 return PCI_ERS_RESULT_DISCONNECT; 111 112 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 113 PCI_EXP_DPC_STATUS_TRIGGER); 114 115 if (!pcie_wait_for_link(pdev, true)) { 116 pci_info(pdev, "Data Link Layer Link Active not set in 1000 msec\n"); 117 return PCI_ERS_RESULT_DISCONNECT; 118 } 119 120 return PCI_ERS_RESULT_RECOVERED; 121 } 122 123 static void dpc_process_rp_pio_error(struct pci_dev *pdev) 124 { 125 u16 cap = pdev->dpc_cap, dpc_status, first_error; 126 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; 127 int i; 128 129 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); 130 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); 131 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", 132 status, mask); 133 134 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); 135 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); 136 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); 137 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", 138 sev, syserr, exc); 139 140 /* Get First Error Pointer */ 141 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); 142 first_error = (dpc_status & 0x1f00) >> 8; 143 144 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { 145 if ((status & ~mask) & (1 << i)) 146 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i], 147 first_error == i ? " (First)" : ""); 148 } 149 150 if (pdev->dpc_rp_log_size < 4) 151 goto clear_status; 152 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, 153 &dw0); 154 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, 155 &dw1); 156 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, 157 &dw2); 158 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, 159 &dw3); 160 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n", 161 dw0, dw1, dw2, dw3); 162 163 if (pdev->dpc_rp_log_size < 5) 164 goto clear_status; 165 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); 166 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log); 167 168 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) { 169 pci_read_config_dword(pdev, 170 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix); 171 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); 172 } 173 clear_status: 174 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status); 175 } 176 177 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev, 178 struct aer_err_info *info) 179 { 180 int pos = dev->aer_cap; 181 u32 status, mask, sev; 182 183 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); 184 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask); 185 status &= ~mask; 186 if (!status) 187 return 0; 188 189 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev); 190 status &= sev; 191 if (status) 192 info->severity = AER_FATAL; 193 else 194 info->severity = AER_NONFATAL; 195 196 return 1; 197 } 198 199 void dpc_process_error(struct pci_dev *pdev) 200 { 201 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason; 202 struct aer_err_info info; 203 204 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 205 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source); 206 207 pci_info(pdev, "containment event, status:%#06x source:%#06x\n", 208 status, source); 209 210 reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; 211 ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; 212 pci_warn(pdev, "%s detected\n", 213 (reason == 0) ? "unmasked uncorrectable error" : 214 (reason == 1) ? "ERR_NONFATAL" : 215 (reason == 2) ? "ERR_FATAL" : 216 (ext_reason == 0) ? "RP PIO error" : 217 (ext_reason == 1) ? "software trigger" : 218 "reserved error"); 219 220 /* show RP PIO error detail information */ 221 if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0) 222 dpc_process_rp_pio_error(pdev); 223 else if (reason == 0 && 224 dpc_get_aer_uncorrect_severity(pdev, &info) && 225 aer_get_device_error_info(pdev, &info)) { 226 aer_print_error(pdev, &info); 227 pci_aer_clear_nonfatal_status(pdev); 228 pci_aer_clear_fatal_status(pdev); 229 } 230 } 231 232 static irqreturn_t dpc_handler(int irq, void *context) 233 { 234 struct pci_dev *pdev = context; 235 236 dpc_process_error(pdev); 237 238 /* We configure DPC so it only triggers on ERR_FATAL */ 239 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link); 240 241 return IRQ_HANDLED; 242 } 243 244 static irqreturn_t dpc_irq(int irq, void *context) 245 { 246 struct pci_dev *pdev = context; 247 u16 cap = pdev->dpc_cap, status; 248 249 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 250 251 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || status == (u16)(~0)) 252 return IRQ_NONE; 253 254 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 255 PCI_EXP_DPC_STATUS_INTERRUPT); 256 if (status & PCI_EXP_DPC_STATUS_TRIGGER) 257 return IRQ_WAKE_THREAD; 258 return IRQ_HANDLED; 259 } 260 261 void pci_dpc_init(struct pci_dev *pdev) 262 { 263 u16 cap; 264 265 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC); 266 if (!pdev->dpc_cap) 267 return; 268 269 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); 270 if (!(cap & PCI_EXP_DPC_CAP_RP_EXT)) 271 return; 272 273 pdev->dpc_rp_extensions = true; 274 pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; 275 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { 276 pci_err(pdev, "RP PIO log size %u is invalid\n", 277 pdev->dpc_rp_log_size); 278 pdev->dpc_rp_log_size = 0; 279 } 280 } 281 282 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 283 static int dpc_probe(struct pcie_device *dev) 284 { 285 struct pci_dev *pdev = dev->port; 286 struct device *device = &dev->device; 287 int status; 288 u16 ctl, cap; 289 290 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native) 291 return -ENOTSUPP; 292 293 status = devm_request_threaded_irq(device, dev->irq, dpc_irq, 294 dpc_handler, IRQF_SHARED, 295 "pcie-dpc", pdev); 296 if (status) { 297 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq, 298 status); 299 return status; 300 } 301 302 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); 303 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); 304 305 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 306 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); 307 pci_info(pdev, "enabled with IRQ %d\n", dev->irq); 308 309 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", 310 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), 311 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP), 312 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size, 313 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE)); 314 315 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16)); 316 return status; 317 } 318 319 static void dpc_remove(struct pcie_device *dev) 320 { 321 struct pci_dev *pdev = dev->port; 322 u16 ctl; 323 324 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); 325 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN); 326 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); 327 } 328 329 static struct pcie_port_service_driver dpcdriver = { 330 .name = "dpc", 331 .port_type = PCIE_ANY_PORT, 332 .service = PCIE_PORT_SERVICE_DPC, 333 .probe = dpc_probe, 334 .remove = dpc_remove, 335 }; 336 337 int __init pcie_dpc_init(void) 338 { 339 return pcie_port_service_register(&dpcdriver); 340 } 341