1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI Express Downstream Port Containment services driver 4 * Author: Keith Busch <keith.busch@intel.com> 5 * 6 * Copyright (C) 2016 Intel Corp. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/init.h> 12 #include <linux/pci.h> 13 14 #include "portdrv.h" 15 #include "../pci.h" 16 17 struct dpc_dev { 18 struct pcie_device *dev; 19 struct work_struct work; 20 u16 cap_pos; 21 bool rp_extensions; 22 u32 rp_pio_status; 23 u8 rp_log_size; 24 }; 25 26 static const char * const rp_pio_error_string[] = { 27 "Configuration Request received UR Completion", /* Bit Position 0 */ 28 "Configuration Request received CA Completion", /* Bit Position 1 */ 29 "Configuration Request Completion Timeout", /* Bit Position 2 */ 30 NULL, 31 NULL, 32 NULL, 33 NULL, 34 NULL, 35 "I/O Request received UR Completion", /* Bit Position 8 */ 36 "I/O Request received CA Completion", /* Bit Position 9 */ 37 "I/O Request Completion Timeout", /* Bit Position 10 */ 38 NULL, 39 NULL, 40 NULL, 41 NULL, 42 NULL, 43 "Memory Request received UR Completion", /* Bit Position 16 */ 44 "Memory Request received CA Completion", /* Bit Position 17 */ 45 "Memory Request Completion Timeout", /* Bit Position 18 */ 46 }; 47 48 static int dpc_wait_rp_inactive(struct dpc_dev *dpc) 49 { 50 unsigned long timeout = jiffies + HZ; 51 struct pci_dev *pdev = dpc->dev->port; 52 struct device *dev = &dpc->dev->device; 53 u16 cap = dpc->cap_pos, status; 54 55 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 56 while (status & PCI_EXP_DPC_RP_BUSY && 57 !time_after(jiffies, timeout)) { 58 msleep(10); 59 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 60 } 61 if (status & PCI_EXP_DPC_RP_BUSY) { 62 dev_warn(dev, "DPC root port still busy\n"); 63 return -EBUSY; 64 } 65 return 0; 66 } 67 68 static void dpc_wait_link_inactive(struct dpc_dev *dpc) 69 { 70 struct pci_dev *pdev = dpc->dev->port; 71 72 pcie_wait_for_link(pdev, false); 73 } 74 75 static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 76 { 77 struct dpc_dev *dpc; 78 struct pcie_device *pciedev; 79 struct device *devdpc; 80 u16 cap, ctl; 81 82 /* 83 * DPC disables the Link automatically in hardware, so it has 84 * already been reset by the time we get here. 85 */ 86 devdpc = pcie_port_find_device(pdev, PCIE_PORT_SERVICE_DPC); 87 pciedev = to_pcie_device(devdpc); 88 dpc = get_service_data(pciedev); 89 cap = dpc->cap_pos; 90 91 /* 92 * Wait until the Link is inactive, then clear DPC Trigger Status 93 * to allow the Port to leave DPC. 94 */ 95 dpc_wait_link_inactive(dpc); 96 97 if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc)) 98 return PCI_ERS_RESULT_DISCONNECT; 99 if (dpc->rp_extensions && dpc->rp_pio_status) { 100 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, 101 dpc->rp_pio_status); 102 dpc->rp_pio_status = 0; 103 } 104 105 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 106 PCI_EXP_DPC_STATUS_TRIGGER); 107 108 pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); 109 pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, 110 ctl | PCI_EXP_DPC_CTL_INT_EN); 111 112 return PCI_ERS_RESULT_RECOVERED; 113 } 114 115 static void dpc_work(struct work_struct *work) 116 { 117 struct dpc_dev *dpc = container_of(work, struct dpc_dev, work); 118 struct pci_dev *pdev = dpc->dev->port; 119 120 /* We configure DPC so it only triggers on ERR_FATAL */ 121 pcie_do_fatal_recovery(pdev, PCIE_PORT_SERVICE_DPC); 122 } 123 124 static void dpc_process_rp_pio_error(struct dpc_dev *dpc) 125 { 126 struct device *dev = &dpc->dev->device; 127 struct pci_dev *pdev = dpc->dev->port; 128 u16 cap = dpc->cap_pos, dpc_status, first_error; 129 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; 130 int i; 131 132 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); 133 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); 134 dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", 135 status, mask); 136 137 dpc->rp_pio_status = status; 138 139 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); 140 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); 141 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); 142 dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", 143 sev, syserr, exc); 144 145 /* Get First Error Pointer */ 146 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); 147 first_error = (dpc_status & 0x1f00) >> 8; 148 149 status &= ~mask; 150 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { 151 if (status & (1 << i)) 152 dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i], 153 first_error == i ? " (First)" : ""); 154 } 155 156 if (dpc->rp_log_size < 4) 157 return; 158 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, 159 &dw0); 160 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, 161 &dw1); 162 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, 163 &dw2); 164 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, 165 &dw3); 166 dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n", 167 dw0, dw1, dw2, dw3); 168 169 if (dpc->rp_log_size < 5) 170 return; 171 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); 172 dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log); 173 174 for (i = 0; i < dpc->rp_log_size - 5; i++) { 175 pci_read_config_dword(pdev, 176 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix); 177 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); 178 } 179 } 180 181 static irqreturn_t dpc_irq(int irq, void *context) 182 { 183 struct dpc_dev *dpc = (struct dpc_dev *)context; 184 struct pci_dev *pdev = dpc->dev->port; 185 struct device *dev = &dpc->dev->device; 186 u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason; 187 188 pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); 189 190 if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0)) 191 return IRQ_NONE; 192 193 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); 194 195 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT)) 196 return IRQ_NONE; 197 198 if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) { 199 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 200 PCI_EXP_DPC_STATUS_INTERRUPT); 201 return IRQ_HANDLED; 202 } 203 204 pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, 205 ctl & ~PCI_EXP_DPC_CTL_INT_EN); 206 207 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, 208 &source); 209 210 dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n", 211 status, source); 212 213 reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; 214 ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; 215 216 dev_warn(dev, "DPC %s detected, remove downstream devices\n", 217 (reason == 0) ? "unmasked uncorrectable error" : 218 (reason == 1) ? "ERR_NONFATAL" : 219 (reason == 2) ? "ERR_FATAL" : 220 (ext_reason == 0) ? "RP PIO error" : 221 (ext_reason == 1) ? "software trigger" : 222 "reserved error"); 223 /* show RP PIO error detail information */ 224 if (dpc->rp_extensions && reason == 3 && ext_reason == 0) 225 dpc_process_rp_pio_error(dpc); 226 227 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, 228 PCI_EXP_DPC_STATUS_INTERRUPT); 229 230 schedule_work(&dpc->work); 231 232 return IRQ_HANDLED; 233 } 234 235 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 236 static int dpc_probe(struct pcie_device *dev) 237 { 238 struct dpc_dev *dpc; 239 struct pci_dev *pdev = dev->port; 240 struct device *device = &dev->device; 241 int status; 242 u16 ctl, cap; 243 244 if (pcie_aer_get_firmware_first(pdev)) 245 return -ENOTSUPP; 246 247 dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL); 248 if (!dpc) 249 return -ENOMEM; 250 251 dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC); 252 dpc->dev = dev; 253 INIT_WORK(&dpc->work, dpc_work); 254 set_service_data(dev, dpc); 255 256 status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED, 257 "pcie-dpc", dpc); 258 if (status) { 259 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq, 260 status); 261 return status; 262 } 263 264 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap); 265 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl); 266 267 dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT); 268 if (dpc->rp_extensions) { 269 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; 270 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) { 271 dev_err(device, "RP PIO log size %u is invalid\n", 272 dpc->rp_log_size); 273 dpc->rp_log_size = 0; 274 } 275 } 276 277 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 278 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); 279 280 dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", 281 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), 282 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP), 283 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size, 284 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE)); 285 return status; 286 } 287 288 static void dpc_remove(struct pcie_device *dev) 289 { 290 struct dpc_dev *dpc = get_service_data(dev); 291 struct pci_dev *pdev = dev->port; 292 u16 ctl; 293 294 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl); 295 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN); 296 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); 297 } 298 299 static struct pcie_port_service_driver dpcdriver = { 300 .name = "dpc", 301 .port_type = PCIE_ANY_PORT, 302 .service = PCIE_PORT_SERVICE_DPC, 303 .probe = dpc_probe, 304 .remove = dpc_remove, 305 .reset_link = dpc_reset_link, 306 }; 307 308 static int __init dpc_service_init(void) 309 { 310 return pcie_port_service_register(&dpcdriver); 311 } 312 device_initcall(dpc_service_init); 313